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KVM: nSVM: Fix IOIO bitmap evaluation
[linux-2.6/btrfs-unstable.git] / arch / x86 / kvm / svm.c
blob3483ac978c76e55681430bd817633d78c7914f34
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
8 *
9 * Authors:
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17 #include <linux/kvm_host.h>
18
19 #include "irq.h"
20 #include "mmu.h"
21 #include "kvm_cache_regs.h"
22 #include "x86.h"
23 #include "cpuid.h"
24
25 #include <linux/module.h>
26 #include <linux/mod_devicetable.h>
27 #include <linux/kernel.h>
28 #include <linux/vmalloc.h>
29 #include <linux/highmem.h>
30 #include <linux/sched.h>
31 #include <linux/ftrace_event.h>
32 #include <linux/slab.h>
33
34 #include <asm/perf_event.h>
35 #include <asm/tlbflush.h>
36 #include <asm/desc.h>
37 #include <asm/debugreg.h>
38 #include <asm/kvm_para.h>
39
40 #include <asm/virtext.h>
41 #include "trace.h"
42
43 #define __ex(x) __kvm_handle_fault_on_reboot(x)
44
45 MODULE_AUTHOR("Qumranet");
46 MODULE_LICENSE("GPL");
47
48 static const struct x86_cpu_id svm_cpu_id[] = {
49 X86_FEATURE_MATCH(X86_FEATURE_SVM),
50 {}
51 };
52 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
53
54 #define IOPM_ALLOC_ORDER 2
55 #define MSRPM_ALLOC_ORDER 1
56
57 #define SEG_TYPE_LDT 2
58 #define SEG_TYPE_BUSY_TSS16 3
59
60 #define SVM_FEATURE_NPT (1 << 0)
61 #define SVM_FEATURE_LBRV (1 << 1)
62 #define SVM_FEATURE_SVML (1 << 2)
63 #define SVM_FEATURE_NRIP (1 << 3)
64 #define SVM_FEATURE_TSC_RATE (1 << 4)
65 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
66 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
67 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
68 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
69
70 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
71 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
72 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
73
74 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
75
76 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
77 #define TSC_RATIO_MIN 0x0000000000000001ULL
78 #define TSC_RATIO_MAX 0x000000ffffffffffULL
79
80 static bool erratum_383_found __read_mostly;
81
82 static const u32 host_save_user_msrs[] = {
83 #ifdef CONFIG_X86_64
84 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
85 MSR_FS_BASE,
86 #endif
87 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
88 };
89
90 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
91
92 struct kvm_vcpu;
93
94 struct nested_state {
95 struct vmcb *hsave;
96 u64 hsave_msr;
97 u64 vm_cr_msr;
98 u64 vmcb;
99
100 /* These are the merged vectors */
101 u32 *msrpm;
102
103 /* gpa pointers to the real vectors */
104 u64 vmcb_msrpm;
105 u64 vmcb_iopm;
106
107 /* A VMEXIT is required but not yet emulated */
108 bool exit_required;
109
110 /* cache for intercepts of the guest */
111 u32 intercept_cr;
112 u32 intercept_dr;
113 u32 intercept_exceptions;
114 u64 intercept;
115
116 /* Nested Paging related state */
117 u64 nested_cr3;
118 };
119
120 #define MSRPM_OFFSETS 16
121 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
122
123 /*
124 * Set osvw_len to higher value when updated Revision Guides
125 * are published and we know what the new status bits are
126 */
127 static uint64_t osvw_len = 4, osvw_status;
128
129 struct vcpu_svm {
130 struct kvm_vcpu vcpu;
131 struct vmcb *vmcb;
132 unsigned long vmcb_pa;
133 struct svm_cpu_data *svm_data;
134 uint64_t asid_generation;
135 uint64_t sysenter_esp;
136 uint64_t sysenter_eip;
137
138 u64 next_rip;
139
140 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
141 struct {
142 u16 fs;
143 u16 gs;
144 u16 ldt;
145 u64 gs_base;
146 } host;
147
148 u32 *msrpm;
149
150 ulong nmi_iret_rip;
151
152 struct nested_state nested;
153
154 bool nmi_singlestep;
155
156 unsigned int3_injected;
157 unsigned long int3_rip;
158 u32 apf_reason;
159
160 u64 tsc_ratio;
161 };
162
163 static DEFINE_PER_CPU(u64, current_tsc_ratio);
164 #define TSC_RATIO_DEFAULT 0x0100000000ULL
165
166 #define MSR_INVALID 0xffffffffU
167
168 static const struct svm_direct_access_msrs {
169 u32 index; /* Index of the MSR */
170 bool always; /* True if intercept is always on */
171 } direct_access_msrs[] = {
172 { .index = MSR_STAR, .always = true },
173 { .index = MSR_IA32_SYSENTER_CS, .always = true },
174 #ifdef CONFIG_X86_64
175 { .index = MSR_GS_BASE, .always = true },
176 { .index = MSR_FS_BASE, .always = true },
177 { .index = MSR_KERNEL_GS_BASE, .always = true },
178 { .index = MSR_LSTAR, .always = true },
179 { .index = MSR_CSTAR, .always = true },
180 { .index = MSR_SYSCALL_MASK, .always = true },
181 #endif
182 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
183 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
184 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
185 { .index = MSR_IA32_LASTINTTOIP, .always = false },
186 { .index = MSR_INVALID, .always = false },
187 };
188
189 /* enable NPT for AMD64 and X86 with PAE */
190 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
191 static bool npt_enabled = true;
192 #else
193 static bool npt_enabled;
194 #endif
195
196 /* allow nested paging (virtualized MMU) for all guests */
197 static int npt = true;
198 module_param(npt, int, S_IRUGO);
199
200 /* allow nested virtualization in KVM/SVM */
201 static int nested = true;
202 module_param(nested, int, S_IRUGO);
203
204 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
205 static void svm_complete_interrupts(struct vcpu_svm *svm);
206
207 static int nested_svm_exit_handled(struct vcpu_svm *svm);
208 static int nested_svm_intercept(struct vcpu_svm *svm);
209 static int nested_svm_vmexit(struct vcpu_svm *svm);
210 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
211 bool has_error_code, u32 error_code);
212 static u64 __scale_tsc(u64 ratio, u64 tsc);
213
214 enum {
215 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
216 pause filter count */
217 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
218 VMCB_ASID, /* ASID */
219 VMCB_INTR, /* int_ctl, int_vector */
220 VMCB_NPT, /* npt_en, nCR3, gPAT */
221 VMCB_CR, /* CR0, CR3, CR4, EFER */
222 VMCB_DR, /* DR6, DR7 */
223 VMCB_DT, /* GDT, IDT */
224 VMCB_SEG, /* CS, DS, SS, ES, CPL */
225 VMCB_CR2, /* CR2 only */
226 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
227 VMCB_DIRTY_MAX,
228 };
229
230 /* TPR and CR2 are always written before VMRUN */
231 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
232
233 static inline void mark_all_dirty(struct vmcb *vmcb)
234 {
235 vmcb->control.clean = 0;
236 }
237
238 static inline void mark_all_clean(struct vmcb *vmcb)
239 {
240 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
241 & ~VMCB_ALWAYS_DIRTY_MASK;
242 }
243
244 static inline void mark_dirty(struct vmcb *vmcb, int bit)
245 {
246 vmcb->control.clean &= ~(1 << bit);
247 }
248
249 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
250 {
251 return container_of(vcpu, struct vcpu_svm, vcpu);
252 }
253
254 static void recalc_intercepts(struct vcpu_svm *svm)
255 {
256 struct vmcb_control_area *c, *h;
257 struct nested_state *g;
258
259 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
260
261 if (!is_guest_mode(&svm->vcpu))
262 return;
263
264 c = &svm->vmcb->control;
265 h = &svm->nested.hsave->control;
266 g = &svm->nested;
267
268 c->intercept_cr = h->intercept_cr | g->intercept_cr;
269 c->intercept_dr = h->intercept_dr | g->intercept_dr;
270 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
271 c->intercept = h->intercept | g->intercept;
272 }
273
274 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
275 {
276 if (is_guest_mode(&svm->vcpu))
277 return svm->nested.hsave;
278 else
279 return svm->vmcb;
280 }
281
282 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
283 {
284 struct vmcb *vmcb = get_host_vmcb(svm);
285
286 vmcb->control.intercept_cr |= (1U << bit);
287
288 recalc_intercepts(svm);
289 }
290
291 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
292 {
293 struct vmcb *vmcb = get_host_vmcb(svm);
294
295 vmcb->control.intercept_cr &= ~(1U << bit);
296
297 recalc_intercepts(svm);
298 }
299
300 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
301 {
302 struct vmcb *vmcb = get_host_vmcb(svm);
303
304 return vmcb->control.intercept_cr & (1U << bit);
305 }
306
307 static inline void set_dr_intercepts(struct vcpu_svm *svm)
308 {
309 struct vmcb *vmcb = get_host_vmcb(svm);
310
311 vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
312 | (1 << INTERCEPT_DR1_READ)
313 | (1 << INTERCEPT_DR2_READ)
314 | (1 << INTERCEPT_DR3_READ)
315 | (1 << INTERCEPT_DR4_READ)
316 | (1 << INTERCEPT_DR5_READ)
317 | (1 << INTERCEPT_DR6_READ)
318 | (1 << INTERCEPT_DR7_READ)
319 | (1 << INTERCEPT_DR0_WRITE)
320 | (1 << INTERCEPT_DR1_WRITE)
321 | (1 << INTERCEPT_DR2_WRITE)
322 | (1 << INTERCEPT_DR3_WRITE)
323 | (1 << INTERCEPT_DR4_WRITE)
324 | (1 << INTERCEPT_DR5_WRITE)
325 | (1 << INTERCEPT_DR6_WRITE)
326 | (1 << INTERCEPT_DR7_WRITE);
327
328 recalc_intercepts(svm);
329 }
330
331 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
332 {
333 struct vmcb *vmcb = get_host_vmcb(svm);
334
335 vmcb->control.intercept_dr = 0;
336
337 recalc_intercepts(svm);
338 }
339
340 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
341 {
342 struct vmcb *vmcb = get_host_vmcb(svm);
343
344 vmcb->control.intercept_exceptions |= (1U << bit);
345
346 recalc_intercepts(svm);
347 }
348
349 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
350 {
351 struct vmcb *vmcb = get_host_vmcb(svm);
352
353 vmcb->control.intercept_exceptions &= ~(1U << bit);
354
355 recalc_intercepts(svm);
356 }
357
358 static inline void set_intercept(struct vcpu_svm *svm, int bit)
359 {
360 struct vmcb *vmcb = get_host_vmcb(svm);
361
362 vmcb->control.intercept |= (1ULL << bit);
363
364 recalc_intercepts(svm);
365 }
366
367 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
368 {
369 struct vmcb *vmcb = get_host_vmcb(svm);
370
371 vmcb->control.intercept &= ~(1ULL << bit);
372
373 recalc_intercepts(svm);
374 }
375
376 static inline void enable_gif(struct vcpu_svm *svm)
377 {
378 svm->vcpu.arch.hflags |= HF_GIF_MASK;
379 }
380
381 static inline void disable_gif(struct vcpu_svm *svm)
382 {
383 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
384 }
385
386 static inline bool gif_set(struct vcpu_svm *svm)
387 {
388 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
389 }
390
391 static unsigned long iopm_base;
392
393 struct kvm_ldttss_desc {
394 u16 limit0;
395 u16 base0;
396 unsigned base1:8, type:5, dpl:2, p:1;
397 unsigned limit1:4, zero0:3, g:1, base2:8;
398 u32 base3;
399 u32 zero1;
400 } __attribute__((packed));
401
402 struct svm_cpu_data {
403 int cpu;
404
405 u64 asid_generation;
406 u32 max_asid;
407 u32 next_asid;
408 struct kvm_ldttss_desc *tss_desc;
409
410 struct page *save_area;
411 };
412
413 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
414
415 struct svm_init_data {
416 int cpu;
417 int r;
418 };
419
420 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
421
422 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
423 #define MSRS_RANGE_SIZE 2048
424 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
425
426 static u32 svm_msrpm_offset(u32 msr)
427 {
428 u32 offset;
429 int i;
430
431 for (i = 0; i < NUM_MSR_MAPS; i++) {
432 if (msr < msrpm_ranges[i] ||
433 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
434 continue;
435
436 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
437 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
438
439 /* Now we have the u8 offset - but need the u32 offset */
440 return offset / 4;
441 }
442
443 /* MSR not in any range */
444 return MSR_INVALID;
445 }
446
447 #define MAX_INST_SIZE 15
448
449 static inline void clgi(void)
450 {
451 asm volatile (__ex(SVM_CLGI));
452 }
453
454 static inline void stgi(void)
455 {
456 asm volatile (__ex(SVM_STGI));
457 }
458
459 static inline void invlpga(unsigned long addr, u32 asid)
460 {
461 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
462 }
463
464 static int get_npt_level(void)
465 {
466 #ifdef CONFIG_X86_64
467 return PT64_ROOT_LEVEL;
468 #else
469 return PT32E_ROOT_LEVEL;
470 #endif
471 }
472
473 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
474 {
475 vcpu->arch.efer = efer;
476 if (!npt_enabled && !(efer & EFER_LMA))
477 efer &= ~EFER_LME;
478
479 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
480 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
481 }
482
483 static int is_external_interrupt(u32 info)
484 {
485 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
486 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
487 }
488
489 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
490 {
491 struct vcpu_svm *svm = to_svm(vcpu);
492 u32 ret = 0;
493
494 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
495 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
496 return ret & mask;
497 }
498
499 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
500 {
501 struct vcpu_svm *svm = to_svm(vcpu);
502
503 if (mask == 0)
504 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
505 else
506 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
507
508 }
509
510 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
511 {
512 struct vcpu_svm *svm = to_svm(vcpu);
513
514 if (svm->vmcb->control.next_rip != 0)
515 svm->next_rip = svm->vmcb->control.next_rip;
516
517 if (!svm->next_rip) {
518 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
519 EMULATE_DONE)
520 printk(KERN_DEBUG "%s: NOP\n", __func__);
521 return;
522 }
523 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
524 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
525 __func__, kvm_rip_read(vcpu), svm->next_rip);
526
527 kvm_rip_write(vcpu, svm->next_rip);
528 svm_set_interrupt_shadow(vcpu, 0);
529 }
530
531 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
532 bool has_error_code, u32 error_code,
533 bool reinject)
534 {
535 struct vcpu_svm *svm = to_svm(vcpu);
536
537 /*
538 * If we are within a nested VM we'd better #VMEXIT and let the guest
539 * handle the exception
540 */
541 if (!reinject &&
542 nested_svm_check_exception(svm, nr, has_error_code, error_code))
543 return;
544
545 if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
546 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
547
548 /*
549 * For guest debugging where we have to reinject #BP if some
550 * INT3 is guest-owned:
551 * Emulate nRIP by moving RIP forward. Will fail if injection
552 * raises a fault that is not intercepted. Still better than
553 * failing in all cases.
554 */
555 skip_emulated_instruction(&svm->vcpu);
556 rip = kvm_rip_read(&svm->vcpu);
557 svm->int3_rip = rip + svm->vmcb->save.cs.base;
558 svm->int3_injected = rip - old_rip;
559 }
560
561 svm->vmcb->control.event_inj = nr
562 | SVM_EVTINJ_VALID
563 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
564 | SVM_EVTINJ_TYPE_EXEPT;
565 svm->vmcb->control.event_inj_err = error_code;
566 }
567
568 static void svm_init_erratum_383(void)
569 {
570 u32 low, high;
571 int err;
572 u64 val;
573
574 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
575 return;
576
577 /* Use _safe variants to not break nested virtualization */
578 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
579 if (err)
580 return;
581
582 val |= (1ULL << 47);
583
584 low = lower_32_bits(val);
585 high = upper_32_bits(val);
586
587 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
588
589 erratum_383_found = true;
590 }
591
592 static void svm_init_osvw(struct kvm_vcpu *vcpu)
593 {
594 /*
595 * Guests should see errata 400 and 415 as fixed (assuming that
596 * HLT and IO instructions are intercepted).
597 */
598 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
599 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
600
601 /*
602 * By increasing VCPU's osvw.length to 3 we are telling the guest that
603 * all osvw.status bits inside that length, including bit 0 (which is
604 * reserved for erratum 298), are valid. However, if host processor's
605 * osvw_len is 0 then osvw_status[0] carries no information. We need to
606 * be conservative here and therefore we tell the guest that erratum 298
607 * is present (because we really don't know).
608 */
609 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
610 vcpu->arch.osvw.status |= 1;
611 }
612
613 static int has_svm(void)
614 {
615 const char *msg;
616
617 if (!cpu_has_svm(&msg)) {
618 printk(KERN_INFO "has_svm: %s\n", msg);
619 return 0;
620 }
621
622 return 1;
623 }
624
625 static void svm_hardware_disable(void *garbage)
626 {
627 /* Make sure we clean up behind us */
628 if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
629 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
630
631 cpu_svm_disable();
632
633 amd_pmu_disable_virt();
634 }
635
636 static int svm_hardware_enable(void *garbage)
637 {
638
639 struct svm_cpu_data *sd;
640 uint64_t efer;
641 struct desc_ptr gdt_descr;
642 struct desc_struct *gdt;
643 int me = raw_smp_processor_id();
644
645 rdmsrl(MSR_EFER, efer);
646 if (efer & EFER_SVME)
647 return -EBUSY;
648
649 if (!has_svm()) {
650 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
651 return -EINVAL;
652 }
653 sd = per_cpu(svm_data, me);
654 if (!sd) {
655 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
656 return -EINVAL;
657 }
658
659 sd->asid_generation = 1;
660 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
661 sd->next_asid = sd->max_asid + 1;
662
663 native_store_gdt(&gdt_descr);
664 gdt = (struct desc_struct *)gdt_descr.address;
665 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
666
667 wrmsrl(MSR_EFER, efer | EFER_SVME);
668
669 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
670
671 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
672 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
673 __get_cpu_var(current_tsc_ratio) = TSC_RATIO_DEFAULT;
674 }
675
676
677 /*
678 * Get OSVW bits.
679 *
680 * Note that it is possible to have a system with mixed processor
681 * revisions and therefore different OSVW bits. If bits are not the same
682 * on different processors then choose the worst case (i.e. if erratum
683 * is present on one processor and not on another then assume that the
684 * erratum is present everywhere).
685 */
686 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
687 uint64_t len, status = 0;
688 int err;
689
690 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
691 if (!err)
692 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
693 &err);
694
695 if (err)
696 osvw_status = osvw_len = 0;
697 else {
698 if (len < osvw_len)
699 osvw_len = len;
700 osvw_status |= status;
701 osvw_status &= (1ULL << osvw_len) - 1;
702 }
703 } else
704 osvw_status = osvw_len = 0;
705
706 svm_init_erratum_383();
707
708 amd_pmu_enable_virt();
709
710 return 0;
711 }
712
713 static void svm_cpu_uninit(int cpu)
714 {
715 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
716
717 if (!sd)
718 return;
719
720 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
721 __free_page(sd->save_area);
722 kfree(sd);
723 }
724
725 static int svm_cpu_init(int cpu)
726 {
727 struct svm_cpu_data *sd;
728 int r;
729
730 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
731 if (!sd)
732 return -ENOMEM;
733 sd->cpu = cpu;
734 sd->save_area = alloc_page(GFP_KERNEL);
735 r = -ENOMEM;
736 if (!sd->save_area)
737 goto err_1;
738
739 per_cpu(svm_data, cpu) = sd;
740
741 return 0;
742
743 err_1:
744 kfree(sd);
745 return r;
746
747 }
748
749 static bool valid_msr_intercept(u32 index)
750 {
751 int i;
752
753 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
754 if (direct_access_msrs[i].index == index)
755 return true;
756
757 return false;
758 }
759
760 static void set_msr_interception(u32 *msrpm, unsigned msr,
761 int read, int write)
762 {
763 u8 bit_read, bit_write;
764 unsigned long tmp;
765 u32 offset;
766
767 /*
768 * If this warning triggers extend the direct_access_msrs list at the
769 * beginning of the file
770 */
771 WARN_ON(!valid_msr_intercept(msr));
772
773 offset = svm_msrpm_offset(msr);
774 bit_read = 2 * (msr & 0x0f);
775 bit_write = 2 * (msr & 0x0f) + 1;
776 tmp = msrpm[offset];
777
778 BUG_ON(offset == MSR_INVALID);
779
780 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
781 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
782
783 msrpm[offset] = tmp;
784 }
785
786 static void svm_vcpu_init_msrpm(u32 *msrpm)
787 {
788 int i;
789
790 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
791
792 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
793 if (!direct_access_msrs[i].always)
794 continue;
795
796 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
797 }
798 }
799
800 static void add_msr_offset(u32 offset)
801 {
802 int i;
803
804 for (i = 0; i < MSRPM_OFFSETS; ++i) {
805
806 /* Offset already in list? */
807 if (msrpm_offsets[i] == offset)
808 return;
809
810 /* Slot used by another offset? */
811 if (msrpm_offsets[i] != MSR_INVALID)
812 continue;
813
814 /* Add offset to list */
815 msrpm_offsets[i] = offset;
816
817 return;
818 }
819
820 /*
821 * If this BUG triggers the msrpm_offsets table has an overflow. Just
822 * increase MSRPM_OFFSETS in this case.
823 */
824 BUG();
825 }
826
827 static void init_msrpm_offsets(void)
828 {
829 int i;
830
831 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
832
833 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
834 u32 offset;
835
836 offset = svm_msrpm_offset(direct_access_msrs[i].index);
837 BUG_ON(offset == MSR_INVALID);
838
839 add_msr_offset(offset);
840 }
841 }
842
843 static void svm_enable_lbrv(struct vcpu_svm *svm)
844 {
845 u32 *msrpm = svm->msrpm;
846
847 svm->vmcb->control.lbr_ctl = 1;
848 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
849 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
850 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
851 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
852 }
853
854 static void svm_disable_lbrv(struct vcpu_svm *svm)
855 {
856 u32 *msrpm = svm->msrpm;
857
858 svm->vmcb->control.lbr_ctl = 0;
859 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
860 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
861 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
862 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
863 }
864
865 static __init int svm_hardware_setup(void)
866 {
867 int cpu;
868 struct page *iopm_pages;
869 void *iopm_va;
870 int r;
871
872 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
873
874 if (!iopm_pages)
875 return -ENOMEM;
876
877 iopm_va = page_address(iopm_pages);
878 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
879 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
880
881 init_msrpm_offsets();
882
883 if (boot_cpu_has(X86_FEATURE_NX))
884 kvm_enable_efer_bits(EFER_NX);
885
886 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
887 kvm_enable_efer_bits(EFER_FFXSR);
888
889 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
890 u64 max;
891
892 kvm_has_tsc_control = true;
893
894 /*
895 * Make sure the user can only configure tsc_khz values that
896 * fit into a signed integer.
897 * A min value is not calculated needed because it will always
898 * be 1 on all machines and a value of 0 is used to disable
899 * tsc-scaling for the vcpu.
900 */
901 max = min(0x7fffffffULL, __scale_tsc(tsc_khz, TSC_RATIO_MAX));
902
903 kvm_max_guest_tsc_khz = max;
904 }
905
906 if (nested) {
907 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
908 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
909 }
910
911 for_each_possible_cpu(cpu) {
912 r = svm_cpu_init(cpu);
913 if (r)
914 goto err;
915 }
916
917 if (!boot_cpu_has(X86_FEATURE_NPT))
918 npt_enabled = false;
919
920 if (npt_enabled && !npt) {
921 printk(KERN_INFO "kvm: Nested Paging disabled\n");
922 npt_enabled = false;
923 }
924
925 if (npt_enabled) {
926 printk(KERN_INFO "kvm: Nested Paging enabled\n");
927 kvm_enable_tdp();
928 } else
929 kvm_disable_tdp();
930
931 return 0;
932
933 err:
934 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
935 iopm_base = 0;
936 return r;
937 }
938
939 static __exit void svm_hardware_unsetup(void)
940 {
941 int cpu;
942
943 for_each_possible_cpu(cpu)
944 svm_cpu_uninit(cpu);
945
946 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
947 iopm_base = 0;
948 }
949
950 static void init_seg(struct vmcb_seg *seg)
951 {
952 seg->selector = 0;
953 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
954 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
955 seg->limit = 0xffff;
956 seg->base = 0;
957 }
958
959 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
960 {
961 seg->selector = 0;
962 seg->attrib = SVM_SELECTOR_P_MASK | type;
963 seg->limit = 0xffff;
964 seg->base = 0;
965 }
966
967 static u64 __scale_tsc(u64 ratio, u64 tsc)
968 {
969 u64 mult, frac, _tsc;
970
971 mult = ratio >> 32;
972 frac = ratio & ((1ULL << 32) - 1);
973
974 _tsc = tsc;
975 _tsc *= mult;
976 _tsc += (tsc >> 32) * frac;
977 _tsc += ((tsc & ((1ULL << 32) - 1)) * frac) >> 32;
978
979 return _tsc;
980 }
981
982 static u64 svm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
983 {
984 struct vcpu_svm *svm = to_svm(vcpu);
985 u64 _tsc = tsc;
986
987 if (svm->tsc_ratio != TSC_RATIO_DEFAULT)
988 _tsc = __scale_tsc(svm->tsc_ratio, tsc);
989
990 return _tsc;
991 }
992
993 static void svm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
994 {
995 struct vcpu_svm *svm = to_svm(vcpu);
996 u64 ratio;
997 u64 khz;
998
999 /* Guest TSC same frequency as host TSC? */
1000 if (!scale) {
1001 svm->tsc_ratio = TSC_RATIO_DEFAULT;
1002 return;
1003 }
1004
1005 /* TSC scaling supported? */
1006 if (!boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1007 if (user_tsc_khz > tsc_khz) {
1008 vcpu->arch.tsc_catchup = 1;
1009 vcpu->arch.tsc_always_catchup = 1;
1010 } else
1011 WARN(1, "user requested TSC rate below hardware speed\n");
1012 return;
1013 }
1014
1015 khz = user_tsc_khz;
1016
1017 /* TSC scaling required - calculate ratio */
1018 ratio = khz << 32;
1019 do_div(ratio, tsc_khz);
1020
1021 if (ratio == 0 || ratio & TSC_RATIO_RSVD) {
1022 WARN_ONCE(1, "Invalid TSC ratio - virtual-tsc-khz=%u\n",
1023 user_tsc_khz);
1024 return;
1025 }
1026 svm->tsc_ratio = ratio;
1027 }
1028
1029 static u64 svm_read_tsc_offset(struct kvm_vcpu *vcpu)
1030 {
1031 struct vcpu_svm *svm = to_svm(vcpu);
1032
1033 return svm->vmcb->control.tsc_offset;
1034 }
1035
1036 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1037 {
1038 struct vcpu_svm *svm = to_svm(vcpu);
1039 u64 g_tsc_offset = 0;
1040
1041 if (is_guest_mode(vcpu)) {
1042 g_tsc_offset = svm->vmcb->control.tsc_offset -
1043 svm->nested.hsave->control.tsc_offset;
1044 svm->nested.hsave->control.tsc_offset = offset;
1045 } else
1046 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1047 svm->vmcb->control.tsc_offset,
1048 offset);
1049
1050 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1051
1052 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1053 }
1054
1055 static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
1056 {
1057 struct vcpu_svm *svm = to_svm(vcpu);
1058
1059 WARN_ON(adjustment < 0);
1060 if (host)
1061 adjustment = svm_scale_tsc(vcpu, adjustment);
1062
1063 svm->vmcb->control.tsc_offset += adjustment;
1064 if (is_guest_mode(vcpu))
1065 svm->nested.hsave->control.tsc_offset += adjustment;
1066 else
1067 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1068 svm->vmcb->control.tsc_offset - adjustment,
1069 svm->vmcb->control.tsc_offset);
1070
1071 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1072 }
1073
1074 static u64 svm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1075 {
1076 u64 tsc;
1077
1078 tsc = svm_scale_tsc(vcpu, native_read_tsc());
1079
1080 return target_tsc - tsc;
1081 }
1082
1083 static void init_vmcb(struct vcpu_svm *svm)
1084 {
1085 struct vmcb_control_area *control = &svm->vmcb->control;
1086 struct vmcb_save_area *save = &svm->vmcb->save;
1087
1088 svm->vcpu.fpu_active = 1;
1089 svm->vcpu.arch.hflags = 0;
1090
1091 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1092 set_cr_intercept(svm, INTERCEPT_CR3_READ);
1093 set_cr_intercept(svm, INTERCEPT_CR4_READ);
1094 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1095 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1096 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1097 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1098
1099 set_dr_intercepts(svm);
1100
1101 set_exception_intercept(svm, PF_VECTOR);
1102 set_exception_intercept(svm, UD_VECTOR);
1103 set_exception_intercept(svm, MC_VECTOR);
1104
1105 set_intercept(svm, INTERCEPT_INTR);
1106 set_intercept(svm, INTERCEPT_NMI);
1107 set_intercept(svm, INTERCEPT_SMI);
1108 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1109 set_intercept(svm, INTERCEPT_RDPMC);
1110 set_intercept(svm, INTERCEPT_CPUID);
1111 set_intercept(svm, INTERCEPT_INVD);
1112 set_intercept(svm, INTERCEPT_HLT);
1113 set_intercept(svm, INTERCEPT_INVLPG);
1114 set_intercept(svm, INTERCEPT_INVLPGA);
1115 set_intercept(svm, INTERCEPT_IOIO_PROT);
1116 set_intercept(svm, INTERCEPT_MSR_PROT);
1117 set_intercept(svm, INTERCEPT_TASK_SWITCH);
1118 set_intercept(svm, INTERCEPT_SHUTDOWN);
1119 set_intercept(svm, INTERCEPT_VMRUN);
1120 set_intercept(svm, INTERCEPT_VMMCALL);
1121 set_intercept(svm, INTERCEPT_VMLOAD);
1122 set_intercept(svm, INTERCEPT_VMSAVE);
1123 set_intercept(svm, INTERCEPT_STGI);
1124 set_intercept(svm, INTERCEPT_CLGI);
1125 set_intercept(svm, INTERCEPT_SKINIT);
1126 set_intercept(svm, INTERCEPT_WBINVD);
1127 set_intercept(svm, INTERCEPT_MONITOR);
1128 set_intercept(svm, INTERCEPT_MWAIT);
1129 set_intercept(svm, INTERCEPT_XSETBV);
1130
1131 control->iopm_base_pa = iopm_base;
1132 control->msrpm_base_pa = __pa(svm->msrpm);
1133 control->int_ctl = V_INTR_MASKING_MASK;
1134
1135 init_seg(&save->es);
1136 init_seg(&save->ss);
1137 init_seg(&save->ds);
1138 init_seg(&save->fs);
1139 init_seg(&save->gs);
1140
1141 save->cs.selector = 0xf000;
1142 save->cs.base = 0xffff0000;
1143 /* Executable/Readable Code Segment */
1144 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1145 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1146 save->cs.limit = 0xffff;
1147
1148 save->gdtr.limit = 0xffff;
1149 save->idtr.limit = 0xffff;
1150
1151 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1152 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1153
1154 svm_set_efer(&svm->vcpu, 0);
1155 save->dr6 = 0xffff0ff0;
1156 kvm_set_rflags(&svm->vcpu, 2);
1157 save->rip = 0x0000fff0;
1158 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1159
1160 /*
1161 * This is the guest-visible cr0 value.
1162 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1163 */
1164 svm->vcpu.arch.cr0 = 0;
1165 (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1166
1167 save->cr4 = X86_CR4_PAE;
1168 /* rdx = ?? */
1169
1170 if (npt_enabled) {
1171 /* Setup VMCB for Nested Paging */
1172 control->nested_ctl = 1;
1173 clr_intercept(svm, INTERCEPT_INVLPG);
1174 clr_exception_intercept(svm, PF_VECTOR);
1175 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1176 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1177 save->g_pat = 0x0007040600070406ULL;
1178 save->cr3 = 0;
1179 save->cr4 = 0;
1180 }
1181 svm->asid_generation = 0;
1182
1183 svm->nested.vmcb = 0;
1184 svm->vcpu.arch.hflags = 0;
1185
1186 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1187 control->pause_filter_count = 3000;
1188 set_intercept(svm, INTERCEPT_PAUSE);
1189 }
1190
1191 mark_all_dirty(svm->vmcb);
1192
1193 enable_gif(svm);
1194 }
1195
1196 static void svm_vcpu_reset(struct kvm_vcpu *vcpu)
1197 {
1198 struct vcpu_svm *svm = to_svm(vcpu);
1199 u32 dummy;
1200 u32 eax = 1;
1201
1202 init_vmcb(svm);
1203
1204 kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy);
1205 kvm_register_write(vcpu, VCPU_REGS_RDX, eax);
1206 }
1207
1208 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1209 {
1210 struct vcpu_svm *svm;
1211 struct page *page;
1212 struct page *msrpm_pages;
1213 struct page *hsave_page;
1214 struct page *nested_msrpm_pages;
1215 int err;
1216
1217 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1218 if (!svm) {
1219 err = -ENOMEM;
1220 goto out;
1221 }
1222
1223 svm->tsc_ratio = TSC_RATIO_DEFAULT;
1224
1225 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1226 if (err)
1227 goto free_svm;
1228
1229 err = -ENOMEM;
1230 page = alloc_page(GFP_KERNEL);
1231 if (!page)
1232 goto uninit;
1233
1234 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1235 if (!msrpm_pages)
1236 goto free_page1;
1237
1238 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1239 if (!nested_msrpm_pages)
1240 goto free_page2;
1241
1242 hsave_page = alloc_page(GFP_KERNEL);
1243 if (!hsave_page)
1244 goto free_page3;
1245
1246 svm->nested.hsave = page_address(hsave_page);
1247
1248 svm->msrpm = page_address(msrpm_pages);
1249 svm_vcpu_init_msrpm(svm->msrpm);
1250
1251 svm->nested.msrpm = page_address(nested_msrpm_pages);
1252 svm_vcpu_init_msrpm(svm->nested.msrpm);
1253
1254 svm->vmcb = page_address(page);
1255 clear_page(svm->vmcb);
1256 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1257 svm->asid_generation = 0;
1258 init_vmcb(svm);
1259
1260 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1261 if (kvm_vcpu_is_bsp(&svm->vcpu))
1262 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1263
1264 svm_init_osvw(&svm->vcpu);
1265
1266 return &svm->vcpu;
1267
1268 free_page3:
1269 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1270 free_page2:
1271 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1272 free_page1:
1273 __free_page(page);
1274 uninit:
1275 kvm_vcpu_uninit(&svm->vcpu);
1276 free_svm:
1277 kmem_cache_free(kvm_vcpu_cache, svm);
1278 out:
1279 return ERR_PTR(err);
1280 }
1281
1282 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1283 {
1284 struct vcpu_svm *svm = to_svm(vcpu);
1285
1286 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1287 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1288 __free_page(virt_to_page(svm->nested.hsave));
1289 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1290 kvm_vcpu_uninit(vcpu);
1291 kmem_cache_free(kvm_vcpu_cache, svm);
1292 }
1293
1294 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1295 {
1296 struct vcpu_svm *svm = to_svm(vcpu);
1297 int i;
1298
1299 if (unlikely(cpu != vcpu->cpu)) {
1300 svm->asid_generation = 0;
1301 mark_all_dirty(svm->vmcb);
1302 }
1303
1304 #ifdef CONFIG_X86_64
1305 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1306 #endif
1307 savesegment(fs, svm->host.fs);
1308 savesegment(gs, svm->host.gs);
1309 svm->host.ldt = kvm_read_ldt();
1310
1311 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1312 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1313
1314 if (static_cpu_has(X86_FEATURE_TSCRATEMSR) &&
1315 svm->tsc_ratio != __get_cpu_var(current_tsc_ratio)) {
1316 __get_cpu_var(current_tsc_ratio) = svm->tsc_ratio;
1317 wrmsrl(MSR_AMD64_TSC_RATIO, svm->tsc_ratio);
1318 }
1319 }
1320
1321 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1322 {
1323 struct vcpu_svm *svm = to_svm(vcpu);
1324 int i;
1325
1326 ++vcpu->stat.host_state_reload;
1327 kvm_load_ldt(svm->host.ldt);
1328 #ifdef CONFIG_X86_64
1329 loadsegment(fs, svm->host.fs);
1330 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1331 load_gs_index(svm->host.gs);
1332 #else
1333 #ifdef CONFIG_X86_32_LAZY_GS
1334 loadsegment(gs, svm->host.gs);
1335 #endif
1336 #endif
1337 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1338 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1339 }
1340
1341 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1342 {
1343 return to_svm(vcpu)->vmcb->save.rflags;
1344 }
1345
1346 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1347 {
1348 /*
1349 * Any change of EFLAGS.VM is accompained by a reload of SS
1350 * (caused by either a task switch or an inter-privilege IRET),
1351 * so we do not need to update the CPL here.
1352 */
1353 to_svm(vcpu)->vmcb->save.rflags = rflags;
1354 }
1355
1356 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1357 {
1358 switch (reg) {
1359 case VCPU_EXREG_PDPTR:
1360 BUG_ON(!npt_enabled);
1361 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1362 break;
1363 default:
1364 BUG();
1365 }
1366 }
1367
1368 static void svm_set_vintr(struct vcpu_svm *svm)
1369 {
1370 set_intercept(svm, INTERCEPT_VINTR);
1371 }
1372
1373 static void svm_clear_vintr(struct vcpu_svm *svm)
1374 {
1375 clr_intercept(svm, INTERCEPT_VINTR);
1376 }
1377
1378 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1379 {
1380 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1381
1382 switch (seg) {
1383 case VCPU_SREG_CS: return &save->cs;
1384 case VCPU_SREG_DS: return &save->ds;
1385 case VCPU_SREG_ES: return &save->es;
1386 case VCPU_SREG_FS: return &save->fs;
1387 case VCPU_SREG_GS: return &save->gs;
1388 case VCPU_SREG_SS: return &save->ss;
1389 case VCPU_SREG_TR: return &save->tr;
1390 case VCPU_SREG_LDTR: return &save->ldtr;
1391 }
1392 BUG();
1393 return NULL;
1394 }
1395
1396 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1397 {
1398 struct vmcb_seg *s = svm_seg(vcpu, seg);
1399
1400 return s->base;
1401 }
1402
1403 static void svm_get_segment(struct kvm_vcpu *vcpu,
1404 struct kvm_segment *var, int seg)
1405 {
1406 struct vmcb_seg *s = svm_seg(vcpu, seg);
1407
1408 var->base = s->base;
1409 var->limit = s->limit;
1410 var->selector = s->selector;
1411 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1412 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1413 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1414 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1415 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1416 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1417 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1418 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
1419
1420 /*
1421 * AMD's VMCB does not have an explicit unusable field, so emulate it
1422 * for cross vendor migration purposes by "not present"
1423 */
1424 var->unusable = !var->present || (var->type == 0);
1425
1426 switch (seg) {
1427 case VCPU_SREG_CS:
1428 /*
1429 * SVM always stores 0 for the 'G' bit in the CS selector in
1430 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1431 * Intel's VMENTRY has a check on the 'G' bit.
1432 */
1433 var->g = s->limit > 0xfffff;
1434 break;
1435 case VCPU_SREG_TR:
1436 /*
1437 * Work around a bug where the busy flag in the tr selector
1438 * isn't exposed
1439 */
1440 var->type |= 0x2;
1441 break;
1442 case VCPU_SREG_DS:
1443 case VCPU_SREG_ES:
1444 case VCPU_SREG_FS:
1445 case VCPU_SREG_GS:
1446 /*
1447 * The accessed bit must always be set in the segment
1448 * descriptor cache, although it can be cleared in the
1449 * descriptor, the cached bit always remains at 1. Since
1450 * Intel has a check on this, set it here to support
1451 * cross-vendor migration.
1452 */
1453 if (!var->unusable)
1454 var->type |= 0x1;
1455 break;
1456 case VCPU_SREG_SS:
1457 /*
1458 * On AMD CPUs sometimes the DB bit in the segment
1459 * descriptor is left as 1, although the whole segment has
1460 * been made unusable. Clear it here to pass an Intel VMX
1461 * entry check when cross vendor migrating.
1462 */
1463 if (var->unusable)
1464 var->db = 0;
1465 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1466 break;
1467 }
1468 }
1469
1470 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1471 {
1472 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1473
1474 return save->cpl;
1475 }
1476
1477 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1478 {
1479 struct vcpu_svm *svm = to_svm(vcpu);
1480
1481 dt->size = svm->vmcb->save.idtr.limit;
1482 dt->address = svm->vmcb->save.idtr.base;
1483 }
1484
1485 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1486 {
1487 struct vcpu_svm *svm = to_svm(vcpu);
1488
1489 svm->vmcb->save.idtr.limit = dt->size;
1490 svm->vmcb->save.idtr.base = dt->address ;
1491 mark_dirty(svm->vmcb, VMCB_DT);
1492 }
1493
1494 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1495 {
1496 struct vcpu_svm *svm = to_svm(vcpu);
1497
1498 dt->size = svm->vmcb->save.gdtr.limit;
1499 dt->address = svm->vmcb->save.gdtr.base;
1500 }
1501
1502 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1503 {
1504 struct vcpu_svm *svm = to_svm(vcpu);
1505
1506 svm->vmcb->save.gdtr.limit = dt->size;
1507 svm->vmcb->save.gdtr.base = dt->address ;
1508 mark_dirty(svm->vmcb, VMCB_DT);
1509 }
1510
1511 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1512 {
1513 }
1514
1515 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
1516 {
1517 }
1518
1519 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1520 {
1521 }
1522
1523 static void update_cr0_intercept(struct vcpu_svm *svm)
1524 {
1525 ulong gcr0 = svm->vcpu.arch.cr0;
1526 u64 *hcr0 = &svm->vmcb->save.cr0;
1527
1528 if (!svm->vcpu.fpu_active)
1529 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1530 else
1531 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1532 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1533
1534 mark_dirty(svm->vmcb, VMCB_CR);
1535
1536 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1537 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1538 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1539 } else {
1540 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1541 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1542 }
1543 }
1544
1545 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1546 {
1547 struct vcpu_svm *svm = to_svm(vcpu);
1548
1549 #ifdef CONFIG_X86_64
1550 if (vcpu->arch.efer & EFER_LME) {
1551 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1552 vcpu->arch.efer |= EFER_LMA;
1553 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1554 }
1555
1556 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1557 vcpu->arch.efer &= ~EFER_LMA;
1558 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1559 }
1560 }
1561 #endif
1562 vcpu->arch.cr0 = cr0;
1563
1564 if (!npt_enabled)
1565 cr0 |= X86_CR0_PG | X86_CR0_WP;
1566
1567 if (!vcpu->fpu_active)
1568 cr0 |= X86_CR0_TS;
1569 /*
1570 * re-enable caching here because the QEMU bios
1571 * does not do it - this results in some delay at
1572 * reboot
1573 */
1574 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1575 svm->vmcb->save.cr0 = cr0;
1576 mark_dirty(svm->vmcb, VMCB_CR);
1577 update_cr0_intercept(svm);
1578 }
1579
1580 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1581 {
1582 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1583 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1584
1585 if (cr4 & X86_CR4_VMXE)
1586 return 1;
1587
1588 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1589 svm_flush_tlb(vcpu);
1590
1591 vcpu->arch.cr4 = cr4;
1592 if (!npt_enabled)
1593 cr4 |= X86_CR4_PAE;
1594 cr4 |= host_cr4_mce;
1595 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1596 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1597 return 0;
1598 }
1599
1600 static void svm_set_segment(struct kvm_vcpu *vcpu,
1601 struct kvm_segment *var, int seg)
1602 {
1603 struct vcpu_svm *svm = to_svm(vcpu);
1604 struct vmcb_seg *s = svm_seg(vcpu, seg);
1605
1606 s->base = var->base;
1607 s->limit = var->limit;
1608 s->selector = var->selector;
1609 if (var->unusable)
1610 s->attrib = 0;
1611 else {
1612 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1613 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1614 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1615 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1616 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1617 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1618 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1619 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1620 }
1621
1622 /*
1623 * This is always accurate, except if SYSRET returned to a segment
1624 * with SS.DPL != 3. Intel does not have this quirk, and always
1625 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1626 * would entail passing the CPL to userspace and back.
1627 */
1628 if (seg == VCPU_SREG_SS)
1629 svm->vmcb->save.cpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1630
1631 mark_dirty(svm->vmcb, VMCB_SEG);
1632 }
1633
1634 static void update_db_bp_intercept(struct kvm_vcpu *vcpu)
1635 {
1636 struct vcpu_svm *svm = to_svm(vcpu);
1637
1638 clr_exception_intercept(svm, DB_VECTOR);
1639 clr_exception_intercept(svm, BP_VECTOR);
1640
1641 if (svm->nmi_singlestep)
1642 set_exception_intercept(svm, DB_VECTOR);
1643
1644 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1645 if (vcpu->guest_debug &
1646 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1647 set_exception_intercept(svm, DB_VECTOR);
1648 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1649 set_exception_intercept(svm, BP_VECTOR);
1650 } else
1651 vcpu->guest_debug = 0;
1652 }
1653
1654 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1655 {
1656 if (sd->next_asid > sd->max_asid) {
1657 ++sd->asid_generation;
1658 sd->next_asid = 1;
1659 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1660 }
1661
1662 svm->asid_generation = sd->asid_generation;
1663 svm->vmcb->control.asid = sd->next_asid++;
1664
1665 mark_dirty(svm->vmcb, VMCB_ASID);
1666 }
1667
1668 static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
1669 {
1670 return to_svm(vcpu)->vmcb->save.dr6;
1671 }
1672
1673 static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
1674 {
1675 struct vcpu_svm *svm = to_svm(vcpu);
1676
1677 svm->vmcb->save.dr6 = value;
1678 mark_dirty(svm->vmcb, VMCB_DR);
1679 }
1680
1681 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
1682 {
1683 struct vcpu_svm *svm = to_svm(vcpu);
1684
1685 get_debugreg(vcpu->arch.db[0], 0);
1686 get_debugreg(vcpu->arch.db[1], 1);
1687 get_debugreg(vcpu->arch.db[2], 2);
1688 get_debugreg(vcpu->arch.db[3], 3);
1689 vcpu->arch.dr6 = svm_get_dr6(vcpu);
1690 vcpu->arch.dr7 = svm->vmcb->save.dr7;
1691
1692 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
1693 set_dr_intercepts(svm);
1694 }
1695
1696 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1697 {
1698 struct vcpu_svm *svm = to_svm(vcpu);
1699
1700 svm->vmcb->save.dr7 = value;
1701 mark_dirty(svm->vmcb, VMCB_DR);
1702 }
1703
1704 static int pf_interception(struct vcpu_svm *svm)
1705 {
1706 u64 fault_address = svm->vmcb->control.exit_info_2;
1707 u32 error_code;
1708 int r = 1;
1709
1710 switch (svm->apf_reason) {
1711 default:
1712 error_code = svm->vmcb->control.exit_info_1;
1713
1714 trace_kvm_page_fault(fault_address, error_code);
1715 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1716 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1717 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
1718 svm->vmcb->control.insn_bytes,
1719 svm->vmcb->control.insn_len);
1720 break;
1721 case KVM_PV_REASON_PAGE_NOT_PRESENT:
1722 svm->apf_reason = 0;
1723 local_irq_disable();
1724 kvm_async_pf_task_wait(fault_address);
1725 local_irq_enable();
1726 break;
1727 case KVM_PV_REASON_PAGE_READY:
1728 svm->apf_reason = 0;
1729 local_irq_disable();
1730 kvm_async_pf_task_wake(fault_address);
1731 local_irq_enable();
1732 break;
1733 }
1734 return r;
1735 }
1736
1737 static int db_interception(struct vcpu_svm *svm)
1738 {
1739 struct kvm_run *kvm_run = svm->vcpu.run;
1740
1741 if (!(svm->vcpu.guest_debug &
1742 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1743 !svm->nmi_singlestep) {
1744 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1745 return 1;
1746 }
1747
1748 if (svm->nmi_singlestep) {
1749 svm->nmi_singlestep = false;
1750 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1751 svm->vmcb->save.rflags &=
1752 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1753 update_db_bp_intercept(&svm->vcpu);
1754 }
1755
1756 if (svm->vcpu.guest_debug &
1757 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1758 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1759 kvm_run->debug.arch.pc =
1760 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1761 kvm_run->debug.arch.exception = DB_VECTOR;
1762 return 0;
1763 }
1764
1765 return 1;
1766 }
1767
1768 static int bp_interception(struct vcpu_svm *svm)
1769 {
1770 struct kvm_run *kvm_run = svm->vcpu.run;
1771
1772 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1773 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1774 kvm_run->debug.arch.exception = BP_VECTOR;
1775 return 0;
1776 }
1777
1778 static int ud_interception(struct vcpu_svm *svm)
1779 {
1780 int er;
1781
1782 er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD);
1783 if (er != EMULATE_DONE)
1784 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1785 return 1;
1786 }
1787
1788 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1789 {
1790 struct vcpu_svm *svm = to_svm(vcpu);
1791
1792 clr_exception_intercept(svm, NM_VECTOR);
1793
1794 svm->vcpu.fpu_active = 1;
1795 update_cr0_intercept(svm);
1796 }
1797
1798 static int nm_interception(struct vcpu_svm *svm)
1799 {
1800 svm_fpu_activate(&svm->vcpu);
1801 return 1;
1802 }
1803
1804 static bool is_erratum_383(void)
1805 {
1806 int err, i;
1807 u64 value;
1808
1809 if (!erratum_383_found)
1810 return false;
1811
1812 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1813 if (err)
1814 return false;
1815
1816 /* Bit 62 may or may not be set for this mce */
1817 value &= ~(1ULL << 62);
1818
1819 if (value != 0xb600000000010015ULL)
1820 return false;
1821
1822 /* Clear MCi_STATUS registers */
1823 for (i = 0; i < 6; ++i)
1824 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1825
1826 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1827 if (!err) {
1828 u32 low, high;
1829
1830 value &= ~(1ULL << 2);
1831 low = lower_32_bits(value);
1832 high = upper_32_bits(value);
1833
1834 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1835 }
1836
1837 /* Flush tlb to evict multi-match entries */
1838 __flush_tlb_all();
1839
1840 return true;
1841 }
1842
1843 static void svm_handle_mce(struct vcpu_svm *svm)
1844 {
1845 if (is_erratum_383()) {
1846 /*
1847 * Erratum 383 triggered. Guest state is corrupt so kill the
1848 * guest.
1849 */
1850 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1851
1852 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1853
1854 return;
1855 }
1856
1857 /*
1858 * On an #MC intercept the MCE handler is not called automatically in
1859 * the host. So do it by hand here.
1860 */
1861 asm volatile (
1862 "int $0x12\n");
1863 /* not sure if we ever come back to this point */
1864
1865 return;
1866 }
1867
1868 static int mc_interception(struct vcpu_svm *svm)
1869 {
1870 return 1;
1871 }
1872
1873 static int shutdown_interception(struct vcpu_svm *svm)
1874 {
1875 struct kvm_run *kvm_run = svm->vcpu.run;
1876
1877 /*
1878 * VMCB is undefined after a SHUTDOWN intercept
1879 * so reinitialize it.
1880 */
1881 clear_page(svm->vmcb);
1882 init_vmcb(svm);
1883
1884 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1885 return 0;
1886 }
1887
1888 static int io_interception(struct vcpu_svm *svm)
1889 {
1890 struct kvm_vcpu *vcpu = &svm->vcpu;
1891 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1892 int size, in, string;
1893 unsigned port;
1894
1895 ++svm->vcpu.stat.io_exits;
1896 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1897 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1898 if (string || in)
1899 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
1900
1901 port = io_info >> 16;
1902 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1903 svm->next_rip = svm->vmcb->control.exit_info_2;
1904 skip_emulated_instruction(&svm->vcpu);
1905
1906 return kvm_fast_pio_out(vcpu, size, port);
1907 }
1908
1909 static int nmi_interception(struct vcpu_svm *svm)
1910 {
1911 return 1;
1912 }
1913
1914 static int intr_interception(struct vcpu_svm *svm)
1915 {
1916 ++svm->vcpu.stat.irq_exits;
1917 return 1;
1918 }
1919
1920 static int nop_on_interception(struct vcpu_svm *svm)
1921 {
1922 return 1;
1923 }
1924
1925 static int halt_interception(struct vcpu_svm *svm)
1926 {
1927 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1928 skip_emulated_instruction(&svm->vcpu);
1929 return kvm_emulate_halt(&svm->vcpu);
1930 }
1931
1932 static int vmmcall_interception(struct vcpu_svm *svm)
1933 {
1934 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1935 skip_emulated_instruction(&svm->vcpu);
1936 kvm_emulate_hypercall(&svm->vcpu);
1937 return 1;
1938 }
1939
1940 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1941 {
1942 struct vcpu_svm *svm = to_svm(vcpu);
1943
1944 return svm->nested.nested_cr3;
1945 }
1946
1947 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
1948 {
1949 struct vcpu_svm *svm = to_svm(vcpu);
1950 u64 cr3 = svm->nested.nested_cr3;
1951 u64 pdpte;
1952 int ret;
1953
1954 ret = kvm_read_guest_page(vcpu->kvm, gpa_to_gfn(cr3), &pdpte,
1955 offset_in_page(cr3) + index * 8, 8);
1956 if (ret)
1957 return 0;
1958 return pdpte;
1959 }
1960
1961 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1962 unsigned long root)
1963 {
1964 struct vcpu_svm *svm = to_svm(vcpu);
1965
1966 svm->vmcb->control.nested_cr3 = root;
1967 mark_dirty(svm->vmcb, VMCB_NPT);
1968 svm_flush_tlb(vcpu);
1969 }
1970
1971 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
1972 struct x86_exception *fault)
1973 {
1974 struct vcpu_svm *svm = to_svm(vcpu);
1975
1976 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1977 svm->vmcb->control.exit_code_hi = 0;
1978 svm->vmcb->control.exit_info_1 = fault->error_code;
1979 svm->vmcb->control.exit_info_2 = fault->address;
1980
1981 nested_svm_vmexit(svm);
1982 }
1983
1984 static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
1985 {
1986 kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu);
1987
1988 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
1989 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
1990 vcpu->arch.mmu.get_pdptr = nested_svm_get_tdp_pdptr;
1991 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
1992 vcpu->arch.mmu.shadow_root_level = get_npt_level();
1993 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
1994 }
1995
1996 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
1997 {
1998 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
1999 }
2000
2001 static int nested_svm_check_permissions(struct vcpu_svm *svm)
2002 {
2003 if (!(svm->vcpu.arch.efer & EFER_SVME)
2004 || !is_paging(&svm->vcpu)) {
2005 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2006 return 1;
2007 }
2008
2009 if (svm->vmcb->save.cpl) {
2010 kvm_inject_gp(&svm->vcpu, 0);
2011 return 1;
2012 }
2013
2014 return 0;
2015 }
2016
2017 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
2018 bool has_error_code, u32 error_code)
2019 {
2020 int vmexit;
2021
2022 if (!is_guest_mode(&svm->vcpu))
2023 return 0;
2024
2025 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
2026 svm->vmcb->control.exit_code_hi = 0;
2027 svm->vmcb->control.exit_info_1 = error_code;
2028 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
2029
2030 vmexit = nested_svm_intercept(svm);
2031 if (vmexit == NESTED_EXIT_DONE)
2032 svm->nested.exit_required = true;
2033
2034 return vmexit;
2035 }
2036
2037 /* This function returns true if it is save to enable the irq window */
2038 static inline bool nested_svm_intr(struct vcpu_svm *svm)
2039 {
2040 if (!is_guest_mode(&svm->vcpu))
2041 return true;
2042
2043 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2044 return true;
2045
2046 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
2047 return false;
2048
2049 /*
2050 * if vmexit was already requested (by intercepted exception
2051 * for instance) do not overwrite it with "external interrupt"
2052 * vmexit.
2053 */
2054 if (svm->nested.exit_required)
2055 return false;
2056
2057 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
2058 svm->vmcb->control.exit_info_1 = 0;
2059 svm->vmcb->control.exit_info_2 = 0;
2060
2061 if (svm->nested.intercept & 1ULL) {
2062 /*
2063 * The #vmexit can't be emulated here directly because this
2064 * code path runs with irqs and preemption disabled. A
2065 * #vmexit emulation might sleep. Only signal request for
2066 * the #vmexit here.
2067 */
2068 svm->nested.exit_required = true;
2069 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
2070 return false;
2071 }
2072
2073 return true;
2074 }
2075
2076 /* This function returns true if it is save to enable the nmi window */
2077 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
2078 {
2079 if (!is_guest_mode(&svm->vcpu))
2080 return true;
2081
2082 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
2083 return true;
2084
2085 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
2086 svm->nested.exit_required = true;
2087
2088 return false;
2089 }
2090
2091 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
2092 {
2093 struct page *page;
2094
2095 might_sleep();
2096
2097 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
2098 if (is_error_page(page))
2099 goto error;
2100
2101 *_page = page;
2102
2103 return kmap(page);
2104
2105 error:
2106 kvm_inject_gp(&svm->vcpu, 0);
2107
2108 return NULL;
2109 }
2110
2111 static void nested_svm_unmap(struct page *page)
2112 {
2113 kunmap(page);
2114 kvm_release_page_dirty(page);
2115 }
2116
2117 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
2118 {
2119 unsigned port, size, iopm_len;
2120 u16 val, mask;
2121 u8 start_bit;
2122 u64 gpa;
2123
2124 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
2125 return NESTED_EXIT_HOST;
2126
2127 port = svm->vmcb->control.exit_info_1 >> 16;
2128 size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >>
2129 SVM_IOIO_SIZE_SHIFT;
2130 gpa = svm->nested.vmcb_iopm + (port / 8);
2131 start_bit = port % 8;
2132 iopm_len = (start_bit + size > 8) ? 2 : 1;
2133 mask = (0xf >> (4 - size)) << start_bit;
2134 val = 0;
2135
2136 if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, iopm_len))
2137 return NESTED_EXIT_DONE;
2138
2139 return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2140 }
2141
2142 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
2143 {
2144 u32 offset, msr, value;
2145 int write, mask;
2146
2147 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2148 return NESTED_EXIT_HOST;
2149
2150 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2151 offset = svm_msrpm_offset(msr);
2152 write = svm->vmcb->control.exit_info_1 & 1;
2153 mask = 1 << ((2 * (msr & 0xf)) + write);
2154
2155 if (offset == MSR_INVALID)
2156 return NESTED_EXIT_DONE;
2157
2158 /* Offset is in 32 bit units but need in 8 bit units */
2159 offset *= 4;
2160
2161 if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
2162 return NESTED_EXIT_DONE;
2163
2164 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2165 }
2166
2167 static int nested_svm_exit_special(struct vcpu_svm *svm)
2168 {
2169 u32 exit_code = svm->vmcb->control.exit_code;
2170
2171 switch (exit_code) {
2172 case SVM_EXIT_INTR:
2173 case SVM_EXIT_NMI:
2174 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
2175 return NESTED_EXIT_HOST;
2176 case SVM_EXIT_NPF:
2177 /* For now we are always handling NPFs when using them */
2178 if (npt_enabled)
2179 return NESTED_EXIT_HOST;
2180 break;
2181 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
2182 /* When we're shadowing, trap PFs, but not async PF */
2183 if (!npt_enabled && svm->apf_reason == 0)
2184 return NESTED_EXIT_HOST;
2185 break;
2186 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
2187 nm_interception(svm);
2188 break;
2189 default:
2190 break;
2191 }
2192
2193 return NESTED_EXIT_CONTINUE;
2194 }
2195
2196 /*
2197 * If this function returns true, this #vmexit was already handled
2198 */
2199 static int nested_svm_intercept(struct vcpu_svm *svm)
2200 {
2201 u32 exit_code = svm->vmcb->control.exit_code;
2202 int vmexit = NESTED_EXIT_HOST;
2203
2204 switch (exit_code) {
2205 case SVM_EXIT_MSR:
2206 vmexit = nested_svm_exit_handled_msr(svm);
2207 break;
2208 case SVM_EXIT_IOIO:
2209 vmexit = nested_svm_intercept_ioio(svm);
2210 break;
2211 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2212 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2213 if (svm->nested.intercept_cr & bit)
2214 vmexit = NESTED_EXIT_DONE;
2215 break;
2216 }
2217 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2218 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2219 if (svm->nested.intercept_dr & bit)
2220 vmexit = NESTED_EXIT_DONE;
2221 break;
2222 }
2223 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2224 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2225 if (svm->nested.intercept_exceptions & excp_bits)
2226 vmexit = NESTED_EXIT_DONE;
2227 /* async page fault always cause vmexit */
2228 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2229 svm->apf_reason != 0)
2230 vmexit = NESTED_EXIT_DONE;
2231 break;
2232 }
2233 case SVM_EXIT_ERR: {
2234 vmexit = NESTED_EXIT_DONE;
2235 break;
2236 }
2237 default: {
2238 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2239 if (svm->nested.intercept & exit_bits)
2240 vmexit = NESTED_EXIT_DONE;
2241 }
2242 }
2243
2244 return vmexit;
2245 }
2246
2247 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2248 {
2249 int vmexit;
2250
2251 vmexit = nested_svm_intercept(svm);
2252
2253 if (vmexit == NESTED_EXIT_DONE)
2254 nested_svm_vmexit(svm);
2255
2256 return vmexit;
2257 }
2258
2259 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2260 {
2261 struct vmcb_control_area *dst = &dst_vmcb->control;
2262 struct vmcb_control_area *from = &from_vmcb->control;
2263
2264 dst->intercept_cr = from->intercept_cr;
2265 dst->intercept_dr = from->intercept_dr;
2266 dst->intercept_exceptions = from->intercept_exceptions;
2267 dst->intercept = from->intercept;
2268 dst->iopm_base_pa = from->iopm_base_pa;
2269 dst->msrpm_base_pa = from->msrpm_base_pa;
2270 dst->tsc_offset = from->tsc_offset;
2271 dst->asid = from->asid;
2272 dst->tlb_ctl = from->tlb_ctl;
2273 dst->int_ctl = from->int_ctl;
2274 dst->int_vector = from->int_vector;
2275 dst->int_state = from->int_state;
2276 dst->exit_code = from->exit_code;
2277 dst->exit_code_hi = from->exit_code_hi;
2278 dst->exit_info_1 = from->exit_info_1;
2279 dst->exit_info_2 = from->exit_info_2;
2280 dst->exit_int_info = from->exit_int_info;
2281 dst->exit_int_info_err = from->exit_int_info_err;
2282 dst->nested_ctl = from->nested_ctl;
2283 dst->event_inj = from->event_inj;
2284 dst->event_inj_err = from->event_inj_err;
2285 dst->nested_cr3 = from->nested_cr3;
2286 dst->lbr_ctl = from->lbr_ctl;
2287 }
2288
2289 static int nested_svm_vmexit(struct vcpu_svm *svm)
2290 {
2291 struct vmcb *nested_vmcb;
2292 struct vmcb *hsave = svm->nested.hsave;
2293 struct vmcb *vmcb = svm->vmcb;
2294 struct page *page;
2295
2296 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2297 vmcb->control.exit_info_1,
2298 vmcb->control.exit_info_2,
2299 vmcb->control.exit_int_info,
2300 vmcb->control.exit_int_info_err,
2301 KVM_ISA_SVM);
2302
2303 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2304 if (!nested_vmcb)
2305 return 1;
2306
2307 /* Exit Guest-Mode */
2308 leave_guest_mode(&svm->vcpu);
2309 svm->nested.vmcb = 0;
2310
2311 /* Give the current vmcb to the guest */
2312 disable_gif(svm);
2313
2314 nested_vmcb->save.es = vmcb->save.es;
2315 nested_vmcb->save.cs = vmcb->save.cs;
2316 nested_vmcb->save.ss = vmcb->save.ss;
2317 nested_vmcb->save.ds = vmcb->save.ds;
2318 nested_vmcb->save.gdtr = vmcb->save.gdtr;
2319 nested_vmcb->save.idtr = vmcb->save.idtr;
2320 nested_vmcb->save.efer = svm->vcpu.arch.efer;
2321 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2322 nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu);
2323 nested_vmcb->save.cr2 = vmcb->save.cr2;
2324 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
2325 nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
2326 nested_vmcb->save.rip = vmcb->save.rip;
2327 nested_vmcb->save.rsp = vmcb->save.rsp;
2328 nested_vmcb->save.rax = vmcb->save.rax;
2329 nested_vmcb->save.dr7 = vmcb->save.dr7;
2330 nested_vmcb->save.dr6 = vmcb->save.dr6;
2331 nested_vmcb->save.cpl = vmcb->save.cpl;
2332
2333 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
2334 nested_vmcb->control.int_vector = vmcb->control.int_vector;
2335 nested_vmcb->control.int_state = vmcb->control.int_state;
2336 nested_vmcb->control.exit_code = vmcb->control.exit_code;
2337 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
2338 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
2339 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
2340 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
2341 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2342 nested_vmcb->control.next_rip = vmcb->control.next_rip;
2343
2344 /*
2345 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2346 * to make sure that we do not lose injected events. So check event_inj
2347 * here and copy it to exit_int_info if it is valid.
2348 * Exit_int_info and event_inj can't be both valid because the case
2349 * below only happens on a VMRUN instruction intercept which has
2350 * no valid exit_int_info set.
2351 */
2352 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2353 struct vmcb_control_area *nc = &nested_vmcb->control;
2354
2355 nc->exit_int_info = vmcb->control.event_inj;
2356 nc->exit_int_info_err = vmcb->control.event_inj_err;
2357 }
2358
2359 nested_vmcb->control.tlb_ctl = 0;
2360 nested_vmcb->control.event_inj = 0;
2361 nested_vmcb->control.event_inj_err = 0;
2362
2363 /* We always set V_INTR_MASKING and remember the old value in hflags */
2364 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2365 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2366
2367 /* Restore the original control entries */
2368 copy_vmcb_control_area(vmcb, hsave);
2369
2370 kvm_clear_exception_queue(&svm->vcpu);
2371 kvm_clear_interrupt_queue(&svm->vcpu);
2372
2373 svm->nested.nested_cr3 = 0;
2374
2375 /* Restore selected save entries */
2376 svm->vmcb->save.es = hsave->save.es;
2377 svm->vmcb->save.cs = hsave->save.cs;
2378 svm->vmcb->save.ss = hsave->save.ss;
2379 svm->vmcb->save.ds = hsave->save.ds;
2380 svm->vmcb->save.gdtr = hsave->save.gdtr;
2381 svm->vmcb->save.idtr = hsave->save.idtr;
2382 kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
2383 svm_set_efer(&svm->vcpu, hsave->save.efer);
2384 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2385 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2386 if (npt_enabled) {
2387 svm->vmcb->save.cr3 = hsave->save.cr3;
2388 svm->vcpu.arch.cr3 = hsave->save.cr3;
2389 } else {
2390 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2391 }
2392 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2393 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2394 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2395 svm->vmcb->save.dr7 = 0;
2396 svm->vmcb->save.cpl = 0;
2397 svm->vmcb->control.exit_int_info = 0;
2398
2399 mark_all_dirty(svm->vmcb);
2400
2401 nested_svm_unmap(page);
2402
2403 nested_svm_uninit_mmu_context(&svm->vcpu);
2404 kvm_mmu_reset_context(&svm->vcpu);
2405 kvm_mmu_load(&svm->vcpu);
2406
2407 return 0;
2408 }
2409
2410 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2411 {
2412 /*
2413 * This function merges the msr permission bitmaps of kvm and the
2414 * nested vmcb. It is optimized in that it only merges the parts where
2415 * the kvm msr permission bitmap may contain zero bits
2416 */
2417 int i;
2418
2419 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2420 return true;
2421
2422 for (i = 0; i < MSRPM_OFFSETS; i++) {
2423 u32 value, p;
2424 u64 offset;
2425
2426 if (msrpm_offsets[i] == 0xffffffff)
2427 break;
2428
2429 p = msrpm_offsets[i];
2430 offset = svm->nested.vmcb_msrpm + (p * 4);
2431
2432 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2433 return false;
2434
2435 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2436 }
2437
2438 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2439
2440 return true;
2441 }
2442
2443 static bool nested_vmcb_checks(struct vmcb *vmcb)
2444 {
2445 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2446 return false;
2447
2448 if (vmcb->control.asid == 0)
2449 return false;
2450
2451 if (vmcb->control.nested_ctl && !npt_enabled)
2452 return false;
2453
2454 return true;
2455 }
2456
2457 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2458 {
2459 struct vmcb *nested_vmcb;
2460 struct vmcb *hsave = svm->nested.hsave;
2461 struct vmcb *vmcb = svm->vmcb;
2462 struct page *page;
2463 u64 vmcb_gpa;
2464
2465 vmcb_gpa = svm->vmcb->save.rax;
2466
2467 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2468 if (!nested_vmcb)
2469 return false;
2470
2471 if (!nested_vmcb_checks(nested_vmcb)) {
2472 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2473 nested_vmcb->control.exit_code_hi = 0;
2474 nested_vmcb->control.exit_info_1 = 0;
2475 nested_vmcb->control.exit_info_2 = 0;
2476
2477 nested_svm_unmap(page);
2478
2479 return false;
2480 }
2481
2482 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2483 nested_vmcb->save.rip,
2484 nested_vmcb->control.int_ctl,
2485 nested_vmcb->control.event_inj,
2486 nested_vmcb->control.nested_ctl);
2487
2488 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2489 nested_vmcb->control.intercept_cr >> 16,
2490 nested_vmcb->control.intercept_exceptions,
2491 nested_vmcb->control.intercept);
2492
2493 /* Clear internal status */
2494 kvm_clear_exception_queue(&svm->vcpu);
2495 kvm_clear_interrupt_queue(&svm->vcpu);
2496
2497 /*
2498 * Save the old vmcb, so we don't need to pick what we save, but can
2499 * restore everything when a VMEXIT occurs
2500 */
2501 hsave->save.es = vmcb->save.es;
2502 hsave->save.cs = vmcb->save.cs;
2503 hsave->save.ss = vmcb->save.ss;
2504 hsave->save.ds = vmcb->save.ds;
2505 hsave->save.gdtr = vmcb->save.gdtr;
2506 hsave->save.idtr = vmcb->save.idtr;
2507 hsave->save.efer = svm->vcpu.arch.efer;
2508 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
2509 hsave->save.cr4 = svm->vcpu.arch.cr4;
2510 hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
2511 hsave->save.rip = kvm_rip_read(&svm->vcpu);
2512 hsave->save.rsp = vmcb->save.rsp;
2513 hsave->save.rax = vmcb->save.rax;
2514 if (npt_enabled)
2515 hsave->save.cr3 = vmcb->save.cr3;
2516 else
2517 hsave->save.cr3 = kvm_read_cr3(&svm->vcpu);
2518
2519 copy_vmcb_control_area(hsave, vmcb);
2520
2521 if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
2522 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2523 else
2524 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2525
2526 if (nested_vmcb->control.nested_ctl) {
2527 kvm_mmu_unload(&svm->vcpu);
2528 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2529 nested_svm_init_mmu_context(&svm->vcpu);
2530 }
2531
2532 /* Load the nested guest state */
2533 svm->vmcb->save.es = nested_vmcb->save.es;
2534 svm->vmcb->save.cs = nested_vmcb->save.cs;
2535 svm->vmcb->save.ss = nested_vmcb->save.ss;
2536 svm->vmcb->save.ds = nested_vmcb->save.ds;
2537 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2538 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2539 kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
2540 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2541 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2542 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2543 if (npt_enabled) {
2544 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2545 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2546 } else
2547 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2548
2549 /* Guest paging mode is active - reset mmu */
2550 kvm_mmu_reset_context(&svm->vcpu);
2551
2552 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2553 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2554 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2555 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2556
2557 /* In case we don't even reach vcpu_run, the fields are not updated */
2558 svm->vmcb->save.rax = nested_vmcb->save.rax;
2559 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2560 svm->vmcb->save.rip = nested_vmcb->save.rip;
2561 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2562 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2563 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2564
2565 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2566 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
2567
2568 /* cache intercepts */
2569 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
2570 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
2571 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2572 svm->nested.intercept = nested_vmcb->control.intercept;
2573
2574 svm_flush_tlb(&svm->vcpu);
2575 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2576 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2577 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2578 else
2579 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2580
2581 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2582 /* We only want the cr8 intercept bits of the guest */
2583 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2584 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2585 }
2586
2587 /* We don't want to see VMMCALLs from a nested guest */
2588 clr_intercept(svm, INTERCEPT_VMMCALL);
2589
2590 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2591 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2592 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2593 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2594 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2595 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2596
2597 nested_svm_unmap(page);
2598
2599 /* Enter Guest-Mode */
2600 enter_guest_mode(&svm->vcpu);
2601
2602 /*
2603 * Merge guest and host intercepts - must be called with vcpu in
2604 * guest-mode to take affect here
2605 */
2606 recalc_intercepts(svm);
2607
2608 svm->nested.vmcb = vmcb_gpa;
2609
2610 enable_gif(svm);
2611
2612 mark_all_dirty(svm->vmcb);
2613
2614 return true;
2615 }
2616
2617 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2618 {
2619 to_vmcb->save.fs = from_vmcb->save.fs;
2620 to_vmcb->save.gs = from_vmcb->save.gs;
2621 to_vmcb->save.tr = from_vmcb->save.tr;
2622 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2623 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2624 to_vmcb->save.star = from_vmcb->save.star;
2625 to_vmcb->save.lstar = from_vmcb->save.lstar;
2626 to_vmcb->save.cstar = from_vmcb->save.cstar;
2627 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2628 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2629 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2630 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2631 }
2632
2633 static int vmload_interception(struct vcpu_svm *svm)
2634 {
2635 struct vmcb *nested_vmcb;
2636 struct page *page;
2637
2638 if (nested_svm_check_permissions(svm))
2639 return 1;
2640
2641 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2642 if (!nested_vmcb)
2643 return 1;
2644
2645 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2646 skip_emulated_instruction(&svm->vcpu);
2647
2648 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2649 nested_svm_unmap(page);
2650
2651 return 1;
2652 }
2653
2654 static int vmsave_interception(struct vcpu_svm *svm)
2655 {
2656 struct vmcb *nested_vmcb;
2657 struct page *page;
2658
2659 if (nested_svm_check_permissions(svm))
2660 return 1;
2661
2662 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2663 if (!nested_vmcb)
2664 return 1;
2665
2666 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2667 skip_emulated_instruction(&svm->vcpu);
2668
2669 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2670 nested_svm_unmap(page);
2671
2672 return 1;
2673 }
2674
2675 static int vmrun_interception(struct vcpu_svm *svm)
2676 {
2677 if (nested_svm_check_permissions(svm))
2678 return 1;
2679
2680 /* Save rip after vmrun instruction */
2681 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
2682
2683 if (!nested_svm_vmrun(svm))
2684 return 1;
2685
2686 if (!nested_svm_vmrun_msrpm(svm))
2687 goto failed;
2688
2689 return 1;
2690
2691 failed:
2692
2693 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2694 svm->vmcb->control.exit_code_hi = 0;
2695 svm->vmcb->control.exit_info_1 = 0;
2696 svm->vmcb->control.exit_info_2 = 0;
2697
2698 nested_svm_vmexit(svm);
2699
2700 return 1;
2701 }
2702
2703 static int stgi_interception(struct vcpu_svm *svm)
2704 {
2705 if (nested_svm_check_permissions(svm))
2706 return 1;
2707
2708 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2709 skip_emulated_instruction(&svm->vcpu);
2710 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2711
2712 enable_gif(svm);
2713
2714 return 1;
2715 }
2716
2717 static int clgi_interception(struct vcpu_svm *svm)
2718 {
2719 if (nested_svm_check_permissions(svm))
2720 return 1;
2721
2722 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2723 skip_emulated_instruction(&svm->vcpu);
2724
2725 disable_gif(svm);
2726
2727 /* After a CLGI no interrupts should come */
2728 svm_clear_vintr(svm);
2729 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2730
2731 mark_dirty(svm->vmcb, VMCB_INTR);
2732
2733 return 1;
2734 }
2735
2736 static int invlpga_interception(struct vcpu_svm *svm)
2737 {
2738 struct kvm_vcpu *vcpu = &svm->vcpu;
2739
2740 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2741 vcpu->arch.regs[VCPU_REGS_RAX]);
2742
2743 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2744 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2745
2746 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2747 skip_emulated_instruction(&svm->vcpu);
2748 return 1;
2749 }
2750
2751 static int skinit_interception(struct vcpu_svm *svm)
2752 {
2753 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2754
2755 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2756 return 1;
2757 }
2758
2759 static int xsetbv_interception(struct vcpu_svm *svm)
2760 {
2761 u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
2762 u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
2763
2764 if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
2765 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2766 skip_emulated_instruction(&svm->vcpu);
2767 }
2768
2769 return 1;
2770 }
2771
2772 static int task_switch_interception(struct vcpu_svm *svm)
2773 {
2774 u16 tss_selector;
2775 int reason;
2776 int int_type = svm->vmcb->control.exit_int_info &
2777 SVM_EXITINTINFO_TYPE_MASK;
2778 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2779 uint32_t type =
2780 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2781 uint32_t idt_v =
2782 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2783 bool has_error_code = false;
2784 u32 error_code = 0;
2785
2786 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2787
2788 if (svm->vmcb->control.exit_info_2 &
2789 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2790 reason = TASK_SWITCH_IRET;
2791 else if (svm->vmcb->control.exit_info_2 &
2792 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2793 reason = TASK_SWITCH_JMP;
2794 else if (idt_v)
2795 reason = TASK_SWITCH_GATE;
2796 else
2797 reason = TASK_SWITCH_CALL;
2798
2799 if (reason == TASK_SWITCH_GATE) {
2800 switch (type) {
2801 case SVM_EXITINTINFO_TYPE_NMI:
2802 svm->vcpu.arch.nmi_injected = false;
2803 break;
2804 case SVM_EXITINTINFO_TYPE_EXEPT:
2805 if (svm->vmcb->control.exit_info_2 &
2806 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2807 has_error_code = true;
2808 error_code =
2809 (u32)svm->vmcb->control.exit_info_2;
2810 }
2811 kvm_clear_exception_queue(&svm->vcpu);
2812 break;
2813 case SVM_EXITINTINFO_TYPE_INTR:
2814 kvm_clear_interrupt_queue(&svm->vcpu);
2815 break;
2816 default:
2817 break;
2818 }
2819 }
2820
2821 if (reason != TASK_SWITCH_GATE ||
2822 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2823 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2824 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2825 skip_emulated_instruction(&svm->vcpu);
2826
2827 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2828 int_vec = -1;
2829
2830 if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
2831 has_error_code, error_code) == EMULATE_FAIL) {
2832 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2833 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2834 svm->vcpu.run->internal.ndata = 0;
2835 return 0;
2836 }
2837 return 1;
2838 }
2839
2840 static int cpuid_interception(struct vcpu_svm *svm)
2841 {
2842 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2843 kvm_emulate_cpuid(&svm->vcpu);
2844 return 1;
2845 }
2846
2847 static int iret_interception(struct vcpu_svm *svm)
2848 {
2849 ++svm->vcpu.stat.nmi_window_exits;
2850 clr_intercept(svm, INTERCEPT_IRET);
2851 svm->vcpu.arch.hflags |= HF_IRET_MASK;
2852 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
2853 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2854 return 1;
2855 }
2856
2857 static int invlpg_interception(struct vcpu_svm *svm)
2858 {
2859 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2860 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2861
2862 kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
2863 skip_emulated_instruction(&svm->vcpu);
2864 return 1;
2865 }
2866
2867 static int emulate_on_interception(struct vcpu_svm *svm)
2868 {
2869 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2870 }
2871
2872 static int rdpmc_interception(struct vcpu_svm *svm)
2873 {
2874 int err;
2875
2876 if (!static_cpu_has(X86_FEATURE_NRIPS))
2877 return emulate_on_interception(svm);
2878
2879 err = kvm_rdpmc(&svm->vcpu);
2880 kvm_complete_insn_gp(&svm->vcpu, err);
2881
2882 return 1;
2883 }
2884
2885 bool check_selective_cr0_intercepted(struct vcpu_svm *svm, unsigned long val)
2886 {
2887 unsigned long cr0 = svm->vcpu.arch.cr0;
2888 bool ret = false;
2889 u64 intercept;
2890
2891 intercept = svm->nested.intercept;
2892
2893 if (!is_guest_mode(&svm->vcpu) ||
2894 (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
2895 return false;
2896
2897 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2898 val &= ~SVM_CR0_SELECTIVE_MASK;
2899
2900 if (cr0 ^ val) {
2901 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2902 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2903 }
2904
2905 return ret;
2906 }
2907
2908 #define CR_VALID (1ULL << 63)
2909
2910 static int cr_interception(struct vcpu_svm *svm)
2911 {
2912 int reg, cr;
2913 unsigned long val;
2914 int err;
2915
2916 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2917 return emulate_on_interception(svm);
2918
2919 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2920 return emulate_on_interception(svm);
2921
2922 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2923 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2924
2925 err = 0;
2926 if (cr >= 16) { /* mov to cr */
2927 cr -= 16;
2928 val = kvm_register_read(&svm->vcpu, reg);
2929 switch (cr) {
2930 case 0:
2931 if (!check_selective_cr0_intercepted(svm, val))
2932 err = kvm_set_cr0(&svm->vcpu, val);
2933 else
2934 return 1;
2935
2936 break;
2937 case 3:
2938 err = kvm_set_cr3(&svm->vcpu, val);
2939 break;
2940 case 4:
2941 err = kvm_set_cr4(&svm->vcpu, val);
2942 break;
2943 case 8:
2944 err = kvm_set_cr8(&svm->vcpu, val);
2945 break;
2946 default:
2947 WARN(1, "unhandled write to CR%d", cr);
2948 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2949 return 1;
2950 }
2951 } else { /* mov from cr */
2952 switch (cr) {
2953 case 0:
2954 val = kvm_read_cr0(&svm->vcpu);
2955 break;
2956 case 2:
2957 val = svm->vcpu.arch.cr2;
2958 break;
2959 case 3:
2960 val = kvm_read_cr3(&svm->vcpu);
2961 break;
2962 case 4:
2963 val = kvm_read_cr4(&svm->vcpu);
2964 break;
2965 case 8:
2966 val = kvm_get_cr8(&svm->vcpu);
2967 break;
2968 default:
2969 WARN(1, "unhandled read from CR%d", cr);
2970 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2971 return 1;
2972 }
2973 kvm_register_write(&svm->vcpu, reg, val);
2974 }
2975 kvm_complete_insn_gp(&svm->vcpu, err);
2976
2977 return 1;
2978 }
2979
2980 static int dr_interception(struct vcpu_svm *svm)
2981 {
2982 int reg, dr;
2983 unsigned long val;
2984 int err;
2985
2986 if (svm->vcpu.guest_debug == 0) {
2987 /*
2988 * No more DR vmexits; force a reload of the debug registers
2989 * and reenter on this instruction. The next vmexit will
2990 * retrieve the full state of the debug registers.
2991 */
2992 clr_dr_intercepts(svm);
2993 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
2994 return 1;
2995 }
2996
2997 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2998 return emulate_on_interception(svm);
2999
3000 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3001 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
3002
3003 if (dr >= 16) { /* mov to DRn */
3004 val = kvm_register_read(&svm->vcpu, reg);
3005 kvm_set_dr(&svm->vcpu, dr - 16, val);
3006 } else {
3007 err = kvm_get_dr(&svm->vcpu, dr, &val);
3008 if (!err)
3009 kvm_register_write(&svm->vcpu, reg, val);
3010 }
3011
3012 skip_emulated_instruction(&svm->vcpu);
3013
3014 return 1;
3015 }
3016
3017 static int cr8_write_interception(struct vcpu_svm *svm)
3018 {
3019 struct kvm_run *kvm_run = svm->vcpu.run;
3020 int r;
3021
3022 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
3023 /* instruction emulation calls kvm_set_cr8() */
3024 r = cr_interception(svm);
3025 if (irqchip_in_kernel(svm->vcpu.kvm))
3026 return r;
3027 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
3028 return r;
3029 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
3030 return 0;
3031 }
3032
3033 u64 svm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
3034 {
3035 struct vmcb *vmcb = get_host_vmcb(to_svm(vcpu));
3036 return vmcb->control.tsc_offset +
3037 svm_scale_tsc(vcpu, host_tsc);
3038 }
3039
3040 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
3041 {
3042 struct vcpu_svm *svm = to_svm(vcpu);
3043
3044 switch (ecx) {
3045 case MSR_IA32_TSC: {
3046 *data = svm->vmcb->control.tsc_offset +
3047 svm_scale_tsc(vcpu, native_read_tsc());
3048
3049 break;
3050 }
3051 case MSR_STAR:
3052 *data = svm->vmcb->save.star;
3053 break;
3054 #ifdef CONFIG_X86_64
3055 case MSR_LSTAR:
3056 *data = svm->vmcb->save.lstar;
3057 break;
3058 case MSR_CSTAR:
3059 *data = svm->vmcb->save.cstar;
3060 break;
3061 case MSR_KERNEL_GS_BASE:
3062 *data = svm->vmcb->save.kernel_gs_base;
3063 break;
3064 case MSR_SYSCALL_MASK:
3065 *data = svm->vmcb->save.sfmask;
3066 break;
3067 #endif
3068 case MSR_IA32_SYSENTER_CS:
3069 *data = svm->vmcb->save.sysenter_cs;
3070 break;
3071 case MSR_IA32_SYSENTER_EIP:
3072 *data = svm->sysenter_eip;
3073 break;
3074 case MSR_IA32_SYSENTER_ESP:
3075 *data = svm->sysenter_esp;
3076 break;
3077 /*
3078 * Nobody will change the following 5 values in the VMCB so we can
3079 * safely return them on rdmsr. They will always be 0 until LBRV is
3080 * implemented.
3081 */
3082 case MSR_IA32_DEBUGCTLMSR:
3083 *data = svm->vmcb->save.dbgctl;
3084 break;
3085 case MSR_IA32_LASTBRANCHFROMIP:
3086 *data = svm->vmcb->save.br_from;
3087 break;
3088 case MSR_IA32_LASTBRANCHTOIP:
3089 *data = svm->vmcb->save.br_to;
3090 break;
3091 case MSR_IA32_LASTINTFROMIP:
3092 *data = svm->vmcb->save.last_excp_from;
3093 break;
3094 case MSR_IA32_LASTINTTOIP:
3095 *data = svm->vmcb->save.last_excp_to;
3096 break;
3097 case MSR_VM_HSAVE_PA:
3098 *data = svm->nested.hsave_msr;
3099 break;
3100 case MSR_VM_CR:
3101 *data = svm->nested.vm_cr_msr;
3102 break;
3103 case MSR_IA32_UCODE_REV:
3104 *data = 0x01000065;
3105 break;
3106 default:
3107 return kvm_get_msr_common(vcpu, ecx, data);
3108 }
3109 return 0;
3110 }
3111
3112 static int rdmsr_interception(struct vcpu_svm *svm)
3113 {
3114 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3115 u64 data;
3116
3117 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
3118 trace_kvm_msr_read_ex(ecx);
3119 kvm_inject_gp(&svm->vcpu, 0);
3120 } else {
3121 trace_kvm_msr_read(ecx, data);
3122
3123 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
3124 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
3125 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3126 skip_emulated_instruction(&svm->vcpu);
3127 }
3128 return 1;
3129 }
3130
3131 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
3132 {
3133 struct vcpu_svm *svm = to_svm(vcpu);
3134 int svm_dis, chg_mask;
3135
3136 if (data & ~SVM_VM_CR_VALID_MASK)
3137 return 1;
3138
3139 chg_mask = SVM_VM_CR_VALID_MASK;
3140
3141 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
3142 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
3143
3144 svm->nested.vm_cr_msr &= ~chg_mask;
3145 svm->nested.vm_cr_msr |= (data & chg_mask);
3146
3147 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
3148
3149 /* check for svm_disable while efer.svme is set */
3150 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
3151 return 1;
3152
3153 return 0;
3154 }
3155
3156 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
3157 {
3158 struct vcpu_svm *svm = to_svm(vcpu);
3159
3160 u32 ecx = msr->index;
3161 u64 data = msr->data;
3162 switch (ecx) {
3163 case MSR_IA32_TSC:
3164 kvm_write_tsc(vcpu, msr);
3165 break;
3166 case MSR_STAR:
3167 svm->vmcb->save.star = data;
3168 break;
3169 #ifdef CONFIG_X86_64
3170 case MSR_LSTAR:
3171 svm->vmcb->save.lstar = data;
3172 break;
3173 case MSR_CSTAR:
3174 svm->vmcb->save.cstar = data;
3175 break;
3176 case MSR_KERNEL_GS_BASE:
3177 svm->vmcb->save.kernel_gs_base = data;
3178 break;
3179 case MSR_SYSCALL_MASK:
3180 svm->vmcb->save.sfmask = data;
3181 break;
3182 #endif
3183 case MSR_IA32_SYSENTER_CS:
3184 svm->vmcb->save.sysenter_cs = data;
3185 break;
3186 case MSR_IA32_SYSENTER_EIP:
3187 svm->sysenter_eip = data;
3188 svm->vmcb->save.sysenter_eip = data;
3189 break;
3190 case MSR_IA32_SYSENTER_ESP:
3191 svm->sysenter_esp = data;
3192 svm->vmcb->save.sysenter_esp = data;
3193 break;
3194 case MSR_IA32_DEBUGCTLMSR:
3195 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
3196 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3197 __func__, data);
3198 break;
3199 }
3200 if (data & DEBUGCTL_RESERVED_BITS)
3201 return 1;
3202
3203 svm->vmcb->save.dbgctl = data;
3204 mark_dirty(svm->vmcb, VMCB_LBR);
3205 if (data & (1ULL<<0))
3206 svm_enable_lbrv(svm);
3207 else
3208 svm_disable_lbrv(svm);
3209 break;
3210 case MSR_VM_HSAVE_PA:
3211 svm->nested.hsave_msr = data;
3212 break;
3213 case MSR_VM_CR:
3214 return svm_set_vm_cr(vcpu, data);
3215 case MSR_VM_IGNNE:
3216 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3217 break;
3218 default:
3219 return kvm_set_msr_common(vcpu, msr);
3220 }
3221 return 0;
3222 }
3223
3224 static int wrmsr_interception(struct vcpu_svm *svm)
3225 {
3226 struct msr_data msr;
3227 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3228 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
3229 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3230
3231 msr.data = data;
3232 msr.index = ecx;
3233 msr.host_initiated = false;
3234
3235 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3236 if (svm_set_msr(&svm->vcpu, &msr)) {
3237 trace_kvm_msr_write_ex(ecx, data);
3238 kvm_inject_gp(&svm->vcpu, 0);
3239 } else {
3240 trace_kvm_msr_write(ecx, data);
3241 skip_emulated_instruction(&svm->vcpu);
3242 }
3243 return 1;
3244 }
3245
3246 static int msr_interception(struct vcpu_svm *svm)
3247 {
3248 if (svm->vmcb->control.exit_info_1)
3249 return wrmsr_interception(svm);
3250 else
3251 return rdmsr_interception(svm);
3252 }
3253
3254 static int interrupt_window_interception(struct vcpu_svm *svm)
3255 {
3256 struct kvm_run *kvm_run = svm->vcpu.run;
3257
3258 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3259 svm_clear_vintr(svm);
3260 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3261 mark_dirty(svm->vmcb, VMCB_INTR);
3262 ++svm->vcpu.stat.irq_window_exits;
3263 /*
3264 * If the user space waits to inject interrupts, exit as soon as
3265 * possible
3266 */
3267 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
3268 kvm_run->request_interrupt_window &&
3269 !kvm_cpu_has_interrupt(&svm->vcpu)) {
3270 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3271 return 0;
3272 }
3273
3274 return 1;
3275 }
3276
3277 static int pause_interception(struct vcpu_svm *svm)
3278 {
3279 kvm_vcpu_on_spin(&(svm->vcpu));
3280 return 1;
3281 }
3282
3283 static int nop_interception(struct vcpu_svm *svm)
3284 {
3285 skip_emulated_instruction(&(svm->vcpu));
3286 return 1;
3287 }
3288
3289 static int monitor_interception(struct vcpu_svm *svm)
3290 {
3291 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
3292 return nop_interception(svm);
3293 }
3294
3295 static int mwait_interception(struct vcpu_svm *svm)
3296 {
3297 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
3298 return nop_interception(svm);
3299 }
3300
3301 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
3302 [SVM_EXIT_READ_CR0] = cr_interception,
3303 [SVM_EXIT_READ_CR3] = cr_interception,
3304 [SVM_EXIT_READ_CR4] = cr_interception,
3305 [SVM_EXIT_READ_CR8] = cr_interception,
3306 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
3307 [SVM_EXIT_WRITE_CR0] = cr_interception,
3308 [SVM_EXIT_WRITE_CR3] = cr_interception,
3309 [SVM_EXIT_WRITE_CR4] = cr_interception,
3310 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
3311 [SVM_EXIT_READ_DR0] = dr_interception,
3312 [SVM_EXIT_READ_DR1] = dr_interception,
3313 [SVM_EXIT_READ_DR2] = dr_interception,
3314 [SVM_EXIT_READ_DR3] = dr_interception,
3315 [SVM_EXIT_READ_DR4] = dr_interception,
3316 [SVM_EXIT_READ_DR5] = dr_interception,
3317 [SVM_EXIT_READ_DR6] = dr_interception,
3318 [SVM_EXIT_READ_DR7] = dr_interception,
3319 [SVM_EXIT_WRITE_DR0] = dr_interception,
3320 [SVM_EXIT_WRITE_DR1] = dr_interception,
3321 [SVM_EXIT_WRITE_DR2] = dr_interception,
3322 [SVM_EXIT_WRITE_DR3] = dr_interception,
3323 [SVM_EXIT_WRITE_DR4] = dr_interception,
3324 [SVM_EXIT_WRITE_DR5] = dr_interception,
3325 [SVM_EXIT_WRITE_DR6] = dr_interception,
3326 [SVM_EXIT_WRITE_DR7] = dr_interception,
3327 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
3328 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
3329 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
3330 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
3331 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
3332 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
3333 [SVM_EXIT_INTR] = intr_interception,
3334 [SVM_EXIT_NMI] = nmi_interception,
3335 [SVM_EXIT_SMI] = nop_on_interception,
3336 [SVM_EXIT_INIT] = nop_on_interception,
3337 [SVM_EXIT_VINTR] = interrupt_window_interception,
3338 [SVM_EXIT_RDPMC] = rdpmc_interception,
3339 [SVM_EXIT_CPUID] = cpuid_interception,
3340 [SVM_EXIT_IRET] = iret_interception,
3341 [SVM_EXIT_INVD] = emulate_on_interception,
3342 [SVM_EXIT_PAUSE] = pause_interception,
3343 [SVM_EXIT_HLT] = halt_interception,
3344 [SVM_EXIT_INVLPG] = invlpg_interception,
3345 [SVM_EXIT_INVLPGA] = invlpga_interception,
3346 [SVM_EXIT_IOIO] = io_interception,
3347 [SVM_EXIT_MSR] = msr_interception,
3348 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
3349 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3350 [SVM_EXIT_VMRUN] = vmrun_interception,
3351 [SVM_EXIT_VMMCALL] = vmmcall_interception,
3352 [SVM_EXIT_VMLOAD] = vmload_interception,
3353 [SVM_EXIT_VMSAVE] = vmsave_interception,
3354 [SVM_EXIT_STGI] = stgi_interception,
3355 [SVM_EXIT_CLGI] = clgi_interception,
3356 [SVM_EXIT_SKINIT] = skinit_interception,
3357 [SVM_EXIT_WBINVD] = emulate_on_interception,
3358 [SVM_EXIT_MONITOR] = monitor_interception,
3359 [SVM_EXIT_MWAIT] = mwait_interception,
3360 [SVM_EXIT_XSETBV] = xsetbv_interception,
3361 [SVM_EXIT_NPF] = pf_interception,
3362 };
3363
3364 static void dump_vmcb(struct kvm_vcpu *vcpu)
3365 {
3366 struct vcpu_svm *svm = to_svm(vcpu);
3367 struct vmcb_control_area *control = &svm->vmcb->control;
3368 struct vmcb_save_area *save = &svm->vmcb->save;
3369
3370 pr_err("VMCB Control Area:\n");
3371 pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
3372 pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
3373 pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
3374 pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
3375 pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
3376 pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
3377 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
3378 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
3379 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
3380 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
3381 pr_err("%-20s%d\n", "asid:", control->asid);
3382 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
3383 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
3384 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
3385 pr_err("%-20s%08x\n", "int_state:", control->int_state);
3386 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
3387 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
3388 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
3389 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
3390 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
3391 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
3392 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
3393 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
3394 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
3395 pr_err("%-20s%lld\n", "lbr_ctl:", control->lbr_ctl);
3396 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
3397 pr_err("VMCB State Save Area:\n");
3398 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3399 "es:",
3400 save->es.selector, save->es.attrib,
3401 save->es.limit, save->es.base);
3402 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3403 "cs:",
3404 save->cs.selector, save->cs.attrib,
3405 save->cs.limit, save->cs.base);
3406 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3407 "ss:",
3408 save->ss.selector, save->ss.attrib,
3409 save->ss.limit, save->ss.base);
3410 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3411 "ds:",
3412 save->ds.selector, save->ds.attrib,
3413 save->ds.limit, save->ds.base);
3414 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3415 "fs:",
3416 save->fs.selector, save->fs.attrib,
3417 save->fs.limit, save->fs.base);
3418 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3419 "gs:",
3420 save->gs.selector, save->gs.attrib,
3421 save->gs.limit, save->gs.base);
3422 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3423 "gdtr:",
3424 save->gdtr.selector, save->gdtr.attrib,
3425 save->gdtr.limit, save->gdtr.base);
3426 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3427 "ldtr:",
3428 save->ldtr.selector, save->ldtr.attrib,
3429 save->ldtr.limit, save->ldtr.base);
3430 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3431 "idtr:",
3432 save->idtr.selector, save->idtr.attrib,
3433 save->idtr.limit, save->idtr.base);
3434 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3435 "tr:",
3436 save->tr.selector, save->tr.attrib,
3437 save->tr.limit, save->tr.base);
3438 pr_err("cpl: %d efer: %016llx\n",
3439 save->cpl, save->efer);
3440 pr_err("%-15s %016llx %-13s %016llx\n",
3441 "cr0:", save->cr0, "cr2:", save->cr2);
3442 pr_err("%-15s %016llx %-13s %016llx\n",
3443 "cr3:", save->cr3, "cr4:", save->cr4);
3444 pr_err("%-15s %016llx %-13s %016llx\n",
3445 "dr6:", save->dr6, "dr7:", save->dr7);
3446 pr_err("%-15s %016llx %-13s %016llx\n",
3447 "rip:", save->rip, "rflags:", save->rflags);
3448 pr_err("%-15s %016llx %-13s %016llx\n",
3449 "rsp:", save->rsp, "rax:", save->rax);
3450 pr_err("%-15s %016llx %-13s %016llx\n",
3451 "star:", save->star, "lstar:", save->lstar);
3452 pr_err("%-15s %016llx %-13s %016llx\n",
3453 "cstar:", save->cstar, "sfmask:", save->sfmask);
3454 pr_err("%-15s %016llx %-13s %016llx\n",
3455 "kernel_gs_base:", save->kernel_gs_base,
3456 "sysenter_cs:", save->sysenter_cs);
3457 pr_err("%-15s %016llx %-13s %016llx\n",
3458 "sysenter_esp:", save->sysenter_esp,
3459 "sysenter_eip:", save->sysenter_eip);
3460 pr_err("%-15s %016llx %-13s %016llx\n",
3461 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
3462 pr_err("%-15s %016llx %-13s %016llx\n",
3463 "br_from:", save->br_from, "br_to:", save->br_to);
3464 pr_err("%-15s %016llx %-13s %016llx\n",
3465 "excp_from:", save->last_excp_from,
3466 "excp_to:", save->last_excp_to);
3467 }
3468
3469 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3470 {
3471 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3472
3473 *info1 = control->exit_info_1;
3474 *info2 = control->exit_info_2;
3475 }
3476
3477 static int handle_exit(struct kvm_vcpu *vcpu)
3478 {
3479 struct vcpu_svm *svm = to_svm(vcpu);
3480 struct kvm_run *kvm_run = vcpu->run;
3481 u32 exit_code = svm->vmcb->control.exit_code;
3482
3483 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
3484 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3485 if (npt_enabled)
3486 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3487
3488 if (unlikely(svm->nested.exit_required)) {
3489 nested_svm_vmexit(svm);
3490 svm->nested.exit_required = false;
3491
3492 return 1;
3493 }
3494
3495 if (is_guest_mode(vcpu)) {
3496 int vmexit;
3497
3498 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3499 svm->vmcb->control.exit_info_1,
3500 svm->vmcb->control.exit_info_2,
3501 svm->vmcb->control.exit_int_info,
3502 svm->vmcb->control.exit_int_info_err,
3503 KVM_ISA_SVM);
3504
3505 vmexit = nested_svm_exit_special(svm);
3506
3507 if (vmexit == NESTED_EXIT_CONTINUE)
3508 vmexit = nested_svm_exit_handled(svm);
3509
3510 if (vmexit == NESTED_EXIT_DONE)
3511 return 1;
3512 }
3513
3514 svm_complete_interrupts(svm);
3515
3516 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3517 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3518 kvm_run->fail_entry.hardware_entry_failure_reason
3519 = svm->vmcb->control.exit_code;
3520 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3521 dump_vmcb(vcpu);
3522 return 0;
3523 }
3524
3525 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3526 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3527 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3528 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3529 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
3530 "exit_code 0x%x\n",
3531 __func__, svm->vmcb->control.exit_int_info,
3532 exit_code);
3533
3534 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
3535 || !svm_exit_handlers[exit_code]) {
3536 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3537 kvm_run->hw.hardware_exit_reason = exit_code;
3538 return 0;
3539 }
3540
3541 return svm_exit_handlers[exit_code](svm);
3542 }
3543
3544 static void reload_tss(struct kvm_vcpu *vcpu)
3545 {
3546 int cpu = raw_smp_processor_id();
3547
3548 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3549 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3550 load_TR_desc();
3551 }
3552
3553 static void pre_svm_run(struct vcpu_svm *svm)
3554 {
3555 int cpu = raw_smp_processor_id();
3556
3557 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3558
3559 /* FIXME: handle wraparound of asid_generation */
3560 if (svm->asid_generation != sd->asid_generation)
3561 new_asid(svm, sd);
3562 }
3563
3564 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3565 {
3566 struct vcpu_svm *svm = to_svm(vcpu);
3567
3568 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3569 vcpu->arch.hflags |= HF_NMI_MASK;
3570 set_intercept(svm, INTERCEPT_IRET);
3571 ++vcpu->stat.nmi_injections;
3572 }
3573
3574 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
3575 {
3576 struct vmcb_control_area *control;
3577
3578 control = &svm->vmcb->control;
3579 control->int_vector = irq;
3580 control->int_ctl &= ~V_INTR_PRIO_MASK;
3581 control->int_ctl |= V_IRQ_MASK |
3582 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
3583 mark_dirty(svm->vmcb, VMCB_INTR);
3584 }
3585
3586 static void svm_set_irq(struct kvm_vcpu *vcpu)
3587 {
3588 struct vcpu_svm *svm = to_svm(vcpu);
3589
3590 BUG_ON(!(gif_set(svm)));
3591
3592 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3593 ++vcpu->stat.irq_injections;
3594
3595 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3596 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3597 }
3598
3599 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3600 {
3601 struct vcpu_svm *svm = to_svm(vcpu);
3602
3603 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3604 return;
3605
3606 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3607
3608 if (irr == -1)
3609 return;
3610
3611 if (tpr >= irr)
3612 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3613 }
3614
3615 static void svm_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
3616 {
3617 return;
3618 }
3619
3620 static int svm_vm_has_apicv(struct kvm *kvm)
3621 {
3622 return 0;
3623 }
3624
3625 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
3626 {
3627 return;
3628 }
3629
3630 static void svm_hwapic_isr_update(struct kvm *kvm, int isr)
3631 {
3632 return;
3633 }
3634
3635 static void svm_sync_pir_to_irr(struct kvm_vcpu *vcpu)
3636 {
3637 return;
3638 }
3639
3640 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3641 {
3642 struct vcpu_svm *svm = to_svm(vcpu);
3643 struct vmcb *vmcb = svm->vmcb;
3644 int ret;
3645 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3646 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3647 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3648
3649 return ret;
3650 }
3651
3652 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3653 {
3654 struct vcpu_svm *svm = to_svm(vcpu);
3655
3656 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3657 }
3658
3659 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3660 {
3661 struct vcpu_svm *svm = to_svm(vcpu);
3662
3663 if (masked) {
3664 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3665 set_intercept(svm, INTERCEPT_IRET);
3666 } else {
3667 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3668 clr_intercept(svm, INTERCEPT_IRET);
3669 }
3670 }
3671
3672 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3673 {
3674 struct vcpu_svm *svm = to_svm(vcpu);
3675 struct vmcb *vmcb = svm->vmcb;
3676 int ret;
3677
3678 if (!gif_set(svm) ||
3679 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3680 return 0;
3681
3682 ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
3683
3684 if (is_guest_mode(vcpu))
3685 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3686
3687 return ret;
3688 }
3689
3690 static void enable_irq_window(struct kvm_vcpu *vcpu)
3691 {
3692 struct vcpu_svm *svm = to_svm(vcpu);
3693
3694 /*
3695 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3696 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3697 * get that intercept, this function will be called again though and
3698 * we'll get the vintr intercept.
3699 */
3700 if (gif_set(svm) && nested_svm_intr(svm)) {
3701 svm_set_vintr(svm);
3702 svm_inject_irq(svm, 0x0);
3703 }
3704 }
3705
3706 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3707 {
3708 struct vcpu_svm *svm = to_svm(vcpu);
3709
3710 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3711 == HF_NMI_MASK)
3712 return; /* IRET will cause a vm exit */
3713
3714 /*
3715 * Something prevents NMI from been injected. Single step over possible
3716 * problem (IRET or exception injection or interrupt shadow)
3717 */
3718 svm->nmi_singlestep = true;
3719 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3720 update_db_bp_intercept(vcpu);
3721 }
3722
3723 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3724 {
3725 return 0;
3726 }
3727
3728 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3729 {
3730 struct vcpu_svm *svm = to_svm(vcpu);
3731
3732 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3733 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3734 else
3735 svm->asid_generation--;
3736 }
3737
3738 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3739 {
3740 }
3741
3742 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3743 {
3744 struct vcpu_svm *svm = to_svm(vcpu);
3745
3746 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3747 return;
3748
3749 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
3750 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3751 kvm_set_cr8(vcpu, cr8);
3752 }
3753 }
3754
3755 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3756 {
3757 struct vcpu_svm *svm = to_svm(vcpu);
3758 u64 cr8;
3759
3760 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3761 return;
3762
3763 cr8 = kvm_get_cr8(vcpu);
3764 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3765 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3766 }
3767
3768 static void svm_complete_interrupts(struct vcpu_svm *svm)
3769 {
3770 u8 vector;
3771 int type;
3772 u32 exitintinfo = svm->vmcb->control.exit_int_info;
3773 unsigned int3_injected = svm->int3_injected;
3774
3775 svm->int3_injected = 0;
3776
3777 /*
3778 * If we've made progress since setting HF_IRET_MASK, we've
3779 * executed an IRET and can allow NMI injection.
3780 */
3781 if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
3782 && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
3783 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3784 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3785 }
3786
3787 svm->vcpu.arch.nmi_injected = false;
3788 kvm_clear_exception_queue(&svm->vcpu);
3789 kvm_clear_interrupt_queue(&svm->vcpu);
3790
3791 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3792 return;
3793
3794 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3795
3796 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3797 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3798
3799 switch (type) {
3800 case SVM_EXITINTINFO_TYPE_NMI:
3801 svm->vcpu.arch.nmi_injected = true;
3802 break;
3803 case SVM_EXITINTINFO_TYPE_EXEPT:
3804 /*
3805 * In case of software exceptions, do not reinject the vector,
3806 * but re-execute the instruction instead. Rewind RIP first
3807 * if we emulated INT3 before.
3808 */
3809 if (kvm_exception_is_soft(vector)) {
3810 if (vector == BP_VECTOR && int3_injected &&
3811 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3812 kvm_rip_write(&svm->vcpu,
3813 kvm_rip_read(&svm->vcpu) -
3814 int3_injected);
3815 break;
3816 }
3817 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3818 u32 err = svm->vmcb->control.exit_int_info_err;
3819 kvm_requeue_exception_e(&svm->vcpu, vector, err);
3820
3821 } else
3822 kvm_requeue_exception(&svm->vcpu, vector);
3823 break;
3824 case SVM_EXITINTINFO_TYPE_INTR:
3825 kvm_queue_interrupt(&svm->vcpu, vector, false);
3826 break;
3827 default:
3828 break;
3829 }
3830 }
3831
3832 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3833 {
3834 struct vcpu_svm *svm = to_svm(vcpu);
3835 struct vmcb_control_area *control = &svm->vmcb->control;
3836
3837 control->exit_int_info = control->event_inj;
3838 control->exit_int_info_err = control->event_inj_err;
3839 control->event_inj = 0;
3840 svm_complete_interrupts(svm);
3841 }
3842
3843 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
3844 {
3845 struct vcpu_svm *svm = to_svm(vcpu);
3846
3847 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3848 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3849 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3850
3851 /*
3852 * A vmexit emulation is required before the vcpu can be executed
3853 * again.
3854 */
3855 if (unlikely(svm->nested.exit_required))
3856 return;
3857
3858 pre_svm_run(svm);
3859
3860 sync_lapic_to_cr8(vcpu);
3861
3862 svm->vmcb->save.cr2 = vcpu->arch.cr2;
3863
3864 clgi();
3865
3866 local_irq_enable();
3867
3868 asm volatile (
3869 "push %%" _ASM_BP "; \n\t"
3870 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
3871 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
3872 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
3873 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
3874 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
3875 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
3876 #ifdef CONFIG_X86_64
3877 "mov %c[r8](%[svm]), %%r8 \n\t"
3878 "mov %c[r9](%[svm]), %%r9 \n\t"
3879 "mov %c[r10](%[svm]), %%r10 \n\t"
3880 "mov %c[r11](%[svm]), %%r11 \n\t"
3881 "mov %c[r12](%[svm]), %%r12 \n\t"
3882 "mov %c[r13](%[svm]), %%r13 \n\t"
3883 "mov %c[r14](%[svm]), %%r14 \n\t"
3884 "mov %c[r15](%[svm]), %%r15 \n\t"
3885 #endif
3886
3887 /* Enter guest mode */
3888 "push %%" _ASM_AX " \n\t"
3889 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
3890 __ex(SVM_VMLOAD) "\n\t"
3891 __ex(SVM_VMRUN) "\n\t"
3892 __ex(SVM_VMSAVE) "\n\t"
3893 "pop %%" _ASM_AX " \n\t"
3894
3895 /* Save guest registers, load host registers */
3896 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
3897 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
3898 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
3899 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
3900 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
3901 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
3902 #ifdef CONFIG_X86_64
3903 "mov %%r8, %c[r8](%[svm]) \n\t"
3904 "mov %%r9, %c[r9](%[svm]) \n\t"
3905 "mov %%r10, %c[r10](%[svm]) \n\t"
3906 "mov %%r11, %c[r11](%[svm]) \n\t"
3907 "mov %%r12, %c[r12](%[svm]) \n\t"
3908 "mov %%r13, %c[r13](%[svm]) \n\t"
3909 "mov %%r14, %c[r14](%[svm]) \n\t"
3910 "mov %%r15, %c[r15](%[svm]) \n\t"
3911 #endif
3912 "pop %%" _ASM_BP
3913 :
3914 : [svm]"a"(svm),
3915 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
3916 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3917 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3918 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3919 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3920 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3921 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
3922 #ifdef CONFIG_X86_64
3923 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3924 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3925 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3926 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3927 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3928 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3929 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3930 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
3931 #endif
3932 : "cc", "memory"
3933 #ifdef CONFIG_X86_64
3934 , "rbx", "rcx", "rdx", "rsi", "rdi"
3935 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3936 #else
3937 , "ebx", "ecx", "edx", "esi", "edi"
3938 #endif
3939 );
3940
3941 #ifdef CONFIG_X86_64
3942 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3943 #else
3944 loadsegment(fs, svm->host.fs);
3945 #ifndef CONFIG_X86_32_LAZY_GS
3946 loadsegment(gs, svm->host.gs);
3947 #endif
3948 #endif
3949
3950 reload_tss(vcpu);
3951
3952 local_irq_disable();
3953
3954 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3955 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3956 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3957 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3958
3959 trace_kvm_exit(svm->vmcb->control.exit_code, vcpu, KVM_ISA_SVM);
3960
3961 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3962 kvm_before_handle_nmi(&svm->vcpu);
3963
3964 stgi();
3965
3966 /* Any pending NMI will happen here */
3967
3968 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3969 kvm_after_handle_nmi(&svm->vcpu);
3970
3971 sync_cr8_to_lapic(vcpu);
3972
3973 svm->next_rip = 0;
3974
3975 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3976
3977 /* if exit due to PF check for async PF */
3978 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3979 svm->apf_reason = kvm_read_and_reset_pf_reason();
3980
3981 if (npt_enabled) {
3982 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3983 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3984 }
3985
3986 /*
3987 * We need to handle MC intercepts here before the vcpu has a chance to
3988 * change the physical cpu
3989 */
3990 if (unlikely(svm->vmcb->control.exit_code ==
3991 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3992 svm_handle_mce(svm);
3993
3994 mark_all_clean(svm->vmcb);
3995 }
3996
3997 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3998 {
3999 struct vcpu_svm *svm = to_svm(vcpu);
4000
4001 svm->vmcb->save.cr3 = root;
4002 mark_dirty(svm->vmcb, VMCB_CR);
4003 svm_flush_tlb(vcpu);
4004 }
4005
4006 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
4007 {
4008 struct vcpu_svm *svm = to_svm(vcpu);
4009
4010 svm->vmcb->control.nested_cr3 = root;
4011 mark_dirty(svm->vmcb, VMCB_NPT);
4012
4013 /* Also sync guest cr3 here in case we live migrate */
4014 svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
4015 mark_dirty(svm->vmcb, VMCB_CR);
4016
4017 svm_flush_tlb(vcpu);
4018 }
4019
4020 static int is_disabled(void)
4021 {
4022 u64 vm_cr;
4023
4024 rdmsrl(MSR_VM_CR, vm_cr);
4025 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
4026 return 1;
4027
4028 return 0;
4029 }
4030
4031 static void
4032 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4033 {
4034 /*
4035 * Patch in the VMMCALL instruction:
4036 */
4037 hypercall[0] = 0x0f;
4038 hypercall[1] = 0x01;
4039 hypercall[2] = 0xd9;
4040 }
4041
4042 static void svm_check_processor_compat(void *rtn)
4043 {
4044 *(int *)rtn = 0;
4045 }
4046
4047 static bool svm_cpu_has_accelerated_tpr(void)
4048 {
4049 return false;
4050 }
4051
4052 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4053 {
4054 return 0;
4055 }
4056
4057 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
4058 {
4059 }
4060
4061 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4062 {
4063 switch (func) {
4064 case 0x80000001:
4065 if (nested)
4066 entry->ecx |= (1 << 2); /* Set SVM bit */
4067 break;
4068 case 0x8000000A:
4069 entry->eax = 1; /* SVM revision 1 */
4070 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
4071 ASID emulation to nested SVM */
4072 entry->ecx = 0; /* Reserved */
4073 entry->edx = 0; /* Per default do not support any
4074 additional features */
4075
4076 /* Support next_rip if host supports it */
4077 if (boot_cpu_has(X86_FEATURE_NRIPS))
4078 entry->edx |= SVM_FEATURE_NRIP;
4079
4080 /* Support NPT for the guest if enabled */
4081 if (npt_enabled)
4082 entry->edx |= SVM_FEATURE_NPT;
4083
4084 break;
4085 }
4086 }
4087
4088 static int svm_get_lpage_level(void)
4089 {
4090 return PT_PDPE_LEVEL;
4091 }
4092
4093 static bool svm_rdtscp_supported(void)
4094 {
4095 return false;
4096 }
4097
4098 static bool svm_invpcid_supported(void)
4099 {
4100 return false;
4101 }
4102
4103 static bool svm_mpx_supported(void)
4104 {
4105 return false;
4106 }
4107
4108 static bool svm_has_wbinvd_exit(void)
4109 {
4110 return true;
4111 }
4112
4113 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
4114 {
4115 struct vcpu_svm *svm = to_svm(vcpu);
4116
4117 set_exception_intercept(svm, NM_VECTOR);
4118 update_cr0_intercept(svm);
4119 }
4120
4121 #define PRE_EX(exit) { .exit_code = (exit), \
4122 .stage = X86_ICPT_PRE_EXCEPT, }
4123 #define POST_EX(exit) { .exit_code = (exit), \
4124 .stage = X86_ICPT_POST_EXCEPT, }
4125 #define POST_MEM(exit) { .exit_code = (exit), \
4126 .stage = X86_ICPT_POST_MEMACCESS, }
4127
4128 static const struct __x86_intercept {
4129 u32 exit_code;
4130 enum x86_intercept_stage stage;
4131 } x86_intercept_map[] = {
4132 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
4133 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
4134 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
4135 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
4136 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
4137 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
4138 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
4139 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
4140 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
4141 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
4142 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
4143 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
4144 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
4145 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
4146 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
4147 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
4148 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
4149 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
4150 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
4151 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
4152 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
4153 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
4154 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
4155 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
4156 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
4157 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
4158 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
4159 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
4160 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
4161 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
4162 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
4163 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
4164 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
4165 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
4166 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
4167 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
4168 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
4169 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
4170 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
4171 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
4172 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
4173 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
4174 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
4175 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
4176 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
4177 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
4178 };
4179
4180 #undef PRE_EX
4181 #undef POST_EX
4182 #undef POST_MEM
4183
4184 static int svm_check_intercept(struct kvm_vcpu *vcpu,
4185 struct x86_instruction_info *info,
4186 enum x86_intercept_stage stage)
4187 {
4188 struct vcpu_svm *svm = to_svm(vcpu);
4189 int vmexit, ret = X86EMUL_CONTINUE;
4190 struct __x86_intercept icpt_info;
4191 struct vmcb *vmcb = svm->vmcb;
4192
4193 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
4194 goto out;
4195
4196 icpt_info = x86_intercept_map[info->intercept];
4197
4198 if (stage != icpt_info.stage)
4199 goto out;
4200
4201 switch (icpt_info.exit_code) {
4202 case SVM_EXIT_READ_CR0:
4203 if (info->intercept == x86_intercept_cr_read)
4204 icpt_info.exit_code += info->modrm_reg;
4205 break;
4206 case SVM_EXIT_WRITE_CR0: {
4207 unsigned long cr0, val;
4208 u64 intercept;
4209
4210 if (info->intercept == x86_intercept_cr_write)
4211 icpt_info.exit_code += info->modrm_reg;
4212
4213 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
4214 info->intercept == x86_intercept_clts)
4215 break;
4216
4217 intercept = svm->nested.intercept;
4218
4219 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
4220 break;
4221
4222 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
4223 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
4224
4225 if (info->intercept == x86_intercept_lmsw) {
4226 cr0 &= 0xfUL;
4227 val &= 0xfUL;
4228 /* lmsw can't clear PE - catch this here */
4229 if (cr0 & X86_CR0_PE)
4230 val |= X86_CR0_PE;
4231 }
4232
4233 if (cr0 ^ val)
4234 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
4235
4236 break;
4237 }
4238 case SVM_EXIT_READ_DR0:
4239 case SVM_EXIT_WRITE_DR0:
4240 icpt_info.exit_code += info->modrm_reg;
4241 break;
4242 case SVM_EXIT_MSR:
4243 if (info->intercept == x86_intercept_wrmsr)
4244 vmcb->control.exit_info_1 = 1;
4245 else
4246 vmcb->control.exit_info_1 = 0;
4247 break;
4248 case SVM_EXIT_PAUSE:
4249 /*
4250 * We get this for NOP only, but pause
4251 * is rep not, check this here
4252 */
4253 if (info->rep_prefix != REPE_PREFIX)
4254 goto out;
4255 case SVM_EXIT_IOIO: {
4256 u64 exit_info;
4257 u32 bytes;
4258
4259 exit_info = (vcpu->arch.regs[VCPU_REGS_RDX] & 0xffff) << 16;
4260
4261 if (info->intercept == x86_intercept_in ||
4262 info->intercept == x86_intercept_ins) {
4263 exit_info |= SVM_IOIO_TYPE_MASK;
4264 bytes = info->src_bytes;
4265 } else {
4266 bytes = info->dst_bytes;
4267 }
4268
4269 if (info->intercept == x86_intercept_outs ||
4270 info->intercept == x86_intercept_ins)
4271 exit_info |= SVM_IOIO_STR_MASK;
4272
4273 if (info->rep_prefix)
4274 exit_info |= SVM_IOIO_REP_MASK;
4275
4276 bytes = min(bytes, 4u);
4277
4278 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
4279
4280 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
4281
4282 vmcb->control.exit_info_1 = exit_info;
4283 vmcb->control.exit_info_2 = info->next_rip;
4284
4285 break;
4286 }
4287 default:
4288 break;
4289 }
4290
4291 vmcb->control.next_rip = info->next_rip;
4292 vmcb->control.exit_code = icpt_info.exit_code;
4293 vmexit = nested_svm_exit_handled(svm);
4294
4295 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
4296 : X86EMUL_CONTINUE;
4297
4298 out:
4299 return ret;
4300 }
4301
4302 static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
4303 {
4304 local_irq_enable();
4305 }
4306
4307 static struct kvm_x86_ops svm_x86_ops = {
4308 .cpu_has_kvm_support = has_svm,
4309 .disabled_by_bios = is_disabled,
4310 .hardware_setup = svm_hardware_setup,
4311 .hardware_unsetup = svm_hardware_unsetup,
4312 .check_processor_compatibility = svm_check_processor_compat,
4313 .hardware_enable = svm_hardware_enable,
4314 .hardware_disable = svm_hardware_disable,
4315 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
4316
4317 .vcpu_create = svm_create_vcpu,
4318 .vcpu_free = svm_free_vcpu,
4319 .vcpu_reset = svm_vcpu_reset,
4320
4321 .prepare_guest_switch = svm_prepare_guest_switch,
4322 .vcpu_load = svm_vcpu_load,
4323 .vcpu_put = svm_vcpu_put,
4324
4325 .update_db_bp_intercept = update_db_bp_intercept,
4326 .get_msr = svm_get_msr,
4327 .set_msr = svm_set_msr,
4328 .get_segment_base = svm_get_segment_base,
4329 .get_segment = svm_get_segment,
4330 .set_segment = svm_set_segment,
4331 .get_cpl = svm_get_cpl,
4332 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
4333 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
4334 .decache_cr3 = svm_decache_cr3,
4335 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
4336 .set_cr0 = svm_set_cr0,
4337 .set_cr3 = svm_set_cr3,
4338 .set_cr4 = svm_set_cr4,
4339 .set_efer = svm_set_efer,
4340 .get_idt = svm_get_idt,
4341 .set_idt = svm_set_idt,
4342 .get_gdt = svm_get_gdt,
4343 .set_gdt = svm_set_gdt,
4344 .get_dr6 = svm_get_dr6,
4345 .set_dr6 = svm_set_dr6,
4346 .set_dr7 = svm_set_dr7,
4347 .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
4348 .cache_reg = svm_cache_reg,
4349 .get_rflags = svm_get_rflags,
4350 .set_rflags = svm_set_rflags,
4351 .fpu_activate = svm_fpu_activate,
4352 .fpu_deactivate = svm_fpu_deactivate,
4353
4354 .tlb_flush = svm_flush_tlb,
4355
4356 .run = svm_vcpu_run,
4357 .handle_exit = handle_exit,
4358 .skip_emulated_instruction = skip_emulated_instruction,
4359 .set_interrupt_shadow = svm_set_interrupt_shadow,
4360 .get_interrupt_shadow = svm_get_interrupt_shadow,
4361 .patch_hypercall = svm_patch_hypercall,
4362 .set_irq = svm_set_irq,
4363 .set_nmi = svm_inject_nmi,
4364 .queue_exception = svm_queue_exception,
4365 .cancel_injection = svm_cancel_injection,
4366 .interrupt_allowed = svm_interrupt_allowed,
4367 .nmi_allowed = svm_nmi_allowed,
4368 .get_nmi_mask = svm_get_nmi_mask,
4369 .set_nmi_mask = svm_set_nmi_mask,
4370 .enable_nmi_window = enable_nmi_window,
4371 .enable_irq_window = enable_irq_window,
4372 .update_cr8_intercept = update_cr8_intercept,
4373 .set_virtual_x2apic_mode = svm_set_virtual_x2apic_mode,
4374 .vm_has_apicv = svm_vm_has_apicv,
4375 .load_eoi_exitmap = svm_load_eoi_exitmap,
4376 .hwapic_isr_update = svm_hwapic_isr_update,
4377 .sync_pir_to_irr = svm_sync_pir_to_irr,
4378
4379 .set_tss_addr = svm_set_tss_addr,
4380 .get_tdp_level = get_npt_level,
4381 .get_mt_mask = svm_get_mt_mask,
4382
4383 .get_exit_info = svm_get_exit_info,
4384
4385 .get_lpage_level = svm_get_lpage_level,
4386
4387 .cpuid_update = svm_cpuid_update,
4388
4389 .rdtscp_supported = svm_rdtscp_supported,
4390 .invpcid_supported = svm_invpcid_supported,
4391 .mpx_supported = svm_mpx_supported,
4392
4393 .set_supported_cpuid = svm_set_supported_cpuid,
4394
4395 .has_wbinvd_exit = svm_has_wbinvd_exit,
4396
4397 .set_tsc_khz = svm_set_tsc_khz,
4398 .read_tsc_offset = svm_read_tsc_offset,
4399 .write_tsc_offset = svm_write_tsc_offset,
4400 .adjust_tsc_offset = svm_adjust_tsc_offset,
4401 .compute_tsc_offset = svm_compute_tsc_offset,
4402 .read_l1_tsc = svm_read_l1_tsc,
4403
4404 .set_tdp_cr3 = set_tdp_cr3,
4405
4406 .check_intercept = svm_check_intercept,
4407 .handle_external_intr = svm_handle_external_intr,
4408 };
4409
4410 static int __init svm_init(void)
4411 {
4412 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
4413 __alignof__(struct vcpu_svm), THIS_MODULE);
4414 }
4415
4416 static void __exit svm_exit(void)
4417 {
4418 kvm_exit();
4419 }
4420
4421 module_init(svm_init)
4422 module_exit(svm_exit)
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