2 * Kernel-based Virtual Machine driver for Linux
6 * Copyright (C) 2006 Qumranet, Inc.
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
16 #include <linux/kvm_host.h>
20 #include "kvm_cache_regs.h"
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/vmalloc.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28 #include <linux/ftrace_event.h>
29 #include <linux/slab.h>
33 #include <asm/virtext.h>
36 #define __ex(x) __kvm_handle_fault_on_reboot(x)
38 MODULE_AUTHOR("Qumranet");
39 MODULE_LICENSE("GPL");
41 #define IOPM_ALLOC_ORDER 2
42 #define MSRPM_ALLOC_ORDER 1
44 #define SEG_TYPE_LDT 2
45 #define SEG_TYPE_BUSY_TSS16 3
47 #define SVM_FEATURE_NPT (1 << 0)
48 #define SVM_FEATURE_LBRV (1 << 1)
49 #define SVM_FEATURE_SVML (1 << 2)
50 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
52 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
53 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
54 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
56 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
58 static const u32 host_save_user_msrs
[] = {
60 MSR_STAR
, MSR_LSTAR
, MSR_CSTAR
, MSR_SYSCALL_MASK
, MSR_KERNEL_GS_BASE
,
63 MSR_IA32_SYSENTER_CS
, MSR_IA32_SYSENTER_ESP
, MSR_IA32_SYSENTER_EIP
,
66 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
75 /* These are the merged vectors */
78 /* gpa pointers to the real vectors */
81 /* A VMEXIT is required but not yet emulated */
84 /* cache for intercepts of the guest */
85 u16 intercept_cr_read
;
86 u16 intercept_cr_write
;
87 u16 intercept_dr_read
;
88 u16 intercept_dr_write
;
89 u32 intercept_exceptions
;
97 unsigned long vmcb_pa
;
98 struct svm_cpu_data
*svm_data
;
99 uint64_t asid_generation
;
100 uint64_t sysenter_esp
;
101 uint64_t sysenter_eip
;
105 u64 host_user_msrs
[NR_HOST_SAVE_USER_MSRS
];
110 struct nested_state nested
;
115 /* enable NPT for AMD64 and X86 with PAE */
116 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
117 static bool npt_enabled
= true;
119 static bool npt_enabled
= false;
123 module_param(npt
, int, S_IRUGO
);
125 static int nested
= 1;
126 module_param(nested
, int, S_IRUGO
);
128 static void svm_flush_tlb(struct kvm_vcpu
*vcpu
);
129 static void svm_complete_interrupts(struct vcpu_svm
*svm
);
131 static int nested_svm_exit_handled(struct vcpu_svm
*svm
);
132 static int nested_svm_intercept(struct vcpu_svm
*svm
);
133 static int nested_svm_vmexit(struct vcpu_svm
*svm
);
134 static int nested_svm_check_exception(struct vcpu_svm
*svm
, unsigned nr
,
135 bool has_error_code
, u32 error_code
);
137 static inline struct vcpu_svm
*to_svm(struct kvm_vcpu
*vcpu
)
139 return container_of(vcpu
, struct vcpu_svm
, vcpu
);
142 static inline bool is_nested(struct vcpu_svm
*svm
)
144 return svm
->nested
.vmcb
;
147 static inline void enable_gif(struct vcpu_svm
*svm
)
149 svm
->vcpu
.arch
.hflags
|= HF_GIF_MASK
;
152 static inline void disable_gif(struct vcpu_svm
*svm
)
154 svm
->vcpu
.arch
.hflags
&= ~HF_GIF_MASK
;
157 static inline bool gif_set(struct vcpu_svm
*svm
)
159 return !!(svm
->vcpu
.arch
.hflags
& HF_GIF_MASK
);
162 static unsigned long iopm_base
;
164 struct kvm_ldttss_desc
{
167 unsigned base1
: 8, type
: 5, dpl
: 2, p
: 1;
168 unsigned limit1
: 4, zero0
: 3, g
: 1, base2
: 8;
171 } __attribute__((packed
));
173 struct svm_cpu_data
{
179 struct kvm_ldttss_desc
*tss_desc
;
181 struct page
*save_area
;
184 static DEFINE_PER_CPU(struct svm_cpu_data
*, svm_data
);
185 static uint32_t svm_features
;
187 struct svm_init_data
{
192 static u32 msrpm_ranges
[] = {0, 0xc0000000, 0xc0010000};
194 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
195 #define MSRS_RANGE_SIZE 2048
196 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
198 #define MAX_INST_SIZE 15
200 static inline u32
svm_has(u32 feat
)
202 return svm_features
& feat
;
205 static inline void clgi(void)
207 asm volatile (__ex(SVM_CLGI
));
210 static inline void stgi(void)
212 asm volatile (__ex(SVM_STGI
));
215 static inline void invlpga(unsigned long addr
, u32 asid
)
217 asm volatile (__ex(SVM_INVLPGA
) :: "a"(addr
), "c"(asid
));
220 static inline void force_new_asid(struct kvm_vcpu
*vcpu
)
222 to_svm(vcpu
)->asid_generation
--;
225 static inline void flush_guest_tlb(struct kvm_vcpu
*vcpu
)
227 force_new_asid(vcpu
);
230 static void svm_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
232 if (!npt_enabled
&& !(efer
& EFER_LMA
))
235 to_svm(vcpu
)->vmcb
->save
.efer
= efer
| EFER_SVME
;
236 vcpu
->arch
.efer
= efer
;
239 static void svm_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
240 bool has_error_code
, u32 error_code
)
242 struct vcpu_svm
*svm
= to_svm(vcpu
);
244 /* If we are within a nested VM we'd better #VMEXIT and let the
245 guest handle the exception */
246 if (nested_svm_check_exception(svm
, nr
, has_error_code
, error_code
))
249 svm
->vmcb
->control
.event_inj
= nr
251 | (has_error_code
? SVM_EVTINJ_VALID_ERR
: 0)
252 | SVM_EVTINJ_TYPE_EXEPT
;
253 svm
->vmcb
->control
.event_inj_err
= error_code
;
256 static int is_external_interrupt(u32 info
)
258 info
&= SVM_EVTINJ_TYPE_MASK
| SVM_EVTINJ_VALID
;
259 return info
== (SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
);
262 static u32
svm_get_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
264 struct vcpu_svm
*svm
= to_svm(vcpu
);
267 if (svm
->vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
)
268 ret
|= X86_SHADOW_INT_STI
| X86_SHADOW_INT_MOV_SS
;
272 static void svm_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
274 struct vcpu_svm
*svm
= to_svm(vcpu
);
277 svm
->vmcb
->control
.int_state
&= ~SVM_INTERRUPT_SHADOW_MASK
;
279 svm
->vmcb
->control
.int_state
|= SVM_INTERRUPT_SHADOW_MASK
;
283 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
285 struct vcpu_svm
*svm
= to_svm(vcpu
);
287 if (!svm
->next_rip
) {
288 if (emulate_instruction(vcpu
, 0, 0, EMULTYPE_SKIP
) !=
290 printk(KERN_DEBUG
"%s: NOP\n", __func__
);
293 if (svm
->next_rip
- kvm_rip_read(vcpu
) > MAX_INST_SIZE
)
294 printk(KERN_ERR
"%s: ip 0x%lx next 0x%llx\n",
295 __func__
, kvm_rip_read(vcpu
), svm
->next_rip
);
297 kvm_rip_write(vcpu
, svm
->next_rip
);
298 svm_set_interrupt_shadow(vcpu
, 0);
301 static int has_svm(void)
305 if (!cpu_has_svm(&msg
)) {
306 printk(KERN_INFO
"has_svm: %s\n", msg
);
313 static void svm_hardware_disable(void *garbage
)
318 static int svm_hardware_enable(void *garbage
)
321 struct svm_cpu_data
*sd
;
323 struct desc_ptr gdt_descr
;
324 struct desc_struct
*gdt
;
325 int me
= raw_smp_processor_id();
327 rdmsrl(MSR_EFER
, efer
);
328 if (efer
& EFER_SVME
)
332 printk(KERN_ERR
"svm_hardware_enable: err EOPNOTSUPP on %d\n",
336 sd
= per_cpu(svm_data
, me
);
339 printk(KERN_ERR
"svm_hardware_enable: svm_data is NULL on %d\n",
344 sd
->asid_generation
= 1;
345 sd
->max_asid
= cpuid_ebx(SVM_CPUID_FUNC
) - 1;
346 sd
->next_asid
= sd
->max_asid
+ 1;
348 kvm_get_gdt(&gdt_descr
);
349 gdt
= (struct desc_struct
*)gdt_descr
.address
;
350 sd
->tss_desc
= (struct kvm_ldttss_desc
*)(gdt
+ GDT_ENTRY_TSS
);
352 wrmsrl(MSR_EFER
, efer
| EFER_SVME
);
354 wrmsrl(MSR_VM_HSAVE_PA
, page_to_pfn(sd
->save_area
) << PAGE_SHIFT
);
359 static void svm_cpu_uninit(int cpu
)
361 struct svm_cpu_data
*sd
= per_cpu(svm_data
, raw_smp_processor_id());
366 per_cpu(svm_data
, raw_smp_processor_id()) = NULL
;
367 __free_page(sd
->save_area
);
371 static int svm_cpu_init(int cpu
)
373 struct svm_cpu_data
*sd
;
376 sd
= kzalloc(sizeof(struct svm_cpu_data
), GFP_KERNEL
);
380 sd
->save_area
= alloc_page(GFP_KERNEL
);
385 per_cpu(svm_data
, cpu
) = sd
;
395 static void set_msr_interception(u32
*msrpm
, unsigned msr
,
400 for (i
= 0; i
< NUM_MSR_MAPS
; i
++) {
401 if (msr
>= msrpm_ranges
[i
] &&
402 msr
< msrpm_ranges
[i
] + MSRS_IN_RANGE
) {
403 u32 msr_offset
= (i
* MSRS_IN_RANGE
+ msr
-
404 msrpm_ranges
[i
]) * 2;
406 u32
*base
= msrpm
+ (msr_offset
/ 32);
407 u32 msr_shift
= msr_offset
% 32;
408 u32 mask
= ((write
) ? 0 : 2) | ((read
) ? 0 : 1);
409 *base
= (*base
& ~(0x3 << msr_shift
)) |
417 static void svm_vcpu_init_msrpm(u32
*msrpm
)
419 memset(msrpm
, 0xff, PAGE_SIZE
* (1 << MSRPM_ALLOC_ORDER
));
422 set_msr_interception(msrpm
, MSR_GS_BASE
, 1, 1);
423 set_msr_interception(msrpm
, MSR_FS_BASE
, 1, 1);
424 set_msr_interception(msrpm
, MSR_KERNEL_GS_BASE
, 1, 1);
425 set_msr_interception(msrpm
, MSR_LSTAR
, 1, 1);
426 set_msr_interception(msrpm
, MSR_CSTAR
, 1, 1);
427 set_msr_interception(msrpm
, MSR_SYSCALL_MASK
, 1, 1);
429 set_msr_interception(msrpm
, MSR_K6_STAR
, 1, 1);
430 set_msr_interception(msrpm
, MSR_IA32_SYSENTER_CS
, 1, 1);
433 static void svm_enable_lbrv(struct vcpu_svm
*svm
)
435 u32
*msrpm
= svm
->msrpm
;
437 svm
->vmcb
->control
.lbr_ctl
= 1;
438 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 1, 1);
439 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHTOIP
, 1, 1);
440 set_msr_interception(msrpm
, MSR_IA32_LASTINTFROMIP
, 1, 1);
441 set_msr_interception(msrpm
, MSR_IA32_LASTINTTOIP
, 1, 1);
444 static void svm_disable_lbrv(struct vcpu_svm
*svm
)
446 u32
*msrpm
= svm
->msrpm
;
448 svm
->vmcb
->control
.lbr_ctl
= 0;
449 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 0, 0);
450 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHTOIP
, 0, 0);
451 set_msr_interception(msrpm
, MSR_IA32_LASTINTFROMIP
, 0, 0);
452 set_msr_interception(msrpm
, MSR_IA32_LASTINTTOIP
, 0, 0);
455 static __init
int svm_hardware_setup(void)
458 struct page
*iopm_pages
;
462 iopm_pages
= alloc_pages(GFP_KERNEL
, IOPM_ALLOC_ORDER
);
467 iopm_va
= page_address(iopm_pages
);
468 memset(iopm_va
, 0xff, PAGE_SIZE
* (1 << IOPM_ALLOC_ORDER
));
469 iopm_base
= page_to_pfn(iopm_pages
) << PAGE_SHIFT
;
471 if (boot_cpu_has(X86_FEATURE_NX
))
472 kvm_enable_efer_bits(EFER_NX
);
474 if (boot_cpu_has(X86_FEATURE_FXSR_OPT
))
475 kvm_enable_efer_bits(EFER_FFXSR
);
478 printk(KERN_INFO
"kvm: Nested Virtualization enabled\n");
479 kvm_enable_efer_bits(EFER_SVME
);
482 for_each_possible_cpu(cpu
) {
483 r
= svm_cpu_init(cpu
);
488 svm_features
= cpuid_edx(SVM_CPUID_FUNC
);
490 if (!svm_has(SVM_FEATURE_NPT
))
493 if (npt_enabled
&& !npt
) {
494 printk(KERN_INFO
"kvm: Nested Paging disabled\n");
499 printk(KERN_INFO
"kvm: Nested Paging enabled\n");
507 __free_pages(iopm_pages
, IOPM_ALLOC_ORDER
);
512 static __exit
void svm_hardware_unsetup(void)
516 for_each_possible_cpu(cpu
)
519 __free_pages(pfn_to_page(iopm_base
>> PAGE_SHIFT
), IOPM_ALLOC_ORDER
);
523 static void init_seg(struct vmcb_seg
*seg
)
526 seg
->attrib
= SVM_SELECTOR_P_MASK
| SVM_SELECTOR_S_MASK
|
527 SVM_SELECTOR_WRITE_MASK
; /* Read/Write Data Segment */
532 static void init_sys_seg(struct vmcb_seg
*seg
, uint32_t type
)
535 seg
->attrib
= SVM_SELECTOR_P_MASK
| type
;
540 static void init_vmcb(struct vcpu_svm
*svm
)
542 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
543 struct vmcb_save_area
*save
= &svm
->vmcb
->save
;
545 svm
->vcpu
.fpu_active
= 1;
547 control
->intercept_cr_read
= INTERCEPT_CR0_MASK
|
551 control
->intercept_cr_write
= INTERCEPT_CR0_MASK
|
556 control
->intercept_dr_read
= INTERCEPT_DR0_MASK
|
565 control
->intercept_dr_write
= INTERCEPT_DR0_MASK
|
574 control
->intercept_exceptions
= (1 << PF_VECTOR
) |
579 control
->intercept
= (1ULL << INTERCEPT_INTR
) |
580 (1ULL << INTERCEPT_NMI
) |
581 (1ULL << INTERCEPT_SMI
) |
582 (1ULL << INTERCEPT_SELECTIVE_CR0
) |
583 (1ULL << INTERCEPT_CPUID
) |
584 (1ULL << INTERCEPT_INVD
) |
585 (1ULL << INTERCEPT_HLT
) |
586 (1ULL << INTERCEPT_INVLPG
) |
587 (1ULL << INTERCEPT_INVLPGA
) |
588 (1ULL << INTERCEPT_IOIO_PROT
) |
589 (1ULL << INTERCEPT_MSR_PROT
) |
590 (1ULL << INTERCEPT_TASK_SWITCH
) |
591 (1ULL << INTERCEPT_SHUTDOWN
) |
592 (1ULL << INTERCEPT_VMRUN
) |
593 (1ULL << INTERCEPT_VMMCALL
) |
594 (1ULL << INTERCEPT_VMLOAD
) |
595 (1ULL << INTERCEPT_VMSAVE
) |
596 (1ULL << INTERCEPT_STGI
) |
597 (1ULL << INTERCEPT_CLGI
) |
598 (1ULL << INTERCEPT_SKINIT
) |
599 (1ULL << INTERCEPT_WBINVD
) |
600 (1ULL << INTERCEPT_MONITOR
) |
601 (1ULL << INTERCEPT_MWAIT
);
603 control
->iopm_base_pa
= iopm_base
;
604 control
->msrpm_base_pa
= __pa(svm
->msrpm
);
605 control
->tsc_offset
= 0;
606 control
->int_ctl
= V_INTR_MASKING_MASK
;
614 save
->cs
.selector
= 0xf000;
615 /* Executable/Readable Code Segment */
616 save
->cs
.attrib
= SVM_SELECTOR_READ_MASK
| SVM_SELECTOR_P_MASK
|
617 SVM_SELECTOR_S_MASK
| SVM_SELECTOR_CODE_MASK
;
618 save
->cs
.limit
= 0xffff;
620 * cs.base should really be 0xffff0000, but vmx can't handle that, so
621 * be consistent with it.
623 * Replace when we have real mode working for vmx.
625 save
->cs
.base
= 0xf0000;
627 save
->gdtr
.limit
= 0xffff;
628 save
->idtr
.limit
= 0xffff;
630 init_sys_seg(&save
->ldtr
, SEG_TYPE_LDT
);
631 init_sys_seg(&save
->tr
, SEG_TYPE_BUSY_TSS16
);
633 save
->efer
= EFER_SVME
;
634 save
->dr6
= 0xffff0ff0;
637 save
->rip
= 0x0000fff0;
638 svm
->vcpu
.arch
.regs
[VCPU_REGS_RIP
] = save
->rip
;
640 /* This is the guest-visible cr0 value.
641 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
643 svm
->vcpu
.arch
.cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
644 kvm_set_cr0(&svm
->vcpu
, svm
->vcpu
.arch
.cr0
);
646 save
->cr4
= X86_CR4_PAE
;
650 /* Setup VMCB for Nested Paging */
651 control
->nested_ctl
= 1;
652 control
->intercept
&= ~((1ULL << INTERCEPT_TASK_SWITCH
) |
653 (1ULL << INTERCEPT_INVLPG
));
654 control
->intercept_exceptions
&= ~(1 << PF_VECTOR
);
655 control
->intercept_cr_read
&= ~INTERCEPT_CR3_MASK
;
656 control
->intercept_cr_write
&= ~INTERCEPT_CR3_MASK
;
657 save
->g_pat
= 0x0007040600070406ULL
;
661 force_new_asid(&svm
->vcpu
);
663 svm
->nested
.vmcb
= 0;
664 svm
->vcpu
.arch
.hflags
= 0;
666 if (svm_has(SVM_FEATURE_PAUSE_FILTER
)) {
667 control
->pause_filter_count
= 3000;
668 control
->intercept
|= (1ULL << INTERCEPT_PAUSE
);
674 static int svm_vcpu_reset(struct kvm_vcpu
*vcpu
)
676 struct vcpu_svm
*svm
= to_svm(vcpu
);
680 if (!kvm_vcpu_is_bsp(vcpu
)) {
681 kvm_rip_write(vcpu
, 0);
682 svm
->vmcb
->save
.cs
.base
= svm
->vcpu
.arch
.sipi_vector
<< 12;
683 svm
->vmcb
->save
.cs
.selector
= svm
->vcpu
.arch
.sipi_vector
<< 8;
685 vcpu
->arch
.regs_avail
= ~0;
686 vcpu
->arch
.regs_dirty
= ~0;
691 static struct kvm_vcpu
*svm_create_vcpu(struct kvm
*kvm
, unsigned int id
)
693 struct vcpu_svm
*svm
;
695 struct page
*msrpm_pages
;
696 struct page
*hsave_page
;
697 struct page
*nested_msrpm_pages
;
700 svm
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
706 err
= kvm_vcpu_init(&svm
->vcpu
, kvm
, id
);
711 page
= alloc_page(GFP_KERNEL
);
715 msrpm_pages
= alloc_pages(GFP_KERNEL
, MSRPM_ALLOC_ORDER
);
719 nested_msrpm_pages
= alloc_pages(GFP_KERNEL
, MSRPM_ALLOC_ORDER
);
720 if (!nested_msrpm_pages
)
723 hsave_page
= alloc_page(GFP_KERNEL
);
727 svm
->nested
.hsave
= page_address(hsave_page
);
729 svm
->msrpm
= page_address(msrpm_pages
);
730 svm_vcpu_init_msrpm(svm
->msrpm
);
732 svm
->nested
.msrpm
= page_address(nested_msrpm_pages
);
734 svm
->vmcb
= page_address(page
);
735 clear_page(svm
->vmcb
);
736 svm
->vmcb_pa
= page_to_pfn(page
) << PAGE_SHIFT
;
737 svm
->asid_generation
= 0;
741 svm
->vcpu
.arch
.apic_base
= 0xfee00000 | MSR_IA32_APICBASE_ENABLE
;
742 if (kvm_vcpu_is_bsp(&svm
->vcpu
))
743 svm
->vcpu
.arch
.apic_base
|= MSR_IA32_APICBASE_BSP
;
748 __free_pages(nested_msrpm_pages
, MSRPM_ALLOC_ORDER
);
750 __free_pages(msrpm_pages
, MSRPM_ALLOC_ORDER
);
754 kvm_vcpu_uninit(&svm
->vcpu
);
756 kmem_cache_free(kvm_vcpu_cache
, svm
);
761 static void svm_free_vcpu(struct kvm_vcpu
*vcpu
)
763 struct vcpu_svm
*svm
= to_svm(vcpu
);
765 __free_page(pfn_to_page(svm
->vmcb_pa
>> PAGE_SHIFT
));
766 __free_pages(virt_to_page(svm
->msrpm
), MSRPM_ALLOC_ORDER
);
767 __free_page(virt_to_page(svm
->nested
.hsave
));
768 __free_pages(virt_to_page(svm
->nested
.msrpm
), MSRPM_ALLOC_ORDER
);
769 kvm_vcpu_uninit(vcpu
);
770 kmem_cache_free(kvm_vcpu_cache
, svm
);
773 static void svm_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
775 struct vcpu_svm
*svm
= to_svm(vcpu
);
778 if (unlikely(cpu
!= vcpu
->cpu
)) {
781 if (check_tsc_unstable()) {
783 * Make sure that the guest sees a monotonically
786 delta
= vcpu
->arch
.host_tsc
- native_read_tsc();
787 svm
->vmcb
->control
.tsc_offset
+= delta
;
789 svm
->nested
.hsave
->control
.tsc_offset
+= delta
;
792 kvm_migrate_timers(vcpu
);
793 svm
->asid_generation
= 0;
796 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
797 rdmsrl(host_save_user_msrs
[i
], svm
->host_user_msrs
[i
]);
800 static void svm_vcpu_put(struct kvm_vcpu
*vcpu
)
802 struct vcpu_svm
*svm
= to_svm(vcpu
);
805 ++vcpu
->stat
.host_state_reload
;
806 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
807 wrmsrl(host_save_user_msrs
[i
], svm
->host_user_msrs
[i
]);
809 vcpu
->arch
.host_tsc
= native_read_tsc();
812 static unsigned long svm_get_rflags(struct kvm_vcpu
*vcpu
)
814 return to_svm(vcpu
)->vmcb
->save
.rflags
;
817 static void svm_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
819 to_svm(vcpu
)->vmcb
->save
.rflags
= rflags
;
822 static void svm_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
825 case VCPU_EXREG_PDPTR
:
826 BUG_ON(!npt_enabled
);
827 load_pdptrs(vcpu
, vcpu
->arch
.cr3
);
834 static void svm_set_vintr(struct vcpu_svm
*svm
)
836 svm
->vmcb
->control
.intercept
|= 1ULL << INTERCEPT_VINTR
;
839 static void svm_clear_vintr(struct vcpu_svm
*svm
)
841 svm
->vmcb
->control
.intercept
&= ~(1ULL << INTERCEPT_VINTR
);
844 static struct vmcb_seg
*svm_seg(struct kvm_vcpu
*vcpu
, int seg
)
846 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
849 case VCPU_SREG_CS
: return &save
->cs
;
850 case VCPU_SREG_DS
: return &save
->ds
;
851 case VCPU_SREG_ES
: return &save
->es
;
852 case VCPU_SREG_FS
: return &save
->fs
;
853 case VCPU_SREG_GS
: return &save
->gs
;
854 case VCPU_SREG_SS
: return &save
->ss
;
855 case VCPU_SREG_TR
: return &save
->tr
;
856 case VCPU_SREG_LDTR
: return &save
->ldtr
;
862 static u64
svm_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
864 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
869 static void svm_get_segment(struct kvm_vcpu
*vcpu
,
870 struct kvm_segment
*var
, int seg
)
872 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
875 var
->limit
= s
->limit
;
876 var
->selector
= s
->selector
;
877 var
->type
= s
->attrib
& SVM_SELECTOR_TYPE_MASK
;
878 var
->s
= (s
->attrib
>> SVM_SELECTOR_S_SHIFT
) & 1;
879 var
->dpl
= (s
->attrib
>> SVM_SELECTOR_DPL_SHIFT
) & 3;
880 var
->present
= (s
->attrib
>> SVM_SELECTOR_P_SHIFT
) & 1;
881 var
->avl
= (s
->attrib
>> SVM_SELECTOR_AVL_SHIFT
) & 1;
882 var
->l
= (s
->attrib
>> SVM_SELECTOR_L_SHIFT
) & 1;
883 var
->db
= (s
->attrib
>> SVM_SELECTOR_DB_SHIFT
) & 1;
884 var
->g
= (s
->attrib
>> SVM_SELECTOR_G_SHIFT
) & 1;
886 /* AMD's VMCB does not have an explicit unusable field, so emulate it
887 * for cross vendor migration purposes by "not present"
889 var
->unusable
= !var
->present
|| (var
->type
== 0);
894 * SVM always stores 0 for the 'G' bit in the CS selector in
895 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
896 * Intel's VMENTRY has a check on the 'G' bit.
898 var
->g
= s
->limit
> 0xfffff;
902 * Work around a bug where the busy flag in the tr selector
912 * The accessed bit must always be set in the segment
913 * descriptor cache, although it can be cleared in the
914 * descriptor, the cached bit always remains at 1. Since
915 * Intel has a check on this, set it here to support
916 * cross-vendor migration.
922 /* On AMD CPUs sometimes the DB bit in the segment
923 * descriptor is left as 1, although the whole segment has
924 * been made unusable. Clear it here to pass an Intel VMX
925 * entry check when cross vendor migrating.
933 static int svm_get_cpl(struct kvm_vcpu
*vcpu
)
935 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
940 static void svm_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
942 struct vcpu_svm
*svm
= to_svm(vcpu
);
944 dt
->size
= svm
->vmcb
->save
.idtr
.limit
;
945 dt
->address
= svm
->vmcb
->save
.idtr
.base
;
948 static void svm_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
950 struct vcpu_svm
*svm
= to_svm(vcpu
);
952 svm
->vmcb
->save
.idtr
.limit
= dt
->size
;
953 svm
->vmcb
->save
.idtr
.base
= dt
->address
;
956 static void svm_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
958 struct vcpu_svm
*svm
= to_svm(vcpu
);
960 dt
->size
= svm
->vmcb
->save
.gdtr
.limit
;
961 dt
->address
= svm
->vmcb
->save
.gdtr
.base
;
964 static void svm_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
966 struct vcpu_svm
*svm
= to_svm(vcpu
);
968 svm
->vmcb
->save
.gdtr
.limit
= dt
->size
;
969 svm
->vmcb
->save
.gdtr
.base
= dt
->address
;
972 static void svm_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
976 static void svm_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
980 static void update_cr0_intercept(struct vcpu_svm
*svm
)
982 ulong gcr0
= svm
->vcpu
.arch
.cr0
;
983 u64
*hcr0
= &svm
->vmcb
->save
.cr0
;
985 if (!svm
->vcpu
.fpu_active
)
986 *hcr0
|= SVM_CR0_SELECTIVE_MASK
;
988 *hcr0
= (*hcr0
& ~SVM_CR0_SELECTIVE_MASK
)
989 | (gcr0
& SVM_CR0_SELECTIVE_MASK
);
992 if (gcr0
== *hcr0
&& svm
->vcpu
.fpu_active
) {
993 svm
->vmcb
->control
.intercept_cr_read
&= ~INTERCEPT_CR0_MASK
;
994 svm
->vmcb
->control
.intercept_cr_write
&= ~INTERCEPT_CR0_MASK
;
996 svm
->vmcb
->control
.intercept_cr_read
|= INTERCEPT_CR0_MASK
;
997 svm
->vmcb
->control
.intercept_cr_write
|= INTERCEPT_CR0_MASK
;
1001 static void svm_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
1003 struct vcpu_svm
*svm
= to_svm(vcpu
);
1005 #ifdef CONFIG_X86_64
1006 if (vcpu
->arch
.efer
& EFER_LME
) {
1007 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
)) {
1008 vcpu
->arch
.efer
|= EFER_LMA
;
1009 svm
->vmcb
->save
.efer
|= EFER_LMA
| EFER_LME
;
1012 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
)) {
1013 vcpu
->arch
.efer
&= ~EFER_LMA
;
1014 svm
->vmcb
->save
.efer
&= ~(EFER_LMA
| EFER_LME
);
1018 vcpu
->arch
.cr0
= cr0
;
1021 cr0
|= X86_CR0_PG
| X86_CR0_WP
;
1023 if (!vcpu
->fpu_active
)
1026 * re-enable caching here because the QEMU bios
1027 * does not do it - this results in some delay at
1030 cr0
&= ~(X86_CR0_CD
| X86_CR0_NW
);
1031 svm
->vmcb
->save
.cr0
= cr0
;
1032 update_cr0_intercept(svm
);
1035 static void svm_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
1037 unsigned long host_cr4_mce
= read_cr4() & X86_CR4_MCE
;
1038 unsigned long old_cr4
= to_svm(vcpu
)->vmcb
->save
.cr4
;
1040 if (npt_enabled
&& ((old_cr4
^ cr4
) & X86_CR4_PGE
))
1041 force_new_asid(vcpu
);
1043 vcpu
->arch
.cr4
= cr4
;
1046 cr4
|= host_cr4_mce
;
1047 to_svm(vcpu
)->vmcb
->save
.cr4
= cr4
;
1050 static void svm_set_segment(struct kvm_vcpu
*vcpu
,
1051 struct kvm_segment
*var
, int seg
)
1053 struct vcpu_svm
*svm
= to_svm(vcpu
);
1054 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1056 s
->base
= var
->base
;
1057 s
->limit
= var
->limit
;
1058 s
->selector
= var
->selector
;
1062 s
->attrib
= (var
->type
& SVM_SELECTOR_TYPE_MASK
);
1063 s
->attrib
|= (var
->s
& 1) << SVM_SELECTOR_S_SHIFT
;
1064 s
->attrib
|= (var
->dpl
& 3) << SVM_SELECTOR_DPL_SHIFT
;
1065 s
->attrib
|= (var
->present
& 1) << SVM_SELECTOR_P_SHIFT
;
1066 s
->attrib
|= (var
->avl
& 1) << SVM_SELECTOR_AVL_SHIFT
;
1067 s
->attrib
|= (var
->l
& 1) << SVM_SELECTOR_L_SHIFT
;
1068 s
->attrib
|= (var
->db
& 1) << SVM_SELECTOR_DB_SHIFT
;
1069 s
->attrib
|= (var
->g
& 1) << SVM_SELECTOR_G_SHIFT
;
1071 if (seg
== VCPU_SREG_CS
)
1073 = (svm
->vmcb
->save
.cs
.attrib
1074 >> SVM_SELECTOR_DPL_SHIFT
) & 3;
1078 static void update_db_intercept(struct kvm_vcpu
*vcpu
)
1080 struct vcpu_svm
*svm
= to_svm(vcpu
);
1082 svm
->vmcb
->control
.intercept_exceptions
&=
1083 ~((1 << DB_VECTOR
) | (1 << BP_VECTOR
));
1085 if (svm
->nmi_singlestep
)
1086 svm
->vmcb
->control
.intercept_exceptions
|= (1 << DB_VECTOR
);
1088 if (vcpu
->guest_debug
& KVM_GUESTDBG_ENABLE
) {
1089 if (vcpu
->guest_debug
&
1090 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
1091 svm
->vmcb
->control
.intercept_exceptions
|=
1093 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
1094 svm
->vmcb
->control
.intercept_exceptions
|=
1097 vcpu
->guest_debug
= 0;
1100 static void svm_guest_debug(struct kvm_vcpu
*vcpu
, struct kvm_guest_debug
*dbg
)
1102 struct vcpu_svm
*svm
= to_svm(vcpu
);
1104 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
)
1105 svm
->vmcb
->save
.dr7
= dbg
->arch
.debugreg
[7];
1107 svm
->vmcb
->save
.dr7
= vcpu
->arch
.dr7
;
1109 update_db_intercept(vcpu
);
1112 static void load_host_msrs(struct kvm_vcpu
*vcpu
)
1114 #ifdef CONFIG_X86_64
1115 wrmsrl(MSR_GS_BASE
, to_svm(vcpu
)->host_gs_base
);
1119 static void save_host_msrs(struct kvm_vcpu
*vcpu
)
1121 #ifdef CONFIG_X86_64
1122 rdmsrl(MSR_GS_BASE
, to_svm(vcpu
)->host_gs_base
);
1126 static void new_asid(struct vcpu_svm
*svm
, struct svm_cpu_data
*sd
)
1128 if (sd
->next_asid
> sd
->max_asid
) {
1129 ++sd
->asid_generation
;
1131 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_FLUSH_ALL_ASID
;
1134 svm
->asid_generation
= sd
->asid_generation
;
1135 svm
->vmcb
->control
.asid
= sd
->next_asid
++;
1138 static int svm_get_dr(struct kvm_vcpu
*vcpu
, int dr
, unsigned long *dest
)
1140 struct vcpu_svm
*svm
= to_svm(vcpu
);
1144 *dest
= vcpu
->arch
.db
[dr
];
1147 if (kvm_read_cr4_bits(vcpu
, X86_CR4_DE
))
1148 return EMULATE_FAIL
; /* will re-inject UD */
1151 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
)
1152 *dest
= vcpu
->arch
.dr6
;
1154 *dest
= svm
->vmcb
->save
.dr6
;
1157 if (kvm_read_cr4_bits(vcpu
, X86_CR4_DE
))
1158 return EMULATE_FAIL
; /* will re-inject UD */
1161 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
)
1162 *dest
= vcpu
->arch
.dr7
;
1164 *dest
= svm
->vmcb
->save
.dr7
;
1168 return EMULATE_DONE
;
1171 static int svm_set_dr(struct kvm_vcpu
*vcpu
, int dr
, unsigned long value
)
1173 struct vcpu_svm
*svm
= to_svm(vcpu
);
1177 vcpu
->arch
.db
[dr
] = value
;
1178 if (!(vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
))
1179 vcpu
->arch
.eff_db
[dr
] = value
;
1182 if (kvm_read_cr4_bits(vcpu
, X86_CR4_DE
))
1183 return EMULATE_FAIL
; /* will re-inject UD */
1186 vcpu
->arch
.dr6
= (value
& DR6_VOLATILE
) | DR6_FIXED_1
;
1189 if (kvm_read_cr4_bits(vcpu
, X86_CR4_DE
))
1190 return EMULATE_FAIL
; /* will re-inject UD */
1193 vcpu
->arch
.dr7
= (value
& DR7_VOLATILE
) | DR7_FIXED_1
;
1194 if (!(vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
)) {
1195 svm
->vmcb
->save
.dr7
= vcpu
->arch
.dr7
;
1196 vcpu
->arch
.switch_db_regs
= (value
& DR7_BP_EN_MASK
);
1201 return EMULATE_DONE
;
1204 static int pf_interception(struct vcpu_svm
*svm
)
1209 fault_address
= svm
->vmcb
->control
.exit_info_2
;
1210 error_code
= svm
->vmcb
->control
.exit_info_1
;
1212 trace_kvm_page_fault(fault_address
, error_code
);
1213 if (!npt_enabled
&& kvm_event_needs_reinjection(&svm
->vcpu
))
1214 kvm_mmu_unprotect_page_virt(&svm
->vcpu
, fault_address
);
1215 return kvm_mmu_page_fault(&svm
->vcpu
, fault_address
, error_code
);
1218 static int db_interception(struct vcpu_svm
*svm
)
1220 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
1222 if (!(svm
->vcpu
.guest_debug
&
1223 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
)) &&
1224 !svm
->nmi_singlestep
) {
1225 kvm_queue_exception(&svm
->vcpu
, DB_VECTOR
);
1229 if (svm
->nmi_singlestep
) {
1230 svm
->nmi_singlestep
= false;
1231 if (!(svm
->vcpu
.guest_debug
& KVM_GUESTDBG_SINGLESTEP
))
1232 svm
->vmcb
->save
.rflags
&=
1233 ~(X86_EFLAGS_TF
| X86_EFLAGS_RF
);
1234 update_db_intercept(&svm
->vcpu
);
1237 if (svm
->vcpu
.guest_debug
&
1238 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
)){
1239 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
1240 kvm_run
->debug
.arch
.pc
=
1241 svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
1242 kvm_run
->debug
.arch
.exception
= DB_VECTOR
;
1249 static int bp_interception(struct vcpu_svm
*svm
)
1251 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
1253 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
1254 kvm_run
->debug
.arch
.pc
= svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
1255 kvm_run
->debug
.arch
.exception
= BP_VECTOR
;
1259 static int ud_interception(struct vcpu_svm
*svm
)
1263 er
= emulate_instruction(&svm
->vcpu
, 0, 0, EMULTYPE_TRAP_UD
);
1264 if (er
!= EMULATE_DONE
)
1265 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
1269 static void svm_fpu_activate(struct kvm_vcpu
*vcpu
)
1271 struct vcpu_svm
*svm
= to_svm(vcpu
);
1272 svm
->vmcb
->control
.intercept_exceptions
&= ~(1 << NM_VECTOR
);
1273 svm
->vcpu
.fpu_active
= 1;
1274 update_cr0_intercept(svm
);
1277 static int nm_interception(struct vcpu_svm
*svm
)
1279 svm_fpu_activate(&svm
->vcpu
);
1283 static int mc_interception(struct vcpu_svm
*svm
)
1286 * On an #MC intercept the MCE handler is not called automatically in
1287 * the host. So do it by hand here.
1291 /* not sure if we ever come back to this point */
1296 static int shutdown_interception(struct vcpu_svm
*svm
)
1298 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
1301 * VMCB is undefined after a SHUTDOWN intercept
1302 * so reinitialize it.
1304 clear_page(svm
->vmcb
);
1307 kvm_run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
1311 static int io_interception(struct vcpu_svm
*svm
)
1313 u32 io_info
= svm
->vmcb
->control
.exit_info_1
; /* address size bug? */
1314 int size
, in
, string
;
1317 ++svm
->vcpu
.stat
.io_exits
;
1319 svm
->next_rip
= svm
->vmcb
->control
.exit_info_2
;
1321 string
= (io_info
& SVM_IOIO_STR_MASK
) != 0;
1324 if (emulate_instruction(&svm
->vcpu
,
1325 0, 0, 0) == EMULATE_DO_MMIO
)
1330 in
= (io_info
& SVM_IOIO_TYPE_MASK
) != 0;
1331 port
= io_info
>> 16;
1332 size
= (io_info
& SVM_IOIO_SIZE_MASK
) >> SVM_IOIO_SIZE_SHIFT
;
1334 skip_emulated_instruction(&svm
->vcpu
);
1335 return kvm_emulate_pio(&svm
->vcpu
, in
, size
, port
);
1338 static int nmi_interception(struct vcpu_svm
*svm
)
1343 static int intr_interception(struct vcpu_svm
*svm
)
1345 ++svm
->vcpu
.stat
.irq_exits
;
1349 static int nop_on_interception(struct vcpu_svm
*svm
)
1354 static int halt_interception(struct vcpu_svm
*svm
)
1356 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 1;
1357 skip_emulated_instruction(&svm
->vcpu
);
1358 return kvm_emulate_halt(&svm
->vcpu
);
1361 static int vmmcall_interception(struct vcpu_svm
*svm
)
1363 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
1364 skip_emulated_instruction(&svm
->vcpu
);
1365 kvm_emulate_hypercall(&svm
->vcpu
);
1369 static int nested_svm_check_permissions(struct vcpu_svm
*svm
)
1371 if (!(svm
->vcpu
.arch
.efer
& EFER_SVME
)
1372 || !is_paging(&svm
->vcpu
)) {
1373 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
1377 if (svm
->vmcb
->save
.cpl
) {
1378 kvm_inject_gp(&svm
->vcpu
, 0);
1385 static int nested_svm_check_exception(struct vcpu_svm
*svm
, unsigned nr
,
1386 bool has_error_code
, u32 error_code
)
1390 if (!is_nested(svm
))
1393 svm
->vmcb
->control
.exit_code
= SVM_EXIT_EXCP_BASE
+ nr
;
1394 svm
->vmcb
->control
.exit_code_hi
= 0;
1395 svm
->vmcb
->control
.exit_info_1
= error_code
;
1396 svm
->vmcb
->control
.exit_info_2
= svm
->vcpu
.arch
.cr2
;
1398 vmexit
= nested_svm_intercept(svm
);
1399 if (vmexit
== NESTED_EXIT_DONE
)
1400 svm
->nested
.exit_required
= true;
1405 static inline int nested_svm_intr(struct vcpu_svm
*svm
)
1407 if (!is_nested(svm
))
1410 if (!(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
))
1413 if (!(svm
->vcpu
.arch
.hflags
& HF_HIF_MASK
))
1416 svm
->vmcb
->control
.exit_code
= SVM_EXIT_INTR
;
1418 if (svm
->nested
.intercept
& 1ULL) {
1420 * The #vmexit can't be emulated here directly because this
1421 * code path runs with irqs and preemtion disabled. A
1422 * #vmexit emulation might sleep. Only signal request for
1425 svm
->nested
.exit_required
= true;
1426 trace_kvm_nested_intr_vmexit(svm
->vmcb
->save
.rip
);
1433 static void *nested_svm_map(struct vcpu_svm
*svm
, u64 gpa
, struct page
**_page
)
1439 page
= gfn_to_page(svm
->vcpu
.kvm
, gpa
>> PAGE_SHIFT
);
1440 if (is_error_page(page
))
1448 kvm_release_page_clean(page
);
1449 kvm_inject_gp(&svm
->vcpu
, 0);
1454 static void nested_svm_unmap(struct page
*page
)
1457 kvm_release_page_dirty(page
);
1460 static bool nested_svm_exit_handled_msr(struct vcpu_svm
*svm
)
1462 u32 param
= svm
->vmcb
->control
.exit_info_1
& 1;
1463 u32 msr
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
1468 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_MSR_PROT
)))
1476 case 0xc0000000 ... 0xc0001fff:
1477 t0
= (8192 + msr
- 0xc0000000) * 2;
1481 case 0xc0010000 ... 0xc0011fff:
1482 t0
= (16384 + msr
- 0xc0010000) * 2;
1491 if (!kvm_read_guest(svm
->vcpu
.kvm
, svm
->nested
.vmcb_msrpm
+ t1
, &val
, 1))
1492 ret
= val
& ((1 << param
) << t0
);
1498 static int nested_svm_exit_special(struct vcpu_svm
*svm
)
1500 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
1502 switch (exit_code
) {
1505 return NESTED_EXIT_HOST
;
1506 /* For now we are always handling NPFs when using them */
1509 return NESTED_EXIT_HOST
;
1511 /* When we're shadowing, trap PFs */
1512 case SVM_EXIT_EXCP_BASE
+ PF_VECTOR
:
1514 return NESTED_EXIT_HOST
;
1520 return NESTED_EXIT_CONTINUE
;
1524 * If this function returns true, this #vmexit was already handled
1526 static int nested_svm_intercept(struct vcpu_svm
*svm
)
1528 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
1529 int vmexit
= NESTED_EXIT_HOST
;
1531 switch (exit_code
) {
1533 vmexit
= nested_svm_exit_handled_msr(svm
);
1535 case SVM_EXIT_READ_CR0
... SVM_EXIT_READ_CR8
: {
1536 u32 cr_bits
= 1 << (exit_code
- SVM_EXIT_READ_CR0
);
1537 if (svm
->nested
.intercept_cr_read
& cr_bits
)
1538 vmexit
= NESTED_EXIT_DONE
;
1541 case SVM_EXIT_WRITE_CR0
... SVM_EXIT_WRITE_CR8
: {
1542 u32 cr_bits
= 1 << (exit_code
- SVM_EXIT_WRITE_CR0
);
1543 if (svm
->nested
.intercept_cr_write
& cr_bits
)
1544 vmexit
= NESTED_EXIT_DONE
;
1547 case SVM_EXIT_READ_DR0
... SVM_EXIT_READ_DR7
: {
1548 u32 dr_bits
= 1 << (exit_code
- SVM_EXIT_READ_DR0
);
1549 if (svm
->nested
.intercept_dr_read
& dr_bits
)
1550 vmexit
= NESTED_EXIT_DONE
;
1553 case SVM_EXIT_WRITE_DR0
... SVM_EXIT_WRITE_DR7
: {
1554 u32 dr_bits
= 1 << (exit_code
- SVM_EXIT_WRITE_DR0
);
1555 if (svm
->nested
.intercept_dr_write
& dr_bits
)
1556 vmexit
= NESTED_EXIT_DONE
;
1559 case SVM_EXIT_EXCP_BASE
... SVM_EXIT_EXCP_BASE
+ 0x1f: {
1560 u32 excp_bits
= 1 << (exit_code
- SVM_EXIT_EXCP_BASE
);
1561 if (svm
->nested
.intercept_exceptions
& excp_bits
)
1562 vmexit
= NESTED_EXIT_DONE
;
1566 u64 exit_bits
= 1ULL << (exit_code
- SVM_EXIT_INTR
);
1567 if (svm
->nested
.intercept
& exit_bits
)
1568 vmexit
= NESTED_EXIT_DONE
;
1575 static int nested_svm_exit_handled(struct vcpu_svm
*svm
)
1579 vmexit
= nested_svm_intercept(svm
);
1581 if (vmexit
== NESTED_EXIT_DONE
)
1582 nested_svm_vmexit(svm
);
1587 static inline void copy_vmcb_control_area(struct vmcb
*dst_vmcb
, struct vmcb
*from_vmcb
)
1589 struct vmcb_control_area
*dst
= &dst_vmcb
->control
;
1590 struct vmcb_control_area
*from
= &from_vmcb
->control
;
1592 dst
->intercept_cr_read
= from
->intercept_cr_read
;
1593 dst
->intercept_cr_write
= from
->intercept_cr_write
;
1594 dst
->intercept_dr_read
= from
->intercept_dr_read
;
1595 dst
->intercept_dr_write
= from
->intercept_dr_write
;
1596 dst
->intercept_exceptions
= from
->intercept_exceptions
;
1597 dst
->intercept
= from
->intercept
;
1598 dst
->iopm_base_pa
= from
->iopm_base_pa
;
1599 dst
->msrpm_base_pa
= from
->msrpm_base_pa
;
1600 dst
->tsc_offset
= from
->tsc_offset
;
1601 dst
->asid
= from
->asid
;
1602 dst
->tlb_ctl
= from
->tlb_ctl
;
1603 dst
->int_ctl
= from
->int_ctl
;
1604 dst
->int_vector
= from
->int_vector
;
1605 dst
->int_state
= from
->int_state
;
1606 dst
->exit_code
= from
->exit_code
;
1607 dst
->exit_code_hi
= from
->exit_code_hi
;
1608 dst
->exit_info_1
= from
->exit_info_1
;
1609 dst
->exit_info_2
= from
->exit_info_2
;
1610 dst
->exit_int_info
= from
->exit_int_info
;
1611 dst
->exit_int_info_err
= from
->exit_int_info_err
;
1612 dst
->nested_ctl
= from
->nested_ctl
;
1613 dst
->event_inj
= from
->event_inj
;
1614 dst
->event_inj_err
= from
->event_inj_err
;
1615 dst
->nested_cr3
= from
->nested_cr3
;
1616 dst
->lbr_ctl
= from
->lbr_ctl
;
1619 static int nested_svm_vmexit(struct vcpu_svm
*svm
)
1621 struct vmcb
*nested_vmcb
;
1622 struct vmcb
*hsave
= svm
->nested
.hsave
;
1623 struct vmcb
*vmcb
= svm
->vmcb
;
1626 trace_kvm_nested_vmexit_inject(vmcb
->control
.exit_code
,
1627 vmcb
->control
.exit_info_1
,
1628 vmcb
->control
.exit_info_2
,
1629 vmcb
->control
.exit_int_info
,
1630 vmcb
->control
.exit_int_info_err
);
1632 nested_vmcb
= nested_svm_map(svm
, svm
->nested
.vmcb
, &page
);
1636 /* Give the current vmcb to the guest */
1639 nested_vmcb
->save
.es
= vmcb
->save
.es
;
1640 nested_vmcb
->save
.cs
= vmcb
->save
.cs
;
1641 nested_vmcb
->save
.ss
= vmcb
->save
.ss
;
1642 nested_vmcb
->save
.ds
= vmcb
->save
.ds
;
1643 nested_vmcb
->save
.gdtr
= vmcb
->save
.gdtr
;
1644 nested_vmcb
->save
.idtr
= vmcb
->save
.idtr
;
1645 nested_vmcb
->save
.cr0
= kvm_read_cr0(&svm
->vcpu
);
1647 nested_vmcb
->save
.cr3
= vmcb
->save
.cr3
;
1649 nested_vmcb
->save
.cr3
= svm
->vcpu
.arch
.cr3
;
1650 nested_vmcb
->save
.cr2
= vmcb
->save
.cr2
;
1651 nested_vmcb
->save
.cr4
= svm
->vcpu
.arch
.cr4
;
1652 nested_vmcb
->save
.rflags
= vmcb
->save
.rflags
;
1653 nested_vmcb
->save
.rip
= vmcb
->save
.rip
;
1654 nested_vmcb
->save
.rsp
= vmcb
->save
.rsp
;
1655 nested_vmcb
->save
.rax
= vmcb
->save
.rax
;
1656 nested_vmcb
->save
.dr7
= vmcb
->save
.dr7
;
1657 nested_vmcb
->save
.dr6
= vmcb
->save
.dr6
;
1658 nested_vmcb
->save
.cpl
= vmcb
->save
.cpl
;
1660 nested_vmcb
->control
.int_ctl
= vmcb
->control
.int_ctl
;
1661 nested_vmcb
->control
.int_vector
= vmcb
->control
.int_vector
;
1662 nested_vmcb
->control
.int_state
= vmcb
->control
.int_state
;
1663 nested_vmcb
->control
.exit_code
= vmcb
->control
.exit_code
;
1664 nested_vmcb
->control
.exit_code_hi
= vmcb
->control
.exit_code_hi
;
1665 nested_vmcb
->control
.exit_info_1
= vmcb
->control
.exit_info_1
;
1666 nested_vmcb
->control
.exit_info_2
= vmcb
->control
.exit_info_2
;
1667 nested_vmcb
->control
.exit_int_info
= vmcb
->control
.exit_int_info
;
1668 nested_vmcb
->control
.exit_int_info_err
= vmcb
->control
.exit_int_info_err
;
1671 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1672 * to make sure that we do not lose injected events. So check event_inj
1673 * here and copy it to exit_int_info if it is valid.
1674 * Exit_int_info and event_inj can't be both valid because the case
1675 * below only happens on a VMRUN instruction intercept which has
1676 * no valid exit_int_info set.
1678 if (vmcb
->control
.event_inj
& SVM_EVTINJ_VALID
) {
1679 struct vmcb_control_area
*nc
= &nested_vmcb
->control
;
1681 nc
->exit_int_info
= vmcb
->control
.event_inj
;
1682 nc
->exit_int_info_err
= vmcb
->control
.event_inj_err
;
1685 nested_vmcb
->control
.tlb_ctl
= 0;
1686 nested_vmcb
->control
.event_inj
= 0;
1687 nested_vmcb
->control
.event_inj_err
= 0;
1689 /* We always set V_INTR_MASKING and remember the old value in hflags */
1690 if (!(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
))
1691 nested_vmcb
->control
.int_ctl
&= ~V_INTR_MASKING_MASK
;
1693 /* Restore the original control entries */
1694 copy_vmcb_control_area(vmcb
, hsave
);
1696 kvm_clear_exception_queue(&svm
->vcpu
);
1697 kvm_clear_interrupt_queue(&svm
->vcpu
);
1699 /* Restore selected save entries */
1700 svm
->vmcb
->save
.es
= hsave
->save
.es
;
1701 svm
->vmcb
->save
.cs
= hsave
->save
.cs
;
1702 svm
->vmcb
->save
.ss
= hsave
->save
.ss
;
1703 svm
->vmcb
->save
.ds
= hsave
->save
.ds
;
1704 svm
->vmcb
->save
.gdtr
= hsave
->save
.gdtr
;
1705 svm
->vmcb
->save
.idtr
= hsave
->save
.idtr
;
1706 svm
->vmcb
->save
.rflags
= hsave
->save
.rflags
;
1707 svm_set_efer(&svm
->vcpu
, hsave
->save
.efer
);
1708 svm_set_cr0(&svm
->vcpu
, hsave
->save
.cr0
| X86_CR0_PE
);
1709 svm_set_cr4(&svm
->vcpu
, hsave
->save
.cr4
);
1711 svm
->vmcb
->save
.cr3
= hsave
->save
.cr3
;
1712 svm
->vcpu
.arch
.cr3
= hsave
->save
.cr3
;
1714 kvm_set_cr3(&svm
->vcpu
, hsave
->save
.cr3
);
1716 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
, hsave
->save
.rax
);
1717 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RSP
, hsave
->save
.rsp
);
1718 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RIP
, hsave
->save
.rip
);
1719 svm
->vmcb
->save
.dr7
= 0;
1720 svm
->vmcb
->save
.cpl
= 0;
1721 svm
->vmcb
->control
.exit_int_info
= 0;
1723 /* Exit nested SVM mode */
1724 svm
->nested
.vmcb
= 0;
1726 nested_svm_unmap(page
);
1728 kvm_mmu_reset_context(&svm
->vcpu
);
1729 kvm_mmu_load(&svm
->vcpu
);
1734 static bool nested_svm_vmrun_msrpm(struct vcpu_svm
*svm
)
1740 nested_msrpm
= nested_svm_map(svm
, svm
->nested
.vmcb_msrpm
, &page
);
1744 for (i
=0; i
< PAGE_SIZE
* (1 << MSRPM_ALLOC_ORDER
) / 4; i
++)
1745 svm
->nested
.msrpm
[i
] = svm
->msrpm
[i
] | nested_msrpm
[i
];
1747 svm
->vmcb
->control
.msrpm_base_pa
= __pa(svm
->nested
.msrpm
);
1749 nested_svm_unmap(page
);
1754 static bool nested_svm_vmrun(struct vcpu_svm
*svm
)
1756 struct vmcb
*nested_vmcb
;
1757 struct vmcb
*hsave
= svm
->nested
.hsave
;
1758 struct vmcb
*vmcb
= svm
->vmcb
;
1761 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
1765 /* nested_vmcb is our indicator if nested SVM is activated */
1766 svm
->nested
.vmcb
= svm
->vmcb
->save
.rax
;
1768 trace_kvm_nested_vmrun(svm
->vmcb
->save
.rip
- 3, svm
->nested
.vmcb
,
1769 nested_vmcb
->save
.rip
,
1770 nested_vmcb
->control
.int_ctl
,
1771 nested_vmcb
->control
.event_inj
,
1772 nested_vmcb
->control
.nested_ctl
);
1774 /* Clear internal status */
1775 kvm_clear_exception_queue(&svm
->vcpu
);
1776 kvm_clear_interrupt_queue(&svm
->vcpu
);
1778 /* Save the old vmcb, so we don't need to pick what we save, but
1779 can restore everything when a VMEXIT occurs */
1780 hsave
->save
.es
= vmcb
->save
.es
;
1781 hsave
->save
.cs
= vmcb
->save
.cs
;
1782 hsave
->save
.ss
= vmcb
->save
.ss
;
1783 hsave
->save
.ds
= vmcb
->save
.ds
;
1784 hsave
->save
.gdtr
= vmcb
->save
.gdtr
;
1785 hsave
->save
.idtr
= vmcb
->save
.idtr
;
1786 hsave
->save
.efer
= svm
->vcpu
.arch
.efer
;
1787 hsave
->save
.cr0
= kvm_read_cr0(&svm
->vcpu
);
1788 hsave
->save
.cr4
= svm
->vcpu
.arch
.cr4
;
1789 hsave
->save
.rflags
= vmcb
->save
.rflags
;
1790 hsave
->save
.rip
= svm
->next_rip
;
1791 hsave
->save
.rsp
= vmcb
->save
.rsp
;
1792 hsave
->save
.rax
= vmcb
->save
.rax
;
1794 hsave
->save
.cr3
= vmcb
->save
.cr3
;
1796 hsave
->save
.cr3
= svm
->vcpu
.arch
.cr3
;
1798 copy_vmcb_control_area(hsave
, vmcb
);
1800 if (svm
->vmcb
->save
.rflags
& X86_EFLAGS_IF
)
1801 svm
->vcpu
.arch
.hflags
|= HF_HIF_MASK
;
1803 svm
->vcpu
.arch
.hflags
&= ~HF_HIF_MASK
;
1805 /* Load the nested guest state */
1806 svm
->vmcb
->save
.es
= nested_vmcb
->save
.es
;
1807 svm
->vmcb
->save
.cs
= nested_vmcb
->save
.cs
;
1808 svm
->vmcb
->save
.ss
= nested_vmcb
->save
.ss
;
1809 svm
->vmcb
->save
.ds
= nested_vmcb
->save
.ds
;
1810 svm
->vmcb
->save
.gdtr
= nested_vmcb
->save
.gdtr
;
1811 svm
->vmcb
->save
.idtr
= nested_vmcb
->save
.idtr
;
1812 svm
->vmcb
->save
.rflags
= nested_vmcb
->save
.rflags
;
1813 svm_set_efer(&svm
->vcpu
, nested_vmcb
->save
.efer
);
1814 svm_set_cr0(&svm
->vcpu
, nested_vmcb
->save
.cr0
);
1815 svm_set_cr4(&svm
->vcpu
, nested_vmcb
->save
.cr4
);
1817 svm
->vmcb
->save
.cr3
= nested_vmcb
->save
.cr3
;
1818 svm
->vcpu
.arch
.cr3
= nested_vmcb
->save
.cr3
;
1820 kvm_set_cr3(&svm
->vcpu
, nested_vmcb
->save
.cr3
);
1821 kvm_mmu_reset_context(&svm
->vcpu
);
1823 svm
->vmcb
->save
.cr2
= svm
->vcpu
.arch
.cr2
= nested_vmcb
->save
.cr2
;
1824 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
, nested_vmcb
->save
.rax
);
1825 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RSP
, nested_vmcb
->save
.rsp
);
1826 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RIP
, nested_vmcb
->save
.rip
);
1827 /* In case we don't even reach vcpu_run, the fields are not updated */
1828 svm
->vmcb
->save
.rax
= nested_vmcb
->save
.rax
;
1829 svm
->vmcb
->save
.rsp
= nested_vmcb
->save
.rsp
;
1830 svm
->vmcb
->save
.rip
= nested_vmcb
->save
.rip
;
1831 svm
->vmcb
->save
.dr7
= nested_vmcb
->save
.dr7
;
1832 svm
->vmcb
->save
.dr6
= nested_vmcb
->save
.dr6
;
1833 svm
->vmcb
->save
.cpl
= nested_vmcb
->save
.cpl
;
1835 svm
->nested
.vmcb_msrpm
= nested_vmcb
->control
.msrpm_base_pa
;
1837 /* cache intercepts */
1838 svm
->nested
.intercept_cr_read
= nested_vmcb
->control
.intercept_cr_read
;
1839 svm
->nested
.intercept_cr_write
= nested_vmcb
->control
.intercept_cr_write
;
1840 svm
->nested
.intercept_dr_read
= nested_vmcb
->control
.intercept_dr_read
;
1841 svm
->nested
.intercept_dr_write
= nested_vmcb
->control
.intercept_dr_write
;
1842 svm
->nested
.intercept_exceptions
= nested_vmcb
->control
.intercept_exceptions
;
1843 svm
->nested
.intercept
= nested_vmcb
->control
.intercept
;
1845 force_new_asid(&svm
->vcpu
);
1846 svm
->vmcb
->control
.int_ctl
= nested_vmcb
->control
.int_ctl
| V_INTR_MASKING_MASK
;
1847 if (nested_vmcb
->control
.int_ctl
& V_INTR_MASKING_MASK
)
1848 svm
->vcpu
.arch
.hflags
|= HF_VINTR_MASK
;
1850 svm
->vcpu
.arch
.hflags
&= ~HF_VINTR_MASK
;
1852 if (svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
) {
1853 /* We only want the cr8 intercept bits of the guest */
1854 svm
->vmcb
->control
.intercept_cr_read
&= ~INTERCEPT_CR8_MASK
;
1855 svm
->vmcb
->control
.intercept_cr_write
&= ~INTERCEPT_CR8_MASK
;
1858 /* We don't want a nested guest to be more powerful than the guest,
1859 so all intercepts are ORed */
1860 svm
->vmcb
->control
.intercept_cr_read
|=
1861 nested_vmcb
->control
.intercept_cr_read
;
1862 svm
->vmcb
->control
.intercept_cr_write
|=
1863 nested_vmcb
->control
.intercept_cr_write
;
1864 svm
->vmcb
->control
.intercept_dr_read
|=
1865 nested_vmcb
->control
.intercept_dr_read
;
1866 svm
->vmcb
->control
.intercept_dr_write
|=
1867 nested_vmcb
->control
.intercept_dr_write
;
1868 svm
->vmcb
->control
.intercept_exceptions
|=
1869 nested_vmcb
->control
.intercept_exceptions
;
1871 svm
->vmcb
->control
.intercept
|= nested_vmcb
->control
.intercept
;
1873 svm
->vmcb
->control
.lbr_ctl
= nested_vmcb
->control
.lbr_ctl
;
1874 svm
->vmcb
->control
.int_vector
= nested_vmcb
->control
.int_vector
;
1875 svm
->vmcb
->control
.int_state
= nested_vmcb
->control
.int_state
;
1876 svm
->vmcb
->control
.tsc_offset
+= nested_vmcb
->control
.tsc_offset
;
1877 svm
->vmcb
->control
.event_inj
= nested_vmcb
->control
.event_inj
;
1878 svm
->vmcb
->control
.event_inj_err
= nested_vmcb
->control
.event_inj_err
;
1880 nested_svm_unmap(page
);
1887 static void nested_svm_vmloadsave(struct vmcb
*from_vmcb
, struct vmcb
*to_vmcb
)
1889 to_vmcb
->save
.fs
= from_vmcb
->save
.fs
;
1890 to_vmcb
->save
.gs
= from_vmcb
->save
.gs
;
1891 to_vmcb
->save
.tr
= from_vmcb
->save
.tr
;
1892 to_vmcb
->save
.ldtr
= from_vmcb
->save
.ldtr
;
1893 to_vmcb
->save
.kernel_gs_base
= from_vmcb
->save
.kernel_gs_base
;
1894 to_vmcb
->save
.star
= from_vmcb
->save
.star
;
1895 to_vmcb
->save
.lstar
= from_vmcb
->save
.lstar
;
1896 to_vmcb
->save
.cstar
= from_vmcb
->save
.cstar
;
1897 to_vmcb
->save
.sfmask
= from_vmcb
->save
.sfmask
;
1898 to_vmcb
->save
.sysenter_cs
= from_vmcb
->save
.sysenter_cs
;
1899 to_vmcb
->save
.sysenter_esp
= from_vmcb
->save
.sysenter_esp
;
1900 to_vmcb
->save
.sysenter_eip
= from_vmcb
->save
.sysenter_eip
;
1903 static int vmload_interception(struct vcpu_svm
*svm
)
1905 struct vmcb
*nested_vmcb
;
1908 if (nested_svm_check_permissions(svm
))
1911 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
1912 skip_emulated_instruction(&svm
->vcpu
);
1914 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
1918 nested_svm_vmloadsave(nested_vmcb
, svm
->vmcb
);
1919 nested_svm_unmap(page
);
1924 static int vmsave_interception(struct vcpu_svm
*svm
)
1926 struct vmcb
*nested_vmcb
;
1929 if (nested_svm_check_permissions(svm
))
1932 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
1933 skip_emulated_instruction(&svm
->vcpu
);
1935 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
1939 nested_svm_vmloadsave(svm
->vmcb
, nested_vmcb
);
1940 nested_svm_unmap(page
);
1945 static int vmrun_interception(struct vcpu_svm
*svm
)
1947 if (nested_svm_check_permissions(svm
))
1950 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
1951 skip_emulated_instruction(&svm
->vcpu
);
1953 if (!nested_svm_vmrun(svm
))
1956 if (!nested_svm_vmrun_msrpm(svm
))
1963 svm
->vmcb
->control
.exit_code
= SVM_EXIT_ERR
;
1964 svm
->vmcb
->control
.exit_code_hi
= 0;
1965 svm
->vmcb
->control
.exit_info_1
= 0;
1966 svm
->vmcb
->control
.exit_info_2
= 0;
1968 nested_svm_vmexit(svm
);
1973 static int stgi_interception(struct vcpu_svm
*svm
)
1975 if (nested_svm_check_permissions(svm
))
1978 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
1979 skip_emulated_instruction(&svm
->vcpu
);
1986 static int clgi_interception(struct vcpu_svm
*svm
)
1988 if (nested_svm_check_permissions(svm
))
1991 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
1992 skip_emulated_instruction(&svm
->vcpu
);
1996 /* After a CLGI no interrupts should come */
1997 svm_clear_vintr(svm
);
1998 svm
->vmcb
->control
.int_ctl
&= ~V_IRQ_MASK
;
2003 static int invlpga_interception(struct vcpu_svm
*svm
)
2005 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
2007 trace_kvm_invlpga(svm
->vmcb
->save
.rip
, vcpu
->arch
.regs
[VCPU_REGS_RCX
],
2008 vcpu
->arch
.regs
[VCPU_REGS_RAX
]);
2010 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2011 kvm_mmu_invlpg(vcpu
, vcpu
->arch
.regs
[VCPU_REGS_RAX
]);
2013 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2014 skip_emulated_instruction(&svm
->vcpu
);
2018 static int skinit_interception(struct vcpu_svm
*svm
)
2020 trace_kvm_skinit(svm
->vmcb
->save
.rip
, svm
->vcpu
.arch
.regs
[VCPU_REGS_RAX
]);
2022 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
2026 static int invalid_op_interception(struct vcpu_svm
*svm
)
2028 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
2032 static int task_switch_interception(struct vcpu_svm
*svm
)
2036 int int_type
= svm
->vmcb
->control
.exit_int_info
&
2037 SVM_EXITINTINFO_TYPE_MASK
;
2038 int int_vec
= svm
->vmcb
->control
.exit_int_info
& SVM_EVTINJ_VEC_MASK
;
2040 svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_TYPE_MASK
;
2042 svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_VALID
;
2044 tss_selector
= (u16
)svm
->vmcb
->control
.exit_info_1
;
2046 if (svm
->vmcb
->control
.exit_info_2
&
2047 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET
))
2048 reason
= TASK_SWITCH_IRET
;
2049 else if (svm
->vmcb
->control
.exit_info_2
&
2050 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP
))
2051 reason
= TASK_SWITCH_JMP
;
2053 reason
= TASK_SWITCH_GATE
;
2055 reason
= TASK_SWITCH_CALL
;
2057 if (reason
== TASK_SWITCH_GATE
) {
2059 case SVM_EXITINTINFO_TYPE_NMI
:
2060 svm
->vcpu
.arch
.nmi_injected
= false;
2062 case SVM_EXITINTINFO_TYPE_EXEPT
:
2063 kvm_clear_exception_queue(&svm
->vcpu
);
2065 case SVM_EXITINTINFO_TYPE_INTR
:
2066 kvm_clear_interrupt_queue(&svm
->vcpu
);
2073 if (reason
!= TASK_SWITCH_GATE
||
2074 int_type
== SVM_EXITINTINFO_TYPE_SOFT
||
2075 (int_type
== SVM_EXITINTINFO_TYPE_EXEPT
&&
2076 (int_vec
== OF_VECTOR
|| int_vec
== BP_VECTOR
)))
2077 skip_emulated_instruction(&svm
->vcpu
);
2079 return kvm_task_switch(&svm
->vcpu
, tss_selector
, reason
);
2082 static int cpuid_interception(struct vcpu_svm
*svm
)
2084 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
2085 kvm_emulate_cpuid(&svm
->vcpu
);
2089 static int iret_interception(struct vcpu_svm
*svm
)
2091 ++svm
->vcpu
.stat
.nmi_window_exits
;
2092 svm
->vmcb
->control
.intercept
&= ~(1UL << INTERCEPT_IRET
);
2093 svm
->vcpu
.arch
.hflags
|= HF_IRET_MASK
;
2097 static int invlpg_interception(struct vcpu_svm
*svm
)
2099 if (emulate_instruction(&svm
->vcpu
, 0, 0, 0) != EMULATE_DONE
)
2100 pr_unimpl(&svm
->vcpu
, "%s: failed\n", __func__
);
2104 static int emulate_on_interception(struct vcpu_svm
*svm
)
2106 if (emulate_instruction(&svm
->vcpu
, 0, 0, 0) != EMULATE_DONE
)
2107 pr_unimpl(&svm
->vcpu
, "%s: failed\n", __func__
);
2111 static int cr8_write_interception(struct vcpu_svm
*svm
)
2113 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
2115 u8 cr8_prev
= kvm_get_cr8(&svm
->vcpu
);
2116 /* instruction emulation calls kvm_set_cr8() */
2117 emulate_instruction(&svm
->vcpu
, 0, 0, 0);
2118 if (irqchip_in_kernel(svm
->vcpu
.kvm
)) {
2119 svm
->vmcb
->control
.intercept_cr_write
&= ~INTERCEPT_CR8_MASK
;
2122 if (cr8_prev
<= kvm_get_cr8(&svm
->vcpu
))
2124 kvm_run
->exit_reason
= KVM_EXIT_SET_TPR
;
2128 static int svm_get_msr(struct kvm_vcpu
*vcpu
, unsigned ecx
, u64
*data
)
2130 struct vcpu_svm
*svm
= to_svm(vcpu
);
2133 case MSR_IA32_TSC
: {
2137 tsc_offset
= svm
->nested
.hsave
->control
.tsc_offset
;
2139 tsc_offset
= svm
->vmcb
->control
.tsc_offset
;
2141 *data
= tsc_offset
+ native_read_tsc();
2145 *data
= svm
->vmcb
->save
.star
;
2147 #ifdef CONFIG_X86_64
2149 *data
= svm
->vmcb
->save
.lstar
;
2152 *data
= svm
->vmcb
->save
.cstar
;
2154 case MSR_KERNEL_GS_BASE
:
2155 *data
= svm
->vmcb
->save
.kernel_gs_base
;
2157 case MSR_SYSCALL_MASK
:
2158 *data
= svm
->vmcb
->save
.sfmask
;
2161 case MSR_IA32_SYSENTER_CS
:
2162 *data
= svm
->vmcb
->save
.sysenter_cs
;
2164 case MSR_IA32_SYSENTER_EIP
:
2165 *data
= svm
->sysenter_eip
;
2167 case MSR_IA32_SYSENTER_ESP
:
2168 *data
= svm
->sysenter_esp
;
2170 /* Nobody will change the following 5 values in the VMCB so
2171 we can safely return them on rdmsr. They will always be 0
2172 until LBRV is implemented. */
2173 case MSR_IA32_DEBUGCTLMSR
:
2174 *data
= svm
->vmcb
->save
.dbgctl
;
2176 case MSR_IA32_LASTBRANCHFROMIP
:
2177 *data
= svm
->vmcb
->save
.br_from
;
2179 case MSR_IA32_LASTBRANCHTOIP
:
2180 *data
= svm
->vmcb
->save
.br_to
;
2182 case MSR_IA32_LASTINTFROMIP
:
2183 *data
= svm
->vmcb
->save
.last_excp_from
;
2185 case MSR_IA32_LASTINTTOIP
:
2186 *data
= svm
->vmcb
->save
.last_excp_to
;
2188 case MSR_VM_HSAVE_PA
:
2189 *data
= svm
->nested
.hsave_msr
;
2194 case MSR_IA32_UCODE_REV
:
2198 return kvm_get_msr_common(vcpu
, ecx
, data
);
2203 static int rdmsr_interception(struct vcpu_svm
*svm
)
2205 u32 ecx
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
2208 if (svm_get_msr(&svm
->vcpu
, ecx
, &data
)) {
2209 trace_kvm_msr_read_ex(ecx
);
2210 kvm_inject_gp(&svm
->vcpu
, 0);
2212 trace_kvm_msr_read(ecx
, data
);
2214 svm
->vcpu
.arch
.regs
[VCPU_REGS_RAX
] = data
& 0xffffffff;
2215 svm
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = data
>> 32;
2216 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
2217 skip_emulated_instruction(&svm
->vcpu
);
2222 static int svm_set_msr(struct kvm_vcpu
*vcpu
, unsigned ecx
, u64 data
)
2224 struct vcpu_svm
*svm
= to_svm(vcpu
);
2227 case MSR_IA32_TSC
: {
2228 u64 tsc_offset
= data
- native_read_tsc();
2229 u64 g_tsc_offset
= 0;
2231 if (is_nested(svm
)) {
2232 g_tsc_offset
= svm
->vmcb
->control
.tsc_offset
-
2233 svm
->nested
.hsave
->control
.tsc_offset
;
2234 svm
->nested
.hsave
->control
.tsc_offset
= tsc_offset
;
2237 svm
->vmcb
->control
.tsc_offset
= tsc_offset
+ g_tsc_offset
;
2242 svm
->vmcb
->save
.star
= data
;
2244 #ifdef CONFIG_X86_64
2246 svm
->vmcb
->save
.lstar
= data
;
2249 svm
->vmcb
->save
.cstar
= data
;
2251 case MSR_KERNEL_GS_BASE
:
2252 svm
->vmcb
->save
.kernel_gs_base
= data
;
2254 case MSR_SYSCALL_MASK
:
2255 svm
->vmcb
->save
.sfmask
= data
;
2258 case MSR_IA32_SYSENTER_CS
:
2259 svm
->vmcb
->save
.sysenter_cs
= data
;
2261 case MSR_IA32_SYSENTER_EIP
:
2262 svm
->sysenter_eip
= data
;
2263 svm
->vmcb
->save
.sysenter_eip
= data
;
2265 case MSR_IA32_SYSENTER_ESP
:
2266 svm
->sysenter_esp
= data
;
2267 svm
->vmcb
->save
.sysenter_esp
= data
;
2269 case MSR_IA32_DEBUGCTLMSR
:
2270 if (!svm_has(SVM_FEATURE_LBRV
)) {
2271 pr_unimpl(vcpu
, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2275 if (data
& DEBUGCTL_RESERVED_BITS
)
2278 svm
->vmcb
->save
.dbgctl
= data
;
2279 if (data
& (1ULL<<0))
2280 svm_enable_lbrv(svm
);
2282 svm_disable_lbrv(svm
);
2284 case MSR_VM_HSAVE_PA
:
2285 svm
->nested
.hsave_msr
= data
;
2289 pr_unimpl(vcpu
, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx
, data
);
2292 return kvm_set_msr_common(vcpu
, ecx
, data
);
2297 static int wrmsr_interception(struct vcpu_svm
*svm
)
2299 u32 ecx
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
2300 u64 data
= (svm
->vcpu
.arch
.regs
[VCPU_REGS_RAX
] & -1u)
2301 | ((u64
)(svm
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
2304 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
2305 if (svm_set_msr(&svm
->vcpu
, ecx
, data
)) {
2306 trace_kvm_msr_write_ex(ecx
, data
);
2307 kvm_inject_gp(&svm
->vcpu
, 0);
2309 trace_kvm_msr_write(ecx
, data
);
2310 skip_emulated_instruction(&svm
->vcpu
);
2315 static int msr_interception(struct vcpu_svm
*svm
)
2317 if (svm
->vmcb
->control
.exit_info_1
)
2318 return wrmsr_interception(svm
);
2320 return rdmsr_interception(svm
);
2323 static int interrupt_window_interception(struct vcpu_svm
*svm
)
2325 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
2327 svm_clear_vintr(svm
);
2328 svm
->vmcb
->control
.int_ctl
&= ~V_IRQ_MASK
;
2330 * If the user space waits to inject interrupts, exit as soon as
2333 if (!irqchip_in_kernel(svm
->vcpu
.kvm
) &&
2334 kvm_run
->request_interrupt_window
&&
2335 !kvm_cpu_has_interrupt(&svm
->vcpu
)) {
2336 ++svm
->vcpu
.stat
.irq_window_exits
;
2337 kvm_run
->exit_reason
= KVM_EXIT_IRQ_WINDOW_OPEN
;
2344 static int pause_interception(struct vcpu_svm
*svm
)
2346 kvm_vcpu_on_spin(&(svm
->vcpu
));
2350 static int (*svm_exit_handlers
[])(struct vcpu_svm
*svm
) = {
2351 [SVM_EXIT_READ_CR0
] = emulate_on_interception
,
2352 [SVM_EXIT_READ_CR3
] = emulate_on_interception
,
2353 [SVM_EXIT_READ_CR4
] = emulate_on_interception
,
2354 [SVM_EXIT_READ_CR8
] = emulate_on_interception
,
2355 [SVM_EXIT_CR0_SEL_WRITE
] = emulate_on_interception
,
2356 [SVM_EXIT_WRITE_CR0
] = emulate_on_interception
,
2357 [SVM_EXIT_WRITE_CR3
] = emulate_on_interception
,
2358 [SVM_EXIT_WRITE_CR4
] = emulate_on_interception
,
2359 [SVM_EXIT_WRITE_CR8
] = cr8_write_interception
,
2360 [SVM_EXIT_READ_DR0
] = emulate_on_interception
,
2361 [SVM_EXIT_READ_DR1
] = emulate_on_interception
,
2362 [SVM_EXIT_READ_DR2
] = emulate_on_interception
,
2363 [SVM_EXIT_READ_DR3
] = emulate_on_interception
,
2364 [SVM_EXIT_READ_DR4
] = emulate_on_interception
,
2365 [SVM_EXIT_READ_DR5
] = emulate_on_interception
,
2366 [SVM_EXIT_READ_DR6
] = emulate_on_interception
,
2367 [SVM_EXIT_READ_DR7
] = emulate_on_interception
,
2368 [SVM_EXIT_WRITE_DR0
] = emulate_on_interception
,
2369 [SVM_EXIT_WRITE_DR1
] = emulate_on_interception
,
2370 [SVM_EXIT_WRITE_DR2
] = emulate_on_interception
,
2371 [SVM_EXIT_WRITE_DR3
] = emulate_on_interception
,
2372 [SVM_EXIT_WRITE_DR4
] = emulate_on_interception
,
2373 [SVM_EXIT_WRITE_DR5
] = emulate_on_interception
,
2374 [SVM_EXIT_WRITE_DR6
] = emulate_on_interception
,
2375 [SVM_EXIT_WRITE_DR7
] = emulate_on_interception
,
2376 [SVM_EXIT_EXCP_BASE
+ DB_VECTOR
] = db_interception
,
2377 [SVM_EXIT_EXCP_BASE
+ BP_VECTOR
] = bp_interception
,
2378 [SVM_EXIT_EXCP_BASE
+ UD_VECTOR
] = ud_interception
,
2379 [SVM_EXIT_EXCP_BASE
+ PF_VECTOR
] = pf_interception
,
2380 [SVM_EXIT_EXCP_BASE
+ NM_VECTOR
] = nm_interception
,
2381 [SVM_EXIT_EXCP_BASE
+ MC_VECTOR
] = mc_interception
,
2382 [SVM_EXIT_INTR
] = intr_interception
,
2383 [SVM_EXIT_NMI
] = nmi_interception
,
2384 [SVM_EXIT_SMI
] = nop_on_interception
,
2385 [SVM_EXIT_INIT
] = nop_on_interception
,
2386 [SVM_EXIT_VINTR
] = interrupt_window_interception
,
2387 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
2388 [SVM_EXIT_CPUID
] = cpuid_interception
,
2389 [SVM_EXIT_IRET
] = iret_interception
,
2390 [SVM_EXIT_INVD
] = emulate_on_interception
,
2391 [SVM_EXIT_PAUSE
] = pause_interception
,
2392 [SVM_EXIT_HLT
] = halt_interception
,
2393 [SVM_EXIT_INVLPG
] = invlpg_interception
,
2394 [SVM_EXIT_INVLPGA
] = invlpga_interception
,
2395 [SVM_EXIT_IOIO
] = io_interception
,
2396 [SVM_EXIT_MSR
] = msr_interception
,
2397 [SVM_EXIT_TASK_SWITCH
] = task_switch_interception
,
2398 [SVM_EXIT_SHUTDOWN
] = shutdown_interception
,
2399 [SVM_EXIT_VMRUN
] = vmrun_interception
,
2400 [SVM_EXIT_VMMCALL
] = vmmcall_interception
,
2401 [SVM_EXIT_VMLOAD
] = vmload_interception
,
2402 [SVM_EXIT_VMSAVE
] = vmsave_interception
,
2403 [SVM_EXIT_STGI
] = stgi_interception
,
2404 [SVM_EXIT_CLGI
] = clgi_interception
,
2405 [SVM_EXIT_SKINIT
] = skinit_interception
,
2406 [SVM_EXIT_WBINVD
] = emulate_on_interception
,
2407 [SVM_EXIT_MONITOR
] = invalid_op_interception
,
2408 [SVM_EXIT_MWAIT
] = invalid_op_interception
,
2409 [SVM_EXIT_NPF
] = pf_interception
,
2412 static int handle_exit(struct kvm_vcpu
*vcpu
)
2414 struct vcpu_svm
*svm
= to_svm(vcpu
);
2415 struct kvm_run
*kvm_run
= vcpu
->run
;
2416 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
2418 trace_kvm_exit(exit_code
, svm
->vmcb
->save
.rip
);
2420 if (unlikely(svm
->nested
.exit_required
)) {
2421 nested_svm_vmexit(svm
);
2422 svm
->nested
.exit_required
= false;
2427 if (is_nested(svm
)) {
2430 trace_kvm_nested_vmexit(svm
->vmcb
->save
.rip
, exit_code
,
2431 svm
->vmcb
->control
.exit_info_1
,
2432 svm
->vmcb
->control
.exit_info_2
,
2433 svm
->vmcb
->control
.exit_int_info
,
2434 svm
->vmcb
->control
.exit_int_info_err
);
2436 vmexit
= nested_svm_exit_special(svm
);
2438 if (vmexit
== NESTED_EXIT_CONTINUE
)
2439 vmexit
= nested_svm_exit_handled(svm
);
2441 if (vmexit
== NESTED_EXIT_DONE
)
2445 svm_complete_interrupts(svm
);
2447 if (!(svm
->vmcb
->control
.intercept_cr_write
& INTERCEPT_CR0_MASK
))
2448 vcpu
->arch
.cr0
= svm
->vmcb
->save
.cr0
;
2450 vcpu
->arch
.cr3
= svm
->vmcb
->save
.cr3
;
2452 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_ERR
) {
2453 kvm_run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
2454 kvm_run
->fail_entry
.hardware_entry_failure_reason
2455 = svm
->vmcb
->control
.exit_code
;
2459 if (is_external_interrupt(svm
->vmcb
->control
.exit_int_info
) &&
2460 exit_code
!= SVM_EXIT_EXCP_BASE
+ PF_VECTOR
&&
2461 exit_code
!= SVM_EXIT_NPF
&& exit_code
!= SVM_EXIT_TASK_SWITCH
)
2462 printk(KERN_ERR
"%s: unexpected exit_ini_info 0x%x "
2464 __func__
, svm
->vmcb
->control
.exit_int_info
,
2467 if (exit_code
>= ARRAY_SIZE(svm_exit_handlers
)
2468 || !svm_exit_handlers
[exit_code
]) {
2469 kvm_run
->exit_reason
= KVM_EXIT_UNKNOWN
;
2470 kvm_run
->hw
.hardware_exit_reason
= exit_code
;
2474 return svm_exit_handlers
[exit_code
](svm
);
2477 static void reload_tss(struct kvm_vcpu
*vcpu
)
2479 int cpu
= raw_smp_processor_id();
2481 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
2482 sd
->tss_desc
->type
= 9; /* available 32/64-bit TSS */
2486 static void pre_svm_run(struct vcpu_svm
*svm
)
2488 int cpu
= raw_smp_processor_id();
2490 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
2492 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_DO_NOTHING
;
2493 /* FIXME: handle wraparound of asid_generation */
2494 if (svm
->asid_generation
!= sd
->asid_generation
)
2498 static void svm_inject_nmi(struct kvm_vcpu
*vcpu
)
2500 struct vcpu_svm
*svm
= to_svm(vcpu
);
2502 svm
->vmcb
->control
.event_inj
= SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_NMI
;
2503 vcpu
->arch
.hflags
|= HF_NMI_MASK
;
2504 svm
->vmcb
->control
.intercept
|= (1UL << INTERCEPT_IRET
);
2505 ++vcpu
->stat
.nmi_injections
;
2508 static inline void svm_inject_irq(struct vcpu_svm
*svm
, int irq
)
2510 struct vmcb_control_area
*control
;
2512 trace_kvm_inj_virq(irq
);
2514 ++svm
->vcpu
.stat
.irq_injections
;
2515 control
= &svm
->vmcb
->control
;
2516 control
->int_vector
= irq
;
2517 control
->int_ctl
&= ~V_INTR_PRIO_MASK
;
2518 control
->int_ctl
|= V_IRQ_MASK
|
2519 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT
);
2522 static void svm_set_irq(struct kvm_vcpu
*vcpu
)
2524 struct vcpu_svm
*svm
= to_svm(vcpu
);
2526 BUG_ON(!(gif_set(svm
)));
2528 svm
->vmcb
->control
.event_inj
= vcpu
->arch
.interrupt
.nr
|
2529 SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
;
2532 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
2534 struct vcpu_svm
*svm
= to_svm(vcpu
);
2536 if (is_nested(svm
) && (vcpu
->arch
.hflags
& HF_VINTR_MASK
))
2543 svm
->vmcb
->control
.intercept_cr_write
|= INTERCEPT_CR8_MASK
;
2546 static int svm_nmi_allowed(struct kvm_vcpu
*vcpu
)
2548 struct vcpu_svm
*svm
= to_svm(vcpu
);
2549 struct vmcb
*vmcb
= svm
->vmcb
;
2550 return !(vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
) &&
2551 !(svm
->vcpu
.arch
.hflags
& HF_NMI_MASK
);
2554 static bool svm_get_nmi_mask(struct kvm_vcpu
*vcpu
)
2556 struct vcpu_svm
*svm
= to_svm(vcpu
);
2558 return !!(svm
->vcpu
.arch
.hflags
& HF_NMI_MASK
);
2561 static void svm_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
2563 struct vcpu_svm
*svm
= to_svm(vcpu
);
2566 svm
->vcpu
.arch
.hflags
|= HF_NMI_MASK
;
2567 svm
->vmcb
->control
.intercept
|= (1UL << INTERCEPT_IRET
);
2569 svm
->vcpu
.arch
.hflags
&= ~HF_NMI_MASK
;
2570 svm
->vmcb
->control
.intercept
&= ~(1UL << INTERCEPT_IRET
);
2574 static int svm_interrupt_allowed(struct kvm_vcpu
*vcpu
)
2576 struct vcpu_svm
*svm
= to_svm(vcpu
);
2577 struct vmcb
*vmcb
= svm
->vmcb
;
2580 if (!gif_set(svm
) ||
2581 (vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
))
2584 ret
= !!(vmcb
->save
.rflags
& X86_EFLAGS_IF
);
2587 return ret
&& !(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
);
2592 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
2594 struct vcpu_svm
*svm
= to_svm(vcpu
);
2596 nested_svm_intr(svm
);
2598 /* In case GIF=0 we can't rely on the CPU to tell us when
2599 * GIF becomes 1, because that's a separate STGI/VMRUN intercept.
2600 * The next time we get that intercept, this function will be
2601 * called again though and we'll get the vintr intercept. */
2604 svm_inject_irq(svm
, 0x0);
2608 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
2610 struct vcpu_svm
*svm
= to_svm(vcpu
);
2612 if ((svm
->vcpu
.arch
.hflags
& (HF_NMI_MASK
| HF_IRET_MASK
))
2614 return; /* IRET will cause a vm exit */
2616 /* Something prevents NMI from been injected. Single step over
2617 possible problem (IRET or exception injection or interrupt
2619 svm
->nmi_singlestep
= true;
2620 svm
->vmcb
->save
.rflags
|= (X86_EFLAGS_TF
| X86_EFLAGS_RF
);
2621 update_db_intercept(vcpu
);
2624 static int svm_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
2629 static void svm_flush_tlb(struct kvm_vcpu
*vcpu
)
2631 force_new_asid(vcpu
);
2634 static void svm_prepare_guest_switch(struct kvm_vcpu
*vcpu
)
2638 static inline void sync_cr8_to_lapic(struct kvm_vcpu
*vcpu
)
2640 struct vcpu_svm
*svm
= to_svm(vcpu
);
2642 if (is_nested(svm
) && (vcpu
->arch
.hflags
& HF_VINTR_MASK
))
2645 if (!(svm
->vmcb
->control
.intercept_cr_write
& INTERCEPT_CR8_MASK
)) {
2646 int cr8
= svm
->vmcb
->control
.int_ctl
& V_TPR_MASK
;
2647 kvm_set_cr8(vcpu
, cr8
);
2651 static inline void sync_lapic_to_cr8(struct kvm_vcpu
*vcpu
)
2653 struct vcpu_svm
*svm
= to_svm(vcpu
);
2656 if (is_nested(svm
) && (vcpu
->arch
.hflags
& HF_VINTR_MASK
))
2659 cr8
= kvm_get_cr8(vcpu
);
2660 svm
->vmcb
->control
.int_ctl
&= ~V_TPR_MASK
;
2661 svm
->vmcb
->control
.int_ctl
|= cr8
& V_TPR_MASK
;
2664 static void svm_complete_interrupts(struct vcpu_svm
*svm
)
2668 u32 exitintinfo
= svm
->vmcb
->control
.exit_int_info
;
2670 if (svm
->vcpu
.arch
.hflags
& HF_IRET_MASK
)
2671 svm
->vcpu
.arch
.hflags
&= ~(HF_NMI_MASK
| HF_IRET_MASK
);
2673 svm
->vcpu
.arch
.nmi_injected
= false;
2674 kvm_clear_exception_queue(&svm
->vcpu
);
2675 kvm_clear_interrupt_queue(&svm
->vcpu
);
2677 if (!(exitintinfo
& SVM_EXITINTINFO_VALID
))
2680 vector
= exitintinfo
& SVM_EXITINTINFO_VEC_MASK
;
2681 type
= exitintinfo
& SVM_EXITINTINFO_TYPE_MASK
;
2684 case SVM_EXITINTINFO_TYPE_NMI
:
2685 svm
->vcpu
.arch
.nmi_injected
= true;
2687 case SVM_EXITINTINFO_TYPE_EXEPT
:
2688 /* In case of software exception do not reinject an exception
2689 vector, but re-execute and instruction instead */
2692 if (kvm_exception_is_soft(vector
))
2694 if (exitintinfo
& SVM_EXITINTINFO_VALID_ERR
) {
2695 u32 err
= svm
->vmcb
->control
.exit_int_info_err
;
2696 kvm_queue_exception_e(&svm
->vcpu
, vector
, err
);
2699 kvm_queue_exception(&svm
->vcpu
, vector
);
2701 case SVM_EXITINTINFO_TYPE_INTR
:
2702 kvm_queue_interrupt(&svm
->vcpu
, vector
, false);
2709 #ifdef CONFIG_X86_64
2715 static void svm_vcpu_run(struct kvm_vcpu
*vcpu
)
2717 struct vcpu_svm
*svm
= to_svm(vcpu
);
2723 * A vmexit emulation is required before the vcpu can be executed
2726 if (unlikely(svm
->nested
.exit_required
))
2729 svm
->vmcb
->save
.rax
= vcpu
->arch
.regs
[VCPU_REGS_RAX
];
2730 svm
->vmcb
->save
.rsp
= vcpu
->arch
.regs
[VCPU_REGS_RSP
];
2731 svm
->vmcb
->save
.rip
= vcpu
->arch
.regs
[VCPU_REGS_RIP
];
2735 sync_lapic_to_cr8(vcpu
);
2737 save_host_msrs(vcpu
);
2738 fs_selector
= kvm_read_fs();
2739 gs_selector
= kvm_read_gs();
2740 ldt_selector
= kvm_read_ldt();
2741 svm
->vmcb
->save
.cr2
= vcpu
->arch
.cr2
;
2742 /* required for live migration with NPT */
2744 svm
->vmcb
->save
.cr3
= vcpu
->arch
.cr3
;
2751 "push %%"R
"bp; \n\t"
2752 "mov %c[rbx](%[svm]), %%"R
"bx \n\t"
2753 "mov %c[rcx](%[svm]), %%"R
"cx \n\t"
2754 "mov %c[rdx](%[svm]), %%"R
"dx \n\t"
2755 "mov %c[rsi](%[svm]), %%"R
"si \n\t"
2756 "mov %c[rdi](%[svm]), %%"R
"di \n\t"
2757 "mov %c[rbp](%[svm]), %%"R
"bp \n\t"
2758 #ifdef CONFIG_X86_64
2759 "mov %c[r8](%[svm]), %%r8 \n\t"
2760 "mov %c[r9](%[svm]), %%r9 \n\t"
2761 "mov %c[r10](%[svm]), %%r10 \n\t"
2762 "mov %c[r11](%[svm]), %%r11 \n\t"
2763 "mov %c[r12](%[svm]), %%r12 \n\t"
2764 "mov %c[r13](%[svm]), %%r13 \n\t"
2765 "mov %c[r14](%[svm]), %%r14 \n\t"
2766 "mov %c[r15](%[svm]), %%r15 \n\t"
2769 /* Enter guest mode */
2771 "mov %c[vmcb](%[svm]), %%"R
"ax \n\t"
2772 __ex(SVM_VMLOAD
) "\n\t"
2773 __ex(SVM_VMRUN
) "\n\t"
2774 __ex(SVM_VMSAVE
) "\n\t"
2777 /* Save guest registers, load host registers */
2778 "mov %%"R
"bx, %c[rbx](%[svm]) \n\t"
2779 "mov %%"R
"cx, %c[rcx](%[svm]) \n\t"
2780 "mov %%"R
"dx, %c[rdx](%[svm]) \n\t"
2781 "mov %%"R
"si, %c[rsi](%[svm]) \n\t"
2782 "mov %%"R
"di, %c[rdi](%[svm]) \n\t"
2783 "mov %%"R
"bp, %c[rbp](%[svm]) \n\t"
2784 #ifdef CONFIG_X86_64
2785 "mov %%r8, %c[r8](%[svm]) \n\t"
2786 "mov %%r9, %c[r9](%[svm]) \n\t"
2787 "mov %%r10, %c[r10](%[svm]) \n\t"
2788 "mov %%r11, %c[r11](%[svm]) \n\t"
2789 "mov %%r12, %c[r12](%[svm]) \n\t"
2790 "mov %%r13, %c[r13](%[svm]) \n\t"
2791 "mov %%r14, %c[r14](%[svm]) \n\t"
2792 "mov %%r15, %c[r15](%[svm]) \n\t"
2797 [vmcb
]"i"(offsetof(struct vcpu_svm
, vmcb_pa
)),
2798 [rbx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
2799 [rcx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
2800 [rdx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
2801 [rsi
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
2802 [rdi
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
2803 [rbp
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RBP
]))
2804 #ifdef CONFIG_X86_64
2805 , [r8
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
2806 [r9
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
2807 [r10
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
2808 [r11
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
2809 [r12
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
2810 [r13
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
2811 [r14
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
2812 [r15
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R15
]))
2815 , R
"bx", R
"cx", R
"dx", R
"si", R
"di"
2816 #ifdef CONFIG_X86_64
2817 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2821 vcpu
->arch
.cr2
= svm
->vmcb
->save
.cr2
;
2822 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = svm
->vmcb
->save
.rax
;
2823 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = svm
->vmcb
->save
.rsp
;
2824 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = svm
->vmcb
->save
.rip
;
2826 kvm_load_fs(fs_selector
);
2827 kvm_load_gs(gs_selector
);
2828 kvm_load_ldt(ldt_selector
);
2829 load_host_msrs(vcpu
);
2833 local_irq_disable();
2837 sync_cr8_to_lapic(vcpu
);
2842 vcpu
->arch
.regs_avail
&= ~(1 << VCPU_EXREG_PDPTR
);
2843 vcpu
->arch
.regs_dirty
&= ~(1 << VCPU_EXREG_PDPTR
);
2849 static void svm_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long root
)
2851 struct vcpu_svm
*svm
= to_svm(vcpu
);
2854 svm
->vmcb
->control
.nested_cr3
= root
;
2855 force_new_asid(vcpu
);
2859 svm
->vmcb
->save
.cr3
= root
;
2860 force_new_asid(vcpu
);
2863 static int is_disabled(void)
2867 rdmsrl(MSR_VM_CR
, vm_cr
);
2868 if (vm_cr
& (1 << SVM_VM_CR_SVM_DISABLE
))
2875 svm_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
2878 * Patch in the VMMCALL instruction:
2880 hypercall
[0] = 0x0f;
2881 hypercall
[1] = 0x01;
2882 hypercall
[2] = 0xd9;
2885 static void svm_check_processor_compat(void *rtn
)
2890 static bool svm_cpu_has_accelerated_tpr(void)
2895 static int get_npt_level(void)
2897 #ifdef CONFIG_X86_64
2898 return PT64_ROOT_LEVEL
;
2900 return PT32E_ROOT_LEVEL
;
2904 static u64
svm_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
2909 static void svm_cpuid_update(struct kvm_vcpu
*vcpu
)
2913 static const struct trace_print_flags svm_exit_reasons_str
[] = {
2914 { SVM_EXIT_READ_CR0
, "read_cr0" },
2915 { SVM_EXIT_READ_CR3
, "read_cr3" },
2916 { SVM_EXIT_READ_CR4
, "read_cr4" },
2917 { SVM_EXIT_READ_CR8
, "read_cr8" },
2918 { SVM_EXIT_WRITE_CR0
, "write_cr0" },
2919 { SVM_EXIT_WRITE_CR3
, "write_cr3" },
2920 { SVM_EXIT_WRITE_CR4
, "write_cr4" },
2921 { SVM_EXIT_WRITE_CR8
, "write_cr8" },
2922 { SVM_EXIT_READ_DR0
, "read_dr0" },
2923 { SVM_EXIT_READ_DR1
, "read_dr1" },
2924 { SVM_EXIT_READ_DR2
, "read_dr2" },
2925 { SVM_EXIT_READ_DR3
, "read_dr3" },
2926 { SVM_EXIT_WRITE_DR0
, "write_dr0" },
2927 { SVM_EXIT_WRITE_DR1
, "write_dr1" },
2928 { SVM_EXIT_WRITE_DR2
, "write_dr2" },
2929 { SVM_EXIT_WRITE_DR3
, "write_dr3" },
2930 { SVM_EXIT_WRITE_DR5
, "write_dr5" },
2931 { SVM_EXIT_WRITE_DR7
, "write_dr7" },
2932 { SVM_EXIT_EXCP_BASE
+ DB_VECTOR
, "DB excp" },
2933 { SVM_EXIT_EXCP_BASE
+ BP_VECTOR
, "BP excp" },
2934 { SVM_EXIT_EXCP_BASE
+ UD_VECTOR
, "UD excp" },
2935 { SVM_EXIT_EXCP_BASE
+ PF_VECTOR
, "PF excp" },
2936 { SVM_EXIT_EXCP_BASE
+ NM_VECTOR
, "NM excp" },
2937 { SVM_EXIT_EXCP_BASE
+ MC_VECTOR
, "MC excp" },
2938 { SVM_EXIT_INTR
, "interrupt" },
2939 { SVM_EXIT_NMI
, "nmi" },
2940 { SVM_EXIT_SMI
, "smi" },
2941 { SVM_EXIT_INIT
, "init" },
2942 { SVM_EXIT_VINTR
, "vintr" },
2943 { SVM_EXIT_CPUID
, "cpuid" },
2944 { SVM_EXIT_INVD
, "invd" },
2945 { SVM_EXIT_HLT
, "hlt" },
2946 { SVM_EXIT_INVLPG
, "invlpg" },
2947 { SVM_EXIT_INVLPGA
, "invlpga" },
2948 { SVM_EXIT_IOIO
, "io" },
2949 { SVM_EXIT_MSR
, "msr" },
2950 { SVM_EXIT_TASK_SWITCH
, "task_switch" },
2951 { SVM_EXIT_SHUTDOWN
, "shutdown" },
2952 { SVM_EXIT_VMRUN
, "vmrun" },
2953 { SVM_EXIT_VMMCALL
, "hypercall" },
2954 { SVM_EXIT_VMLOAD
, "vmload" },
2955 { SVM_EXIT_VMSAVE
, "vmsave" },
2956 { SVM_EXIT_STGI
, "stgi" },
2957 { SVM_EXIT_CLGI
, "clgi" },
2958 { SVM_EXIT_SKINIT
, "skinit" },
2959 { SVM_EXIT_WBINVD
, "wbinvd" },
2960 { SVM_EXIT_MONITOR
, "monitor" },
2961 { SVM_EXIT_MWAIT
, "mwait" },
2962 { SVM_EXIT_NPF
, "npf" },
2966 static int svm_get_lpage_level(void)
2968 return PT_PDPE_LEVEL
;
2971 static bool svm_rdtscp_supported(void)
2976 static void svm_fpu_deactivate(struct kvm_vcpu
*vcpu
)
2978 struct vcpu_svm
*svm
= to_svm(vcpu
);
2980 update_cr0_intercept(svm
);
2981 svm
->vmcb
->control
.intercept_exceptions
|= 1 << NM_VECTOR
;
2984 static struct kvm_x86_ops svm_x86_ops
= {
2985 .cpu_has_kvm_support
= has_svm
,
2986 .disabled_by_bios
= is_disabled
,
2987 .hardware_setup
= svm_hardware_setup
,
2988 .hardware_unsetup
= svm_hardware_unsetup
,
2989 .check_processor_compatibility
= svm_check_processor_compat
,
2990 .hardware_enable
= svm_hardware_enable
,
2991 .hardware_disable
= svm_hardware_disable
,
2992 .cpu_has_accelerated_tpr
= svm_cpu_has_accelerated_tpr
,
2994 .vcpu_create
= svm_create_vcpu
,
2995 .vcpu_free
= svm_free_vcpu
,
2996 .vcpu_reset
= svm_vcpu_reset
,
2998 .prepare_guest_switch
= svm_prepare_guest_switch
,
2999 .vcpu_load
= svm_vcpu_load
,
3000 .vcpu_put
= svm_vcpu_put
,
3002 .set_guest_debug
= svm_guest_debug
,
3003 .get_msr
= svm_get_msr
,
3004 .set_msr
= svm_set_msr
,
3005 .get_segment_base
= svm_get_segment_base
,
3006 .get_segment
= svm_get_segment
,
3007 .set_segment
= svm_set_segment
,
3008 .get_cpl
= svm_get_cpl
,
3009 .get_cs_db_l_bits
= kvm_get_cs_db_l_bits
,
3010 .decache_cr0_guest_bits
= svm_decache_cr0_guest_bits
,
3011 .decache_cr4_guest_bits
= svm_decache_cr4_guest_bits
,
3012 .set_cr0
= svm_set_cr0
,
3013 .set_cr3
= svm_set_cr3
,
3014 .set_cr4
= svm_set_cr4
,
3015 .set_efer
= svm_set_efer
,
3016 .get_idt
= svm_get_idt
,
3017 .set_idt
= svm_set_idt
,
3018 .get_gdt
= svm_get_gdt
,
3019 .set_gdt
= svm_set_gdt
,
3020 .get_dr
= svm_get_dr
,
3021 .set_dr
= svm_set_dr
,
3022 .cache_reg
= svm_cache_reg
,
3023 .get_rflags
= svm_get_rflags
,
3024 .set_rflags
= svm_set_rflags
,
3025 .fpu_activate
= svm_fpu_activate
,
3026 .fpu_deactivate
= svm_fpu_deactivate
,
3028 .tlb_flush
= svm_flush_tlb
,
3030 .run
= svm_vcpu_run
,
3031 .handle_exit
= handle_exit
,
3032 .skip_emulated_instruction
= skip_emulated_instruction
,
3033 .set_interrupt_shadow
= svm_set_interrupt_shadow
,
3034 .get_interrupt_shadow
= svm_get_interrupt_shadow
,
3035 .patch_hypercall
= svm_patch_hypercall
,
3036 .set_irq
= svm_set_irq
,
3037 .set_nmi
= svm_inject_nmi
,
3038 .queue_exception
= svm_queue_exception
,
3039 .interrupt_allowed
= svm_interrupt_allowed
,
3040 .nmi_allowed
= svm_nmi_allowed
,
3041 .get_nmi_mask
= svm_get_nmi_mask
,
3042 .set_nmi_mask
= svm_set_nmi_mask
,
3043 .enable_nmi_window
= enable_nmi_window
,
3044 .enable_irq_window
= enable_irq_window
,
3045 .update_cr8_intercept
= update_cr8_intercept
,
3047 .set_tss_addr
= svm_set_tss_addr
,
3048 .get_tdp_level
= get_npt_level
,
3049 .get_mt_mask
= svm_get_mt_mask
,
3051 .exit_reasons_str
= svm_exit_reasons_str
,
3052 .get_lpage_level
= svm_get_lpage_level
,
3054 .cpuid_update
= svm_cpuid_update
,
3056 .rdtscp_supported
= svm_rdtscp_supported
,
3059 static int __init
svm_init(void)
3061 return kvm_init(&svm_x86_ops
, sizeof(struct vcpu_svm
),
3065 static void __exit
svm_exit(void)
3070 module_init(svm_init
)
3071 module_exit(svm_exit
)