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ARM: shmobile: r8a7779: Register GPIO devices
[linux-2.6/btrfs-unstable.git] / arch / arm / mach-shmobile / setup-r8a7779.c
bloba460ba3dedcb1af67083b402f78a7592ec0818b1
1 /*
2 * r8a7779 processor support
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/irq.h>
24 #include <linux/of_platform.h>
25 #include <linux/platform_data/gpio-rcar.h>
26 #include <linux/platform_device.h>
27 #include <linux/delay.h>
28 #include <linux/input.h>
29 #include <linux/io.h>
30 #include <linux/serial_sci.h>
31 #include <linux/sh_intc.h>
32 #include <linux/sh_timer.h>
33 #include <linux/dma-mapping.h>
34 #include <mach/hardware.h>
35 #include <mach/irqs.h>
36 #include <mach/r8a7779.h>
37 #include <mach/common.h>
38 #include <asm/mach-types.h>
39 #include <asm/mach/arch.h>
40 #include <asm/mach/time.h>
41 #include <asm/mach/map.h>
42 #include <asm/hardware/cache-l2x0.h>
43
44 static struct map_desc r8a7779_io_desc[] __initdata = {
45 /* 2M entity map for 0xf0000000 (MPCORE) */
46 {
47 .virtual = 0xf0000000,
48 .pfn = __phys_to_pfn(0xf0000000),
49 .length = SZ_2M,
50 .type = MT_DEVICE_NONSHARED
51 },
52 /* 16M entity map for 0xfexxxxxx (DMAC-S/HPBREG/INTC2/LRAM/DBSC) */
53 {
54 .virtual = 0xfe000000,
55 .pfn = __phys_to_pfn(0xfe000000),
56 .length = SZ_16M,
57 .type = MT_DEVICE_NONSHARED
58 },
59 };
60
61 void __init r8a7779_map_io(void)
62 {
63 iotable_init(r8a7779_io_desc, ARRAY_SIZE(r8a7779_io_desc));
64 }
65
66 static struct resource r8a7779_pfc_resources[] = {
67 [0] = {
68 .start = 0xfffc0000,
69 .end = 0xfffc023b,
70 .flags = IORESOURCE_MEM,
71 },
72 };
73
74 static struct platform_device r8a7779_pfc_device = {
75 .name = "pfc-r8a7779",
76 .id = -1,
77 .resource = r8a7779_pfc_resources,
78 .num_resources = ARRAY_SIZE(r8a7779_pfc_resources),
79 };
80
81 #define R8A7779_GPIO(idx, npins) \
82 static struct resource r8a7779_gpio##idx##_resources[] = { \
83 [0] = { \
84 .start = 0xffc40000 + 0x1000 * (idx), \
85 .end = 0xffc4002b + 0x1000 * (idx), \
86 .flags = IORESOURCE_MEM, \
87 }, \
88 [1] = { \
89 .start = gic_iid(0xad + (idx)), \
90 .flags = IORESOURCE_IRQ, \
91 } \
92 }; \
93 \
94 static struct gpio_rcar_config r8a7779_gpio##idx##_platform_data = { \
95 .gpio_base = 32 * (idx), \
96 .irq_base = 0, \
97 .number_of_pins = npins, \
98 .pctl_name = "pfc-r8a7779", \
99 }; \
100 \
101 static struct platform_device r8a7779_gpio##idx##_device = { \
102 .name = "gpio_rcar", \
103 .id = idx, \
104 .resource = r8a7779_gpio##idx##_resources, \
105 .num_resources = ARRAY_SIZE(r8a7779_gpio##idx##_resources), \
106 .dev = { \
107 .platform_data = &r8a7779_gpio##idx##_platform_data, \
108 }, \
109 }
110
111 R8A7779_GPIO(0, 32);
112 R8A7779_GPIO(1, 32);
113 R8A7779_GPIO(2, 32);
114 R8A7779_GPIO(3, 32);
115 R8A7779_GPIO(4, 32);
116 R8A7779_GPIO(5, 32);
117 R8A7779_GPIO(6, 9);
118
119 static struct platform_device *r8a7779_pinctrl_devices[] __initdata = {
120 &r8a7779_pfc_device,
121 &r8a7779_gpio0_device,
122 &r8a7779_gpio1_device,
123 &r8a7779_gpio2_device,
124 &r8a7779_gpio3_device,
125 &r8a7779_gpio4_device,
126 &r8a7779_gpio5_device,
127 &r8a7779_gpio6_device,
128 };
129
130 void __init r8a7779_pinmux_init(void)
131 {
132 platform_add_devices(r8a7779_pinctrl_devices,
133 ARRAY_SIZE(r8a7779_pinctrl_devices));
134 }
135
136 static struct plat_sci_port scif0_platform_data = {
137 .mapbase = 0xffe40000,
138 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
139 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
140 .scbrr_algo_id = SCBRR_ALGO_2,
141 .type = PORT_SCIF,
142 .irqs = SCIx_IRQ_MUXED(gic_iid(0x78)),
143 };
144
145 static struct platform_device scif0_device = {
146 .name = "sh-sci",
147 .id = 0,
148 .dev = {
149 .platform_data = &scif0_platform_data,
150 },
151 };
152
153 static struct plat_sci_port scif1_platform_data = {
154 .mapbase = 0xffe41000,
155 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
156 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
157 .scbrr_algo_id = SCBRR_ALGO_2,
158 .type = PORT_SCIF,
159 .irqs = SCIx_IRQ_MUXED(gic_iid(0x79)),
160 };
161
162 static struct platform_device scif1_device = {
163 .name = "sh-sci",
164 .id = 1,
165 .dev = {
166 .platform_data = &scif1_platform_data,
167 },
168 };
169
170 static struct plat_sci_port scif2_platform_data = {
171 .mapbase = 0xffe42000,
172 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
173 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
174 .scbrr_algo_id = SCBRR_ALGO_2,
175 .type = PORT_SCIF,
176 .irqs = SCIx_IRQ_MUXED(gic_iid(0x7a)),
177 };
178
179 static struct platform_device scif2_device = {
180 .name = "sh-sci",
181 .id = 2,
182 .dev = {
183 .platform_data = &scif2_platform_data,
184 },
185 };
186
187 static struct plat_sci_port scif3_platform_data = {
188 .mapbase = 0xffe43000,
189 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
190 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
191 .scbrr_algo_id = SCBRR_ALGO_2,
192 .type = PORT_SCIF,
193 .irqs = SCIx_IRQ_MUXED(gic_iid(0x7b)),
194 };
195
196 static struct platform_device scif3_device = {
197 .name = "sh-sci",
198 .id = 3,
199 .dev = {
200 .platform_data = &scif3_platform_data,
201 },
202 };
203
204 static struct plat_sci_port scif4_platform_data = {
205 .mapbase = 0xffe44000,
206 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
207 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
208 .scbrr_algo_id = SCBRR_ALGO_2,
209 .type = PORT_SCIF,
210 .irqs = SCIx_IRQ_MUXED(gic_iid(0x7c)),
211 };
212
213 static struct platform_device scif4_device = {
214 .name = "sh-sci",
215 .id = 4,
216 .dev = {
217 .platform_data = &scif4_platform_data,
218 },
219 };
220
221 static struct plat_sci_port scif5_platform_data = {
222 .mapbase = 0xffe45000,
223 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
224 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
225 .scbrr_algo_id = SCBRR_ALGO_2,
226 .type = PORT_SCIF,
227 .irqs = SCIx_IRQ_MUXED(gic_iid(0x7d)),
228 };
229
230 static struct platform_device scif5_device = {
231 .name = "sh-sci",
232 .id = 5,
233 .dev = {
234 .platform_data = &scif5_platform_data,
235 },
236 };
237
238 /* TMU */
239 static struct sh_timer_config tmu00_platform_data = {
240 .name = "TMU00",
241 .channel_offset = 0x4,
242 .timer_bit = 0,
243 .clockevent_rating = 200,
244 };
245
246 static struct resource tmu00_resources[] = {
247 [0] = {
248 .name = "TMU00",
249 .start = 0xffd80008,
250 .end = 0xffd80013,
251 .flags = IORESOURCE_MEM,
252 },
253 [1] = {
254 .start = gic_iid(0x40),
255 .flags = IORESOURCE_IRQ,
256 },
257 };
258
259 static struct platform_device tmu00_device = {
260 .name = "sh_tmu",
261 .id = 0,
262 .dev = {
263 .platform_data = &tmu00_platform_data,
264 },
265 .resource = tmu00_resources,
266 .num_resources = ARRAY_SIZE(tmu00_resources),
267 };
268
269 static struct sh_timer_config tmu01_platform_data = {
270 .name = "TMU01",
271 .channel_offset = 0x10,
272 .timer_bit = 1,
273 .clocksource_rating = 200,
274 };
275
276 static struct resource tmu01_resources[] = {
277 [0] = {
278 .name = "TMU01",
279 .start = 0xffd80014,
280 .end = 0xffd8001f,
281 .flags = IORESOURCE_MEM,
282 },
283 [1] = {
284 .start = gic_iid(0x41),
285 .flags = IORESOURCE_IRQ,
286 },
287 };
288
289 static struct platform_device tmu01_device = {
290 .name = "sh_tmu",
291 .id = 1,
292 .dev = {
293 .platform_data = &tmu01_platform_data,
294 },
295 .resource = tmu01_resources,
296 .num_resources = ARRAY_SIZE(tmu01_resources),
297 };
298
299 /* I2C */
300 static struct resource rcar_i2c0_res[] = {
301 {
302 .start = 0xffc70000,
303 .end = 0xffc70fff,
304 .flags = IORESOURCE_MEM,
305 }, {
306 .start = gic_iid(0x6f),
307 .flags = IORESOURCE_IRQ,
308 },
309 };
310
311 static struct platform_device i2c0_device = {
312 .name = "i2c-rcar",
313 .id = 0,
314 .resource = rcar_i2c0_res,
315 .num_resources = ARRAY_SIZE(rcar_i2c0_res),
316 };
317
318 static struct resource rcar_i2c1_res[] = {
319 {
320 .start = 0xffc71000,
321 .end = 0xffc71fff,
322 .flags = IORESOURCE_MEM,
323 }, {
324 .start = gic_iid(0x72),
325 .flags = IORESOURCE_IRQ,
326 },
327 };
328
329 static struct platform_device i2c1_device = {
330 .name = "i2c-rcar",
331 .id = 1,
332 .resource = rcar_i2c1_res,
333 .num_resources = ARRAY_SIZE(rcar_i2c1_res),
334 };
335
336 static struct resource rcar_i2c2_res[] = {
337 {
338 .start = 0xffc72000,
339 .end = 0xffc72fff,
340 .flags = IORESOURCE_MEM,
341 }, {
342 .start = gic_iid(0x70),
343 .flags = IORESOURCE_IRQ,
344 },
345 };
346
347 static struct platform_device i2c2_device = {
348 .name = "i2c-rcar",
349 .id = 2,
350 .resource = rcar_i2c2_res,
351 .num_resources = ARRAY_SIZE(rcar_i2c2_res),
352 };
353
354 static struct resource rcar_i2c3_res[] = {
355 {
356 .start = 0xffc73000,
357 .end = 0xffc73fff,
358 .flags = IORESOURCE_MEM,
359 }, {
360 .start = gic_iid(0x71),
361 .flags = IORESOURCE_IRQ,
362 },
363 };
364
365 static struct platform_device i2c3_device = {
366 .name = "i2c-rcar",
367 .id = 3,
368 .resource = rcar_i2c3_res,
369 .num_resources = ARRAY_SIZE(rcar_i2c3_res),
370 };
371
372 static struct resource sata_resources[] = {
373 [0] = {
374 .name = "rcar-sata",
375 .start = 0xfc600000,
376 .end = 0xfc601fff,
377 .flags = IORESOURCE_MEM,
378 },
379 [1] = {
380 .start = gic_iid(0x84),
381 .flags = IORESOURCE_IRQ,
382 },
383 };
384
385 static struct platform_device sata_device = {
386 .name = "sata_rcar",
387 .id = -1,
388 .resource = sata_resources,
389 .num_resources = ARRAY_SIZE(sata_resources),
390 .dev = {
391 .dma_mask = &sata_device.dev.coherent_dma_mask,
392 .coherent_dma_mask = DMA_BIT_MASK(32),
393 },
394 };
395
396 static struct platform_device *r8a7779_devices_dt[] __initdata = {
397 &scif0_device,
398 &scif1_device,
399 &scif2_device,
400 &scif3_device,
401 &scif4_device,
402 &scif5_device,
403 &tmu00_device,
404 &tmu01_device,
405 };
406
407 static struct platform_device *r8a7779_late_devices[] __initdata = {
408 &i2c0_device,
409 &i2c1_device,
410 &i2c2_device,
411 &i2c3_device,
412 &sata_device,
413 };
414
415 void __init r8a7779_add_standard_devices(void)
416 {
417 #ifdef CONFIG_CACHE_L2X0
418 /* Early BRESP enable, Shared attribute override enable, 64K*16way */
419 l2x0_init(IOMEM(0xf0100000), 0x40470000, 0x82000fff);
420 #endif
421 r8a7779_pm_init();
422
423 r8a7779_init_pm_domains();
424
425 platform_add_devices(r8a7779_devices_dt,
426 ARRAY_SIZE(r8a7779_devices_dt));
427 platform_add_devices(r8a7779_late_devices,
428 ARRAY_SIZE(r8a7779_late_devices));
429 }
430
431 /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
432 void __init __weak r8a7779_register_twd(void) { }
433
434 void __init r8a7779_earlytimer_init(void)
435 {
436 r8a7779_clock_init();
437 shmobile_earlytimer_init();
438 r8a7779_register_twd();
439 }
440
441 void __init r8a7779_add_early_devices(void)
442 {
443 early_platform_add_devices(r8a7779_devices_dt,
444 ARRAY_SIZE(r8a7779_devices_dt));
445
446 /* Early serial console setup is not included here due to
447 * memory map collisions. The SCIF serial ports in r8a7779
448 * are difficult to entity map 1:1 due to collision with the
449 * virtual memory range used by the coherent DMA code on ARM.
450 *
451 * Anyone wanting to debug early can remove UPF_IOREMAP from
452 * the sh-sci serial console platform data, adjust mapbase
453 * to a static M:N virt:phys mapping that needs to be added to
454 * the mappings passed with iotable_init() above.
455 *
456 * Then add a call to shmobile_setup_console() from this function.
457 *
458 * As a final step pass earlyprint=sh-sci.2,115200 on the kernel
459 * command line in case of the marzen board.
460 */
461 }
462
463 #ifdef CONFIG_USE_OF
464 void __init r8a7779_init_delay(void)
465 {
466 shmobile_setup_delay(1000, 2, 4); /* Cortex-A9 @ 1000MHz */
467 }
468
469 static const struct of_dev_auxdata r8a7779_auxdata_lookup[] __initconst = {
470 {},
471 };
472
473 void __init r8a7779_add_standard_devices_dt(void)
474 {
475 /* clocks are setup late during boot in the case of DT */
476 r8a7779_clock_init();
477
478 platform_add_devices(r8a7779_devices_dt,
479 ARRAY_SIZE(r8a7779_devices_dt));
480 of_platform_populate(NULL, of_default_bus_match_table,
481 r8a7779_auxdata_lookup, NULL);
482 }
483
484 static const char *r8a7779_compat_dt[] __initdata = {
485 "renesas,r8a7779",
486 NULL,
487 };
488
489 DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)")
490 .map_io = r8a7779_map_io,
491 .init_early = r8a7779_init_delay,
492 .nr_irqs = NR_IRQS_LEGACY,
493 .init_irq = r8a7779_init_irq_dt,
494 .init_machine = r8a7779_add_standard_devices_dt,
495 .init_time = shmobile_timer_init,
496 .dt_compat = r8a7779_compat_dt,
497 MACHINE_END
498 #endif /* CONFIG_USE_OF */
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