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ALSA: ak4117: Do not free priv until timer handler hasn't actually stopped using it
[linux-2.6/btrfs-unstable.git] / arch / x86 / kvm / svm.c
blobe81df8fce0275781a654f356fe77e38129d5210a
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
8 *
9 * Authors:
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17 #include <linux/kvm_host.h>
18
19 #include "irq.h"
20 #include "mmu.h"
21 #include "kvm_cache_regs.h"
22 #include "x86.h"
23 #include "cpuid.h"
24
25 #include <linux/module.h>
26 #include <linux/mod_devicetable.h>
27 #include <linux/kernel.h>
28 #include <linux/vmalloc.h>
29 #include <linux/highmem.h>
30 #include <linux/sched.h>
31 #include <linux/ftrace_event.h>
32 #include <linux/slab.h>
33
34 #include <asm/perf_event.h>
35 #include <asm/tlbflush.h>
36 #include <asm/desc.h>
37 #include <asm/kvm_para.h>
38
39 #include <asm/virtext.h>
40 #include "trace.h"
41
42 #define __ex(x) __kvm_handle_fault_on_reboot(x)
43
44 MODULE_AUTHOR("Qumranet");
45 MODULE_LICENSE("GPL");
46
47 static const struct x86_cpu_id svm_cpu_id[] = {
48 X86_FEATURE_MATCH(X86_FEATURE_SVM),
49 {}
50 };
51 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
52
53 #define IOPM_ALLOC_ORDER 2
54 #define MSRPM_ALLOC_ORDER 1
55
56 #define SEG_TYPE_LDT 2
57 #define SEG_TYPE_BUSY_TSS16 3
58
59 #define SVM_FEATURE_NPT (1 << 0)
60 #define SVM_FEATURE_LBRV (1 << 1)
61 #define SVM_FEATURE_SVML (1 << 2)
62 #define SVM_FEATURE_NRIP (1 << 3)
63 #define SVM_FEATURE_TSC_RATE (1 << 4)
64 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
65 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
66 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
67 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
68
69 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
70 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
71 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
72
73 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
74
75 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
76 #define TSC_RATIO_MIN 0x0000000000000001ULL
77 #define TSC_RATIO_MAX 0x000000ffffffffffULL
78
79 static bool erratum_383_found __read_mostly;
80
81 static const u32 host_save_user_msrs[] = {
82 #ifdef CONFIG_X86_64
83 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
84 MSR_FS_BASE,
85 #endif
86 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
87 };
88
89 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
90
91 struct kvm_vcpu;
92
93 struct nested_state {
94 struct vmcb *hsave;
95 u64 hsave_msr;
96 u64 vm_cr_msr;
97 u64 vmcb;
98
99 /* These are the merged vectors */
100 u32 *msrpm;
101
102 /* gpa pointers to the real vectors */
103 u64 vmcb_msrpm;
104 u64 vmcb_iopm;
105
106 /* A VMEXIT is required but not yet emulated */
107 bool exit_required;
108
109 /* cache for intercepts of the guest */
110 u32 intercept_cr;
111 u32 intercept_dr;
112 u32 intercept_exceptions;
113 u64 intercept;
114
115 /* Nested Paging related state */
116 u64 nested_cr3;
117 };
118
119 #define MSRPM_OFFSETS 16
120 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
121
122 /*
123 * Set osvw_len to higher value when updated Revision Guides
124 * are published and we know what the new status bits are
125 */
126 static uint64_t osvw_len = 4, osvw_status;
127
128 struct vcpu_svm {
129 struct kvm_vcpu vcpu;
130 struct vmcb *vmcb;
131 unsigned long vmcb_pa;
132 struct svm_cpu_data *svm_data;
133 uint64_t asid_generation;
134 uint64_t sysenter_esp;
135 uint64_t sysenter_eip;
136
137 u64 next_rip;
138
139 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
140 struct {
141 u16 fs;
142 u16 gs;
143 u16 ldt;
144 u64 gs_base;
145 } host;
146
147 u32 *msrpm;
148
149 ulong nmi_iret_rip;
150
151 struct nested_state nested;
152
153 bool nmi_singlestep;
154
155 unsigned int3_injected;
156 unsigned long int3_rip;
157 u32 apf_reason;
158
159 u64 tsc_ratio;
160 };
161
162 static DEFINE_PER_CPU(u64, current_tsc_ratio);
163 #define TSC_RATIO_DEFAULT 0x0100000000ULL
164
165 #define MSR_INVALID 0xffffffffU
166
167 static const struct svm_direct_access_msrs {
168 u32 index; /* Index of the MSR */
169 bool always; /* True if intercept is always on */
170 } direct_access_msrs[] = {
171 { .index = MSR_STAR, .always = true },
172 { .index = MSR_IA32_SYSENTER_CS, .always = true },
173 #ifdef CONFIG_X86_64
174 { .index = MSR_GS_BASE, .always = true },
175 { .index = MSR_FS_BASE, .always = true },
176 { .index = MSR_KERNEL_GS_BASE, .always = true },
177 { .index = MSR_LSTAR, .always = true },
178 { .index = MSR_CSTAR, .always = true },
179 { .index = MSR_SYSCALL_MASK, .always = true },
180 #endif
181 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
182 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
183 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
184 { .index = MSR_IA32_LASTINTTOIP, .always = false },
185 { .index = MSR_INVALID, .always = false },
186 };
187
188 /* enable NPT for AMD64 and X86 with PAE */
189 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
190 static bool npt_enabled = true;
191 #else
192 static bool npt_enabled;
193 #endif
194
195 /* allow nested paging (virtualized MMU) for all guests */
196 static int npt = true;
197 module_param(npt, int, S_IRUGO);
198
199 /* allow nested virtualization in KVM/SVM */
200 static int nested = true;
201 module_param(nested, int, S_IRUGO);
202
203 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
204 static void svm_complete_interrupts(struct vcpu_svm *svm);
205
206 static int nested_svm_exit_handled(struct vcpu_svm *svm);
207 static int nested_svm_intercept(struct vcpu_svm *svm);
208 static int nested_svm_vmexit(struct vcpu_svm *svm);
209 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
210 bool has_error_code, u32 error_code);
211 static u64 __scale_tsc(u64 ratio, u64 tsc);
212
213 enum {
214 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
215 pause filter count */
216 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
217 VMCB_ASID, /* ASID */
218 VMCB_INTR, /* int_ctl, int_vector */
219 VMCB_NPT, /* npt_en, nCR3, gPAT */
220 VMCB_CR, /* CR0, CR3, CR4, EFER */
221 VMCB_DR, /* DR6, DR7 */
222 VMCB_DT, /* GDT, IDT */
223 VMCB_SEG, /* CS, DS, SS, ES, CPL */
224 VMCB_CR2, /* CR2 only */
225 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
226 VMCB_DIRTY_MAX,
227 };
228
229 /* TPR and CR2 are always written before VMRUN */
230 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
231
232 static inline void mark_all_dirty(struct vmcb *vmcb)
233 {
234 vmcb->control.clean = 0;
235 }
236
237 static inline void mark_all_clean(struct vmcb *vmcb)
238 {
239 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
240 & ~VMCB_ALWAYS_DIRTY_MASK;
241 }
242
243 static inline void mark_dirty(struct vmcb *vmcb, int bit)
244 {
245 vmcb->control.clean &= ~(1 << bit);
246 }
247
248 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
249 {
250 return container_of(vcpu, struct vcpu_svm, vcpu);
251 }
252
253 static void recalc_intercepts(struct vcpu_svm *svm)
254 {
255 struct vmcb_control_area *c, *h;
256 struct nested_state *g;
257
258 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
259
260 if (!is_guest_mode(&svm->vcpu))
261 return;
262
263 c = &svm->vmcb->control;
264 h = &svm->nested.hsave->control;
265 g = &svm->nested;
266
267 c->intercept_cr = h->intercept_cr | g->intercept_cr;
268 c->intercept_dr = h->intercept_dr | g->intercept_dr;
269 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
270 c->intercept = h->intercept | g->intercept;
271 }
272
273 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
274 {
275 if (is_guest_mode(&svm->vcpu))
276 return svm->nested.hsave;
277 else
278 return svm->vmcb;
279 }
280
281 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
282 {
283 struct vmcb *vmcb = get_host_vmcb(svm);
284
285 vmcb->control.intercept_cr |= (1U << bit);
286
287 recalc_intercepts(svm);
288 }
289
290 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
291 {
292 struct vmcb *vmcb = get_host_vmcb(svm);
293
294 vmcb->control.intercept_cr &= ~(1U << bit);
295
296 recalc_intercepts(svm);
297 }
298
299 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
300 {
301 struct vmcb *vmcb = get_host_vmcb(svm);
302
303 return vmcb->control.intercept_cr & (1U << bit);
304 }
305
306 static inline void set_dr_intercept(struct vcpu_svm *svm, int bit)
307 {
308 struct vmcb *vmcb = get_host_vmcb(svm);
309
310 vmcb->control.intercept_dr |= (1U << bit);
311
312 recalc_intercepts(svm);
313 }
314
315 static inline void clr_dr_intercept(struct vcpu_svm *svm, int bit)
316 {
317 struct vmcb *vmcb = get_host_vmcb(svm);
318
319 vmcb->control.intercept_dr &= ~(1U << bit);
320
321 recalc_intercepts(svm);
322 }
323
324 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
325 {
326 struct vmcb *vmcb = get_host_vmcb(svm);
327
328 vmcb->control.intercept_exceptions |= (1U << bit);
329
330 recalc_intercepts(svm);
331 }
332
333 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
334 {
335 struct vmcb *vmcb = get_host_vmcb(svm);
336
337 vmcb->control.intercept_exceptions &= ~(1U << bit);
338
339 recalc_intercepts(svm);
340 }
341
342 static inline void set_intercept(struct vcpu_svm *svm, int bit)
343 {
344 struct vmcb *vmcb = get_host_vmcb(svm);
345
346 vmcb->control.intercept |= (1ULL << bit);
347
348 recalc_intercepts(svm);
349 }
350
351 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
352 {
353 struct vmcb *vmcb = get_host_vmcb(svm);
354
355 vmcb->control.intercept &= ~(1ULL << bit);
356
357 recalc_intercepts(svm);
358 }
359
360 static inline void enable_gif(struct vcpu_svm *svm)
361 {
362 svm->vcpu.arch.hflags |= HF_GIF_MASK;
363 }
364
365 static inline void disable_gif(struct vcpu_svm *svm)
366 {
367 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
368 }
369
370 static inline bool gif_set(struct vcpu_svm *svm)
371 {
372 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
373 }
374
375 static unsigned long iopm_base;
376
377 struct kvm_ldttss_desc {
378 u16 limit0;
379 u16 base0;
380 unsigned base1:8, type:5, dpl:2, p:1;
381 unsigned limit1:4, zero0:3, g:1, base2:8;
382 u32 base3;
383 u32 zero1;
384 } __attribute__((packed));
385
386 struct svm_cpu_data {
387 int cpu;
388
389 u64 asid_generation;
390 u32 max_asid;
391 u32 next_asid;
392 struct kvm_ldttss_desc *tss_desc;
393
394 struct page *save_area;
395 };
396
397 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
398
399 struct svm_init_data {
400 int cpu;
401 int r;
402 };
403
404 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
405
406 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
407 #define MSRS_RANGE_SIZE 2048
408 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
409
410 static u32 svm_msrpm_offset(u32 msr)
411 {
412 u32 offset;
413 int i;
414
415 for (i = 0; i < NUM_MSR_MAPS; i++) {
416 if (msr < msrpm_ranges[i] ||
417 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
418 continue;
419
420 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
421 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
422
423 /* Now we have the u8 offset - but need the u32 offset */
424 return offset / 4;
425 }
426
427 /* MSR not in any range */
428 return MSR_INVALID;
429 }
430
431 #define MAX_INST_SIZE 15
432
433 static inline void clgi(void)
434 {
435 asm volatile (__ex(SVM_CLGI));
436 }
437
438 static inline void stgi(void)
439 {
440 asm volatile (__ex(SVM_STGI));
441 }
442
443 static inline void invlpga(unsigned long addr, u32 asid)
444 {
445 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
446 }
447
448 static int get_npt_level(void)
449 {
450 #ifdef CONFIG_X86_64
451 return PT64_ROOT_LEVEL;
452 #else
453 return PT32E_ROOT_LEVEL;
454 #endif
455 }
456
457 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
458 {
459 vcpu->arch.efer = efer;
460 if (!npt_enabled && !(efer & EFER_LMA))
461 efer &= ~EFER_LME;
462
463 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
464 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
465 }
466
467 static int is_external_interrupt(u32 info)
468 {
469 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
470 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
471 }
472
473 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
474 {
475 struct vcpu_svm *svm = to_svm(vcpu);
476 u32 ret = 0;
477
478 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
479 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
480 return ret & mask;
481 }
482
483 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
484 {
485 struct vcpu_svm *svm = to_svm(vcpu);
486
487 if (mask == 0)
488 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
489 else
490 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
491
492 }
493
494 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
495 {
496 struct vcpu_svm *svm = to_svm(vcpu);
497
498 if (svm->vmcb->control.next_rip != 0)
499 svm->next_rip = svm->vmcb->control.next_rip;
500
501 if (!svm->next_rip) {
502 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
503 EMULATE_DONE)
504 printk(KERN_DEBUG "%s: NOP\n", __func__);
505 return;
506 }
507 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
508 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
509 __func__, kvm_rip_read(vcpu), svm->next_rip);
510
511 kvm_rip_write(vcpu, svm->next_rip);
512 svm_set_interrupt_shadow(vcpu, 0);
513 }
514
515 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
516 bool has_error_code, u32 error_code,
517 bool reinject)
518 {
519 struct vcpu_svm *svm = to_svm(vcpu);
520
521 /*
522 * If we are within a nested VM we'd better #VMEXIT and let the guest
523 * handle the exception
524 */
525 if (!reinject &&
526 nested_svm_check_exception(svm, nr, has_error_code, error_code))
527 return;
528
529 if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
530 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
531
532 /*
533 * For guest debugging where we have to reinject #BP if some
534 * INT3 is guest-owned:
535 * Emulate nRIP by moving RIP forward. Will fail if injection
536 * raises a fault that is not intercepted. Still better than
537 * failing in all cases.
538 */
539 skip_emulated_instruction(&svm->vcpu);
540 rip = kvm_rip_read(&svm->vcpu);
541 svm->int3_rip = rip + svm->vmcb->save.cs.base;
542 svm->int3_injected = rip - old_rip;
543 }
544
545 svm->vmcb->control.event_inj = nr
546 | SVM_EVTINJ_VALID
547 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
548 | SVM_EVTINJ_TYPE_EXEPT;
549 svm->vmcb->control.event_inj_err = error_code;
550 }
551
552 static void svm_init_erratum_383(void)
553 {
554 u32 low, high;
555 int err;
556 u64 val;
557
558 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
559 return;
560
561 /* Use _safe variants to not break nested virtualization */
562 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
563 if (err)
564 return;
565
566 val |= (1ULL << 47);
567
568 low = lower_32_bits(val);
569 high = upper_32_bits(val);
570
571 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
572
573 erratum_383_found = true;
574 }
575
576 static void svm_init_osvw(struct kvm_vcpu *vcpu)
577 {
578 /*
579 * Guests should see errata 400 and 415 as fixed (assuming that
580 * HLT and IO instructions are intercepted).
581 */
582 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
583 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
584
585 /*
586 * By increasing VCPU's osvw.length to 3 we are telling the guest that
587 * all osvw.status bits inside that length, including bit 0 (which is
588 * reserved for erratum 298), are valid. However, if host processor's
589 * osvw_len is 0 then osvw_status[0] carries no information. We need to
590 * be conservative here and therefore we tell the guest that erratum 298
591 * is present (because we really don't know).
592 */
593 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
594 vcpu->arch.osvw.status |= 1;
595 }
596
597 static int has_svm(void)
598 {
599 const char *msg;
600
601 if (!cpu_has_svm(&msg)) {
602 printk(KERN_INFO "has_svm: %s\n", msg);
603 return 0;
604 }
605
606 return 1;
607 }
608
609 static void svm_hardware_disable(void *garbage)
610 {
611 /* Make sure we clean up behind us */
612 if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
613 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
614
615 cpu_svm_disable();
616
617 amd_pmu_disable_virt();
618 }
619
620 static int svm_hardware_enable(void *garbage)
621 {
622
623 struct svm_cpu_data *sd;
624 uint64_t efer;
625 struct desc_ptr gdt_descr;
626 struct desc_struct *gdt;
627 int me = raw_smp_processor_id();
628
629 rdmsrl(MSR_EFER, efer);
630 if (efer & EFER_SVME)
631 return -EBUSY;
632
633 if (!has_svm()) {
634 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
635 return -EINVAL;
636 }
637 sd = per_cpu(svm_data, me);
638 if (!sd) {
639 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
640 return -EINVAL;
641 }
642
643 sd->asid_generation = 1;
644 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
645 sd->next_asid = sd->max_asid + 1;
646
647 native_store_gdt(&gdt_descr);
648 gdt = (struct desc_struct *)gdt_descr.address;
649 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
650
651 wrmsrl(MSR_EFER, efer | EFER_SVME);
652
653 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
654
655 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
656 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
657 __get_cpu_var(current_tsc_ratio) = TSC_RATIO_DEFAULT;
658 }
659
660
661 /*
662 * Get OSVW bits.
663 *
664 * Note that it is possible to have a system with mixed processor
665 * revisions and therefore different OSVW bits. If bits are not the same
666 * on different processors then choose the worst case (i.e. if erratum
667 * is present on one processor and not on another then assume that the
668 * erratum is present everywhere).
669 */
670 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
671 uint64_t len, status = 0;
672 int err;
673
674 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
675 if (!err)
676 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
677 &err);
678
679 if (err)
680 osvw_status = osvw_len = 0;
681 else {
682 if (len < osvw_len)
683 osvw_len = len;
684 osvw_status |= status;
685 osvw_status &= (1ULL << osvw_len) - 1;
686 }
687 } else
688 osvw_status = osvw_len = 0;
689
690 svm_init_erratum_383();
691
692 amd_pmu_enable_virt();
693
694 return 0;
695 }
696
697 static void svm_cpu_uninit(int cpu)
698 {
699 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
700
701 if (!sd)
702 return;
703
704 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
705 __free_page(sd->save_area);
706 kfree(sd);
707 }
708
709 static int svm_cpu_init(int cpu)
710 {
711 struct svm_cpu_data *sd;
712 int r;
713
714 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
715 if (!sd)
716 return -ENOMEM;
717 sd->cpu = cpu;
718 sd->save_area = alloc_page(GFP_KERNEL);
719 r = -ENOMEM;
720 if (!sd->save_area)
721 goto err_1;
722
723 per_cpu(svm_data, cpu) = sd;
724
725 return 0;
726
727 err_1:
728 kfree(sd);
729 return r;
730
731 }
732
733 static bool valid_msr_intercept(u32 index)
734 {
735 int i;
736
737 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
738 if (direct_access_msrs[i].index == index)
739 return true;
740
741 return false;
742 }
743
744 static void set_msr_interception(u32 *msrpm, unsigned msr,
745 int read, int write)
746 {
747 u8 bit_read, bit_write;
748 unsigned long tmp;
749 u32 offset;
750
751 /*
752 * If this warning triggers extend the direct_access_msrs list at the
753 * beginning of the file
754 */
755 WARN_ON(!valid_msr_intercept(msr));
756
757 offset = svm_msrpm_offset(msr);
758 bit_read = 2 * (msr & 0x0f);
759 bit_write = 2 * (msr & 0x0f) + 1;
760 tmp = msrpm[offset];
761
762 BUG_ON(offset == MSR_INVALID);
763
764 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
765 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
766
767 msrpm[offset] = tmp;
768 }
769
770 static void svm_vcpu_init_msrpm(u32 *msrpm)
771 {
772 int i;
773
774 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
775
776 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
777 if (!direct_access_msrs[i].always)
778 continue;
779
780 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
781 }
782 }
783
784 static void add_msr_offset(u32 offset)
785 {
786 int i;
787
788 for (i = 0; i < MSRPM_OFFSETS; ++i) {
789
790 /* Offset already in list? */
791 if (msrpm_offsets[i] == offset)
792 return;
793
794 /* Slot used by another offset? */
795 if (msrpm_offsets[i] != MSR_INVALID)
796 continue;
797
798 /* Add offset to list */
799 msrpm_offsets[i] = offset;
800
801 return;
802 }
803
804 /*
805 * If this BUG triggers the msrpm_offsets table has an overflow. Just
806 * increase MSRPM_OFFSETS in this case.
807 */
808 BUG();
809 }
810
811 static void init_msrpm_offsets(void)
812 {
813 int i;
814
815 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
816
817 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
818 u32 offset;
819
820 offset = svm_msrpm_offset(direct_access_msrs[i].index);
821 BUG_ON(offset == MSR_INVALID);
822
823 add_msr_offset(offset);
824 }
825 }
826
827 static void svm_enable_lbrv(struct vcpu_svm *svm)
828 {
829 u32 *msrpm = svm->msrpm;
830
831 svm->vmcb->control.lbr_ctl = 1;
832 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
833 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
834 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
835 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
836 }
837
838 static void svm_disable_lbrv(struct vcpu_svm *svm)
839 {
840 u32 *msrpm = svm->msrpm;
841
842 svm->vmcb->control.lbr_ctl = 0;
843 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
844 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
845 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
846 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
847 }
848
849 static __init int svm_hardware_setup(void)
850 {
851 int cpu;
852 struct page *iopm_pages;
853 void *iopm_va;
854 int r;
855
856 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
857
858 if (!iopm_pages)
859 return -ENOMEM;
860
861 iopm_va = page_address(iopm_pages);
862 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
863 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
864
865 init_msrpm_offsets();
866
867 if (boot_cpu_has(X86_FEATURE_NX))
868 kvm_enable_efer_bits(EFER_NX);
869
870 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
871 kvm_enable_efer_bits(EFER_FFXSR);
872
873 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
874 u64 max;
875
876 kvm_has_tsc_control = true;
877
878 /*
879 * Make sure the user can only configure tsc_khz values that
880 * fit into a signed integer.
881 * A min value is not calculated needed because it will always
882 * be 1 on all machines and a value of 0 is used to disable
883 * tsc-scaling for the vcpu.
884 */
885 max = min(0x7fffffffULL, __scale_tsc(tsc_khz, TSC_RATIO_MAX));
886
887 kvm_max_guest_tsc_khz = max;
888 }
889
890 if (nested) {
891 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
892 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
893 }
894
895 for_each_possible_cpu(cpu) {
896 r = svm_cpu_init(cpu);
897 if (r)
898 goto err;
899 }
900
901 if (!boot_cpu_has(X86_FEATURE_NPT))
902 npt_enabled = false;
903
904 if (npt_enabled && !npt) {
905 printk(KERN_INFO "kvm: Nested Paging disabled\n");
906 npt_enabled = false;
907 }
908
909 if (npt_enabled) {
910 printk(KERN_INFO "kvm: Nested Paging enabled\n");
911 kvm_enable_tdp();
912 } else
913 kvm_disable_tdp();
914
915 return 0;
916
917 err:
918 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
919 iopm_base = 0;
920 return r;
921 }
922
923 static __exit void svm_hardware_unsetup(void)
924 {
925 int cpu;
926
927 for_each_possible_cpu(cpu)
928 svm_cpu_uninit(cpu);
929
930 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
931 iopm_base = 0;
932 }
933
934 static void init_seg(struct vmcb_seg *seg)
935 {
936 seg->selector = 0;
937 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
938 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
939 seg->limit = 0xffff;
940 seg->base = 0;
941 }
942
943 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
944 {
945 seg->selector = 0;
946 seg->attrib = SVM_SELECTOR_P_MASK | type;
947 seg->limit = 0xffff;
948 seg->base = 0;
949 }
950
951 static u64 __scale_tsc(u64 ratio, u64 tsc)
952 {
953 u64 mult, frac, _tsc;
954
955 mult = ratio >> 32;
956 frac = ratio & ((1ULL << 32) - 1);
957
958 _tsc = tsc;
959 _tsc *= mult;
960 _tsc += (tsc >> 32) * frac;
961 _tsc += ((tsc & ((1ULL << 32) - 1)) * frac) >> 32;
962
963 return _tsc;
964 }
965
966 static u64 svm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
967 {
968 struct vcpu_svm *svm = to_svm(vcpu);
969 u64 _tsc = tsc;
970
971 if (svm->tsc_ratio != TSC_RATIO_DEFAULT)
972 _tsc = __scale_tsc(svm->tsc_ratio, tsc);
973
974 return _tsc;
975 }
976
977 static void svm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
978 {
979 struct vcpu_svm *svm = to_svm(vcpu);
980 u64 ratio;
981 u64 khz;
982
983 /* Guest TSC same frequency as host TSC? */
984 if (!scale) {
985 svm->tsc_ratio = TSC_RATIO_DEFAULT;
986 return;
987 }
988
989 /* TSC scaling supported? */
990 if (!boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
991 if (user_tsc_khz > tsc_khz) {
992 vcpu->arch.tsc_catchup = 1;
993 vcpu->arch.tsc_always_catchup = 1;
994 } else
995 WARN(1, "user requested TSC rate below hardware speed\n");
996 return;
997 }
998
999 khz = user_tsc_khz;
1000
1001 /* TSC scaling required - calculate ratio */
1002 ratio = khz << 32;
1003 do_div(ratio, tsc_khz);
1004
1005 if (ratio == 0 || ratio & TSC_RATIO_RSVD) {
1006 WARN_ONCE(1, "Invalid TSC ratio - virtual-tsc-khz=%u\n",
1007 user_tsc_khz);
1008 return;
1009 }
1010 svm->tsc_ratio = ratio;
1011 }
1012
1013 static u64 svm_read_tsc_offset(struct kvm_vcpu *vcpu)
1014 {
1015 struct vcpu_svm *svm = to_svm(vcpu);
1016
1017 return svm->vmcb->control.tsc_offset;
1018 }
1019
1020 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1021 {
1022 struct vcpu_svm *svm = to_svm(vcpu);
1023 u64 g_tsc_offset = 0;
1024
1025 if (is_guest_mode(vcpu)) {
1026 g_tsc_offset = svm->vmcb->control.tsc_offset -
1027 svm->nested.hsave->control.tsc_offset;
1028 svm->nested.hsave->control.tsc_offset = offset;
1029 } else
1030 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1031 svm->vmcb->control.tsc_offset,
1032 offset);
1033
1034 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1035
1036 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1037 }
1038
1039 static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
1040 {
1041 struct vcpu_svm *svm = to_svm(vcpu);
1042
1043 WARN_ON(adjustment < 0);
1044 if (host)
1045 adjustment = svm_scale_tsc(vcpu, adjustment);
1046
1047 svm->vmcb->control.tsc_offset += adjustment;
1048 if (is_guest_mode(vcpu))
1049 svm->nested.hsave->control.tsc_offset += adjustment;
1050 else
1051 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1052 svm->vmcb->control.tsc_offset - adjustment,
1053 svm->vmcb->control.tsc_offset);
1054
1055 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1056 }
1057
1058 static u64 svm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1059 {
1060 u64 tsc;
1061
1062 tsc = svm_scale_tsc(vcpu, native_read_tsc());
1063
1064 return target_tsc - tsc;
1065 }
1066
1067 static void init_vmcb(struct vcpu_svm *svm)
1068 {
1069 struct vmcb_control_area *control = &svm->vmcb->control;
1070 struct vmcb_save_area *save = &svm->vmcb->save;
1071
1072 svm->vcpu.fpu_active = 1;
1073 svm->vcpu.arch.hflags = 0;
1074
1075 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1076 set_cr_intercept(svm, INTERCEPT_CR3_READ);
1077 set_cr_intercept(svm, INTERCEPT_CR4_READ);
1078 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1079 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1080 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1081 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1082
1083 set_dr_intercept(svm, INTERCEPT_DR0_READ);
1084 set_dr_intercept(svm, INTERCEPT_DR1_READ);
1085 set_dr_intercept(svm, INTERCEPT_DR2_READ);
1086 set_dr_intercept(svm, INTERCEPT_DR3_READ);
1087 set_dr_intercept(svm, INTERCEPT_DR4_READ);
1088 set_dr_intercept(svm, INTERCEPT_DR5_READ);
1089 set_dr_intercept(svm, INTERCEPT_DR6_READ);
1090 set_dr_intercept(svm, INTERCEPT_DR7_READ);
1091
1092 set_dr_intercept(svm, INTERCEPT_DR0_WRITE);
1093 set_dr_intercept(svm, INTERCEPT_DR1_WRITE);
1094 set_dr_intercept(svm, INTERCEPT_DR2_WRITE);
1095 set_dr_intercept(svm, INTERCEPT_DR3_WRITE);
1096 set_dr_intercept(svm, INTERCEPT_DR4_WRITE);
1097 set_dr_intercept(svm, INTERCEPT_DR5_WRITE);
1098 set_dr_intercept(svm, INTERCEPT_DR6_WRITE);
1099 set_dr_intercept(svm, INTERCEPT_DR7_WRITE);
1100
1101 set_exception_intercept(svm, PF_VECTOR);
1102 set_exception_intercept(svm, UD_VECTOR);
1103 set_exception_intercept(svm, MC_VECTOR);
1104
1105 set_intercept(svm, INTERCEPT_INTR);
1106 set_intercept(svm, INTERCEPT_NMI);
1107 set_intercept(svm, INTERCEPT_SMI);
1108 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1109 set_intercept(svm, INTERCEPT_RDPMC);
1110 set_intercept(svm, INTERCEPT_CPUID);
1111 set_intercept(svm, INTERCEPT_INVD);
1112 set_intercept(svm, INTERCEPT_HLT);
1113 set_intercept(svm, INTERCEPT_INVLPG);
1114 set_intercept(svm, INTERCEPT_INVLPGA);
1115 set_intercept(svm, INTERCEPT_IOIO_PROT);
1116 set_intercept(svm, INTERCEPT_MSR_PROT);
1117 set_intercept(svm, INTERCEPT_TASK_SWITCH);
1118 set_intercept(svm, INTERCEPT_SHUTDOWN);
1119 set_intercept(svm, INTERCEPT_VMRUN);
1120 set_intercept(svm, INTERCEPT_VMMCALL);
1121 set_intercept(svm, INTERCEPT_VMLOAD);
1122 set_intercept(svm, INTERCEPT_VMSAVE);
1123 set_intercept(svm, INTERCEPT_STGI);
1124 set_intercept(svm, INTERCEPT_CLGI);
1125 set_intercept(svm, INTERCEPT_SKINIT);
1126 set_intercept(svm, INTERCEPT_WBINVD);
1127 set_intercept(svm, INTERCEPT_MONITOR);
1128 set_intercept(svm, INTERCEPT_MWAIT);
1129 set_intercept(svm, INTERCEPT_XSETBV);
1130
1131 control->iopm_base_pa = iopm_base;
1132 control->msrpm_base_pa = __pa(svm->msrpm);
1133 control->int_ctl = V_INTR_MASKING_MASK;
1134
1135 init_seg(&save->es);
1136 init_seg(&save->ss);
1137 init_seg(&save->ds);
1138 init_seg(&save->fs);
1139 init_seg(&save->gs);
1140
1141 save->cs.selector = 0xf000;
1142 save->cs.base = 0xffff0000;
1143 /* Executable/Readable Code Segment */
1144 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1145 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1146 save->cs.limit = 0xffff;
1147
1148 save->gdtr.limit = 0xffff;
1149 save->idtr.limit = 0xffff;
1150
1151 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1152 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1153
1154 svm_set_efer(&svm->vcpu, 0);
1155 save->dr6 = 0xffff0ff0;
1156 kvm_set_rflags(&svm->vcpu, 2);
1157 save->rip = 0x0000fff0;
1158 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1159
1160 /*
1161 * This is the guest-visible cr0 value.
1162 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1163 */
1164 svm->vcpu.arch.cr0 = 0;
1165 (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1166
1167 save->cr4 = X86_CR4_PAE;
1168 /* rdx = ?? */
1169
1170 if (npt_enabled) {
1171 /* Setup VMCB for Nested Paging */
1172 control->nested_ctl = 1;
1173 clr_intercept(svm, INTERCEPT_INVLPG);
1174 clr_exception_intercept(svm, PF_VECTOR);
1175 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1176 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1177 save->g_pat = 0x0007040600070406ULL;
1178 save->cr3 = 0;
1179 save->cr4 = 0;
1180 }
1181 svm->asid_generation = 0;
1182
1183 svm->nested.vmcb = 0;
1184 svm->vcpu.arch.hflags = 0;
1185
1186 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1187 control->pause_filter_count = 3000;
1188 set_intercept(svm, INTERCEPT_PAUSE);
1189 }
1190
1191 mark_all_dirty(svm->vmcb);
1192
1193 enable_gif(svm);
1194 }
1195
1196 static void svm_vcpu_reset(struct kvm_vcpu *vcpu)
1197 {
1198 struct vcpu_svm *svm = to_svm(vcpu);
1199 u32 dummy;
1200 u32 eax = 1;
1201
1202 init_vmcb(svm);
1203
1204 kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy);
1205 kvm_register_write(vcpu, VCPU_REGS_RDX, eax);
1206 }
1207
1208 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1209 {
1210 struct vcpu_svm *svm;
1211 struct page *page;
1212 struct page *msrpm_pages;
1213 struct page *hsave_page;
1214 struct page *nested_msrpm_pages;
1215 int err;
1216
1217 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1218 if (!svm) {
1219 err = -ENOMEM;
1220 goto out;
1221 }
1222
1223 svm->tsc_ratio = TSC_RATIO_DEFAULT;
1224
1225 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1226 if (err)
1227 goto free_svm;
1228
1229 err = -ENOMEM;
1230 page = alloc_page(GFP_KERNEL);
1231 if (!page)
1232 goto uninit;
1233
1234 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1235 if (!msrpm_pages)
1236 goto free_page1;
1237
1238 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1239 if (!nested_msrpm_pages)
1240 goto free_page2;
1241
1242 hsave_page = alloc_page(GFP_KERNEL);
1243 if (!hsave_page)
1244 goto free_page3;
1245
1246 svm->nested.hsave = page_address(hsave_page);
1247
1248 svm->msrpm = page_address(msrpm_pages);
1249 svm_vcpu_init_msrpm(svm->msrpm);
1250
1251 svm->nested.msrpm = page_address(nested_msrpm_pages);
1252 svm_vcpu_init_msrpm(svm->nested.msrpm);
1253
1254 svm->vmcb = page_address(page);
1255 clear_page(svm->vmcb);
1256 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1257 svm->asid_generation = 0;
1258 init_vmcb(svm);
1259
1260 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1261 if (kvm_vcpu_is_bsp(&svm->vcpu))
1262 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1263
1264 svm_init_osvw(&svm->vcpu);
1265
1266 return &svm->vcpu;
1267
1268 free_page3:
1269 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1270 free_page2:
1271 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1272 free_page1:
1273 __free_page(page);
1274 uninit:
1275 kvm_vcpu_uninit(&svm->vcpu);
1276 free_svm:
1277 kmem_cache_free(kvm_vcpu_cache, svm);
1278 out:
1279 return ERR_PTR(err);
1280 }
1281
1282 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1283 {
1284 struct vcpu_svm *svm = to_svm(vcpu);
1285
1286 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1287 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1288 __free_page(virt_to_page(svm->nested.hsave));
1289 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1290 kvm_vcpu_uninit(vcpu);
1291 kmem_cache_free(kvm_vcpu_cache, svm);
1292 }
1293
1294 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1295 {
1296 struct vcpu_svm *svm = to_svm(vcpu);
1297 int i;
1298
1299 if (unlikely(cpu != vcpu->cpu)) {
1300 svm->asid_generation = 0;
1301 mark_all_dirty(svm->vmcb);
1302 }
1303
1304 #ifdef CONFIG_X86_64
1305 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1306 #endif
1307 savesegment(fs, svm->host.fs);
1308 savesegment(gs, svm->host.gs);
1309 svm->host.ldt = kvm_read_ldt();
1310
1311 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1312 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1313
1314 if (static_cpu_has(X86_FEATURE_TSCRATEMSR) &&
1315 svm->tsc_ratio != __get_cpu_var(current_tsc_ratio)) {
1316 __get_cpu_var(current_tsc_ratio) = svm->tsc_ratio;
1317 wrmsrl(MSR_AMD64_TSC_RATIO, svm->tsc_ratio);
1318 }
1319 }
1320
1321 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1322 {
1323 struct vcpu_svm *svm = to_svm(vcpu);
1324 int i;
1325
1326 ++vcpu->stat.host_state_reload;
1327 kvm_load_ldt(svm->host.ldt);
1328 #ifdef CONFIG_X86_64
1329 loadsegment(fs, svm->host.fs);
1330 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1331 load_gs_index(svm->host.gs);
1332 #else
1333 #ifdef CONFIG_X86_32_LAZY_GS
1334 loadsegment(gs, svm->host.gs);
1335 #endif
1336 #endif
1337 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1338 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1339 }
1340
1341 static void svm_update_cpl(struct kvm_vcpu *vcpu)
1342 {
1343 struct vcpu_svm *svm = to_svm(vcpu);
1344 int cpl;
1345
1346 if (!is_protmode(vcpu))
1347 cpl = 0;
1348 else if (svm->vmcb->save.rflags & X86_EFLAGS_VM)
1349 cpl = 3;
1350 else
1351 cpl = svm->vmcb->save.cs.selector & 0x3;
1352
1353 svm->vmcb->save.cpl = cpl;
1354 }
1355
1356 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1357 {
1358 return to_svm(vcpu)->vmcb->save.rflags;
1359 }
1360
1361 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1362 {
1363 unsigned long old_rflags = to_svm(vcpu)->vmcb->save.rflags;
1364
1365 to_svm(vcpu)->vmcb->save.rflags = rflags;
1366 if ((old_rflags ^ rflags) & X86_EFLAGS_VM)
1367 svm_update_cpl(vcpu);
1368 }
1369
1370 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1371 {
1372 switch (reg) {
1373 case VCPU_EXREG_PDPTR:
1374 BUG_ON(!npt_enabled);
1375 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1376 break;
1377 default:
1378 BUG();
1379 }
1380 }
1381
1382 static void svm_set_vintr(struct vcpu_svm *svm)
1383 {
1384 set_intercept(svm, INTERCEPT_VINTR);
1385 }
1386
1387 static void svm_clear_vintr(struct vcpu_svm *svm)
1388 {
1389 clr_intercept(svm, INTERCEPT_VINTR);
1390 }
1391
1392 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1393 {
1394 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1395
1396 switch (seg) {
1397 case VCPU_SREG_CS: return &save->cs;
1398 case VCPU_SREG_DS: return &save->ds;
1399 case VCPU_SREG_ES: return &save->es;
1400 case VCPU_SREG_FS: return &save->fs;
1401 case VCPU_SREG_GS: return &save->gs;
1402 case VCPU_SREG_SS: return &save->ss;
1403 case VCPU_SREG_TR: return &save->tr;
1404 case VCPU_SREG_LDTR: return &save->ldtr;
1405 }
1406 BUG();
1407 return NULL;
1408 }
1409
1410 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1411 {
1412 struct vmcb_seg *s = svm_seg(vcpu, seg);
1413
1414 return s->base;
1415 }
1416
1417 static void svm_get_segment(struct kvm_vcpu *vcpu,
1418 struct kvm_segment *var, int seg)
1419 {
1420 struct vmcb_seg *s = svm_seg(vcpu, seg);
1421
1422 var->base = s->base;
1423 var->limit = s->limit;
1424 var->selector = s->selector;
1425 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1426 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1427 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1428 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1429 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1430 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1431 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1432 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
1433
1434 /*
1435 * AMD's VMCB does not have an explicit unusable field, so emulate it
1436 * for cross vendor migration purposes by "not present"
1437 */
1438 var->unusable = !var->present || (var->type == 0);
1439
1440 switch (seg) {
1441 case VCPU_SREG_CS:
1442 /*
1443 * SVM always stores 0 for the 'G' bit in the CS selector in
1444 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1445 * Intel's VMENTRY has a check on the 'G' bit.
1446 */
1447 var->g = s->limit > 0xfffff;
1448 break;
1449 case VCPU_SREG_TR:
1450 /*
1451 * Work around a bug where the busy flag in the tr selector
1452 * isn't exposed
1453 */
1454 var->type |= 0x2;
1455 break;
1456 case VCPU_SREG_DS:
1457 case VCPU_SREG_ES:
1458 case VCPU_SREG_FS:
1459 case VCPU_SREG_GS:
1460 /*
1461 * The accessed bit must always be set in the segment
1462 * descriptor cache, although it can be cleared in the
1463 * descriptor, the cached bit always remains at 1. Since
1464 * Intel has a check on this, set it here to support
1465 * cross-vendor migration.
1466 */
1467 if (!var->unusable)
1468 var->type |= 0x1;
1469 break;
1470 case VCPU_SREG_SS:
1471 /*
1472 * On AMD CPUs sometimes the DB bit in the segment
1473 * descriptor is left as 1, although the whole segment has
1474 * been made unusable. Clear it here to pass an Intel VMX
1475 * entry check when cross vendor migrating.
1476 */
1477 if (var->unusable)
1478 var->db = 0;
1479 break;
1480 }
1481 }
1482
1483 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1484 {
1485 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1486
1487 return save->cpl;
1488 }
1489
1490 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1491 {
1492 struct vcpu_svm *svm = to_svm(vcpu);
1493
1494 dt->size = svm->vmcb->save.idtr.limit;
1495 dt->address = svm->vmcb->save.idtr.base;
1496 }
1497
1498 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1499 {
1500 struct vcpu_svm *svm = to_svm(vcpu);
1501
1502 svm->vmcb->save.idtr.limit = dt->size;
1503 svm->vmcb->save.idtr.base = dt->address ;
1504 mark_dirty(svm->vmcb, VMCB_DT);
1505 }
1506
1507 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1508 {
1509 struct vcpu_svm *svm = to_svm(vcpu);
1510
1511 dt->size = svm->vmcb->save.gdtr.limit;
1512 dt->address = svm->vmcb->save.gdtr.base;
1513 }
1514
1515 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1516 {
1517 struct vcpu_svm *svm = to_svm(vcpu);
1518
1519 svm->vmcb->save.gdtr.limit = dt->size;
1520 svm->vmcb->save.gdtr.base = dt->address ;
1521 mark_dirty(svm->vmcb, VMCB_DT);
1522 }
1523
1524 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1525 {
1526 }
1527
1528 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
1529 {
1530 }
1531
1532 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1533 {
1534 }
1535
1536 static void update_cr0_intercept(struct vcpu_svm *svm)
1537 {
1538 ulong gcr0 = svm->vcpu.arch.cr0;
1539 u64 *hcr0 = &svm->vmcb->save.cr0;
1540
1541 if (!svm->vcpu.fpu_active)
1542 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1543 else
1544 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1545 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1546
1547 mark_dirty(svm->vmcb, VMCB_CR);
1548
1549 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1550 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1551 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1552 } else {
1553 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1554 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1555 }
1556 }
1557
1558 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1559 {
1560 struct vcpu_svm *svm = to_svm(vcpu);
1561
1562 #ifdef CONFIG_X86_64
1563 if (vcpu->arch.efer & EFER_LME) {
1564 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1565 vcpu->arch.efer |= EFER_LMA;
1566 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1567 }
1568
1569 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1570 vcpu->arch.efer &= ~EFER_LMA;
1571 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1572 }
1573 }
1574 #endif
1575 vcpu->arch.cr0 = cr0;
1576
1577 if (!npt_enabled)
1578 cr0 |= X86_CR0_PG | X86_CR0_WP;
1579
1580 if (!vcpu->fpu_active)
1581 cr0 |= X86_CR0_TS;
1582 /*
1583 * re-enable caching here because the QEMU bios
1584 * does not do it - this results in some delay at
1585 * reboot
1586 */
1587 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1588 svm->vmcb->save.cr0 = cr0;
1589 mark_dirty(svm->vmcb, VMCB_CR);
1590 update_cr0_intercept(svm);
1591 }
1592
1593 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1594 {
1595 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1596 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1597
1598 if (cr4 & X86_CR4_VMXE)
1599 return 1;
1600
1601 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1602 svm_flush_tlb(vcpu);
1603
1604 vcpu->arch.cr4 = cr4;
1605 if (!npt_enabled)
1606 cr4 |= X86_CR4_PAE;
1607 cr4 |= host_cr4_mce;
1608 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1609 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1610 return 0;
1611 }
1612
1613 static void svm_set_segment(struct kvm_vcpu *vcpu,
1614 struct kvm_segment *var, int seg)
1615 {
1616 struct vcpu_svm *svm = to_svm(vcpu);
1617 struct vmcb_seg *s = svm_seg(vcpu, seg);
1618
1619 s->base = var->base;
1620 s->limit = var->limit;
1621 s->selector = var->selector;
1622 if (var->unusable)
1623 s->attrib = 0;
1624 else {
1625 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1626 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1627 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1628 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1629 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1630 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1631 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1632 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1633 }
1634 if (seg == VCPU_SREG_CS)
1635 svm_update_cpl(vcpu);
1636
1637 mark_dirty(svm->vmcb, VMCB_SEG);
1638 }
1639
1640 static void update_db_bp_intercept(struct kvm_vcpu *vcpu)
1641 {
1642 struct vcpu_svm *svm = to_svm(vcpu);
1643
1644 clr_exception_intercept(svm, DB_VECTOR);
1645 clr_exception_intercept(svm, BP_VECTOR);
1646
1647 if (svm->nmi_singlestep)
1648 set_exception_intercept(svm, DB_VECTOR);
1649
1650 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1651 if (vcpu->guest_debug &
1652 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1653 set_exception_intercept(svm, DB_VECTOR);
1654 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1655 set_exception_intercept(svm, BP_VECTOR);
1656 } else
1657 vcpu->guest_debug = 0;
1658 }
1659
1660 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1661 {
1662 if (sd->next_asid > sd->max_asid) {
1663 ++sd->asid_generation;
1664 sd->next_asid = 1;
1665 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1666 }
1667
1668 svm->asid_generation = sd->asid_generation;
1669 svm->vmcb->control.asid = sd->next_asid++;
1670
1671 mark_dirty(svm->vmcb, VMCB_ASID);
1672 }
1673
1674 static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
1675 {
1676 return to_svm(vcpu)->vmcb->save.dr6;
1677 }
1678
1679 static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
1680 {
1681 struct vcpu_svm *svm = to_svm(vcpu);
1682
1683 svm->vmcb->save.dr6 = value;
1684 mark_dirty(svm->vmcb, VMCB_DR);
1685 }
1686
1687 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1688 {
1689 struct vcpu_svm *svm = to_svm(vcpu);
1690
1691 svm->vmcb->save.dr7 = value;
1692 mark_dirty(svm->vmcb, VMCB_DR);
1693 }
1694
1695 static int pf_interception(struct vcpu_svm *svm)
1696 {
1697 u64 fault_address = svm->vmcb->control.exit_info_2;
1698 u32 error_code;
1699 int r = 1;
1700
1701 switch (svm->apf_reason) {
1702 default:
1703 error_code = svm->vmcb->control.exit_info_1;
1704
1705 trace_kvm_page_fault(fault_address, error_code);
1706 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1707 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1708 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
1709 svm->vmcb->control.insn_bytes,
1710 svm->vmcb->control.insn_len);
1711 break;
1712 case KVM_PV_REASON_PAGE_NOT_PRESENT:
1713 svm->apf_reason = 0;
1714 local_irq_disable();
1715 kvm_async_pf_task_wait(fault_address);
1716 local_irq_enable();
1717 break;
1718 case KVM_PV_REASON_PAGE_READY:
1719 svm->apf_reason = 0;
1720 local_irq_disable();
1721 kvm_async_pf_task_wake(fault_address);
1722 local_irq_enable();
1723 break;
1724 }
1725 return r;
1726 }
1727
1728 static int db_interception(struct vcpu_svm *svm)
1729 {
1730 struct kvm_run *kvm_run = svm->vcpu.run;
1731
1732 if (!(svm->vcpu.guest_debug &
1733 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1734 !svm->nmi_singlestep) {
1735 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1736 return 1;
1737 }
1738
1739 if (svm->nmi_singlestep) {
1740 svm->nmi_singlestep = false;
1741 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1742 svm->vmcb->save.rflags &=
1743 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1744 update_db_bp_intercept(&svm->vcpu);
1745 }
1746
1747 if (svm->vcpu.guest_debug &
1748 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1749 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1750 kvm_run->debug.arch.pc =
1751 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1752 kvm_run->debug.arch.exception = DB_VECTOR;
1753 return 0;
1754 }
1755
1756 return 1;
1757 }
1758
1759 static int bp_interception(struct vcpu_svm *svm)
1760 {
1761 struct kvm_run *kvm_run = svm->vcpu.run;
1762
1763 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1764 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1765 kvm_run->debug.arch.exception = BP_VECTOR;
1766 return 0;
1767 }
1768
1769 static int ud_interception(struct vcpu_svm *svm)
1770 {
1771 int er;
1772
1773 er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD);
1774 if (er != EMULATE_DONE)
1775 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1776 return 1;
1777 }
1778
1779 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1780 {
1781 struct vcpu_svm *svm = to_svm(vcpu);
1782
1783 clr_exception_intercept(svm, NM_VECTOR);
1784
1785 svm->vcpu.fpu_active = 1;
1786 update_cr0_intercept(svm);
1787 }
1788
1789 static int nm_interception(struct vcpu_svm *svm)
1790 {
1791 svm_fpu_activate(&svm->vcpu);
1792 return 1;
1793 }
1794
1795 static bool is_erratum_383(void)
1796 {
1797 int err, i;
1798 u64 value;
1799
1800 if (!erratum_383_found)
1801 return false;
1802
1803 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1804 if (err)
1805 return false;
1806
1807 /* Bit 62 may or may not be set for this mce */
1808 value &= ~(1ULL << 62);
1809
1810 if (value != 0xb600000000010015ULL)
1811 return false;
1812
1813 /* Clear MCi_STATUS registers */
1814 for (i = 0; i < 6; ++i)
1815 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1816
1817 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1818 if (!err) {
1819 u32 low, high;
1820
1821 value &= ~(1ULL << 2);
1822 low = lower_32_bits(value);
1823 high = upper_32_bits(value);
1824
1825 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1826 }
1827
1828 /* Flush tlb to evict multi-match entries */
1829 __flush_tlb_all();
1830
1831 return true;
1832 }
1833
1834 static void svm_handle_mce(struct vcpu_svm *svm)
1835 {
1836 if (is_erratum_383()) {
1837 /*
1838 * Erratum 383 triggered. Guest state is corrupt so kill the
1839 * guest.
1840 */
1841 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1842
1843 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1844
1845 return;
1846 }
1847
1848 /*
1849 * On an #MC intercept the MCE handler is not called automatically in
1850 * the host. So do it by hand here.
1851 */
1852 asm volatile (
1853 "int $0x12\n");
1854 /* not sure if we ever come back to this point */
1855
1856 return;
1857 }
1858
1859 static int mc_interception(struct vcpu_svm *svm)
1860 {
1861 return 1;
1862 }
1863
1864 static int shutdown_interception(struct vcpu_svm *svm)
1865 {
1866 struct kvm_run *kvm_run = svm->vcpu.run;
1867
1868 /*
1869 * VMCB is undefined after a SHUTDOWN intercept
1870 * so reinitialize it.
1871 */
1872 clear_page(svm->vmcb);
1873 init_vmcb(svm);
1874
1875 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1876 return 0;
1877 }
1878
1879 static int io_interception(struct vcpu_svm *svm)
1880 {
1881 struct kvm_vcpu *vcpu = &svm->vcpu;
1882 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1883 int size, in, string;
1884 unsigned port;
1885
1886 ++svm->vcpu.stat.io_exits;
1887 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1888 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1889 if (string || in)
1890 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
1891
1892 port = io_info >> 16;
1893 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1894 svm->next_rip = svm->vmcb->control.exit_info_2;
1895 skip_emulated_instruction(&svm->vcpu);
1896
1897 return kvm_fast_pio_out(vcpu, size, port);
1898 }
1899
1900 static int nmi_interception(struct vcpu_svm *svm)
1901 {
1902 return 1;
1903 }
1904
1905 static int intr_interception(struct vcpu_svm *svm)
1906 {
1907 ++svm->vcpu.stat.irq_exits;
1908 return 1;
1909 }
1910
1911 static int nop_on_interception(struct vcpu_svm *svm)
1912 {
1913 return 1;
1914 }
1915
1916 static int halt_interception(struct vcpu_svm *svm)
1917 {
1918 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1919 skip_emulated_instruction(&svm->vcpu);
1920 return kvm_emulate_halt(&svm->vcpu);
1921 }
1922
1923 static int vmmcall_interception(struct vcpu_svm *svm)
1924 {
1925 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1926 skip_emulated_instruction(&svm->vcpu);
1927 kvm_emulate_hypercall(&svm->vcpu);
1928 return 1;
1929 }
1930
1931 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1932 {
1933 struct vcpu_svm *svm = to_svm(vcpu);
1934
1935 return svm->nested.nested_cr3;
1936 }
1937
1938 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
1939 {
1940 struct vcpu_svm *svm = to_svm(vcpu);
1941 u64 cr3 = svm->nested.nested_cr3;
1942 u64 pdpte;
1943 int ret;
1944
1945 ret = kvm_read_guest_page(vcpu->kvm, gpa_to_gfn(cr3), &pdpte,
1946 offset_in_page(cr3) + index * 8, 8);
1947 if (ret)
1948 return 0;
1949 return pdpte;
1950 }
1951
1952 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1953 unsigned long root)
1954 {
1955 struct vcpu_svm *svm = to_svm(vcpu);
1956
1957 svm->vmcb->control.nested_cr3 = root;
1958 mark_dirty(svm->vmcb, VMCB_NPT);
1959 svm_flush_tlb(vcpu);
1960 }
1961
1962 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
1963 struct x86_exception *fault)
1964 {
1965 struct vcpu_svm *svm = to_svm(vcpu);
1966
1967 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1968 svm->vmcb->control.exit_code_hi = 0;
1969 svm->vmcb->control.exit_info_1 = fault->error_code;
1970 svm->vmcb->control.exit_info_2 = fault->address;
1971
1972 nested_svm_vmexit(svm);
1973 }
1974
1975 static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
1976 {
1977 kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu);
1978
1979 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
1980 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
1981 vcpu->arch.mmu.get_pdptr = nested_svm_get_tdp_pdptr;
1982 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
1983 vcpu->arch.mmu.shadow_root_level = get_npt_level();
1984 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
1985 }
1986
1987 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
1988 {
1989 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
1990 }
1991
1992 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1993 {
1994 if (!(svm->vcpu.arch.efer & EFER_SVME)
1995 || !is_paging(&svm->vcpu)) {
1996 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1997 return 1;
1998 }
1999
2000 if (svm->vmcb->save.cpl) {
2001 kvm_inject_gp(&svm->vcpu, 0);
2002 return 1;
2003 }
2004
2005 return 0;
2006 }
2007
2008 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
2009 bool has_error_code, u32 error_code)
2010 {
2011 int vmexit;
2012
2013 if (!is_guest_mode(&svm->vcpu))
2014 return 0;
2015
2016 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
2017 svm->vmcb->control.exit_code_hi = 0;
2018 svm->vmcb->control.exit_info_1 = error_code;
2019 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
2020
2021 vmexit = nested_svm_intercept(svm);
2022 if (vmexit == NESTED_EXIT_DONE)
2023 svm->nested.exit_required = true;
2024
2025 return vmexit;
2026 }
2027
2028 /* This function returns true if it is save to enable the irq window */
2029 static inline bool nested_svm_intr(struct vcpu_svm *svm)
2030 {
2031 if (!is_guest_mode(&svm->vcpu))
2032 return true;
2033
2034 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2035 return true;
2036
2037 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
2038 return false;
2039
2040 /*
2041 * if vmexit was already requested (by intercepted exception
2042 * for instance) do not overwrite it with "external interrupt"
2043 * vmexit.
2044 */
2045 if (svm->nested.exit_required)
2046 return false;
2047
2048 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
2049 svm->vmcb->control.exit_info_1 = 0;
2050 svm->vmcb->control.exit_info_2 = 0;
2051
2052 if (svm->nested.intercept & 1ULL) {
2053 /*
2054 * The #vmexit can't be emulated here directly because this
2055 * code path runs with irqs and preemption disabled. A
2056 * #vmexit emulation might sleep. Only signal request for
2057 * the #vmexit here.
2058 */
2059 svm->nested.exit_required = true;
2060 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
2061 return false;
2062 }
2063
2064 return true;
2065 }
2066
2067 /* This function returns true if it is save to enable the nmi window */
2068 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
2069 {
2070 if (!is_guest_mode(&svm->vcpu))
2071 return true;
2072
2073 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
2074 return true;
2075
2076 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
2077 svm->nested.exit_required = true;
2078
2079 return false;
2080 }
2081
2082 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
2083 {
2084 struct page *page;
2085
2086 might_sleep();
2087
2088 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
2089 if (is_error_page(page))
2090 goto error;
2091
2092 *_page = page;
2093
2094 return kmap(page);
2095
2096 error:
2097 kvm_inject_gp(&svm->vcpu, 0);
2098
2099 return NULL;
2100 }
2101
2102 static void nested_svm_unmap(struct page *page)
2103 {
2104 kunmap(page);
2105 kvm_release_page_dirty(page);
2106 }
2107
2108 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
2109 {
2110 unsigned port;
2111 u8 val, bit;
2112 u64 gpa;
2113
2114 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
2115 return NESTED_EXIT_HOST;
2116
2117 port = svm->vmcb->control.exit_info_1 >> 16;
2118 gpa = svm->nested.vmcb_iopm + (port / 8);
2119 bit = port % 8;
2120 val = 0;
2121
2122 if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
2123 val &= (1 << bit);
2124
2125 return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2126 }
2127
2128 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
2129 {
2130 u32 offset, msr, value;
2131 int write, mask;
2132
2133 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2134 return NESTED_EXIT_HOST;
2135
2136 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2137 offset = svm_msrpm_offset(msr);
2138 write = svm->vmcb->control.exit_info_1 & 1;
2139 mask = 1 << ((2 * (msr & 0xf)) + write);
2140
2141 if (offset == MSR_INVALID)
2142 return NESTED_EXIT_DONE;
2143
2144 /* Offset is in 32 bit units but need in 8 bit units */
2145 offset *= 4;
2146
2147 if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
2148 return NESTED_EXIT_DONE;
2149
2150 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2151 }
2152
2153 static int nested_svm_exit_special(struct vcpu_svm *svm)
2154 {
2155 u32 exit_code = svm->vmcb->control.exit_code;
2156
2157 switch (exit_code) {
2158 case SVM_EXIT_INTR:
2159 case SVM_EXIT_NMI:
2160 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
2161 return NESTED_EXIT_HOST;
2162 case SVM_EXIT_NPF:
2163 /* For now we are always handling NPFs when using them */
2164 if (npt_enabled)
2165 return NESTED_EXIT_HOST;
2166 break;
2167 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
2168 /* When we're shadowing, trap PFs, but not async PF */
2169 if (!npt_enabled && svm->apf_reason == 0)
2170 return NESTED_EXIT_HOST;
2171 break;
2172 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
2173 nm_interception(svm);
2174 break;
2175 default:
2176 break;
2177 }
2178
2179 return NESTED_EXIT_CONTINUE;
2180 }
2181
2182 /*
2183 * If this function returns true, this #vmexit was already handled
2184 */
2185 static int nested_svm_intercept(struct vcpu_svm *svm)
2186 {
2187 u32 exit_code = svm->vmcb->control.exit_code;
2188 int vmexit = NESTED_EXIT_HOST;
2189
2190 switch (exit_code) {
2191 case SVM_EXIT_MSR:
2192 vmexit = nested_svm_exit_handled_msr(svm);
2193 break;
2194 case SVM_EXIT_IOIO:
2195 vmexit = nested_svm_intercept_ioio(svm);
2196 break;
2197 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2198 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2199 if (svm->nested.intercept_cr & bit)
2200 vmexit = NESTED_EXIT_DONE;
2201 break;
2202 }
2203 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2204 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2205 if (svm->nested.intercept_dr & bit)
2206 vmexit = NESTED_EXIT_DONE;
2207 break;
2208 }
2209 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2210 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2211 if (svm->nested.intercept_exceptions & excp_bits)
2212 vmexit = NESTED_EXIT_DONE;
2213 /* async page fault always cause vmexit */
2214 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2215 svm->apf_reason != 0)
2216 vmexit = NESTED_EXIT_DONE;
2217 break;
2218 }
2219 case SVM_EXIT_ERR: {
2220 vmexit = NESTED_EXIT_DONE;
2221 break;
2222 }
2223 default: {
2224 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2225 if (svm->nested.intercept & exit_bits)
2226 vmexit = NESTED_EXIT_DONE;
2227 }
2228 }
2229
2230 return vmexit;
2231 }
2232
2233 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2234 {
2235 int vmexit;
2236
2237 vmexit = nested_svm_intercept(svm);
2238
2239 if (vmexit == NESTED_EXIT_DONE)
2240 nested_svm_vmexit(svm);
2241
2242 return vmexit;
2243 }
2244
2245 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2246 {
2247 struct vmcb_control_area *dst = &dst_vmcb->control;
2248 struct vmcb_control_area *from = &from_vmcb->control;
2249
2250 dst->intercept_cr = from->intercept_cr;
2251 dst->intercept_dr = from->intercept_dr;
2252 dst->intercept_exceptions = from->intercept_exceptions;
2253 dst->intercept = from->intercept;
2254 dst->iopm_base_pa = from->iopm_base_pa;
2255 dst->msrpm_base_pa = from->msrpm_base_pa;
2256 dst->tsc_offset = from->tsc_offset;
2257 dst->asid = from->asid;
2258 dst->tlb_ctl = from->tlb_ctl;
2259 dst->int_ctl = from->int_ctl;
2260 dst->int_vector = from->int_vector;
2261 dst->int_state = from->int_state;
2262 dst->exit_code = from->exit_code;
2263 dst->exit_code_hi = from->exit_code_hi;
2264 dst->exit_info_1 = from->exit_info_1;
2265 dst->exit_info_2 = from->exit_info_2;
2266 dst->exit_int_info = from->exit_int_info;
2267 dst->exit_int_info_err = from->exit_int_info_err;
2268 dst->nested_ctl = from->nested_ctl;
2269 dst->event_inj = from->event_inj;
2270 dst->event_inj_err = from->event_inj_err;
2271 dst->nested_cr3 = from->nested_cr3;
2272 dst->lbr_ctl = from->lbr_ctl;
2273 }
2274
2275 static int nested_svm_vmexit(struct vcpu_svm *svm)
2276 {
2277 struct vmcb *nested_vmcb;
2278 struct vmcb *hsave = svm->nested.hsave;
2279 struct vmcb *vmcb = svm->vmcb;
2280 struct page *page;
2281
2282 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2283 vmcb->control.exit_info_1,
2284 vmcb->control.exit_info_2,
2285 vmcb->control.exit_int_info,
2286 vmcb->control.exit_int_info_err,
2287 KVM_ISA_SVM);
2288
2289 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2290 if (!nested_vmcb)
2291 return 1;
2292
2293 /* Exit Guest-Mode */
2294 leave_guest_mode(&svm->vcpu);
2295 svm->nested.vmcb = 0;
2296
2297 /* Give the current vmcb to the guest */
2298 disable_gif(svm);
2299
2300 nested_vmcb->save.es = vmcb->save.es;
2301 nested_vmcb->save.cs = vmcb->save.cs;
2302 nested_vmcb->save.ss = vmcb->save.ss;
2303 nested_vmcb->save.ds = vmcb->save.ds;
2304 nested_vmcb->save.gdtr = vmcb->save.gdtr;
2305 nested_vmcb->save.idtr = vmcb->save.idtr;
2306 nested_vmcb->save.efer = svm->vcpu.arch.efer;
2307 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2308 nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu);
2309 nested_vmcb->save.cr2 = vmcb->save.cr2;
2310 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
2311 nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
2312 nested_vmcb->save.rip = vmcb->save.rip;
2313 nested_vmcb->save.rsp = vmcb->save.rsp;
2314 nested_vmcb->save.rax = vmcb->save.rax;
2315 nested_vmcb->save.dr7 = vmcb->save.dr7;
2316 nested_vmcb->save.dr6 = vmcb->save.dr6;
2317 nested_vmcb->save.cpl = vmcb->save.cpl;
2318
2319 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
2320 nested_vmcb->control.int_vector = vmcb->control.int_vector;
2321 nested_vmcb->control.int_state = vmcb->control.int_state;
2322 nested_vmcb->control.exit_code = vmcb->control.exit_code;
2323 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
2324 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
2325 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
2326 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
2327 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2328 nested_vmcb->control.next_rip = vmcb->control.next_rip;
2329
2330 /*
2331 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2332 * to make sure that we do not lose injected events. So check event_inj
2333 * here and copy it to exit_int_info if it is valid.
2334 * Exit_int_info and event_inj can't be both valid because the case
2335 * below only happens on a VMRUN instruction intercept which has
2336 * no valid exit_int_info set.
2337 */
2338 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2339 struct vmcb_control_area *nc = &nested_vmcb->control;
2340
2341 nc->exit_int_info = vmcb->control.event_inj;
2342 nc->exit_int_info_err = vmcb->control.event_inj_err;
2343 }
2344
2345 nested_vmcb->control.tlb_ctl = 0;
2346 nested_vmcb->control.event_inj = 0;
2347 nested_vmcb->control.event_inj_err = 0;
2348
2349 /* We always set V_INTR_MASKING and remember the old value in hflags */
2350 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2351 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2352
2353 /* Restore the original control entries */
2354 copy_vmcb_control_area(vmcb, hsave);
2355
2356 kvm_clear_exception_queue(&svm->vcpu);
2357 kvm_clear_interrupt_queue(&svm->vcpu);
2358
2359 svm->nested.nested_cr3 = 0;
2360
2361 /* Restore selected save entries */
2362 svm->vmcb->save.es = hsave->save.es;
2363 svm->vmcb->save.cs = hsave->save.cs;
2364 svm->vmcb->save.ss = hsave->save.ss;
2365 svm->vmcb->save.ds = hsave->save.ds;
2366 svm->vmcb->save.gdtr = hsave->save.gdtr;
2367 svm->vmcb->save.idtr = hsave->save.idtr;
2368 kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
2369 svm_set_efer(&svm->vcpu, hsave->save.efer);
2370 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2371 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2372 if (npt_enabled) {
2373 svm->vmcb->save.cr3 = hsave->save.cr3;
2374 svm->vcpu.arch.cr3 = hsave->save.cr3;
2375 } else {
2376 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2377 }
2378 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2379 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2380 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2381 svm->vmcb->save.dr7 = 0;
2382 svm->vmcb->save.cpl = 0;
2383 svm->vmcb->control.exit_int_info = 0;
2384
2385 mark_all_dirty(svm->vmcb);
2386
2387 nested_svm_unmap(page);
2388
2389 nested_svm_uninit_mmu_context(&svm->vcpu);
2390 kvm_mmu_reset_context(&svm->vcpu);
2391 kvm_mmu_load(&svm->vcpu);
2392
2393 return 0;
2394 }
2395
2396 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2397 {
2398 /*
2399 * This function merges the msr permission bitmaps of kvm and the
2400 * nested vmcb. It is optimized in that it only merges the parts where
2401 * the kvm msr permission bitmap may contain zero bits
2402 */
2403 int i;
2404
2405 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2406 return true;
2407
2408 for (i = 0; i < MSRPM_OFFSETS; i++) {
2409 u32 value, p;
2410 u64 offset;
2411
2412 if (msrpm_offsets[i] == 0xffffffff)
2413 break;
2414
2415 p = msrpm_offsets[i];
2416 offset = svm->nested.vmcb_msrpm + (p * 4);
2417
2418 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2419 return false;
2420
2421 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2422 }
2423
2424 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2425
2426 return true;
2427 }
2428
2429 static bool nested_vmcb_checks(struct vmcb *vmcb)
2430 {
2431 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2432 return false;
2433
2434 if (vmcb->control.asid == 0)
2435 return false;
2436
2437 if (vmcb->control.nested_ctl && !npt_enabled)
2438 return false;
2439
2440 return true;
2441 }
2442
2443 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2444 {
2445 struct vmcb *nested_vmcb;
2446 struct vmcb *hsave = svm->nested.hsave;
2447 struct vmcb *vmcb = svm->vmcb;
2448 struct page *page;
2449 u64 vmcb_gpa;
2450
2451 vmcb_gpa = svm->vmcb->save.rax;
2452
2453 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2454 if (!nested_vmcb)
2455 return false;
2456
2457 if (!nested_vmcb_checks(nested_vmcb)) {
2458 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2459 nested_vmcb->control.exit_code_hi = 0;
2460 nested_vmcb->control.exit_info_1 = 0;
2461 nested_vmcb->control.exit_info_2 = 0;
2462
2463 nested_svm_unmap(page);
2464
2465 return false;
2466 }
2467
2468 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2469 nested_vmcb->save.rip,
2470 nested_vmcb->control.int_ctl,
2471 nested_vmcb->control.event_inj,
2472 nested_vmcb->control.nested_ctl);
2473
2474 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2475 nested_vmcb->control.intercept_cr >> 16,
2476 nested_vmcb->control.intercept_exceptions,
2477 nested_vmcb->control.intercept);
2478
2479 /* Clear internal status */
2480 kvm_clear_exception_queue(&svm->vcpu);
2481 kvm_clear_interrupt_queue(&svm->vcpu);
2482
2483 /*
2484 * Save the old vmcb, so we don't need to pick what we save, but can
2485 * restore everything when a VMEXIT occurs
2486 */
2487 hsave->save.es = vmcb->save.es;
2488 hsave->save.cs = vmcb->save.cs;
2489 hsave->save.ss = vmcb->save.ss;
2490 hsave->save.ds = vmcb->save.ds;
2491 hsave->save.gdtr = vmcb->save.gdtr;
2492 hsave->save.idtr = vmcb->save.idtr;
2493 hsave->save.efer = svm->vcpu.arch.efer;
2494 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
2495 hsave->save.cr4 = svm->vcpu.arch.cr4;
2496 hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
2497 hsave->save.rip = kvm_rip_read(&svm->vcpu);
2498 hsave->save.rsp = vmcb->save.rsp;
2499 hsave->save.rax = vmcb->save.rax;
2500 if (npt_enabled)
2501 hsave->save.cr3 = vmcb->save.cr3;
2502 else
2503 hsave->save.cr3 = kvm_read_cr3(&svm->vcpu);
2504
2505 copy_vmcb_control_area(hsave, vmcb);
2506
2507 if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
2508 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2509 else
2510 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2511
2512 if (nested_vmcb->control.nested_ctl) {
2513 kvm_mmu_unload(&svm->vcpu);
2514 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2515 nested_svm_init_mmu_context(&svm->vcpu);
2516 }
2517
2518 /* Load the nested guest state */
2519 svm->vmcb->save.es = nested_vmcb->save.es;
2520 svm->vmcb->save.cs = nested_vmcb->save.cs;
2521 svm->vmcb->save.ss = nested_vmcb->save.ss;
2522 svm->vmcb->save.ds = nested_vmcb->save.ds;
2523 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2524 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2525 kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
2526 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2527 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2528 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2529 if (npt_enabled) {
2530 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2531 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2532 } else
2533 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2534
2535 /* Guest paging mode is active - reset mmu */
2536 kvm_mmu_reset_context(&svm->vcpu);
2537
2538 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2539 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2540 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2541 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2542
2543 /* In case we don't even reach vcpu_run, the fields are not updated */
2544 svm->vmcb->save.rax = nested_vmcb->save.rax;
2545 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2546 svm->vmcb->save.rip = nested_vmcb->save.rip;
2547 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2548 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2549 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2550
2551 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2552 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
2553
2554 /* cache intercepts */
2555 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
2556 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
2557 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2558 svm->nested.intercept = nested_vmcb->control.intercept;
2559
2560 svm_flush_tlb(&svm->vcpu);
2561 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2562 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2563 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2564 else
2565 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2566
2567 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2568 /* We only want the cr8 intercept bits of the guest */
2569 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2570 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2571 }
2572
2573 /* We don't want to see VMMCALLs from a nested guest */
2574 clr_intercept(svm, INTERCEPT_VMMCALL);
2575
2576 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2577 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2578 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2579 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2580 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2581 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2582
2583 nested_svm_unmap(page);
2584
2585 /* Enter Guest-Mode */
2586 enter_guest_mode(&svm->vcpu);
2587
2588 /*
2589 * Merge guest and host intercepts - must be called with vcpu in
2590 * guest-mode to take affect here
2591 */
2592 recalc_intercepts(svm);
2593
2594 svm->nested.vmcb = vmcb_gpa;
2595
2596 enable_gif(svm);
2597
2598 mark_all_dirty(svm->vmcb);
2599
2600 return true;
2601 }
2602
2603 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2604 {
2605 to_vmcb->save.fs = from_vmcb->save.fs;
2606 to_vmcb->save.gs = from_vmcb->save.gs;
2607 to_vmcb->save.tr = from_vmcb->save.tr;
2608 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2609 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2610 to_vmcb->save.star = from_vmcb->save.star;
2611 to_vmcb->save.lstar = from_vmcb->save.lstar;
2612 to_vmcb->save.cstar = from_vmcb->save.cstar;
2613 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2614 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2615 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2616 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2617 }
2618
2619 static int vmload_interception(struct vcpu_svm *svm)
2620 {
2621 struct vmcb *nested_vmcb;
2622 struct page *page;
2623
2624 if (nested_svm_check_permissions(svm))
2625 return 1;
2626
2627 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2628 if (!nested_vmcb)
2629 return 1;
2630
2631 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2632 skip_emulated_instruction(&svm->vcpu);
2633
2634 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2635 nested_svm_unmap(page);
2636
2637 return 1;
2638 }
2639
2640 static int vmsave_interception(struct vcpu_svm *svm)
2641 {
2642 struct vmcb *nested_vmcb;
2643 struct page *page;
2644
2645 if (nested_svm_check_permissions(svm))
2646 return 1;
2647
2648 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2649 if (!nested_vmcb)
2650 return 1;
2651
2652 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2653 skip_emulated_instruction(&svm->vcpu);
2654
2655 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2656 nested_svm_unmap(page);
2657
2658 return 1;
2659 }
2660
2661 static int vmrun_interception(struct vcpu_svm *svm)
2662 {
2663 if (nested_svm_check_permissions(svm))
2664 return 1;
2665
2666 /* Save rip after vmrun instruction */
2667 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
2668
2669 if (!nested_svm_vmrun(svm))
2670 return 1;
2671
2672 if (!nested_svm_vmrun_msrpm(svm))
2673 goto failed;
2674
2675 return 1;
2676
2677 failed:
2678
2679 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2680 svm->vmcb->control.exit_code_hi = 0;
2681 svm->vmcb->control.exit_info_1 = 0;
2682 svm->vmcb->control.exit_info_2 = 0;
2683
2684 nested_svm_vmexit(svm);
2685
2686 return 1;
2687 }
2688
2689 static int stgi_interception(struct vcpu_svm *svm)
2690 {
2691 if (nested_svm_check_permissions(svm))
2692 return 1;
2693
2694 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2695 skip_emulated_instruction(&svm->vcpu);
2696 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2697
2698 enable_gif(svm);
2699
2700 return 1;
2701 }
2702
2703 static int clgi_interception(struct vcpu_svm *svm)
2704 {
2705 if (nested_svm_check_permissions(svm))
2706 return 1;
2707
2708 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2709 skip_emulated_instruction(&svm->vcpu);
2710
2711 disable_gif(svm);
2712
2713 /* After a CLGI no interrupts should come */
2714 svm_clear_vintr(svm);
2715 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2716
2717 mark_dirty(svm->vmcb, VMCB_INTR);
2718
2719 return 1;
2720 }
2721
2722 static int invlpga_interception(struct vcpu_svm *svm)
2723 {
2724 struct kvm_vcpu *vcpu = &svm->vcpu;
2725
2726 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2727 vcpu->arch.regs[VCPU_REGS_RAX]);
2728
2729 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2730 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2731
2732 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2733 skip_emulated_instruction(&svm->vcpu);
2734 return 1;
2735 }
2736
2737 static int skinit_interception(struct vcpu_svm *svm)
2738 {
2739 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2740
2741 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2742 return 1;
2743 }
2744
2745 static int xsetbv_interception(struct vcpu_svm *svm)
2746 {
2747 u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
2748 u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
2749
2750 if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
2751 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2752 skip_emulated_instruction(&svm->vcpu);
2753 }
2754
2755 return 1;
2756 }
2757
2758 static int invalid_op_interception(struct vcpu_svm *svm)
2759 {
2760 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2761 return 1;
2762 }
2763
2764 static int task_switch_interception(struct vcpu_svm *svm)
2765 {
2766 u16 tss_selector;
2767 int reason;
2768 int int_type = svm->vmcb->control.exit_int_info &
2769 SVM_EXITINTINFO_TYPE_MASK;
2770 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2771 uint32_t type =
2772 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2773 uint32_t idt_v =
2774 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2775 bool has_error_code = false;
2776 u32 error_code = 0;
2777
2778 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2779
2780 if (svm->vmcb->control.exit_info_2 &
2781 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2782 reason = TASK_SWITCH_IRET;
2783 else if (svm->vmcb->control.exit_info_2 &
2784 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2785 reason = TASK_SWITCH_JMP;
2786 else if (idt_v)
2787 reason = TASK_SWITCH_GATE;
2788 else
2789 reason = TASK_SWITCH_CALL;
2790
2791 if (reason == TASK_SWITCH_GATE) {
2792 switch (type) {
2793 case SVM_EXITINTINFO_TYPE_NMI:
2794 svm->vcpu.arch.nmi_injected = false;
2795 break;
2796 case SVM_EXITINTINFO_TYPE_EXEPT:
2797 if (svm->vmcb->control.exit_info_2 &
2798 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2799 has_error_code = true;
2800 error_code =
2801 (u32)svm->vmcb->control.exit_info_2;
2802 }
2803 kvm_clear_exception_queue(&svm->vcpu);
2804 break;
2805 case SVM_EXITINTINFO_TYPE_INTR:
2806 kvm_clear_interrupt_queue(&svm->vcpu);
2807 break;
2808 default:
2809 break;
2810 }
2811 }
2812
2813 if (reason != TASK_SWITCH_GATE ||
2814 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2815 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2816 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2817 skip_emulated_instruction(&svm->vcpu);
2818
2819 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2820 int_vec = -1;
2821
2822 if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
2823 has_error_code, error_code) == EMULATE_FAIL) {
2824 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2825 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2826 svm->vcpu.run->internal.ndata = 0;
2827 return 0;
2828 }
2829 return 1;
2830 }
2831
2832 static int cpuid_interception(struct vcpu_svm *svm)
2833 {
2834 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2835 kvm_emulate_cpuid(&svm->vcpu);
2836 return 1;
2837 }
2838
2839 static int iret_interception(struct vcpu_svm *svm)
2840 {
2841 ++svm->vcpu.stat.nmi_window_exits;
2842 clr_intercept(svm, INTERCEPT_IRET);
2843 svm->vcpu.arch.hflags |= HF_IRET_MASK;
2844 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
2845 return 1;
2846 }
2847
2848 static int invlpg_interception(struct vcpu_svm *svm)
2849 {
2850 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2851 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2852
2853 kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
2854 skip_emulated_instruction(&svm->vcpu);
2855 return 1;
2856 }
2857
2858 static int emulate_on_interception(struct vcpu_svm *svm)
2859 {
2860 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2861 }
2862
2863 static int rdpmc_interception(struct vcpu_svm *svm)
2864 {
2865 int err;
2866
2867 if (!static_cpu_has(X86_FEATURE_NRIPS))
2868 return emulate_on_interception(svm);
2869
2870 err = kvm_rdpmc(&svm->vcpu);
2871 kvm_complete_insn_gp(&svm->vcpu, err);
2872
2873 return 1;
2874 }
2875
2876 bool check_selective_cr0_intercepted(struct vcpu_svm *svm, unsigned long val)
2877 {
2878 unsigned long cr0 = svm->vcpu.arch.cr0;
2879 bool ret = false;
2880 u64 intercept;
2881
2882 intercept = svm->nested.intercept;
2883
2884 if (!is_guest_mode(&svm->vcpu) ||
2885 (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
2886 return false;
2887
2888 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2889 val &= ~SVM_CR0_SELECTIVE_MASK;
2890
2891 if (cr0 ^ val) {
2892 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2893 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2894 }
2895
2896 return ret;
2897 }
2898
2899 #define CR_VALID (1ULL << 63)
2900
2901 static int cr_interception(struct vcpu_svm *svm)
2902 {
2903 int reg, cr;
2904 unsigned long val;
2905 int err;
2906
2907 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2908 return emulate_on_interception(svm);
2909
2910 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2911 return emulate_on_interception(svm);
2912
2913 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2914 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2915
2916 err = 0;
2917 if (cr >= 16) { /* mov to cr */
2918 cr -= 16;
2919 val = kvm_register_read(&svm->vcpu, reg);
2920 switch (cr) {
2921 case 0:
2922 if (!check_selective_cr0_intercepted(svm, val))
2923 err = kvm_set_cr0(&svm->vcpu, val);
2924 else
2925 return 1;
2926
2927 break;
2928 case 3:
2929 err = kvm_set_cr3(&svm->vcpu, val);
2930 break;
2931 case 4:
2932 err = kvm_set_cr4(&svm->vcpu, val);
2933 break;
2934 case 8:
2935 err = kvm_set_cr8(&svm->vcpu, val);
2936 break;
2937 default:
2938 WARN(1, "unhandled write to CR%d", cr);
2939 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2940 return 1;
2941 }
2942 } else { /* mov from cr */
2943 switch (cr) {
2944 case 0:
2945 val = kvm_read_cr0(&svm->vcpu);
2946 break;
2947 case 2:
2948 val = svm->vcpu.arch.cr2;
2949 break;
2950 case 3:
2951 val = kvm_read_cr3(&svm->vcpu);
2952 break;
2953 case 4:
2954 val = kvm_read_cr4(&svm->vcpu);
2955 break;
2956 case 8:
2957 val = kvm_get_cr8(&svm->vcpu);
2958 break;
2959 default:
2960 WARN(1, "unhandled read from CR%d", cr);
2961 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2962 return 1;
2963 }
2964 kvm_register_write(&svm->vcpu, reg, val);
2965 }
2966 kvm_complete_insn_gp(&svm->vcpu, err);
2967
2968 return 1;
2969 }
2970
2971 static int dr_interception(struct vcpu_svm *svm)
2972 {
2973 int reg, dr;
2974 unsigned long val;
2975 int err;
2976
2977 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2978 return emulate_on_interception(svm);
2979
2980 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2981 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2982
2983 if (dr >= 16) { /* mov to DRn */
2984 val = kvm_register_read(&svm->vcpu, reg);
2985 kvm_set_dr(&svm->vcpu, dr - 16, val);
2986 } else {
2987 err = kvm_get_dr(&svm->vcpu, dr, &val);
2988 if (!err)
2989 kvm_register_write(&svm->vcpu, reg, val);
2990 }
2991
2992 skip_emulated_instruction(&svm->vcpu);
2993
2994 return 1;
2995 }
2996
2997 static int cr8_write_interception(struct vcpu_svm *svm)
2998 {
2999 struct kvm_run *kvm_run = svm->vcpu.run;
3000 int r;
3001
3002 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
3003 /* instruction emulation calls kvm_set_cr8() */
3004 r = cr_interception(svm);
3005 if (irqchip_in_kernel(svm->vcpu.kvm)) {
3006 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3007 return r;
3008 }
3009 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
3010 return r;
3011 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
3012 return 0;
3013 }
3014
3015 u64 svm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
3016 {
3017 struct vmcb *vmcb = get_host_vmcb(to_svm(vcpu));
3018 return vmcb->control.tsc_offset +
3019 svm_scale_tsc(vcpu, host_tsc);
3020 }
3021
3022 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
3023 {
3024 struct vcpu_svm *svm = to_svm(vcpu);
3025
3026 switch (ecx) {
3027 case MSR_IA32_TSC: {
3028 *data = svm->vmcb->control.tsc_offset +
3029 svm_scale_tsc(vcpu, native_read_tsc());
3030
3031 break;
3032 }
3033 case MSR_STAR:
3034 *data = svm->vmcb->save.star;
3035 break;
3036 #ifdef CONFIG_X86_64
3037 case MSR_LSTAR:
3038 *data = svm->vmcb->save.lstar;
3039 break;
3040 case MSR_CSTAR:
3041 *data = svm->vmcb->save.cstar;
3042 break;
3043 case MSR_KERNEL_GS_BASE:
3044 *data = svm->vmcb->save.kernel_gs_base;
3045 break;
3046 case MSR_SYSCALL_MASK:
3047 *data = svm->vmcb->save.sfmask;
3048 break;
3049 #endif
3050 case MSR_IA32_SYSENTER_CS:
3051 *data = svm->vmcb->save.sysenter_cs;
3052 break;
3053 case MSR_IA32_SYSENTER_EIP:
3054 *data = svm->sysenter_eip;
3055 break;
3056 case MSR_IA32_SYSENTER_ESP:
3057 *data = svm->sysenter_esp;
3058 break;
3059 /*
3060 * Nobody will change the following 5 values in the VMCB so we can
3061 * safely return them on rdmsr. They will always be 0 until LBRV is
3062 * implemented.
3063 */
3064 case MSR_IA32_DEBUGCTLMSR:
3065 *data = svm->vmcb->save.dbgctl;
3066 break;
3067 case MSR_IA32_LASTBRANCHFROMIP:
3068 *data = svm->vmcb->save.br_from;
3069 break;
3070 case MSR_IA32_LASTBRANCHTOIP:
3071 *data = svm->vmcb->save.br_to;
3072 break;
3073 case MSR_IA32_LASTINTFROMIP:
3074 *data = svm->vmcb->save.last_excp_from;
3075 break;
3076 case MSR_IA32_LASTINTTOIP:
3077 *data = svm->vmcb->save.last_excp_to;
3078 break;
3079 case MSR_VM_HSAVE_PA:
3080 *data = svm->nested.hsave_msr;
3081 break;
3082 case MSR_VM_CR:
3083 *data = svm->nested.vm_cr_msr;
3084 break;
3085 case MSR_IA32_UCODE_REV:
3086 *data = 0x01000065;
3087 break;
3088 default:
3089 return kvm_get_msr_common(vcpu, ecx, data);
3090 }
3091 return 0;
3092 }
3093
3094 static int rdmsr_interception(struct vcpu_svm *svm)
3095 {
3096 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3097 u64 data;
3098
3099 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
3100 trace_kvm_msr_read_ex(ecx);
3101 kvm_inject_gp(&svm->vcpu, 0);
3102 } else {
3103 trace_kvm_msr_read(ecx, data);
3104
3105 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
3106 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
3107 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3108 skip_emulated_instruction(&svm->vcpu);
3109 }
3110 return 1;
3111 }
3112
3113 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
3114 {
3115 struct vcpu_svm *svm = to_svm(vcpu);
3116 int svm_dis, chg_mask;
3117
3118 if (data & ~SVM_VM_CR_VALID_MASK)
3119 return 1;
3120
3121 chg_mask = SVM_VM_CR_VALID_MASK;
3122
3123 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
3124 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
3125
3126 svm->nested.vm_cr_msr &= ~chg_mask;
3127 svm->nested.vm_cr_msr |= (data & chg_mask);
3128
3129 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
3130
3131 /* check for svm_disable while efer.svme is set */
3132 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
3133 return 1;
3134
3135 return 0;
3136 }
3137
3138 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
3139 {
3140 struct vcpu_svm *svm = to_svm(vcpu);
3141
3142 u32 ecx = msr->index;
3143 u64 data = msr->data;
3144 switch (ecx) {
3145 case MSR_IA32_TSC:
3146 kvm_write_tsc(vcpu, msr);
3147 break;
3148 case MSR_STAR:
3149 svm->vmcb->save.star = data;
3150 break;
3151 #ifdef CONFIG_X86_64
3152 case MSR_LSTAR:
3153 svm->vmcb->save.lstar = data;
3154 break;
3155 case MSR_CSTAR:
3156 svm->vmcb->save.cstar = data;
3157 break;
3158 case MSR_KERNEL_GS_BASE:
3159 svm->vmcb->save.kernel_gs_base = data;
3160 break;
3161 case MSR_SYSCALL_MASK:
3162 svm->vmcb->save.sfmask = data;
3163 break;
3164 #endif
3165 case MSR_IA32_SYSENTER_CS:
3166 svm->vmcb->save.sysenter_cs = data;
3167 break;
3168 case MSR_IA32_SYSENTER_EIP:
3169 svm->sysenter_eip = data;
3170 svm->vmcb->save.sysenter_eip = data;
3171 break;
3172 case MSR_IA32_SYSENTER_ESP:
3173 svm->sysenter_esp = data;
3174 svm->vmcb->save.sysenter_esp = data;
3175 break;
3176 case MSR_IA32_DEBUGCTLMSR:
3177 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
3178 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3179 __func__, data);
3180 break;
3181 }
3182 if (data & DEBUGCTL_RESERVED_BITS)
3183 return 1;
3184
3185 svm->vmcb->save.dbgctl = data;
3186 mark_dirty(svm->vmcb, VMCB_LBR);
3187 if (data & (1ULL<<0))
3188 svm_enable_lbrv(svm);
3189 else
3190 svm_disable_lbrv(svm);
3191 break;
3192 case MSR_VM_HSAVE_PA:
3193 svm->nested.hsave_msr = data;
3194 break;
3195 case MSR_VM_CR:
3196 return svm_set_vm_cr(vcpu, data);
3197 case MSR_VM_IGNNE:
3198 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3199 break;
3200 default:
3201 return kvm_set_msr_common(vcpu, msr);
3202 }
3203 return 0;
3204 }
3205
3206 static int wrmsr_interception(struct vcpu_svm *svm)
3207 {
3208 struct msr_data msr;
3209 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3210 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
3211 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3212
3213 msr.data = data;
3214 msr.index = ecx;
3215 msr.host_initiated = false;
3216
3217 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3218 if (svm_set_msr(&svm->vcpu, &msr)) {
3219 trace_kvm_msr_write_ex(ecx, data);
3220 kvm_inject_gp(&svm->vcpu, 0);
3221 } else {
3222 trace_kvm_msr_write(ecx, data);
3223 skip_emulated_instruction(&svm->vcpu);
3224 }
3225 return 1;
3226 }
3227
3228 static int msr_interception(struct vcpu_svm *svm)
3229 {
3230 if (svm->vmcb->control.exit_info_1)
3231 return wrmsr_interception(svm);
3232 else
3233 return rdmsr_interception(svm);
3234 }
3235
3236 static int interrupt_window_interception(struct vcpu_svm *svm)
3237 {
3238 struct kvm_run *kvm_run = svm->vcpu.run;
3239
3240 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3241 svm_clear_vintr(svm);
3242 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3243 mark_dirty(svm->vmcb, VMCB_INTR);
3244 ++svm->vcpu.stat.irq_window_exits;
3245 /*
3246 * If the user space waits to inject interrupts, exit as soon as
3247 * possible
3248 */
3249 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
3250 kvm_run->request_interrupt_window &&
3251 !kvm_cpu_has_interrupt(&svm->vcpu)) {
3252 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3253 return 0;
3254 }
3255
3256 return 1;
3257 }
3258
3259 static int pause_interception(struct vcpu_svm *svm)
3260 {
3261 kvm_vcpu_on_spin(&(svm->vcpu));
3262 return 1;
3263 }
3264
3265 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
3266 [SVM_EXIT_READ_CR0] = cr_interception,
3267 [SVM_EXIT_READ_CR3] = cr_interception,
3268 [SVM_EXIT_READ_CR4] = cr_interception,
3269 [SVM_EXIT_READ_CR8] = cr_interception,
3270 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
3271 [SVM_EXIT_WRITE_CR0] = cr_interception,
3272 [SVM_EXIT_WRITE_CR3] = cr_interception,
3273 [SVM_EXIT_WRITE_CR4] = cr_interception,
3274 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
3275 [SVM_EXIT_READ_DR0] = dr_interception,
3276 [SVM_EXIT_READ_DR1] = dr_interception,
3277 [SVM_EXIT_READ_DR2] = dr_interception,
3278 [SVM_EXIT_READ_DR3] = dr_interception,
3279 [SVM_EXIT_READ_DR4] = dr_interception,
3280 [SVM_EXIT_READ_DR5] = dr_interception,
3281 [SVM_EXIT_READ_DR6] = dr_interception,
3282 [SVM_EXIT_READ_DR7] = dr_interception,
3283 [SVM_EXIT_WRITE_DR0] = dr_interception,
3284 [SVM_EXIT_WRITE_DR1] = dr_interception,
3285 [SVM_EXIT_WRITE_DR2] = dr_interception,
3286 [SVM_EXIT_WRITE_DR3] = dr_interception,
3287 [SVM_EXIT_WRITE_DR4] = dr_interception,
3288 [SVM_EXIT_WRITE_DR5] = dr_interception,
3289 [SVM_EXIT_WRITE_DR6] = dr_interception,
3290 [SVM_EXIT_WRITE_DR7] = dr_interception,
3291 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
3292 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
3293 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
3294 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
3295 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
3296 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
3297 [SVM_EXIT_INTR] = intr_interception,
3298 [SVM_EXIT_NMI] = nmi_interception,
3299 [SVM_EXIT_SMI] = nop_on_interception,
3300 [SVM_EXIT_INIT] = nop_on_interception,
3301 [SVM_EXIT_VINTR] = interrupt_window_interception,
3302 [SVM_EXIT_RDPMC] = rdpmc_interception,
3303 [SVM_EXIT_CPUID] = cpuid_interception,
3304 [SVM_EXIT_IRET] = iret_interception,
3305 [SVM_EXIT_INVD] = emulate_on_interception,
3306 [SVM_EXIT_PAUSE] = pause_interception,
3307 [SVM_EXIT_HLT] = halt_interception,
3308 [SVM_EXIT_INVLPG] = invlpg_interception,
3309 [SVM_EXIT_INVLPGA] = invlpga_interception,
3310 [SVM_EXIT_IOIO] = io_interception,
3311 [SVM_EXIT_MSR] = msr_interception,
3312 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
3313 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3314 [SVM_EXIT_VMRUN] = vmrun_interception,
3315 [SVM_EXIT_VMMCALL] = vmmcall_interception,
3316 [SVM_EXIT_VMLOAD] = vmload_interception,
3317 [SVM_EXIT_VMSAVE] = vmsave_interception,
3318 [SVM_EXIT_STGI] = stgi_interception,
3319 [SVM_EXIT_CLGI] = clgi_interception,
3320 [SVM_EXIT_SKINIT] = skinit_interception,
3321 [SVM_EXIT_WBINVD] = emulate_on_interception,
3322 [SVM_EXIT_MONITOR] = invalid_op_interception,
3323 [SVM_EXIT_MWAIT] = invalid_op_interception,
3324 [SVM_EXIT_XSETBV] = xsetbv_interception,
3325 [SVM_EXIT_NPF] = pf_interception,
3326 };
3327
3328 static void dump_vmcb(struct kvm_vcpu *vcpu)
3329 {
3330 struct vcpu_svm *svm = to_svm(vcpu);
3331 struct vmcb_control_area *control = &svm->vmcb->control;
3332 struct vmcb_save_area *save = &svm->vmcb->save;
3333
3334 pr_err("VMCB Control Area:\n");
3335 pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
3336 pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
3337 pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
3338 pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
3339 pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
3340 pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
3341 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
3342 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
3343 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
3344 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
3345 pr_err("%-20s%d\n", "asid:", control->asid);
3346 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
3347 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
3348 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
3349 pr_err("%-20s%08x\n", "int_state:", control->int_state);
3350 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
3351 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
3352 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
3353 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
3354 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
3355 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
3356 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
3357 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
3358 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
3359 pr_err("%-20s%lld\n", "lbr_ctl:", control->lbr_ctl);
3360 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
3361 pr_err("VMCB State Save Area:\n");
3362 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3363 "es:",
3364 save->es.selector, save->es.attrib,
3365 save->es.limit, save->es.base);
3366 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3367 "cs:",
3368 save->cs.selector, save->cs.attrib,
3369 save->cs.limit, save->cs.base);
3370 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3371 "ss:",
3372 save->ss.selector, save->ss.attrib,
3373 save->ss.limit, save->ss.base);
3374 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3375 "ds:",
3376 save->ds.selector, save->ds.attrib,
3377 save->ds.limit, save->ds.base);
3378 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3379 "fs:",
3380 save->fs.selector, save->fs.attrib,
3381 save->fs.limit, save->fs.base);
3382 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3383 "gs:",
3384 save->gs.selector, save->gs.attrib,
3385 save->gs.limit, save->gs.base);
3386 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3387 "gdtr:",
3388 save->gdtr.selector, save->gdtr.attrib,
3389 save->gdtr.limit, save->gdtr.base);
3390 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3391 "ldtr:",
3392 save->ldtr.selector, save->ldtr.attrib,
3393 save->ldtr.limit, save->ldtr.base);
3394 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3395 "idtr:",
3396 save->idtr.selector, save->idtr.attrib,
3397 save->idtr.limit, save->idtr.base);
3398 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3399 "tr:",
3400 save->tr.selector, save->tr.attrib,
3401 save->tr.limit, save->tr.base);
3402 pr_err("cpl: %d efer: %016llx\n",
3403 save->cpl, save->efer);
3404 pr_err("%-15s %016llx %-13s %016llx\n",
3405 "cr0:", save->cr0, "cr2:", save->cr2);
3406 pr_err("%-15s %016llx %-13s %016llx\n",
3407 "cr3:", save->cr3, "cr4:", save->cr4);
3408 pr_err("%-15s %016llx %-13s %016llx\n",
3409 "dr6:", save->dr6, "dr7:", save->dr7);
3410 pr_err("%-15s %016llx %-13s %016llx\n",
3411 "rip:", save->rip, "rflags:", save->rflags);
3412 pr_err("%-15s %016llx %-13s %016llx\n",
3413 "rsp:", save->rsp, "rax:", save->rax);
3414 pr_err("%-15s %016llx %-13s %016llx\n",
3415 "star:", save->star, "lstar:", save->lstar);
3416 pr_err("%-15s %016llx %-13s %016llx\n",
3417 "cstar:", save->cstar, "sfmask:", save->sfmask);
3418 pr_err("%-15s %016llx %-13s %016llx\n",
3419 "kernel_gs_base:", save->kernel_gs_base,
3420 "sysenter_cs:", save->sysenter_cs);
3421 pr_err("%-15s %016llx %-13s %016llx\n",
3422 "sysenter_esp:", save->sysenter_esp,
3423 "sysenter_eip:", save->sysenter_eip);
3424 pr_err("%-15s %016llx %-13s %016llx\n",
3425 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
3426 pr_err("%-15s %016llx %-13s %016llx\n",
3427 "br_from:", save->br_from, "br_to:", save->br_to);
3428 pr_err("%-15s %016llx %-13s %016llx\n",
3429 "excp_from:", save->last_excp_from,
3430 "excp_to:", save->last_excp_to);
3431 }
3432
3433 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3434 {
3435 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3436
3437 *info1 = control->exit_info_1;
3438 *info2 = control->exit_info_2;
3439 }
3440
3441 static int handle_exit(struct kvm_vcpu *vcpu)
3442 {
3443 struct vcpu_svm *svm = to_svm(vcpu);
3444 struct kvm_run *kvm_run = vcpu->run;
3445 u32 exit_code = svm->vmcb->control.exit_code;
3446
3447 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
3448 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3449 if (npt_enabled)
3450 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3451
3452 if (unlikely(svm->nested.exit_required)) {
3453 nested_svm_vmexit(svm);
3454 svm->nested.exit_required = false;
3455
3456 return 1;
3457 }
3458
3459 if (is_guest_mode(vcpu)) {
3460 int vmexit;
3461
3462 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3463 svm->vmcb->control.exit_info_1,
3464 svm->vmcb->control.exit_info_2,
3465 svm->vmcb->control.exit_int_info,
3466 svm->vmcb->control.exit_int_info_err,
3467 KVM_ISA_SVM);
3468
3469 vmexit = nested_svm_exit_special(svm);
3470
3471 if (vmexit == NESTED_EXIT_CONTINUE)
3472 vmexit = nested_svm_exit_handled(svm);
3473
3474 if (vmexit == NESTED_EXIT_DONE)
3475 return 1;
3476 }
3477
3478 svm_complete_interrupts(svm);
3479
3480 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3481 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3482 kvm_run->fail_entry.hardware_entry_failure_reason
3483 = svm->vmcb->control.exit_code;
3484 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3485 dump_vmcb(vcpu);
3486 return 0;
3487 }
3488
3489 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3490 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3491 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3492 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3493 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
3494 "exit_code 0x%x\n",
3495 __func__, svm->vmcb->control.exit_int_info,
3496 exit_code);
3497
3498 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
3499 || !svm_exit_handlers[exit_code]) {
3500 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3501 kvm_run->hw.hardware_exit_reason = exit_code;
3502 return 0;
3503 }
3504
3505 return svm_exit_handlers[exit_code](svm);
3506 }
3507
3508 static void reload_tss(struct kvm_vcpu *vcpu)
3509 {
3510 int cpu = raw_smp_processor_id();
3511
3512 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3513 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3514 load_TR_desc();
3515 }
3516
3517 static void pre_svm_run(struct vcpu_svm *svm)
3518 {
3519 int cpu = raw_smp_processor_id();
3520
3521 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3522
3523 /* FIXME: handle wraparound of asid_generation */
3524 if (svm->asid_generation != sd->asid_generation)
3525 new_asid(svm, sd);
3526 }
3527
3528 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3529 {
3530 struct vcpu_svm *svm = to_svm(vcpu);
3531
3532 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3533 vcpu->arch.hflags |= HF_NMI_MASK;
3534 set_intercept(svm, INTERCEPT_IRET);
3535 ++vcpu->stat.nmi_injections;
3536 }
3537
3538 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
3539 {
3540 struct vmcb_control_area *control;
3541
3542 control = &svm->vmcb->control;
3543 control->int_vector = irq;
3544 control->int_ctl &= ~V_INTR_PRIO_MASK;
3545 control->int_ctl |= V_IRQ_MASK |
3546 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
3547 mark_dirty(svm->vmcb, VMCB_INTR);
3548 }
3549
3550 static void svm_set_irq(struct kvm_vcpu *vcpu)
3551 {
3552 struct vcpu_svm *svm = to_svm(vcpu);
3553
3554 BUG_ON(!(gif_set(svm)));
3555
3556 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3557 ++vcpu->stat.irq_injections;
3558
3559 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3560 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3561 }
3562
3563 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3564 {
3565 struct vcpu_svm *svm = to_svm(vcpu);
3566
3567 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3568 return;
3569
3570 if (irr == -1)
3571 return;
3572
3573 if (tpr >= irr)
3574 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3575 }
3576
3577 static void svm_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
3578 {
3579 return;
3580 }
3581
3582 static int svm_vm_has_apicv(struct kvm *kvm)
3583 {
3584 return 0;
3585 }
3586
3587 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
3588 {
3589 return;
3590 }
3591
3592 static void svm_hwapic_isr_update(struct kvm *kvm, int isr)
3593 {
3594 return;
3595 }
3596
3597 static void svm_sync_pir_to_irr(struct kvm_vcpu *vcpu)
3598 {
3599 return;
3600 }
3601
3602 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3603 {
3604 struct vcpu_svm *svm = to_svm(vcpu);
3605 struct vmcb *vmcb = svm->vmcb;
3606 int ret;
3607 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3608 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3609 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3610
3611 return ret;
3612 }
3613
3614 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3615 {
3616 struct vcpu_svm *svm = to_svm(vcpu);
3617
3618 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3619 }
3620
3621 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3622 {
3623 struct vcpu_svm *svm = to_svm(vcpu);
3624
3625 if (masked) {
3626 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3627 set_intercept(svm, INTERCEPT_IRET);
3628 } else {
3629 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3630 clr_intercept(svm, INTERCEPT_IRET);
3631 }
3632 }
3633
3634 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3635 {
3636 struct vcpu_svm *svm = to_svm(vcpu);
3637 struct vmcb *vmcb = svm->vmcb;
3638 int ret;
3639
3640 if (!gif_set(svm) ||
3641 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3642 return 0;
3643
3644 ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
3645
3646 if (is_guest_mode(vcpu))
3647 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3648
3649 return ret;
3650 }
3651
3652 static int enable_irq_window(struct kvm_vcpu *vcpu)
3653 {
3654 struct vcpu_svm *svm = to_svm(vcpu);
3655
3656 /*
3657 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3658 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3659 * get that intercept, this function will be called again though and
3660 * we'll get the vintr intercept.
3661 */
3662 if (gif_set(svm) && nested_svm_intr(svm)) {
3663 svm_set_vintr(svm);
3664 svm_inject_irq(svm, 0x0);
3665 }
3666 return 0;
3667 }
3668
3669 static int enable_nmi_window(struct kvm_vcpu *vcpu)
3670 {
3671 struct vcpu_svm *svm = to_svm(vcpu);
3672
3673 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3674 == HF_NMI_MASK)
3675 return 0; /* IRET will cause a vm exit */
3676
3677 /*
3678 * Something prevents NMI from been injected. Single step over possible
3679 * problem (IRET or exception injection or interrupt shadow)
3680 */
3681 svm->nmi_singlestep = true;
3682 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3683 update_db_bp_intercept(vcpu);
3684 return 0;
3685 }
3686
3687 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3688 {
3689 return 0;
3690 }
3691
3692 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3693 {
3694 struct vcpu_svm *svm = to_svm(vcpu);
3695
3696 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3697 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3698 else
3699 svm->asid_generation--;
3700 }
3701
3702 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3703 {
3704 }
3705
3706 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3707 {
3708 struct vcpu_svm *svm = to_svm(vcpu);
3709
3710 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3711 return;
3712
3713 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
3714 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3715 kvm_set_cr8(vcpu, cr8);
3716 }
3717 }
3718
3719 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3720 {
3721 struct vcpu_svm *svm = to_svm(vcpu);
3722 u64 cr8;
3723
3724 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3725 return;
3726
3727 cr8 = kvm_get_cr8(vcpu);
3728 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3729 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3730 }
3731
3732 static void svm_complete_interrupts(struct vcpu_svm *svm)
3733 {
3734 u8 vector;
3735 int type;
3736 u32 exitintinfo = svm->vmcb->control.exit_int_info;
3737 unsigned int3_injected = svm->int3_injected;
3738
3739 svm->int3_injected = 0;
3740
3741 /*
3742 * If we've made progress since setting HF_IRET_MASK, we've
3743 * executed an IRET and can allow NMI injection.
3744 */
3745 if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
3746 && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
3747 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3748 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3749 }
3750
3751 svm->vcpu.arch.nmi_injected = false;
3752 kvm_clear_exception_queue(&svm->vcpu);
3753 kvm_clear_interrupt_queue(&svm->vcpu);
3754
3755 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3756 return;
3757
3758 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3759
3760 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3761 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3762
3763 switch (type) {
3764 case SVM_EXITINTINFO_TYPE_NMI:
3765 svm->vcpu.arch.nmi_injected = true;
3766 break;
3767 case SVM_EXITINTINFO_TYPE_EXEPT:
3768 /*
3769 * In case of software exceptions, do not reinject the vector,
3770 * but re-execute the instruction instead. Rewind RIP first
3771 * if we emulated INT3 before.
3772 */
3773 if (kvm_exception_is_soft(vector)) {
3774 if (vector == BP_VECTOR && int3_injected &&
3775 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3776 kvm_rip_write(&svm->vcpu,
3777 kvm_rip_read(&svm->vcpu) -
3778 int3_injected);
3779 break;
3780 }
3781 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3782 u32 err = svm->vmcb->control.exit_int_info_err;
3783 kvm_requeue_exception_e(&svm->vcpu, vector, err);
3784
3785 } else
3786 kvm_requeue_exception(&svm->vcpu, vector);
3787 break;
3788 case SVM_EXITINTINFO_TYPE_INTR:
3789 kvm_queue_interrupt(&svm->vcpu, vector, false);
3790 break;
3791 default:
3792 break;
3793 }
3794 }
3795
3796 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3797 {
3798 struct vcpu_svm *svm = to_svm(vcpu);
3799 struct vmcb_control_area *control = &svm->vmcb->control;
3800
3801 control->exit_int_info = control->event_inj;
3802 control->exit_int_info_err = control->event_inj_err;
3803 control->event_inj = 0;
3804 svm_complete_interrupts(svm);
3805 }
3806
3807 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
3808 {
3809 struct vcpu_svm *svm = to_svm(vcpu);
3810
3811 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3812 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3813 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3814
3815 /*
3816 * A vmexit emulation is required before the vcpu can be executed
3817 * again.
3818 */
3819 if (unlikely(svm->nested.exit_required))
3820 return;
3821
3822 pre_svm_run(svm);
3823
3824 sync_lapic_to_cr8(vcpu);
3825
3826 svm->vmcb->save.cr2 = vcpu->arch.cr2;
3827
3828 clgi();
3829
3830 local_irq_enable();
3831
3832 asm volatile (
3833 "push %%" _ASM_BP "; \n\t"
3834 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
3835 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
3836 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
3837 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
3838 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
3839 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
3840 #ifdef CONFIG_X86_64
3841 "mov %c[r8](%[svm]), %%r8 \n\t"
3842 "mov %c[r9](%[svm]), %%r9 \n\t"
3843 "mov %c[r10](%[svm]), %%r10 \n\t"
3844 "mov %c[r11](%[svm]), %%r11 \n\t"
3845 "mov %c[r12](%[svm]), %%r12 \n\t"
3846 "mov %c[r13](%[svm]), %%r13 \n\t"
3847 "mov %c[r14](%[svm]), %%r14 \n\t"
3848 "mov %c[r15](%[svm]), %%r15 \n\t"
3849 #endif
3850
3851 /* Enter guest mode */
3852 "push %%" _ASM_AX " \n\t"
3853 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
3854 __ex(SVM_VMLOAD) "\n\t"
3855 __ex(SVM_VMRUN) "\n\t"
3856 __ex(SVM_VMSAVE) "\n\t"
3857 "pop %%" _ASM_AX " \n\t"
3858
3859 /* Save guest registers, load host registers */
3860 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
3861 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
3862 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
3863 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
3864 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
3865 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
3866 #ifdef CONFIG_X86_64
3867 "mov %%r8, %c[r8](%[svm]) \n\t"
3868 "mov %%r9, %c[r9](%[svm]) \n\t"
3869 "mov %%r10, %c[r10](%[svm]) \n\t"
3870 "mov %%r11, %c[r11](%[svm]) \n\t"
3871 "mov %%r12, %c[r12](%[svm]) \n\t"
3872 "mov %%r13, %c[r13](%[svm]) \n\t"
3873 "mov %%r14, %c[r14](%[svm]) \n\t"
3874 "mov %%r15, %c[r15](%[svm]) \n\t"
3875 #endif
3876 "pop %%" _ASM_BP
3877 :
3878 : [svm]"a"(svm),
3879 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
3880 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3881 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3882 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3883 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3884 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3885 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
3886 #ifdef CONFIG_X86_64
3887 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3888 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3889 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3890 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3891 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3892 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3893 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3894 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
3895 #endif
3896 : "cc", "memory"
3897 #ifdef CONFIG_X86_64
3898 , "rbx", "rcx", "rdx", "rsi", "rdi"
3899 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3900 #else
3901 , "ebx", "ecx", "edx", "esi", "edi"
3902 #endif
3903 );
3904
3905 #ifdef CONFIG_X86_64
3906 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3907 #else
3908 loadsegment(fs, svm->host.fs);
3909 #ifndef CONFIG_X86_32_LAZY_GS
3910 loadsegment(gs, svm->host.gs);
3911 #endif
3912 #endif
3913
3914 reload_tss(vcpu);
3915
3916 local_irq_disable();
3917
3918 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3919 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3920 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3921 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3922
3923 trace_kvm_exit(svm->vmcb->control.exit_code, vcpu, KVM_ISA_SVM);
3924
3925 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3926 kvm_before_handle_nmi(&svm->vcpu);
3927
3928 stgi();
3929
3930 /* Any pending NMI will happen here */
3931
3932 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3933 kvm_after_handle_nmi(&svm->vcpu);
3934
3935 sync_cr8_to_lapic(vcpu);
3936
3937 svm->next_rip = 0;
3938
3939 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3940
3941 /* if exit due to PF check for async PF */
3942 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3943 svm->apf_reason = kvm_read_and_reset_pf_reason();
3944
3945 if (npt_enabled) {
3946 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3947 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3948 }
3949
3950 /*
3951 * We need to handle MC intercepts here before the vcpu has a chance to
3952 * change the physical cpu
3953 */
3954 if (unlikely(svm->vmcb->control.exit_code ==
3955 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3956 svm_handle_mce(svm);
3957
3958 mark_all_clean(svm->vmcb);
3959 }
3960
3961 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3962 {
3963 struct vcpu_svm *svm = to_svm(vcpu);
3964
3965 svm->vmcb->save.cr3 = root;
3966 mark_dirty(svm->vmcb, VMCB_CR);
3967 svm_flush_tlb(vcpu);
3968 }
3969
3970 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3971 {
3972 struct vcpu_svm *svm = to_svm(vcpu);
3973
3974 svm->vmcb->control.nested_cr3 = root;
3975 mark_dirty(svm->vmcb, VMCB_NPT);
3976
3977 /* Also sync guest cr3 here in case we live migrate */
3978 svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
3979 mark_dirty(svm->vmcb, VMCB_CR);
3980
3981 svm_flush_tlb(vcpu);
3982 }
3983
3984 static int is_disabled(void)
3985 {
3986 u64 vm_cr;
3987
3988 rdmsrl(MSR_VM_CR, vm_cr);
3989 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3990 return 1;
3991
3992 return 0;
3993 }
3994
3995 static void
3996 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3997 {
3998 /*
3999 * Patch in the VMMCALL instruction:
4000 */
4001 hypercall[0] = 0x0f;
4002 hypercall[1] = 0x01;
4003 hypercall[2] = 0xd9;
4004 }
4005
4006 static void svm_check_processor_compat(void *rtn)
4007 {
4008 *(int *)rtn = 0;
4009 }
4010
4011 static bool svm_cpu_has_accelerated_tpr(void)
4012 {
4013 return false;
4014 }
4015
4016 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4017 {
4018 return 0;
4019 }
4020
4021 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
4022 {
4023 }
4024
4025 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4026 {
4027 switch (func) {
4028 case 0x80000001:
4029 if (nested)
4030 entry->ecx |= (1 << 2); /* Set SVM bit */
4031 break;
4032 case 0x8000000A:
4033 entry->eax = 1; /* SVM revision 1 */
4034 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
4035 ASID emulation to nested SVM */
4036 entry->ecx = 0; /* Reserved */
4037 entry->edx = 0; /* Per default do not support any
4038 additional features */
4039
4040 /* Support next_rip if host supports it */
4041 if (boot_cpu_has(X86_FEATURE_NRIPS))
4042 entry->edx |= SVM_FEATURE_NRIP;
4043
4044 /* Support NPT for the guest if enabled */
4045 if (npt_enabled)
4046 entry->edx |= SVM_FEATURE_NPT;
4047
4048 break;
4049 }
4050 }
4051
4052 static int svm_get_lpage_level(void)
4053 {
4054 return PT_PDPE_LEVEL;
4055 }
4056
4057 static bool svm_rdtscp_supported(void)
4058 {
4059 return false;
4060 }
4061
4062 static bool svm_invpcid_supported(void)
4063 {
4064 return false;
4065 }
4066
4067 static bool svm_has_wbinvd_exit(void)
4068 {
4069 return true;
4070 }
4071
4072 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
4073 {
4074 struct vcpu_svm *svm = to_svm(vcpu);
4075
4076 set_exception_intercept(svm, NM_VECTOR);
4077 update_cr0_intercept(svm);
4078 }
4079
4080 #define PRE_EX(exit) { .exit_code = (exit), \
4081 .stage = X86_ICPT_PRE_EXCEPT, }
4082 #define POST_EX(exit) { .exit_code = (exit), \
4083 .stage = X86_ICPT_POST_EXCEPT, }
4084 #define POST_MEM(exit) { .exit_code = (exit), \
4085 .stage = X86_ICPT_POST_MEMACCESS, }
4086
4087 static const struct __x86_intercept {
4088 u32 exit_code;
4089 enum x86_intercept_stage stage;
4090 } x86_intercept_map[] = {
4091 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
4092 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
4093 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
4094 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
4095 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
4096 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
4097 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
4098 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
4099 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
4100 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
4101 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
4102 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
4103 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
4104 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
4105 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
4106 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
4107 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
4108 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
4109 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
4110 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
4111 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
4112 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
4113 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
4114 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
4115 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
4116 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
4117 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
4118 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
4119 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
4120 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
4121 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
4122 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
4123 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
4124 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
4125 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
4126 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
4127 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
4128 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
4129 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
4130 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
4131 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
4132 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
4133 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
4134 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
4135 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
4136 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
4137 };
4138
4139 #undef PRE_EX
4140 #undef POST_EX
4141 #undef POST_MEM
4142
4143 static int svm_check_intercept(struct kvm_vcpu *vcpu,
4144 struct x86_instruction_info *info,
4145 enum x86_intercept_stage stage)
4146 {
4147 struct vcpu_svm *svm = to_svm(vcpu);
4148 int vmexit, ret = X86EMUL_CONTINUE;
4149 struct __x86_intercept icpt_info;
4150 struct vmcb *vmcb = svm->vmcb;
4151
4152 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
4153 goto out;
4154
4155 icpt_info = x86_intercept_map[info->intercept];
4156
4157 if (stage != icpt_info.stage)
4158 goto out;
4159
4160 switch (icpt_info.exit_code) {
4161 case SVM_EXIT_READ_CR0:
4162 if (info->intercept == x86_intercept_cr_read)
4163 icpt_info.exit_code += info->modrm_reg;
4164 break;
4165 case SVM_EXIT_WRITE_CR0: {
4166 unsigned long cr0, val;
4167 u64 intercept;
4168
4169 if (info->intercept == x86_intercept_cr_write)
4170 icpt_info.exit_code += info->modrm_reg;
4171
4172 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0)
4173 break;
4174
4175 intercept = svm->nested.intercept;
4176
4177 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
4178 break;
4179
4180 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
4181 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
4182
4183 if (info->intercept == x86_intercept_lmsw) {
4184 cr0 &= 0xfUL;
4185 val &= 0xfUL;
4186 /* lmsw can't clear PE - catch this here */
4187 if (cr0 & X86_CR0_PE)
4188 val |= X86_CR0_PE;
4189 }
4190
4191 if (cr0 ^ val)
4192 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
4193
4194 break;
4195 }
4196 case SVM_EXIT_READ_DR0:
4197 case SVM_EXIT_WRITE_DR0:
4198 icpt_info.exit_code += info->modrm_reg;
4199 break;
4200 case SVM_EXIT_MSR:
4201 if (info->intercept == x86_intercept_wrmsr)
4202 vmcb->control.exit_info_1 = 1;
4203 else
4204 vmcb->control.exit_info_1 = 0;
4205 break;
4206 case SVM_EXIT_PAUSE:
4207 /*
4208 * We get this for NOP only, but pause
4209 * is rep not, check this here
4210 */
4211 if (info->rep_prefix != REPE_PREFIX)
4212 goto out;
4213 case SVM_EXIT_IOIO: {
4214 u64 exit_info;
4215 u32 bytes;
4216
4217 exit_info = (vcpu->arch.regs[VCPU_REGS_RDX] & 0xffff) << 16;
4218
4219 if (info->intercept == x86_intercept_in ||
4220 info->intercept == x86_intercept_ins) {
4221 exit_info |= SVM_IOIO_TYPE_MASK;
4222 bytes = info->src_bytes;
4223 } else {
4224 bytes = info->dst_bytes;
4225 }
4226
4227 if (info->intercept == x86_intercept_outs ||
4228 info->intercept == x86_intercept_ins)
4229 exit_info |= SVM_IOIO_STR_MASK;
4230
4231 if (info->rep_prefix)
4232 exit_info |= SVM_IOIO_REP_MASK;
4233
4234 bytes = min(bytes, 4u);
4235
4236 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
4237
4238 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
4239
4240 vmcb->control.exit_info_1 = exit_info;
4241 vmcb->control.exit_info_2 = info->next_rip;
4242
4243 break;
4244 }
4245 default:
4246 break;
4247 }
4248
4249 vmcb->control.next_rip = info->next_rip;
4250 vmcb->control.exit_code = icpt_info.exit_code;
4251 vmexit = nested_svm_exit_handled(svm);
4252
4253 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
4254 : X86EMUL_CONTINUE;
4255
4256 out:
4257 return ret;
4258 }
4259
4260 static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
4261 {
4262 local_irq_enable();
4263 }
4264
4265 static struct kvm_x86_ops svm_x86_ops = {
4266 .cpu_has_kvm_support = has_svm,
4267 .disabled_by_bios = is_disabled,
4268 .hardware_setup = svm_hardware_setup,
4269 .hardware_unsetup = svm_hardware_unsetup,
4270 .check_processor_compatibility = svm_check_processor_compat,
4271 .hardware_enable = svm_hardware_enable,
4272 .hardware_disable = svm_hardware_disable,
4273 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
4274
4275 .vcpu_create = svm_create_vcpu,
4276 .vcpu_free = svm_free_vcpu,
4277 .vcpu_reset = svm_vcpu_reset,
4278
4279 .prepare_guest_switch = svm_prepare_guest_switch,
4280 .vcpu_load = svm_vcpu_load,
4281 .vcpu_put = svm_vcpu_put,
4282
4283 .update_db_bp_intercept = update_db_bp_intercept,
4284 .get_msr = svm_get_msr,
4285 .set_msr = svm_set_msr,
4286 .get_segment_base = svm_get_segment_base,
4287 .get_segment = svm_get_segment,
4288 .set_segment = svm_set_segment,
4289 .get_cpl = svm_get_cpl,
4290 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
4291 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
4292 .decache_cr3 = svm_decache_cr3,
4293 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
4294 .set_cr0 = svm_set_cr0,
4295 .set_cr3 = svm_set_cr3,
4296 .set_cr4 = svm_set_cr4,
4297 .set_efer = svm_set_efer,
4298 .get_idt = svm_get_idt,
4299 .set_idt = svm_set_idt,
4300 .get_gdt = svm_get_gdt,
4301 .set_gdt = svm_set_gdt,
4302 .get_dr6 = svm_get_dr6,
4303 .set_dr6 = svm_set_dr6,
4304 .set_dr7 = svm_set_dr7,
4305 .cache_reg = svm_cache_reg,
4306 .get_rflags = svm_get_rflags,
4307 .set_rflags = svm_set_rflags,
4308 .fpu_activate = svm_fpu_activate,
4309 .fpu_deactivate = svm_fpu_deactivate,
4310
4311 .tlb_flush = svm_flush_tlb,
4312
4313 .run = svm_vcpu_run,
4314 .handle_exit = handle_exit,
4315 .skip_emulated_instruction = skip_emulated_instruction,
4316 .set_interrupt_shadow = svm_set_interrupt_shadow,
4317 .get_interrupt_shadow = svm_get_interrupt_shadow,
4318 .patch_hypercall = svm_patch_hypercall,
4319 .set_irq = svm_set_irq,
4320 .set_nmi = svm_inject_nmi,
4321 .queue_exception = svm_queue_exception,
4322 .cancel_injection = svm_cancel_injection,
4323 .interrupt_allowed = svm_interrupt_allowed,
4324 .nmi_allowed = svm_nmi_allowed,
4325 .get_nmi_mask = svm_get_nmi_mask,
4326 .set_nmi_mask = svm_set_nmi_mask,
4327 .enable_nmi_window = enable_nmi_window,
4328 .enable_irq_window = enable_irq_window,
4329 .update_cr8_intercept = update_cr8_intercept,
4330 .set_virtual_x2apic_mode = svm_set_virtual_x2apic_mode,
4331 .vm_has_apicv = svm_vm_has_apicv,
4332 .load_eoi_exitmap = svm_load_eoi_exitmap,
4333 .hwapic_isr_update = svm_hwapic_isr_update,
4334 .sync_pir_to_irr = svm_sync_pir_to_irr,
4335
4336 .set_tss_addr = svm_set_tss_addr,
4337 .get_tdp_level = get_npt_level,
4338 .get_mt_mask = svm_get_mt_mask,
4339
4340 .get_exit_info = svm_get_exit_info,
4341
4342 .get_lpage_level = svm_get_lpage_level,
4343
4344 .cpuid_update = svm_cpuid_update,
4345
4346 .rdtscp_supported = svm_rdtscp_supported,
4347 .invpcid_supported = svm_invpcid_supported,
4348
4349 .set_supported_cpuid = svm_set_supported_cpuid,
4350
4351 .has_wbinvd_exit = svm_has_wbinvd_exit,
4352
4353 .set_tsc_khz = svm_set_tsc_khz,
4354 .read_tsc_offset = svm_read_tsc_offset,
4355 .write_tsc_offset = svm_write_tsc_offset,
4356 .adjust_tsc_offset = svm_adjust_tsc_offset,
4357 .compute_tsc_offset = svm_compute_tsc_offset,
4358 .read_l1_tsc = svm_read_l1_tsc,
4359
4360 .set_tdp_cr3 = set_tdp_cr3,
4361
4362 .check_intercept = svm_check_intercept,
4363 .handle_external_intr = svm_handle_external_intr,
4364 };
4365
4366 static int __init svm_init(void)
4367 {
4368 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
4369 __alignof__(struct vcpu_svm), THIS_MODULE);
4370 }
4371
4372 static void __exit svm_exit(void)
4373 {
4374 kvm_exit();
4375 }
4376
4377 module_init(svm_init)
4378 module_exit(svm_exit)
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