| blob | 23ee1498c98c1016572e5e0f466bb87ce52ecd95 |
1 /*
2 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
9 /*
10 * Carveout for multimedia usecases
11 * It should be the last 48MB of the first 512MB memory part
12 * In theory, it should not even exist. That zone should be reserved
13 * dynamically during the .reserve callback.
14 */
15 /memreserve/ 0x9d000000 0x03000000;
17 /include/ "skeleton.dtsi"
19 / {
20 compatible = "ti,omap4430", "ti,omap4";
21 interrupt-parent = <&gic>;
23 aliases {
24 serial0 = &uart1;
25 serial1 = &uart2;
26 serial2 = &uart3;
27 serial3 = &uart4;
28 };
30 cpus {
31 cpu@0 {
32 compatible = "arm,cortex-a9";
33 next-level-cache = <&L2>;
34 };
35 cpu@1 {
36 compatible = "arm,cortex-a9";
37 next-level-cache = <&L2>;
38 };
39 };
41 gic: interrupt-controller@48241000 {
42 compatible = "arm,cortex-a9-gic";
43 interrupt-controller;
44 #interrupt-cells = <3>;
45 reg = <0x48241000 0x1000>,
46 <0x48240100 0x0100>;
47 };
49 L2: l2-cache-controller@48242000 {
50 compatible = "arm,pl310-cache";
51 reg = <0x48242000 0x1000>;
52 cache-unified;
53 cache-level = <2>;
54 };
56 local-timer@0x48240600 {
57 compatible = "arm,cortex-a9-twd-timer";
58 reg = <0x48240600 0x20>;
59 interrupts = <1 13 0x304>;
60 };
62 /*
63 * The soc node represents the soc top level view. It is uses for IPs
64 * that are not memory mapped in the MPU view or for the MPU itself.
65 */
66 soc {
67 compatible = "ti,omap-infra";
68 mpu {
69 compatible = "ti,omap4-mpu";
70 ti,hwmods = "mpu";
71 };
73 dsp {
74 compatible = "ti,omap3-c64";
75 ti,hwmods = "dsp";
76 };
78 iva {
79 compatible = "ti,ivahd";
80 ti,hwmods = "iva";
81 };
82 };
84 /*
85 * XXX: Use a flat representation of the OMAP4 interconnect.
86 * The real OMAP interconnect network is quite complex.
87 * Since that will not bring real advantage to represent that in DT for
88 * the moment, just use a fake OCP bus entry to represent the whole bus
89 * hierarchy.
90 */
91 ocp {
92 compatible = "ti,omap4-l3-noc", "simple-bus";
93 #address-cells = <1>;
94 #size-cells = <1>;
95 ranges;
96 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
98 counter32k: counter@4a304000 {
99 compatible = "ti,omap-counter32k";
100 reg = <0x4a304000 0x20>;
101 ti,hwmods = "counter_32k";
102 };
104 omap4_pmx_core: pinmux@4a100040 {
105 compatible = "ti,omap4-padconf", "pinctrl-single";
106 reg = <0x4a100040 0x0196>;
107 #address-cells = <1>;
108 #size-cells = <0>;
109 pinctrl-single,register-width = <16>;
110 pinctrl-single,function-mask = <0x7fff>;
111 };
112 omap4_pmx_wkup: pinmux@4a31e040 {
113 compatible = "ti,omap4-padconf", "pinctrl-single";
114 reg = <0x4a31e040 0x0038>;
115 #address-cells = <1>;
116 #size-cells = <0>;
117 pinctrl-single,register-width = <16>;
118 pinctrl-single,function-mask = <0x7fff>;
119 };
121 gpio1: gpio@4a310000 {
122 compatible = "ti,omap4-gpio";
123 reg = <0x4a310000 0x200>;
124 interrupts = <0 29 0x4>;
125 ti,hwmods = "gpio1";
126 gpio-controller;
127 #gpio-cells = <2>;
128 interrupt-controller;
129 #interrupt-cells = <1>;
130 };
132 gpio2: gpio@48055000 {
133 compatible = "ti,omap4-gpio";
134 reg = <0x48055000 0x200>;
135 interrupts = <0 30 0x4>;
136 ti,hwmods = "gpio2";
137 gpio-controller;
138 #gpio-cells = <2>;
139 interrupt-controller;
140 #interrupt-cells = <1>;
141 };
143 gpio3: gpio@48057000 {
144 compatible = "ti,omap4-gpio";
145 reg = <0x48057000 0x200>;
146 interrupts = <0 31 0x4>;
147 ti,hwmods = "gpio3";
148 gpio-controller;
149 #gpio-cells = <2>;
150 interrupt-controller;
151 #interrupt-cells = <1>;
152 };
154 gpio4: gpio@48059000 {
155 compatible = "ti,omap4-gpio";
156 reg = <0x48059000 0x200>;
157 interrupts = <0 32 0x4>;
158 ti,hwmods = "gpio4";
159 gpio-controller;
160 #gpio-cells = <2>;
161 interrupt-controller;
162 #interrupt-cells = <1>;
163 };
165 gpio5: gpio@4805b000 {
166 compatible = "ti,omap4-gpio";
167 reg = <0x4805b000 0x200>;
168 interrupts = <0 33 0x4>;
169 ti,hwmods = "gpio5";
170 gpio-controller;
171 #gpio-cells = <2>;
172 interrupt-controller;
173 #interrupt-cells = <1>;
174 };
176 gpio6: gpio@4805d000 {
177 compatible = "ti,omap4-gpio";
178 reg = <0x4805d000 0x200>;
179 interrupts = <0 34 0x4>;
180 ti,hwmods = "gpio6";
181 gpio-controller;
182 #gpio-cells = <2>;
183 interrupt-controller;
184 #interrupt-cells = <1>;
185 };
187 uart1: serial@4806a000 {
188 compatible = "ti,omap4-uart";
189 reg = <0x4806a000 0x100>;
190 interrupts = <0 72 0x4>;
191 ti,hwmods = "uart1";
192 clock-frequency = <48000000>;
193 };
195 uart2: serial@4806c000 {
196 compatible = "ti,omap4-uart";
197 reg = <0x4806c000 0x100>;
198 interrupts = <0 73 0x4>;
199 ti,hwmods = "uart2";
200 clock-frequency = <48000000>;
201 };
203 uart3: serial@48020000 {
204 compatible = "ti,omap4-uart";
205 reg = <0x48020000 0x100>;
206 interrupts = <0 74 0x4>;
207 ti,hwmods = "uart3";
208 clock-frequency = <48000000>;
209 };
211 uart4: serial@4806e000 {
212 compatible = "ti,omap4-uart";
213 reg = <0x4806e000 0x100>;
214 interrupts = <0 70 0x4>;
215 ti,hwmods = "uart4";
216 clock-frequency = <48000000>;
217 };
219 i2c1: i2c@48070000 {
220 compatible = "ti,omap4-i2c";
221 reg = <0x48070000 0x100>;
222 interrupts = <0 56 0x4>;
223 #address-cells = <1>;
224 #size-cells = <0>;
225 ti,hwmods = "i2c1";
226 };
228 i2c2: i2c@48072000 {
229 compatible = "ti,omap4-i2c";
230 reg = <0x48072000 0x100>;
231 interrupts = <0 57 0x4>;
232 #address-cells = <1>;
233 #size-cells = <0>;
234 ti,hwmods = "i2c2";
235 };
237 i2c3: i2c@48060000 {
238 compatible = "ti,omap4-i2c";
239 reg = <0x48060000 0x100>;
240 interrupts = <0 61 0x4>;
241 #address-cells = <1>;
242 #size-cells = <0>;
243 ti,hwmods = "i2c3";
244 };
246 i2c4: i2c@48350000 {
247 compatible = "ti,omap4-i2c";
248 reg = <0x48350000 0x100>;
249 interrupts = <0 62 0x4>;
250 #address-cells = <1>;
251 #size-cells = <0>;
252 ti,hwmods = "i2c4";
253 };
255 mcspi1: spi@48098000 {
256 compatible = "ti,omap4-mcspi";
257 reg = <0x48098000 0x200>;
258 interrupts = <0 65 0x4>;
259 #address-cells = <1>;
260 #size-cells = <0>;
261 ti,hwmods = "mcspi1";
262 ti,spi-num-cs = <4>;
263 };
265 mcspi2: spi@4809a000 {
266 compatible = "ti,omap4-mcspi";
267 reg = <0x4809a000 0x200>;
268 interrupts = <0 66 0x4>;
269 #address-cells = <1>;
270 #size-cells = <0>;
271 ti,hwmods = "mcspi2";
272 ti,spi-num-cs = <2>;
273 };
275 mcspi3: spi@480b8000 {
276 compatible = "ti,omap4-mcspi";
277 reg = <0x480b8000 0x200>;
278 interrupts = <0 91 0x4>;
279 #address-cells = <1>;
280 #size-cells = <0>;
281 ti,hwmods = "mcspi3";
282 ti,spi-num-cs = <2>;
283 };
285 mcspi4: spi@480ba000 {
286 compatible = "ti,omap4-mcspi";
287 reg = <0x480ba000 0x200>;
288 interrupts = <0 48 0x4>;
289 #address-cells = <1>;
290 #size-cells = <0>;
291 ti,hwmods = "mcspi4";
292 ti,spi-num-cs = <1>;
293 };
295 mmc1: mmc@4809c000 {
296 compatible = "ti,omap4-hsmmc";
297 reg = <0x4809c000 0x400>;
298 interrupts = <0 83 0x4>;
299 ti,hwmods = "mmc1";
300 ti,dual-volt;
301 ti,needs-special-reset;
302 };
304 mmc2: mmc@480b4000 {
305 compatible = "ti,omap4-hsmmc";
306 reg = <0x480b4000 0x400>;
307 interrupts = <0 86 0x4>;
308 ti,hwmods = "mmc2";
309 ti,needs-special-reset;
310 };
312 mmc3: mmc@480ad000 {
313 compatible = "ti,omap4-hsmmc";
314 reg = <0x480ad000 0x400>;
315 interrupts = <0 94 0x4>;
316 ti,hwmods = "mmc3";
317 ti,needs-special-reset;
318 };
320 mmc4: mmc@480d1000 {
321 compatible = "ti,omap4-hsmmc";
322 reg = <0x480d1000 0x400>;
323 interrupts = <0 96 0x4>;
324 ti,hwmods = "mmc4";
325 ti,needs-special-reset;
326 };
328 mmc5: mmc@480d5000 {
329 compatible = "ti,omap4-hsmmc";
330 reg = <0x480d5000 0x400>;
331 interrupts = <0 59 0x4>;
332 ti,hwmods = "mmc5";
333 ti,needs-special-reset;
334 };
336 wdt2: wdt@4a314000 {
337 compatible = "ti,omap4-wdt", "ti,omap3-wdt";
338 reg = <0x4a314000 0x80>;
339 interrupts = <0 80 0x4>;
340 ti,hwmods = "wd_timer2";
341 };
343 mcpdm: mcpdm@40132000 {
344 compatible = "ti,omap4-mcpdm";
345 reg = <0x40132000 0x7f>, /* MPU private access */
346 <0x49032000 0x7f>; /* L3 Interconnect */
347 reg-names = "mpu", "dma";
348 interrupts = <0 112 0x4>;
349 ti,hwmods = "mcpdm";
350 };
352 dmic: dmic@4012e000 {
353 compatible = "ti,omap4-dmic";
354 reg = <0x4012e000 0x7f>, /* MPU private access */
355 <0x4902e000 0x7f>; /* L3 Interconnect */
356 reg-names = "mpu", "dma";
357 interrupts = <0 114 0x4>;
358 ti,hwmods = "dmic";
359 };
361 mcbsp1: mcbsp@40122000 {
362 compatible = "ti,omap4-mcbsp";
363 reg = <0x40122000 0xff>, /* MPU private access */
364 <0x49022000 0xff>; /* L3 Interconnect */
365 reg-names = "mpu", "dma";
366 interrupts = <0 17 0x4>;
367 interrupt-names = "common";
368 ti,buffer-size = <128>;
369 ti,hwmods = "mcbsp1";
370 };
372 mcbsp2: mcbsp@40124000 {
373 compatible = "ti,omap4-mcbsp";
374 reg = <0x40124000 0xff>, /* MPU private access */
375 <0x49024000 0xff>; /* L3 Interconnect */
376 reg-names = "mpu", "dma";
377 interrupts = <0 22 0x4>;
378 interrupt-names = "common";
379 ti,buffer-size = <128>;
380 ti,hwmods = "mcbsp2";
381 };
383 mcbsp3: mcbsp@40126000 {
384 compatible = "ti,omap4-mcbsp";
385 reg = <0x40126000 0xff>, /* MPU private access */
386 <0x49026000 0xff>; /* L3 Interconnect */
387 reg-names = "mpu", "dma";
388 interrupts = <0 23 0x4>;
389 interrupt-names = "common";
390 ti,buffer-size = <128>;
391 ti,hwmods = "mcbsp3";
392 };
394 mcbsp4: mcbsp@48096000 {
395 compatible = "ti,omap4-mcbsp";
396 reg = <0x48096000 0xff>; /* L4 Interconnect */
397 reg-names = "mpu";
398 interrupts = <0 16 0x4>;
399 interrupt-names = "common";
400 ti,buffer-size = <128>;
401 ti,hwmods = "mcbsp4";
402 };
404 keypad: keypad@4a31c000 {
405 compatible = "ti,omap4-keypad";
406 reg = <0x4a31c000 0x80>;
407 interrupts = <0 120 0x4>;
408 reg-names = "mpu";
409 ti,hwmods = "kbd";
410 };
412 emif1: emif@4c000000 {
413 compatible = "ti,emif-4d";
414 reg = <0x4c000000 0x100>;
415 interrupts = <0 110 0x4>;
416 ti,hwmods = "emif1";
417 phy-type = <1>;
418 hw-caps-read-idle-ctrl;
419 hw-caps-ll-interface;
420 hw-caps-temp-alert;
421 };
423 emif2: emif@4d000000 {
424 compatible = "ti,emif-4d";
425 reg = <0x4d000000 0x100>;
426 interrupts = <0 111 0x4>;
427 ti,hwmods = "emif2";
428 phy-type = <1>;
429 hw-caps-read-idle-ctrl;
430 hw-caps-ll-interface;
431 hw-caps-temp-alert;
432 };
434 ocp2scp@4a0ad000 {
435 compatible = "ti,omap-ocp2scp";
436 reg = <0x4a0ad000 0x1f>;
437 #address-cells = <1>;
438 #size-cells = <1>;
439 ranges;
440 ti,hwmods = "ocp2scp_usb_phy";
441 };
443 timer1: timer@4a318000 {
444 compatible = "ti,omap2-timer";
445 reg = <0x4a318000 0x80>;
446 interrupts = <0 37 0x4>;
447 ti,hwmods = "timer1";
448 ti,timer-alwon;
449 };
451 timer2: timer@48032000 {
452 compatible = "ti,omap2-timer";
453 reg = <0x48032000 0x80>;
454 interrupts = <0 38 0x4>;
455 ti,hwmods = "timer2";
456 };
458 timer3: timer@48034000 {
459 compatible = "ti,omap2-timer";
460 reg = <0x48034000 0x80>;
461 interrupts = <0 39 0x4>;
462 ti,hwmods = "timer3";
463 };
465 timer4: timer@48036000 {
466 compatible = "ti,omap2-timer";
467 reg = <0x48036000 0x80>;
468 interrupts = <0 40 0x4>;
469 ti,hwmods = "timer4";
470 };
472 timer5: timer@49038000 {
473 compatible = "ti,omap2-timer";
474 reg = <0x49038000 0x80>;
475 interrupts = <0 41 0x4>;
476 ti,hwmods = "timer5";
477 ti,timer-dsp;
478 };
480 timer6: timer@4903a000 {
481 compatible = "ti,omap2-timer";
482 reg = <0x4903a000 0x80>;
483 interrupts = <0 42 0x4>;
484 ti,hwmods = "timer6";
485 ti,timer-dsp;
486 };
488 timer7: timer@4903c000 {
489 compatible = "ti,omap2-timer";
490 reg = <0x4903c000 0x80>;
491 interrupts = <0 43 0x4>;
492 ti,hwmods = "timer7";
493 ti,timer-dsp;
494 };
496 timer8: timer@4903e000 {
497 compatible = "ti,omap2-timer";
498 reg = <0x4903e000 0x80>;
499 interrupts = <0 44 0x4>;
500 ti,hwmods = "timer8";
501 ti,timer-pwm;
502 ti,timer-dsp;
503 };
505 timer9: timer@4803e000 {
506 compatible = "ti,omap2-timer";
507 reg = <0x4803e000 0x80>;
508 interrupts = <0 45 0x4>;
509 ti,hwmods = "timer9";
510 ti,timer-pwm;
511 };
513 timer10: timer@48086000 {
514 compatible = "ti,omap2-timer";
515 reg = <0x48086000 0x80>;
516 interrupts = <0 46 0x4>;
517 ti,hwmods = "timer10";
518 ti,timer-pwm;
519 };
521 timer11: timer@48088000 {
522 compatible = "ti,omap2-timer";
523 reg = <0x48088000 0x80>;
524 interrupts = <0 47 0x4>;
525 ti,hwmods = "timer11";
526 ti,timer-pwm;
527 };
528 };
529 };