| blob | a1e05853afcd583c15da3ad259c8f715992b2d7f |
1 /*
2 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/omap.h>
13 #include "skeleton.dtsi"
15 / {
16 compatible = "ti,omap4430", "ti,omap4";
17 interrupt-parent = <&gic>;
19 aliases {
20 i2c0 = &i2c1;
21 i2c1 = &i2c2;
22 i2c2 = &i2c3;
23 i2c3 = &i2c4;
24 serial0 = &uart1;
25 serial1 = &uart2;
26 serial2 = &uart3;
27 serial3 = &uart4;
28 };
30 cpus {
31 #address-cells = <1>;
32 #size-cells = <0>;
34 cpu@0 {
35 compatible = "arm,cortex-a9";
36 device_type = "cpu";
37 next-level-cache = <&L2>;
38 reg = <0x0>;
39 };
40 cpu@1 {
41 compatible = "arm,cortex-a9";
42 device_type = "cpu";
43 next-level-cache = <&L2>;
44 reg = <0x1>;
45 };
46 };
48 gic: interrupt-controller@48241000 {
49 compatible = "arm,cortex-a9-gic";
50 interrupt-controller;
51 #interrupt-cells = <3>;
52 reg = <0x48241000 0x1000>,
53 <0x48240100 0x0100>;
54 };
56 L2: l2-cache-controller@48242000 {
57 compatible = "arm,pl310-cache";
58 reg = <0x48242000 0x1000>;
59 cache-unified;
60 cache-level = <2>;
61 };
63 local-timer@48240600 {
64 compatible = "arm,cortex-a9-twd-timer";
65 reg = <0x48240600 0x20>;
66 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
67 };
69 /*
70 * The soc node represents the soc top level view. It is uses for IPs
71 * that are not memory mapped in the MPU view or for the MPU itself.
72 */
73 soc {
74 compatible = "ti,omap-infra";
75 mpu {
76 compatible = "ti,omap4-mpu";
77 ti,hwmods = "mpu";
78 };
80 dsp {
81 compatible = "ti,omap3-c64";
82 ti,hwmods = "dsp";
83 };
85 iva {
86 compatible = "ti,ivahd";
87 ti,hwmods = "iva";
88 };
89 };
91 /*
92 * XXX: Use a flat representation of the OMAP4 interconnect.
93 * The real OMAP interconnect network is quite complex.
94 * Since that will not bring real advantage to represent that in DT for
95 * the moment, just use a fake OCP bus entry to represent the whole bus
96 * hierarchy.
97 */
98 ocp {
99 compatible = "ti,omap4-l3-noc", "simple-bus";
100 #address-cells = <1>;
101 #size-cells = <1>;
102 ranges;
103 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
104 reg = <0x44000000 0x1000>,
105 <0x44800000 0x2000>,
106 <0x45000000 0x1000>;
107 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
108 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
110 counter32k: counter@4a304000 {
111 compatible = "ti,omap-counter32k";
112 reg = <0x4a304000 0x20>;
113 ti,hwmods = "counter_32k";
114 };
116 omap4_pmx_core: pinmux@4a100040 {
117 compatible = "ti,omap4-padconf", "pinctrl-single";
118 reg = <0x4a100040 0x0196>;
119 #address-cells = <1>;
120 #size-cells = <0>;
121 #interrupt-cells = <1>;
122 interrupt-controller;
123 pinctrl-single,register-width = <16>;
124 pinctrl-single,function-mask = <0x7fff>;
125 };
126 omap4_pmx_wkup: pinmux@4a31e040 {
127 compatible = "ti,omap4-padconf", "pinctrl-single";
128 reg = <0x4a31e040 0x0038>;
129 #address-cells = <1>;
130 #size-cells = <0>;
131 #interrupt-cells = <1>;
132 interrupt-controller;
133 pinctrl-single,register-width = <16>;
134 pinctrl-single,function-mask = <0x7fff>;
135 };
137 sdma: dma-controller@4a056000 {
138 compatible = "ti,omap4430-sdma";
139 reg = <0x4a056000 0x1000>;
140 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
141 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
142 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
143 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
144 #dma-cells = <1>;
145 #dma-channels = <32>;
146 #dma-requests = <127>;
147 };
149 gpio1: gpio@4a310000 {
150 compatible = "ti,omap4-gpio";
151 reg = <0x4a310000 0x200>;
152 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
153 ti,hwmods = "gpio1";
154 ti,gpio-always-on;
155 gpio-controller;
156 #gpio-cells = <2>;
157 interrupt-controller;
158 #interrupt-cells = <2>;
159 };
161 gpio2: gpio@48055000 {
162 compatible = "ti,omap4-gpio";
163 reg = <0x48055000 0x200>;
164 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
165 ti,hwmods = "gpio2";
166 gpio-controller;
167 #gpio-cells = <2>;
168 interrupt-controller;
169 #interrupt-cells = <2>;
170 };
172 gpio3: gpio@48057000 {
173 compatible = "ti,omap4-gpio";
174 reg = <0x48057000 0x200>;
175 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
176 ti,hwmods = "gpio3";
177 gpio-controller;
178 #gpio-cells = <2>;
179 interrupt-controller;
180 #interrupt-cells = <2>;
181 };
183 gpio4: gpio@48059000 {
184 compatible = "ti,omap4-gpio";
185 reg = <0x48059000 0x200>;
186 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
187 ti,hwmods = "gpio4";
188 gpio-controller;
189 #gpio-cells = <2>;
190 interrupt-controller;
191 #interrupt-cells = <2>;
192 };
194 gpio5: gpio@4805b000 {
195 compatible = "ti,omap4-gpio";
196 reg = <0x4805b000 0x200>;
197 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
198 ti,hwmods = "gpio5";
199 gpio-controller;
200 #gpio-cells = <2>;
201 interrupt-controller;
202 #interrupt-cells = <2>;
203 };
205 gpio6: gpio@4805d000 {
206 compatible = "ti,omap4-gpio";
207 reg = <0x4805d000 0x200>;
208 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
209 ti,hwmods = "gpio6";
210 gpio-controller;
211 #gpio-cells = <2>;
212 interrupt-controller;
213 #interrupt-cells = <2>;
214 };
216 gpmc: gpmc@50000000 {
217 compatible = "ti,omap4430-gpmc";
218 reg = <0x50000000 0x1000>;
219 #address-cells = <2>;
220 #size-cells = <1>;
221 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
222 gpmc,num-cs = <8>;
223 gpmc,num-waitpins = <4>;
224 ti,hwmods = "gpmc";
225 ti,no-idle-on-init;
226 };
228 uart1: serial@4806a000 {
229 compatible = "ti,omap4-uart";
230 reg = <0x4806a000 0x100>;
231 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
232 ti,hwmods = "uart1";
233 clock-frequency = <48000000>;
234 };
236 uart2: serial@4806c000 {
237 compatible = "ti,omap4-uart";
238 reg = <0x4806c000 0x100>;
239 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
240 ti,hwmods = "uart2";
241 clock-frequency = <48000000>;
242 };
244 uart3: serial@48020000 {
245 compatible = "ti,omap4-uart";
246 reg = <0x48020000 0x100>;
247 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
248 ti,hwmods = "uart3";
249 clock-frequency = <48000000>;
250 };
252 uart4: serial@4806e000 {
253 compatible = "ti,omap4-uart";
254 reg = <0x4806e000 0x100>;
255 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
256 ti,hwmods = "uart4";
257 clock-frequency = <48000000>;
258 };
260 hwspinlock: spinlock@4a0f6000 {
261 compatible = "ti,omap4-hwspinlock";
262 reg = <0x4a0f6000 0x1000>;
263 ti,hwmods = "spinlock";
264 };
266 i2c1: i2c@48070000 {
267 compatible = "ti,omap4-i2c";
268 reg = <0x48070000 0x100>;
269 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
270 #address-cells = <1>;
271 #size-cells = <0>;
272 ti,hwmods = "i2c1";
273 };
275 i2c2: i2c@48072000 {
276 compatible = "ti,omap4-i2c";
277 reg = <0x48072000 0x100>;
278 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
279 #address-cells = <1>;
280 #size-cells = <0>;
281 ti,hwmods = "i2c2";
282 };
284 i2c3: i2c@48060000 {
285 compatible = "ti,omap4-i2c";
286 reg = <0x48060000 0x100>;
287 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
288 #address-cells = <1>;
289 #size-cells = <0>;
290 ti,hwmods = "i2c3";
291 };
293 i2c4: i2c@48350000 {
294 compatible = "ti,omap4-i2c";
295 reg = <0x48350000 0x100>;
296 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
297 #address-cells = <1>;
298 #size-cells = <0>;
299 ti,hwmods = "i2c4";
300 };
302 mcspi1: spi@48098000 {
303 compatible = "ti,omap4-mcspi";
304 reg = <0x48098000 0x200>;
305 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
306 #address-cells = <1>;
307 #size-cells = <0>;
308 ti,hwmods = "mcspi1";
309 ti,spi-num-cs = <4>;
310 dmas = <&sdma 35>,
311 <&sdma 36>,
312 <&sdma 37>,
313 <&sdma 38>,
314 <&sdma 39>,
315 <&sdma 40>,
316 <&sdma 41>,
317 <&sdma 42>;
318 dma-names = "tx0", "rx0", "tx1", "rx1",
319 "tx2", "rx2", "tx3", "rx3";
320 };
322 mcspi2: spi@4809a000 {
323 compatible = "ti,omap4-mcspi";
324 reg = <0x4809a000 0x200>;
325 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
326 #address-cells = <1>;
327 #size-cells = <0>;
328 ti,hwmods = "mcspi2";
329 ti,spi-num-cs = <2>;
330 dmas = <&sdma 43>,
331 <&sdma 44>,
332 <&sdma 45>,
333 <&sdma 46>;
334 dma-names = "tx0", "rx0", "tx1", "rx1";
335 };
337 mcspi3: spi@480b8000 {
338 compatible = "ti,omap4-mcspi";
339 reg = <0x480b8000 0x200>;
340 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
341 #address-cells = <1>;
342 #size-cells = <0>;
343 ti,hwmods = "mcspi3";
344 ti,spi-num-cs = <2>;
345 dmas = <&sdma 15>, <&sdma 16>;
346 dma-names = "tx0", "rx0";
347 };
349 mcspi4: spi@480ba000 {
350 compatible = "ti,omap4-mcspi";
351 reg = <0x480ba000 0x200>;
352 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
353 #address-cells = <1>;
354 #size-cells = <0>;
355 ti,hwmods = "mcspi4";
356 ti,spi-num-cs = <1>;
357 dmas = <&sdma 70>, <&sdma 71>;
358 dma-names = "tx0", "rx0";
359 };
361 mmc1: mmc@4809c000 {
362 compatible = "ti,omap4-hsmmc";
363 reg = <0x4809c000 0x400>;
364 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
365 ti,hwmods = "mmc1";
366 ti,dual-volt;
367 ti,needs-special-reset;
368 dmas = <&sdma 61>, <&sdma 62>;
369 dma-names = "tx", "rx";
370 };
372 mmc2: mmc@480b4000 {
373 compatible = "ti,omap4-hsmmc";
374 reg = <0x480b4000 0x400>;
375 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
376 ti,hwmods = "mmc2";
377 ti,needs-special-reset;
378 dmas = <&sdma 47>, <&sdma 48>;
379 dma-names = "tx", "rx";
380 };
382 mmc3: mmc@480ad000 {
383 compatible = "ti,omap4-hsmmc";
384 reg = <0x480ad000 0x400>;
385 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
386 ti,hwmods = "mmc3";
387 ti,needs-special-reset;
388 dmas = <&sdma 77>, <&sdma 78>;
389 dma-names = "tx", "rx";
390 };
392 mmc4: mmc@480d1000 {
393 compatible = "ti,omap4-hsmmc";
394 reg = <0x480d1000 0x400>;
395 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
396 ti,hwmods = "mmc4";
397 ti,needs-special-reset;
398 dmas = <&sdma 57>, <&sdma 58>;
399 dma-names = "tx", "rx";
400 };
402 mmc5: mmc@480d5000 {
403 compatible = "ti,omap4-hsmmc";
404 reg = <0x480d5000 0x400>;
405 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
406 ti,hwmods = "mmc5";
407 ti,needs-special-reset;
408 dmas = <&sdma 59>, <&sdma 60>;
409 dma-names = "tx", "rx";
410 };
412 wdt2: wdt@4a314000 {
413 compatible = "ti,omap4-wdt", "ti,omap3-wdt";
414 reg = <0x4a314000 0x80>;
415 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
416 ti,hwmods = "wd_timer2";
417 };
419 mcpdm: mcpdm@40132000 {
420 compatible = "ti,omap4-mcpdm";
421 reg = <0x40132000 0x7f>, /* MPU private access */
422 <0x49032000 0x7f>; /* L3 Interconnect */
423 reg-names = "mpu", "dma";
424 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
425 ti,hwmods = "mcpdm";
426 dmas = <&sdma 65>,
427 <&sdma 66>;
428 dma-names = "up_link", "dn_link";
429 };
431 dmic: dmic@4012e000 {
432 compatible = "ti,omap4-dmic";
433 reg = <0x4012e000 0x7f>, /* MPU private access */
434 <0x4902e000 0x7f>; /* L3 Interconnect */
435 reg-names = "mpu", "dma";
436 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
437 ti,hwmods = "dmic";
438 dmas = <&sdma 67>;
439 dma-names = "up_link";
440 };
442 mcbsp1: mcbsp@40122000 {
443 compatible = "ti,omap4-mcbsp";
444 reg = <0x40122000 0xff>, /* MPU private access */
445 <0x49022000 0xff>; /* L3 Interconnect */
446 reg-names = "mpu", "dma";
447 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
448 interrupt-names = "common";
449 ti,buffer-size = <128>;
450 ti,hwmods = "mcbsp1";
451 dmas = <&sdma 33>,
452 <&sdma 34>;
453 dma-names = "tx", "rx";
454 };
456 mcbsp2: mcbsp@40124000 {
457 compatible = "ti,omap4-mcbsp";
458 reg = <0x40124000 0xff>, /* MPU private access */
459 <0x49024000 0xff>; /* L3 Interconnect */
460 reg-names = "mpu", "dma";
461 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
462 interrupt-names = "common";
463 ti,buffer-size = <128>;
464 ti,hwmods = "mcbsp2";
465 dmas = <&sdma 17>,
466 <&sdma 18>;
467 dma-names = "tx", "rx";
468 };
470 mcbsp3: mcbsp@40126000 {
471 compatible = "ti,omap4-mcbsp";
472 reg = <0x40126000 0xff>, /* MPU private access */
473 <0x49026000 0xff>; /* L3 Interconnect */
474 reg-names = "mpu", "dma";
475 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
476 interrupt-names = "common";
477 ti,buffer-size = <128>;
478 ti,hwmods = "mcbsp3";
479 dmas = <&sdma 19>,
480 <&sdma 20>;
481 dma-names = "tx", "rx";
482 };
484 mcbsp4: mcbsp@48096000 {
485 compatible = "ti,omap4-mcbsp";
486 reg = <0x48096000 0xff>; /* L4 Interconnect */
487 reg-names = "mpu";
488 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
489 interrupt-names = "common";
490 ti,buffer-size = <128>;
491 ti,hwmods = "mcbsp4";
492 dmas = <&sdma 31>,
493 <&sdma 32>;
494 dma-names = "tx", "rx";
495 };
497 keypad: keypad@4a31c000 {
498 compatible = "ti,omap4-keypad";
499 reg = <0x4a31c000 0x80>;
500 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
501 reg-names = "mpu";
502 ti,hwmods = "kbd";
503 };
505 emif1: emif@4c000000 {
506 compatible = "ti,emif-4d";
507 reg = <0x4c000000 0x100>;
508 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
509 ti,hwmods = "emif1";
510 ti,no-idle-on-init;
511 phy-type = <1>;
512 hw-caps-read-idle-ctrl;
513 hw-caps-ll-interface;
514 hw-caps-temp-alert;
515 };
517 emif2: emif@4d000000 {
518 compatible = "ti,emif-4d";
519 reg = <0x4d000000 0x100>;
520 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
521 ti,hwmods = "emif2";
522 ti,no-idle-on-init;
523 phy-type = <1>;
524 hw-caps-read-idle-ctrl;
525 hw-caps-ll-interface;
526 hw-caps-temp-alert;
527 };
529 ocp2scp@4a0ad000 {
530 compatible = "ti,omap-ocp2scp";
531 reg = <0x4a0ad000 0x1f>;
532 #address-cells = <1>;
533 #size-cells = <1>;
534 ranges;
535 ti,hwmods = "ocp2scp_usb_phy";
536 usb2_phy: usb2phy@4a0ad080 {
537 compatible = "ti,omap-usb2";
538 reg = <0x4a0ad080 0x58>;
539 ctrl-module = <&omap_control_usb2phy>;
540 #phy-cells = <0>;
541 };
542 };
544 timer1: timer@4a318000 {
545 compatible = "ti,omap3430-timer";
546 reg = <0x4a318000 0x80>;
547 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
548 ti,hwmods = "timer1";
549 ti,timer-alwon;
550 };
552 timer2: timer@48032000 {
553 compatible = "ti,omap3430-timer";
554 reg = <0x48032000 0x80>;
555 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
556 ti,hwmods = "timer2";
557 };
559 timer3: timer@48034000 {
560 compatible = "ti,omap4430-timer";
561 reg = <0x48034000 0x80>;
562 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
563 ti,hwmods = "timer3";
564 };
566 timer4: timer@48036000 {
567 compatible = "ti,omap4430-timer";
568 reg = <0x48036000 0x80>;
569 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
570 ti,hwmods = "timer4";
571 };
573 timer5: timer@40138000 {
574 compatible = "ti,omap4430-timer";
575 reg = <0x40138000 0x80>,
576 <0x49038000 0x80>;
577 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
578 ti,hwmods = "timer5";
579 ti,timer-dsp;
580 };
582 timer6: timer@4013a000 {
583 compatible = "ti,omap4430-timer";
584 reg = <0x4013a000 0x80>,
585 <0x4903a000 0x80>;
586 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
587 ti,hwmods = "timer6";
588 ti,timer-dsp;
589 };
591 timer7: timer@4013c000 {
592 compatible = "ti,omap4430-timer";
593 reg = <0x4013c000 0x80>,
594 <0x4903c000 0x80>;
595 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
596 ti,hwmods = "timer7";
597 ti,timer-dsp;
598 };
600 timer8: timer@4013e000 {
601 compatible = "ti,omap4430-timer";
602 reg = <0x4013e000 0x80>,
603 <0x4903e000 0x80>;
604 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
605 ti,hwmods = "timer8";
606 ti,timer-pwm;
607 ti,timer-dsp;
608 };
610 timer9: timer@4803e000 {
611 compatible = "ti,omap4430-timer";
612 reg = <0x4803e000 0x80>;
613 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
614 ti,hwmods = "timer9";
615 ti,timer-pwm;
616 };
618 timer10: timer@48086000 {
619 compatible = "ti,omap3430-timer";
620 reg = <0x48086000 0x80>;
621 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
622 ti,hwmods = "timer10";
623 ti,timer-pwm;
624 };
626 timer11: timer@48088000 {
627 compatible = "ti,omap4430-timer";
628 reg = <0x48088000 0x80>;
629 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
630 ti,hwmods = "timer11";
631 ti,timer-pwm;
632 };
634 usbhstll: usbhstll@4a062000 {
635 compatible = "ti,usbhs-tll";
636 reg = <0x4a062000 0x1000>;
637 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
638 ti,hwmods = "usb_tll_hs";
639 };
641 usbhshost: usbhshost@4a064000 {
642 compatible = "ti,usbhs-host";
643 reg = <0x4a064000 0x800>;
644 ti,hwmods = "usb_host_hs";
645 #address-cells = <1>;
646 #size-cells = <1>;
647 ranges;
649 usbhsohci: ohci@4a064800 {
650 compatible = "ti,ohci-omap3", "usb-ohci";
651 reg = <0x4a064800 0x400>;
652 interrupt-parent = <&gic>;
653 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
654 };
656 usbhsehci: ehci@4a064c00 {
657 compatible = "ti,ehci-omap", "usb-ehci";
658 reg = <0x4a064c00 0x400>;
659 interrupt-parent = <&gic>;
660 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
661 };
662 };
664 omap_control_usb2phy: control-phy@4a002300 {
665 compatible = "ti,control-phy-usb2";
666 reg = <0x4a002300 0x4>;
667 reg-names = "power";
668 };
670 omap_control_usbotg: control-phy@4a00233c {
671 compatible = "ti,control-phy-otghs";
672 reg = <0x4a00233c 0x4>;
673 reg-names = "otghs_control";
674 };
676 usb_otg_hs: usb_otg_hs@4a0ab000 {
677 compatible = "ti,omap4-musb";
678 reg = <0x4a0ab000 0x7ff>;
679 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
680 interrupt-names = "mc", "dma";
681 ti,hwmods = "usb_otg_hs";
682 usb-phy = <&usb2_phy>;
683 phys = <&usb2_phy>;
684 phy-names = "usb2-phy";
685 multipoint = <1>;
686 num-eps = <16>;
687 ram-bits = <12>;
688 ctrl-module = <&omap_control_usbotg>;
689 };
691 aes: aes@4b501000 {
692 compatible = "ti,omap4-aes";
693 ti,hwmods = "aes";
694 reg = <0x4b501000 0xa0>;
695 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
696 dmas = <&sdma 111>, <&sdma 110>;
697 dma-names = "tx", "rx";
698 };
700 des: des@480a5000 {
701 compatible = "ti,omap4-des";
702 ti,hwmods = "des";
703 reg = <0x480a5000 0xa0>;
704 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
705 dmas = <&sdma 117>, <&sdma 116>;
706 dma-names = "tx", "rx";
707 };
708 };
709 };