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serial/imx: propagate error from of_alias_get_id instead of using -ENODEV
[linux-2.6.git] / drivers / tty / serial / imx.c
blob2813f0210377246a3b47bea49441fcc3545dc51d
1 /*
2 * Driver for Motorola IMX serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Author: Sascha Hauer <sascha@saschahauer.de>
7 * Copyright (C) 2004 Pengutronix
8 *
9 * Copyright (C) 2009 emlix GmbH
10 * Author: Fabian Godehardt (added IrDA support for iMX)
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 * [29-Mar-2005] Mike Lee
27 * Added hardware handshake
28 */
29
30 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
31 #define SUPPORT_SYSRQ
32 #endif
33
34 #include <linux/module.h>
35 #include <linux/ioport.h>
36 #include <linux/init.h>
37 #include <linux/console.h>
38 #include <linux/sysrq.h>
39 #include <linux/platform_device.h>
40 #include <linux/tty.h>
41 #include <linux/tty_flip.h>
42 #include <linux/serial_core.h>
43 #include <linux/serial.h>
44 #include <linux/clk.h>
45 #include <linux/delay.h>
46 #include <linux/rational.h>
47 #include <linux/slab.h>
48 #include <linux/of.h>
49 #include <linux/of_device.h>
50
51 #include <asm/io.h>
52 #include <asm/irq.h>
53 #include <mach/imx-uart.h>
54
55 /* Register definitions */
56 #define URXD0 0x0 /* Receiver Register */
57 #define URTX0 0x40 /* Transmitter Register */
58 #define UCR1 0x80 /* Control Register 1 */
59 #define UCR2 0x84 /* Control Register 2 */
60 #define UCR3 0x88 /* Control Register 3 */
61 #define UCR4 0x8c /* Control Register 4 */
62 #define UFCR 0x90 /* FIFO Control Register */
63 #define USR1 0x94 /* Status Register 1 */
64 #define USR2 0x98 /* Status Register 2 */
65 #define UESC 0x9c /* Escape Character Register */
66 #define UTIM 0xa0 /* Escape Timer Register */
67 #define UBIR 0xa4 /* BRM Incremental Register */
68 #define UBMR 0xa8 /* BRM Modulator Register */
69 #define UBRC 0xac /* Baud Rate Count Register */
70 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
71 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
72 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
73
74 /* UART Control Register Bit Fields.*/
75 #define URXD_CHARRDY (1<<15)
76 #define URXD_ERR (1<<14)
77 #define URXD_OVRRUN (1<<13)
78 #define URXD_FRMERR (1<<12)
79 #define URXD_BRK (1<<11)
80 #define URXD_PRERR (1<<10)
81 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */
82 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
83 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
84 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
85 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
86 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
87 #define UCR1_IREN (1<<7) /* Infrared interface enable */
88 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
89 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
90 #define UCR1_SNDBRK (1<<4) /* Send break */
91 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
92 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
93 #define UCR1_DOZE (1<<1) /* Doze */
94 #define UCR1_UARTEN (1<<0) /* UART enabled */
95 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
96 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
97 #define UCR2_CTSC (1<<13) /* CTS pin control */
98 #define UCR2_CTS (1<<12) /* Clear to send */
99 #define UCR2_ESCEN (1<<11) /* Escape enable */
100 #define UCR2_PREN (1<<8) /* Parity enable */
101 #define UCR2_PROE (1<<7) /* Parity odd/even */
102 #define UCR2_STPB (1<<6) /* Stop */
103 #define UCR2_WS (1<<5) /* Word size */
104 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
105 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
106 #define UCR2_RXEN (1<<1) /* Receiver enabled */
107 #define UCR2_SRST (1<<0) /* SW reset */
108 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
109 #define UCR3_PARERREN (1<<12) /* Parity enable */
110 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
111 #define UCR3_DSR (1<<10) /* Data set ready */
112 #define UCR3_DCD (1<<9) /* Data carrier detect */
113 #define UCR3_RI (1<<8) /* Ring indicator */
114 #define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
115 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
116 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
117 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
118 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
119 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
120 #define UCR3_BPEN (1<<0) /* Preset registers enable */
121 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
122 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
123 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
124 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
125 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
126 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
127 #define UCR4_IRSC (1<<5) /* IR special case */
128 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
129 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
130 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
131 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
132 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
133 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
134 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
135 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
136 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
137 #define USR1_RTSS (1<<14) /* RTS pin status */
138 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
139 #define USR1_RTSD (1<<12) /* RTS delta */
140 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
141 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
142 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
143 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
144 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
145 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
146 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
147 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
148 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
149 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
150 #define USR2_IDLE (1<<12) /* Idle condition */
151 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
152 #define USR2_WAKE (1<<7) /* Wake */
153 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
154 #define USR2_TXDC (1<<3) /* Transmitter complete */
155 #define USR2_BRCD (1<<2) /* Break condition */
156 #define USR2_ORE (1<<1) /* Overrun error */
157 #define USR2_RDR (1<<0) /* Recv data ready */
158 #define UTS_FRCPERR (1<<13) /* Force parity error */
159 #define UTS_LOOP (1<<12) /* Loop tx and rx */
160 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
161 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
162 #define UTS_TXFULL (1<<4) /* TxFIFO full */
163 #define UTS_RXFULL (1<<3) /* RxFIFO full */
164 #define UTS_SOFTRST (1<<0) /* Software reset */
165
166 /* We've been assigned a range on the "Low-density serial ports" major */
167 #define SERIAL_IMX_MAJOR 207
168 #define MINOR_START 16
169 #define DEV_NAME "ttymxc"
170 #define MAX_INTERNAL_IRQ MXC_INTERNAL_IRQS
171
172 /*
173 * This determines how often we check the modem status signals
174 * for any change. They generally aren't connected to an IRQ
175 * so we have to poll them. We also check immediately before
176 * filling the TX fifo incase CTS has been dropped.
177 */
178 #define MCTRL_TIMEOUT (250*HZ/1000)
179
180 #define DRIVER_NAME "IMX-uart"
181
182 #define UART_NR 8
183
184 /* i.mx21 type uart runs on all i.mx except i.mx1 */
185 enum imx_uart_type {
186 IMX1_UART,
187 IMX21_UART,
188 };
189
190 /* device type dependent stuff */
191 struct imx_uart_data {
192 unsigned uts_reg;
193 enum imx_uart_type devtype;
194 };
195
196 struct imx_port {
197 struct uart_port port;
198 struct timer_list timer;
199 unsigned int old_status;
200 int txirq,rxirq,rtsirq;
201 unsigned int have_rtscts:1;
202 unsigned int use_irda:1;
203 unsigned int irda_inv_rx:1;
204 unsigned int irda_inv_tx:1;
205 unsigned short trcv_delay; /* transceiver delay */
206 struct clk *clk;
207 struct imx_uart_data *devdata;
208 };
209
210 #ifdef CONFIG_IRDA
211 #define USE_IRDA(sport) ((sport)->use_irda)
212 #else
213 #define USE_IRDA(sport) (0)
214 #endif
215
216 static struct imx_uart_data imx_uart_devdata[] = {
217 [IMX1_UART] = {
218 .uts_reg = IMX1_UTS,
219 .devtype = IMX1_UART,
220 },
221 [IMX21_UART] = {
222 .uts_reg = IMX21_UTS,
223 .devtype = IMX21_UART,
224 },
225 };
226
227 static struct platform_device_id imx_uart_devtype[] = {
228 {
229 .name = "imx1-uart",
230 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
231 }, {
232 .name = "imx21-uart",
233 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
234 }, {
235 /* sentinel */
236 }
237 };
238 MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
239
240 static struct of_device_id imx_uart_dt_ids[] = {
241 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
242 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
243 { /* sentinel */ }
244 };
245 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
246
247 static inline unsigned uts_reg(struct imx_port *sport)
248 {
249 return sport->devdata->uts_reg;
250 }
251
252 static inline int is_imx1_uart(struct imx_port *sport)
253 {
254 return sport->devdata->devtype == IMX1_UART;
255 }
256
257 static inline int is_imx21_uart(struct imx_port *sport)
258 {
259 return sport->devdata->devtype == IMX21_UART;
260 }
261
262 /*
263 * Handle any change of modem status signal since we were last called.
264 */
265 static void imx_mctrl_check(struct imx_port *sport)
266 {
267 unsigned int status, changed;
268
269 status = sport->port.ops->get_mctrl(&sport->port);
270 changed = status ^ sport->old_status;
271
272 if (changed == 0)
273 return;
274
275 sport->old_status = status;
276
277 if (changed & TIOCM_RI)
278 sport->port.icount.rng++;
279 if (changed & TIOCM_DSR)
280 sport->port.icount.dsr++;
281 if (changed & TIOCM_CAR)
282 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
283 if (changed & TIOCM_CTS)
284 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
285
286 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
287 }
288
289 /*
290 * This is our per-port timeout handler, for checking the
291 * modem status signals.
292 */
293 static void imx_timeout(unsigned long data)
294 {
295 struct imx_port *sport = (struct imx_port *)data;
296 unsigned long flags;
297
298 if (sport->port.state) {
299 spin_lock_irqsave(&sport->port.lock, flags);
300 imx_mctrl_check(sport);
301 spin_unlock_irqrestore(&sport->port.lock, flags);
302
303 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
304 }
305 }
306
307 /*
308 * interrupts disabled on entry
309 */
310 static void imx_stop_tx(struct uart_port *port)
311 {
312 struct imx_port *sport = (struct imx_port *)port;
313 unsigned long temp;
314
315 if (USE_IRDA(sport)) {
316 /* half duplex - wait for end of transmission */
317 int n = 256;
318 while ((--n > 0) &&
319 !(readl(sport->port.membase + USR2) & USR2_TXDC)) {
320 udelay(5);
321 barrier();
322 }
323 /*
324 * irda transceiver - wait a bit more to avoid
325 * cutoff, hardware dependent
326 */
327 udelay(sport->trcv_delay);
328
329 /*
330 * half duplex - reactivate receive mode,
331 * flush receive pipe echo crap
332 */
333 if (readl(sport->port.membase + USR2) & USR2_TXDC) {
334 temp = readl(sport->port.membase + UCR1);
335 temp &= ~(UCR1_TXMPTYEN | UCR1_TRDYEN);
336 writel(temp, sport->port.membase + UCR1);
337
338 temp = readl(sport->port.membase + UCR4);
339 temp &= ~(UCR4_TCEN);
340 writel(temp, sport->port.membase + UCR4);
341
342 while (readl(sport->port.membase + URXD0) &
343 URXD_CHARRDY)
344 barrier();
345
346 temp = readl(sport->port.membase + UCR1);
347 temp |= UCR1_RRDYEN;
348 writel(temp, sport->port.membase + UCR1);
349
350 temp = readl(sport->port.membase + UCR4);
351 temp |= UCR4_DREN;
352 writel(temp, sport->port.membase + UCR4);
353 }
354 return;
355 }
356
357 temp = readl(sport->port.membase + UCR1);
358 writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1);
359 }
360
361 /*
362 * interrupts disabled on entry
363 */
364 static void imx_stop_rx(struct uart_port *port)
365 {
366 struct imx_port *sport = (struct imx_port *)port;
367 unsigned long temp;
368
369 temp = readl(sport->port.membase + UCR2);
370 writel(temp &~ UCR2_RXEN, sport->port.membase + UCR2);
371 }
372
373 /*
374 * Set the modem control timer to fire immediately.
375 */
376 static void imx_enable_ms(struct uart_port *port)
377 {
378 struct imx_port *sport = (struct imx_port *)port;
379
380 mod_timer(&sport->timer, jiffies);
381 }
382
383 static inline void imx_transmit_buffer(struct imx_port *sport)
384 {
385 struct circ_buf *xmit = &sport->port.state->xmit;
386
387 while (!uart_circ_empty(xmit) &&
388 !(readl(sport->port.membase + uts_reg(sport))
389 & UTS_TXFULL)) {
390 /* send xmit->buf[xmit->tail]
391 * out the port here */
392 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
393 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
394 sport->port.icount.tx++;
395 }
396
397 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
398 uart_write_wakeup(&sport->port);
399
400 if (uart_circ_empty(xmit))
401 imx_stop_tx(&sport->port);
402 }
403
404 /*
405 * interrupts disabled on entry
406 */
407 static void imx_start_tx(struct uart_port *port)
408 {
409 struct imx_port *sport = (struct imx_port *)port;
410 unsigned long temp;
411
412 if (USE_IRDA(sport)) {
413 /* half duplex in IrDA mode; have to disable receive mode */
414 temp = readl(sport->port.membase + UCR4);
415 temp &= ~(UCR4_DREN);
416 writel(temp, sport->port.membase + UCR4);
417
418 temp = readl(sport->port.membase + UCR1);
419 temp &= ~(UCR1_RRDYEN);
420 writel(temp, sport->port.membase + UCR1);
421 }
422
423 temp = readl(sport->port.membase + UCR1);
424 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
425
426 if (USE_IRDA(sport)) {
427 temp = readl(sport->port.membase + UCR1);
428 temp |= UCR1_TRDYEN;
429 writel(temp, sport->port.membase + UCR1);
430
431 temp = readl(sport->port.membase + UCR4);
432 temp |= UCR4_TCEN;
433 writel(temp, sport->port.membase + UCR4);
434 }
435
436 if (readl(sport->port.membase + uts_reg(sport)) & UTS_TXEMPTY)
437 imx_transmit_buffer(sport);
438 }
439
440 static irqreturn_t imx_rtsint(int irq, void *dev_id)
441 {
442 struct imx_port *sport = dev_id;
443 unsigned int val;
444 unsigned long flags;
445
446 spin_lock_irqsave(&sport->port.lock, flags);
447
448 writel(USR1_RTSD, sport->port.membase + USR1);
449 val = readl(sport->port.membase + USR1) & USR1_RTSS;
450 uart_handle_cts_change(&sport->port, !!val);
451 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
452
453 spin_unlock_irqrestore(&sport->port.lock, flags);
454 return IRQ_HANDLED;
455 }
456
457 static irqreturn_t imx_txint(int irq, void *dev_id)
458 {
459 struct imx_port *sport = dev_id;
460 struct circ_buf *xmit = &sport->port.state->xmit;
461 unsigned long flags;
462
463 spin_lock_irqsave(&sport->port.lock,flags);
464 if (sport->port.x_char)
465 {
466 /* Send next char */
467 writel(sport->port.x_char, sport->port.membase + URTX0);
468 goto out;
469 }
470
471 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
472 imx_stop_tx(&sport->port);
473 goto out;
474 }
475
476 imx_transmit_buffer(sport);
477
478 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
479 uart_write_wakeup(&sport->port);
480
481 out:
482 spin_unlock_irqrestore(&sport->port.lock,flags);
483 return IRQ_HANDLED;
484 }
485
486 static irqreturn_t imx_rxint(int irq, void *dev_id)
487 {
488 struct imx_port *sport = dev_id;
489 unsigned int rx,flg,ignored = 0;
490 struct tty_struct *tty = sport->port.state->port.tty;
491 unsigned long flags, temp;
492
493 spin_lock_irqsave(&sport->port.lock,flags);
494
495 while (readl(sport->port.membase + USR2) & USR2_RDR) {
496 flg = TTY_NORMAL;
497 sport->port.icount.rx++;
498
499 rx = readl(sport->port.membase + URXD0);
500
501 temp = readl(sport->port.membase + USR2);
502 if (temp & USR2_BRCD) {
503 writel(USR2_BRCD, sport->port.membase + USR2);
504 if (uart_handle_break(&sport->port))
505 continue;
506 }
507
508 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
509 continue;
510
511 if (unlikely(rx & URXD_ERR)) {
512 if (rx & URXD_BRK)
513 sport->port.icount.brk++;
514 else if (rx & URXD_PRERR)
515 sport->port.icount.parity++;
516 else if (rx & URXD_FRMERR)
517 sport->port.icount.frame++;
518 if (rx & URXD_OVRRUN)
519 sport->port.icount.overrun++;
520
521 if (rx & sport->port.ignore_status_mask) {
522 if (++ignored > 100)
523 goto out;
524 continue;
525 }
526
527 rx &= sport->port.read_status_mask;
528
529 if (rx & URXD_BRK)
530 flg = TTY_BREAK;
531 else if (rx & URXD_PRERR)
532 flg = TTY_PARITY;
533 else if (rx & URXD_FRMERR)
534 flg = TTY_FRAME;
535 if (rx & URXD_OVRRUN)
536 flg = TTY_OVERRUN;
537
538 #ifdef SUPPORT_SYSRQ
539 sport->port.sysrq = 0;
540 #endif
541 }
542
543 tty_insert_flip_char(tty, rx, flg);
544 }
545
546 out:
547 spin_unlock_irqrestore(&sport->port.lock,flags);
548 tty_flip_buffer_push(tty);
549 return IRQ_HANDLED;
550 }
551
552 static irqreturn_t imx_int(int irq, void *dev_id)
553 {
554 struct imx_port *sport = dev_id;
555 unsigned int sts;
556
557 sts = readl(sport->port.membase + USR1);
558
559 if (sts & USR1_RRDY)
560 imx_rxint(irq, dev_id);
561
562 if (sts & USR1_TRDY &&
563 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN)
564 imx_txint(irq, dev_id);
565
566 if (sts & USR1_RTSD)
567 imx_rtsint(irq, dev_id);
568
569 if (sts & USR1_AWAKE)
570 writel(USR1_AWAKE, sport->port.membase + USR1);
571
572 return IRQ_HANDLED;
573 }
574
575 /*
576 * Return TIOCSER_TEMT when transmitter is not busy.
577 */
578 static unsigned int imx_tx_empty(struct uart_port *port)
579 {
580 struct imx_port *sport = (struct imx_port *)port;
581
582 return (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
583 }
584
585 /*
586 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
587 */
588 static unsigned int imx_get_mctrl(struct uart_port *port)
589 {
590 struct imx_port *sport = (struct imx_port *)port;
591 unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
592
593 if (readl(sport->port.membase + USR1) & USR1_RTSS)
594 tmp |= TIOCM_CTS;
595
596 if (readl(sport->port.membase + UCR2) & UCR2_CTS)
597 tmp |= TIOCM_RTS;
598
599 return tmp;
600 }
601
602 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
603 {
604 struct imx_port *sport = (struct imx_port *)port;
605 unsigned long temp;
606
607 temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS;
608
609 if (mctrl & TIOCM_RTS)
610 temp |= UCR2_CTS;
611
612 writel(temp, sport->port.membase + UCR2);
613 }
614
615 /*
616 * Interrupts always disabled.
617 */
618 static void imx_break_ctl(struct uart_port *port, int break_state)
619 {
620 struct imx_port *sport = (struct imx_port *)port;
621 unsigned long flags, temp;
622
623 spin_lock_irqsave(&sport->port.lock, flags);
624
625 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
626
627 if ( break_state != 0 )
628 temp |= UCR1_SNDBRK;
629
630 writel(temp, sport->port.membase + UCR1);
631
632 spin_unlock_irqrestore(&sport->port.lock, flags);
633 }
634
635 #define TXTL 2 /* reset default */
636 #define RXTL 1 /* reset default */
637
638 static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
639 {
640 unsigned int val;
641 unsigned int ufcr_rfdiv;
642
643 /* set receiver / transmitter trigger level.
644 * RFDIV is set such way to satisfy requested uartclk value
645 */
646 val = TXTL << 10 | RXTL;
647 ufcr_rfdiv = (clk_get_rate(sport->clk) + sport->port.uartclk / 2)
648 / sport->port.uartclk;
649
650 if(!ufcr_rfdiv)
651 ufcr_rfdiv = 1;
652
653 val |= UFCR_RFDIV_REG(ufcr_rfdiv);
654
655 writel(val, sport->port.membase + UFCR);
656
657 return 0;
658 }
659
660 /* half the RX buffer size */
661 #define CTSTL 16
662
663 static int imx_startup(struct uart_port *port)
664 {
665 struct imx_port *sport = (struct imx_port *)port;
666 int retval;
667 unsigned long flags, temp;
668
669 imx_setup_ufcr(sport, 0);
670
671 /* disable the DREN bit (Data Ready interrupt enable) before
672 * requesting IRQs
673 */
674 temp = readl(sport->port.membase + UCR4);
675
676 if (USE_IRDA(sport))
677 temp |= UCR4_IRSC;
678
679 /* set the trigger level for CTS */
680 temp &= ~(UCR4_CTSTL_MASK<< UCR4_CTSTL_SHF);
681 temp |= CTSTL<< UCR4_CTSTL_SHF;
682
683 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
684
685 if (USE_IRDA(sport)) {
686 /* reset fifo's and state machines */
687 int i = 100;
688 temp = readl(sport->port.membase + UCR2);
689 temp &= ~UCR2_SRST;
690 writel(temp, sport->port.membase + UCR2);
691 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) &&
692 (--i > 0)) {
693 udelay(1);
694 }
695 }
696
697 /*
698 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
699 * chips only have one interrupt.
700 */
701 if (sport->txirq > 0) {
702 retval = request_irq(sport->rxirq, imx_rxint, 0,
703 DRIVER_NAME, sport);
704 if (retval)
705 goto error_out1;
706
707 retval = request_irq(sport->txirq, imx_txint, 0,
708 DRIVER_NAME, sport);
709 if (retval)
710 goto error_out2;
711
712 /* do not use RTS IRQ on IrDA */
713 if (!USE_IRDA(sport)) {
714 retval = request_irq(sport->rtsirq, imx_rtsint,
715 (sport->rtsirq < MAX_INTERNAL_IRQ) ? 0 :
716 IRQF_TRIGGER_FALLING |
717 IRQF_TRIGGER_RISING,
718 DRIVER_NAME, sport);
719 if (retval)
720 goto error_out3;
721 }
722 } else {
723 retval = request_irq(sport->port.irq, imx_int, 0,
724 DRIVER_NAME, sport);
725 if (retval) {
726 free_irq(sport->port.irq, sport);
727 goto error_out1;
728 }
729 }
730
731 /*
732 * Finally, clear and enable interrupts
733 */
734 writel(USR1_RTSD, sport->port.membase + USR1);
735
736 temp = readl(sport->port.membase + UCR1);
737 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
738
739 if (USE_IRDA(sport)) {
740 temp |= UCR1_IREN;
741 temp &= ~(UCR1_RTSDEN);
742 }
743
744 writel(temp, sport->port.membase + UCR1);
745
746 temp = readl(sport->port.membase + UCR2);
747 temp |= (UCR2_RXEN | UCR2_TXEN);
748 writel(temp, sport->port.membase + UCR2);
749
750 if (USE_IRDA(sport)) {
751 /* clear RX-FIFO */
752 int i = 64;
753 while ((--i > 0) &&
754 (readl(sport->port.membase + URXD0) & URXD_CHARRDY)) {
755 barrier();
756 }
757 }
758
759 if (is_imx21_uart(sport)) {
760 temp = readl(sport->port.membase + UCR3);
761 temp |= IMX21_UCR3_RXDMUXSEL;
762 writel(temp, sport->port.membase + UCR3);
763 }
764
765 if (USE_IRDA(sport)) {
766 temp = readl(sport->port.membase + UCR4);
767 if (sport->irda_inv_rx)
768 temp |= UCR4_INVR;
769 else
770 temp &= ~(UCR4_INVR);
771 writel(temp | UCR4_DREN, sport->port.membase + UCR4);
772
773 temp = readl(sport->port.membase + UCR3);
774 if (sport->irda_inv_tx)
775 temp |= UCR3_INVT;
776 else
777 temp &= ~(UCR3_INVT);
778 writel(temp, sport->port.membase + UCR3);
779 }
780
781 /*
782 * Enable modem status interrupts
783 */
784 spin_lock_irqsave(&sport->port.lock,flags);
785 imx_enable_ms(&sport->port);
786 spin_unlock_irqrestore(&sport->port.lock,flags);
787
788 if (USE_IRDA(sport)) {
789 struct imxuart_platform_data *pdata;
790 pdata = sport->port.dev->platform_data;
791 sport->irda_inv_rx = pdata->irda_inv_rx;
792 sport->irda_inv_tx = pdata->irda_inv_tx;
793 sport->trcv_delay = pdata->transceiver_delay;
794 if (pdata->irda_enable)
795 pdata->irda_enable(1);
796 }
797
798 return 0;
799
800 error_out3:
801 if (sport->txirq)
802 free_irq(sport->txirq, sport);
803 error_out2:
804 if (sport->rxirq)
805 free_irq(sport->rxirq, sport);
806 error_out1:
807 return retval;
808 }
809
810 static void imx_shutdown(struct uart_port *port)
811 {
812 struct imx_port *sport = (struct imx_port *)port;
813 unsigned long temp;
814
815 temp = readl(sport->port.membase + UCR2);
816 temp &= ~(UCR2_TXEN);
817 writel(temp, sport->port.membase + UCR2);
818
819 if (USE_IRDA(sport)) {
820 struct imxuart_platform_data *pdata;
821 pdata = sport->port.dev->platform_data;
822 if (pdata->irda_enable)
823 pdata->irda_enable(0);
824 }
825
826 /*
827 * Stop our timer.
828 */
829 del_timer_sync(&sport->timer);
830
831 /*
832 * Free the interrupts
833 */
834 if (sport->txirq > 0) {
835 if (!USE_IRDA(sport))
836 free_irq(sport->rtsirq, sport);
837 free_irq(sport->txirq, sport);
838 free_irq(sport->rxirq, sport);
839 } else
840 free_irq(sport->port.irq, sport);
841
842 /*
843 * Disable all interrupts, port and break condition.
844 */
845
846 temp = readl(sport->port.membase + UCR1);
847 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
848 if (USE_IRDA(sport))
849 temp &= ~(UCR1_IREN);
850
851 writel(temp, sport->port.membase + UCR1);
852 }
853
854 static void
855 imx_set_termios(struct uart_port *port, struct ktermios *termios,
856 struct ktermios *old)
857 {
858 struct imx_port *sport = (struct imx_port *)port;
859 unsigned long flags;
860 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot;
861 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
862 unsigned int div, ufcr;
863 unsigned long num, denom;
864 uint64_t tdiv64;
865
866 /*
867 * If we don't support modem control lines, don't allow
868 * these to be set.
869 */
870 if (0) {
871 termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
872 termios->c_cflag |= CLOCAL;
873 }
874
875 /*
876 * We only support CS7 and CS8.
877 */
878 while ((termios->c_cflag & CSIZE) != CS7 &&
879 (termios->c_cflag & CSIZE) != CS8) {
880 termios->c_cflag &= ~CSIZE;
881 termios->c_cflag |= old_csize;
882 old_csize = CS8;
883 }
884
885 if ((termios->c_cflag & CSIZE) == CS8)
886 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
887 else
888 ucr2 = UCR2_SRST | UCR2_IRTS;
889
890 if (termios->c_cflag & CRTSCTS) {
891 if( sport->have_rtscts ) {
892 ucr2 &= ~UCR2_IRTS;
893 ucr2 |= UCR2_CTSC;
894 } else {
895 termios->c_cflag &= ~CRTSCTS;
896 }
897 }
898
899 if (termios->c_cflag & CSTOPB)
900 ucr2 |= UCR2_STPB;
901 if (termios->c_cflag & PARENB) {
902 ucr2 |= UCR2_PREN;
903 if (termios->c_cflag & PARODD)
904 ucr2 |= UCR2_PROE;
905 }
906
907 /*
908 * Ask the core to calculate the divisor for us.
909 */
910 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
911 quot = uart_get_divisor(port, baud);
912
913 spin_lock_irqsave(&sport->port.lock, flags);
914
915 sport->port.read_status_mask = 0;
916 if (termios->c_iflag & INPCK)
917 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
918 if (termios->c_iflag & (BRKINT | PARMRK))
919 sport->port.read_status_mask |= URXD_BRK;
920
921 /*
922 * Characters to ignore
923 */
924 sport->port.ignore_status_mask = 0;
925 if (termios->c_iflag & IGNPAR)
926 sport->port.ignore_status_mask |= URXD_PRERR;
927 if (termios->c_iflag & IGNBRK) {
928 sport->port.ignore_status_mask |= URXD_BRK;
929 /*
930 * If we're ignoring parity and break indicators,
931 * ignore overruns too (for real raw support).
932 */
933 if (termios->c_iflag & IGNPAR)
934 sport->port.ignore_status_mask |= URXD_OVRRUN;
935 }
936
937 del_timer_sync(&sport->timer);
938
939 /*
940 * Update the per-port timeout.
941 */
942 uart_update_timeout(port, termios->c_cflag, baud);
943
944 /*
945 * disable interrupts and drain transmitter
946 */
947 old_ucr1 = readl(sport->port.membase + UCR1);
948 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
949 sport->port.membase + UCR1);
950
951 while ( !(readl(sport->port.membase + USR2) & USR2_TXDC))
952 barrier();
953
954 /* then, disable everything */
955 old_txrxen = readl(sport->port.membase + UCR2);
956 writel(old_txrxen & ~( UCR2_TXEN | UCR2_RXEN),
957 sport->port.membase + UCR2);
958 old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
959
960 if (USE_IRDA(sport)) {
961 /*
962 * use maximum available submodule frequency to
963 * avoid missing short pulses due to low sampling rate
964 */
965 div = 1;
966 } else {
967 div = sport->port.uartclk / (baud * 16);
968 if (div > 7)
969 div = 7;
970 if (!div)
971 div = 1;
972 }
973
974 rational_best_approximation(16 * div * baud, sport->port.uartclk,
975 1 << 16, 1 << 16, &num, &denom);
976
977 tdiv64 = sport->port.uartclk;
978 tdiv64 *= num;
979 do_div(tdiv64, denom * 16 * div);
980 tty_termios_encode_baud_rate(termios,
981 (speed_t)tdiv64, (speed_t)tdiv64);
982
983 num -= 1;
984 denom -= 1;
985
986 ufcr = readl(sport->port.membase + UFCR);
987 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
988 writel(ufcr, sport->port.membase + UFCR);
989
990 writel(num, sport->port.membase + UBIR);
991 writel(denom, sport->port.membase + UBMR);
992
993 if (is_imx21_uart(sport))
994 writel(sport->port.uartclk / div / 1000,
995 sport->port.membase + IMX21_ONEMS);
996
997 writel(old_ucr1, sport->port.membase + UCR1);
998
999 /* set the parity, stop bits and data size */
1000 writel(ucr2 | old_txrxen, sport->port.membase + UCR2);
1001
1002 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1003 imx_enable_ms(&sport->port);
1004
1005 spin_unlock_irqrestore(&sport->port.lock, flags);
1006 }
1007
1008 static const char *imx_type(struct uart_port *port)
1009 {
1010 struct imx_port *sport = (struct imx_port *)port;
1011
1012 return sport->port.type == PORT_IMX ? "IMX" : NULL;
1013 }
1014
1015 /*
1016 * Release the memory region(s) being used by 'port'.
1017 */
1018 static void imx_release_port(struct uart_port *port)
1019 {
1020 struct platform_device *pdev = to_platform_device(port->dev);
1021 struct resource *mmres;
1022
1023 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1024 release_mem_region(mmres->start, resource_size(mmres));
1025 }
1026
1027 /*
1028 * Request the memory region(s) being used by 'port'.
1029 */
1030 static int imx_request_port(struct uart_port *port)
1031 {
1032 struct platform_device *pdev = to_platform_device(port->dev);
1033 struct resource *mmres;
1034 void *ret;
1035
1036 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1037 if (!mmres)
1038 return -ENODEV;
1039
1040 ret = request_mem_region(mmres->start, resource_size(mmres), "imx-uart");
1041
1042 return ret ? 0 : -EBUSY;
1043 }
1044
1045 /*
1046 * Configure/autoconfigure the port.
1047 */
1048 static void imx_config_port(struct uart_port *port, int flags)
1049 {
1050 struct imx_port *sport = (struct imx_port *)port;
1051
1052 if (flags & UART_CONFIG_TYPE &&
1053 imx_request_port(&sport->port) == 0)
1054 sport->port.type = PORT_IMX;
1055 }
1056
1057 /*
1058 * Verify the new serial_struct (for TIOCSSERIAL).
1059 * The only change we allow are to the flags and type, and
1060 * even then only between PORT_IMX and PORT_UNKNOWN
1061 */
1062 static int
1063 imx_verify_port(struct uart_port *port, struct serial_struct *ser)
1064 {
1065 struct imx_port *sport = (struct imx_port *)port;
1066 int ret = 0;
1067
1068 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1069 ret = -EINVAL;
1070 if (sport->port.irq != ser->irq)
1071 ret = -EINVAL;
1072 if (ser->io_type != UPIO_MEM)
1073 ret = -EINVAL;
1074 if (sport->port.uartclk / 16 != ser->baud_base)
1075 ret = -EINVAL;
1076 if ((void *)sport->port.mapbase != ser->iomem_base)
1077 ret = -EINVAL;
1078 if (sport->port.iobase != ser->port)
1079 ret = -EINVAL;
1080 if (ser->hub6 != 0)
1081 ret = -EINVAL;
1082 return ret;
1083 }
1084
1085 static struct uart_ops imx_pops = {
1086 .tx_empty = imx_tx_empty,
1087 .set_mctrl = imx_set_mctrl,
1088 .get_mctrl = imx_get_mctrl,
1089 .stop_tx = imx_stop_tx,
1090 .start_tx = imx_start_tx,
1091 .stop_rx = imx_stop_rx,
1092 .enable_ms = imx_enable_ms,
1093 .break_ctl = imx_break_ctl,
1094 .startup = imx_startup,
1095 .shutdown = imx_shutdown,
1096 .set_termios = imx_set_termios,
1097 .type = imx_type,
1098 .release_port = imx_release_port,
1099 .request_port = imx_request_port,
1100 .config_port = imx_config_port,
1101 .verify_port = imx_verify_port,
1102 };
1103
1104 static struct imx_port *imx_ports[UART_NR];
1105
1106 #ifdef CONFIG_SERIAL_IMX_CONSOLE
1107 static void imx_console_putchar(struct uart_port *port, int ch)
1108 {
1109 struct imx_port *sport = (struct imx_port *)port;
1110
1111 while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)
1112 barrier();
1113
1114 writel(ch, sport->port.membase + URTX0);
1115 }
1116
1117 /*
1118 * Interrupts are disabled on entering
1119 */
1120 static void
1121 imx_console_write(struct console *co, const char *s, unsigned int count)
1122 {
1123 struct imx_port *sport = imx_ports[co->index];
1124 unsigned int old_ucr1, old_ucr2, ucr1;
1125
1126 /*
1127 * First, save UCR1/2 and then disable interrupts
1128 */
1129 ucr1 = old_ucr1 = readl(sport->port.membase + UCR1);
1130 old_ucr2 = readl(sport->port.membase + UCR2);
1131
1132 if (is_imx1_uart(sport))
1133 ucr1 |= IMX1_UCR1_UARTCLKEN;
1134 ucr1 |= UCR1_UARTEN;
1135 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1136
1137 writel(ucr1, sport->port.membase + UCR1);
1138
1139 writel(old_ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
1140
1141 uart_console_write(&sport->port, s, count, imx_console_putchar);
1142
1143 /*
1144 * Finally, wait for transmitter to become empty
1145 * and restore UCR1/2
1146 */
1147 while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
1148
1149 writel(old_ucr1, sport->port.membase + UCR1);
1150 writel(old_ucr2, sport->port.membase + UCR2);
1151 }
1152
1153 /*
1154 * If the port was already initialised (eg, by a boot loader),
1155 * try to determine the current setup.
1156 */
1157 static void __init
1158 imx_console_get_options(struct imx_port *sport, int *baud,
1159 int *parity, int *bits)
1160 {
1161
1162 if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {
1163 /* ok, the port was enabled */
1164 unsigned int ucr2, ubir,ubmr, uartclk;
1165 unsigned int baud_raw;
1166 unsigned int ucfr_rfdiv;
1167
1168 ucr2 = readl(sport->port.membase + UCR2);
1169
1170 *parity = 'n';
1171 if (ucr2 & UCR2_PREN) {
1172 if (ucr2 & UCR2_PROE)
1173 *parity = 'o';
1174 else
1175 *parity = 'e';
1176 }
1177
1178 if (ucr2 & UCR2_WS)
1179 *bits = 8;
1180 else
1181 *bits = 7;
1182
1183 ubir = readl(sport->port.membase + UBIR) & 0xffff;
1184 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
1185
1186 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
1187 if (ucfr_rfdiv == 6)
1188 ucfr_rfdiv = 7;
1189 else
1190 ucfr_rfdiv = 6 - ucfr_rfdiv;
1191
1192 uartclk = clk_get_rate(sport->clk);
1193 uartclk /= ucfr_rfdiv;
1194
1195 { /*
1196 * The next code provides exact computation of
1197 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
1198 * without need of float support or long long division,
1199 * which would be required to prevent 32bit arithmetic overflow
1200 */
1201 unsigned int mul = ubir + 1;
1202 unsigned int div = 16 * (ubmr + 1);
1203 unsigned int rem = uartclk % div;
1204
1205 baud_raw = (uartclk / div) * mul;
1206 baud_raw += (rem * mul + div / 2) / div;
1207 *baud = (baud_raw + 50) / 100 * 100;
1208 }
1209
1210 if(*baud != baud_raw)
1211 printk(KERN_INFO "Serial: Console IMX rounded baud rate from %d to %d\n",
1212 baud_raw, *baud);
1213 }
1214 }
1215
1216 static int __init
1217 imx_console_setup(struct console *co, char *options)
1218 {
1219 struct imx_port *sport;
1220 int baud = 9600;
1221 int bits = 8;
1222 int parity = 'n';
1223 int flow = 'n';
1224
1225 /*
1226 * Check whether an invalid uart number has been specified, and
1227 * if so, search for the first available port that does have
1228 * console support.
1229 */
1230 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1231 co->index = 0;
1232 sport = imx_ports[co->index];
1233 if(sport == NULL)
1234 return -ENODEV;
1235
1236 if (options)
1237 uart_parse_options(options, &baud, &parity, &bits, &flow);
1238 else
1239 imx_console_get_options(sport, &baud, &parity, &bits);
1240
1241 imx_setup_ufcr(sport, 0);
1242
1243 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
1244 }
1245
1246 static struct uart_driver imx_reg;
1247 static struct console imx_console = {
1248 .name = DEV_NAME,
1249 .write = imx_console_write,
1250 .device = uart_console_device,
1251 .setup = imx_console_setup,
1252 .flags = CON_PRINTBUFFER,
1253 .index = -1,
1254 .data = &imx_reg,
1255 };
1256
1257 #define IMX_CONSOLE &imx_console
1258 #else
1259 #define IMX_CONSOLE NULL
1260 #endif
1261
1262 static struct uart_driver imx_reg = {
1263 .owner = THIS_MODULE,
1264 .driver_name = DRIVER_NAME,
1265 .dev_name = DEV_NAME,
1266 .major = SERIAL_IMX_MAJOR,
1267 .minor = MINOR_START,
1268 .nr = ARRAY_SIZE(imx_ports),
1269 .cons = IMX_CONSOLE,
1270 };
1271
1272 static int serial_imx_suspend(struct platform_device *dev, pm_message_t state)
1273 {
1274 struct imx_port *sport = platform_get_drvdata(dev);
1275 unsigned int val;
1276
1277 /* enable wakeup from i.MX UART */
1278 val = readl(sport->port.membase + UCR3);
1279 val |= UCR3_AWAKEN;
1280 writel(val, sport->port.membase + UCR3);
1281
1282 if (sport)
1283 uart_suspend_port(&imx_reg, &sport->port);
1284
1285 return 0;
1286 }
1287
1288 static int serial_imx_resume(struct platform_device *dev)
1289 {
1290 struct imx_port *sport = platform_get_drvdata(dev);
1291 unsigned int val;
1292
1293 /* disable wakeup from i.MX UART */
1294 val = readl(sport->port.membase + UCR3);
1295 val &= ~UCR3_AWAKEN;
1296 writel(val, sport->port.membase + UCR3);
1297
1298 if (sport)
1299 uart_resume_port(&imx_reg, &sport->port);
1300
1301 return 0;
1302 }
1303
1304 #ifdef CONFIG_OF
1305 static int serial_imx_probe_dt(struct imx_port *sport,
1306 struct platform_device *pdev)
1307 {
1308 struct device_node *np = pdev->dev.of_node;
1309 const struct of_device_id *of_id =
1310 of_match_device(imx_uart_dt_ids, &pdev->dev);
1311 int ret;
1312
1313 if (!np)
1314 return -ENODEV;
1315
1316 ret = of_alias_get_id(np, "serial");
1317 if (ret < 0) {
1318 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
1319 return ret;
1320 }
1321 sport->port.line = ret;
1322
1323 if (of_get_property(np, "fsl,uart-has-rtscts", NULL))
1324 sport->have_rtscts = 1;
1325
1326 if (of_get_property(np, "fsl,irda-mode", NULL))
1327 sport->use_irda = 1;
1328
1329 sport->devdata = of_id->data;
1330
1331 return 0;
1332 }
1333 #else
1334 static inline int serial_imx_probe_dt(struct imx_port *sport,
1335 struct platform_device *pdev)
1336 {
1337 return -ENODEV;
1338 }
1339 #endif
1340
1341 static void serial_imx_probe_pdata(struct imx_port *sport,
1342 struct platform_device *pdev)
1343 {
1344 struct imxuart_platform_data *pdata = pdev->dev.platform_data;
1345
1346 sport->port.line = pdev->id;
1347 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data;
1348
1349 if (!pdata)
1350 return;
1351
1352 if (pdata->flags & IMXUART_HAVE_RTSCTS)
1353 sport->have_rtscts = 1;
1354
1355 if (pdata->flags & IMXUART_IRDA)
1356 sport->use_irda = 1;
1357 }
1358
1359 static int serial_imx_probe(struct platform_device *pdev)
1360 {
1361 struct imx_port *sport;
1362 struct imxuart_platform_data *pdata;
1363 void __iomem *base;
1364 int ret = 0;
1365 struct resource *res;
1366
1367 sport = kzalloc(sizeof(*sport), GFP_KERNEL);
1368 if (!sport)
1369 return -ENOMEM;
1370
1371 ret = serial_imx_probe_dt(sport, pdev);
1372 if (ret == -ENODEV)
1373 serial_imx_probe_pdata(sport, pdev);
1374
1375 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1376 if (!res) {
1377 ret = -ENODEV;
1378 goto free;
1379 }
1380
1381 base = ioremap(res->start, PAGE_SIZE);
1382 if (!base) {
1383 ret = -ENOMEM;
1384 goto free;
1385 }
1386
1387 sport->port.dev = &pdev->dev;
1388 sport->port.mapbase = res->start;
1389 sport->port.membase = base;
1390 sport->port.type = PORT_IMX,
1391 sport->port.iotype = UPIO_MEM;
1392 sport->port.irq = platform_get_irq(pdev, 0);
1393 sport->rxirq = platform_get_irq(pdev, 0);
1394 sport->txirq = platform_get_irq(pdev, 1);
1395 sport->rtsirq = platform_get_irq(pdev, 2);
1396 sport->port.fifosize = 32;
1397 sport->port.ops = &imx_pops;
1398 sport->port.flags = UPF_BOOT_AUTOCONF;
1399 init_timer(&sport->timer);
1400 sport->timer.function = imx_timeout;
1401 sport->timer.data = (unsigned long)sport;
1402
1403 sport->clk = clk_get(&pdev->dev, "uart");
1404 if (IS_ERR(sport->clk)) {
1405 ret = PTR_ERR(sport->clk);
1406 goto unmap;
1407 }
1408 clk_enable(sport->clk);
1409
1410 sport->port.uartclk = clk_get_rate(sport->clk);
1411
1412 imx_ports[sport->port.line] = sport;
1413
1414 pdata = pdev->dev.platform_data;
1415 if (pdata && pdata->init) {
1416 ret = pdata->init(pdev);
1417 if (ret)
1418 goto clkput;
1419 }
1420
1421 ret = uart_add_one_port(&imx_reg, &sport->port);
1422 if (ret)
1423 goto deinit;
1424 platform_set_drvdata(pdev, &sport->port);
1425
1426 return 0;
1427 deinit:
1428 if (pdata && pdata->exit)
1429 pdata->exit(pdev);
1430 clkput:
1431 clk_put(sport->clk);
1432 clk_disable(sport->clk);
1433 unmap:
1434 iounmap(sport->port.membase);
1435 free:
1436 kfree(sport);
1437
1438 return ret;
1439 }
1440
1441 static int serial_imx_remove(struct platform_device *pdev)
1442 {
1443 struct imxuart_platform_data *pdata;
1444 struct imx_port *sport = platform_get_drvdata(pdev);
1445
1446 pdata = pdev->dev.platform_data;
1447
1448 platform_set_drvdata(pdev, NULL);
1449
1450 if (sport) {
1451 uart_remove_one_port(&imx_reg, &sport->port);
1452 clk_put(sport->clk);
1453 }
1454
1455 clk_disable(sport->clk);
1456
1457 if (pdata && pdata->exit)
1458 pdata->exit(pdev);
1459
1460 iounmap(sport->port.membase);
1461 kfree(sport);
1462
1463 return 0;
1464 }
1465
1466 static struct platform_driver serial_imx_driver = {
1467 .probe = serial_imx_probe,
1468 .remove = serial_imx_remove,
1469
1470 .suspend = serial_imx_suspend,
1471 .resume = serial_imx_resume,
1472 .id_table = imx_uart_devtype,
1473 .driver = {
1474 .name = "imx-uart",
1475 .owner = THIS_MODULE,
1476 .of_match_table = imx_uart_dt_ids,
1477 },
1478 };
1479
1480 static int __init imx_serial_init(void)
1481 {
1482 int ret;
1483
1484 printk(KERN_INFO "Serial: IMX driver\n");
1485
1486 ret = uart_register_driver(&imx_reg);
1487 if (ret)
1488 return ret;
1489
1490 ret = platform_driver_register(&serial_imx_driver);
1491 if (ret != 0)
1492 uart_unregister_driver(&imx_reg);
1493
1494 return ret;
1495 }
1496
1497 static void __exit imx_serial_exit(void)
1498 {
1499 platform_driver_unregister(&serial_imx_driver);
1500 uart_unregister_driver(&imx_reg);
1501 }
1502
1503 module_init(imx_serial_init);
1504 module_exit(imx_serial_exit);
1505
1506 MODULE_AUTHOR("Sascha Hauer");
1507 MODULE_DESCRIPTION("IMX generic serial port driver");
1508 MODULE_LICENSE("GPL");
1509 MODULE_ALIAS("platform:imx-uart");
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