3 * Copyright (c) 2002-2007 Xilinx Inc.
4 * Copyright (c) 2009-2010 Intel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 * This code was implemented by Mocean Laboratories AB when porting linux
21 * to the automotive development board Russellville. The copyright holder
22 * as seen in the header is Intel corporation.
23 * Mocean Laboratories forked off the GNU/Linux platform work into a
24 * separate company called Pelagicore AB, which committed the code to the
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/init.h>
34 #include <linux/errno.h>
35 #include <linux/delay.h>
36 #include <linux/platform_device.h>
37 #include <linux/i2c.h>
38 #include <linux/interrupt.h>
39 #include <linux/wait.h>
40 #include <linux/i2c-xiic.h>
42 #include <linux/slab.h>
43 #include <linux/of_i2c.h>
45 #define DRIVER_NAME "xiic-i2c"
47 enum xilinx_i2c_state
{
54 * struct xiic_i2c - Internal representation of the XIIC I2C bus
55 * @base: Memory base of the HW registers
56 * @wait: Wait queue for callers
57 * @adap: Kernel adapter representation
58 * @tx_msg: Messages from above to be sent
59 * @lock: Mutual exclusion
60 * @tx_pos: Current pos in TX message
61 * @nmsgs: Number of messages in tx_msg
63 * @rx_msg: Current RX message
64 * @rx_pos: Position within current RX message
68 wait_queue_head_t wait
;
69 struct i2c_adapter adap
;
70 struct i2c_msg
*tx_msg
;
74 enum xilinx_i2c_state state
;
75 struct i2c_msg
*rx_msg
;
80 #define XIIC_MSB_OFFSET 0
81 #define XIIC_REG_OFFSET (0x100+XIIC_MSB_OFFSET)
84 * Register offsets in bytes from RegisterBase. Three is added to the
85 * base offset to access LSB (IBM style) of the word
87 #define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */
88 #define XIIC_SR_REG_OFFSET (0x04+XIIC_REG_OFFSET) /* Status Register */
89 #define XIIC_DTR_REG_OFFSET (0x08+XIIC_REG_OFFSET) /* Data Tx Register */
90 #define XIIC_DRR_REG_OFFSET (0x0C+XIIC_REG_OFFSET) /* Data Rx Register */
91 #define XIIC_ADR_REG_OFFSET (0x10+XIIC_REG_OFFSET) /* Address Register */
92 #define XIIC_TFO_REG_OFFSET (0x14+XIIC_REG_OFFSET) /* Tx FIFO Occupancy */
93 #define XIIC_RFO_REG_OFFSET (0x18+XIIC_REG_OFFSET) /* Rx FIFO Occupancy */
94 #define XIIC_TBA_REG_OFFSET (0x1C+XIIC_REG_OFFSET) /* 10 Bit Address reg */
95 #define XIIC_RFD_REG_OFFSET (0x20+XIIC_REG_OFFSET) /* Rx FIFO Depth reg */
96 #define XIIC_GPO_REG_OFFSET (0x24+XIIC_REG_OFFSET) /* Output Register */
98 /* Control Register masks */
99 #define XIIC_CR_ENABLE_DEVICE_MASK 0x01 /* Device enable = 1 */
100 #define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */
101 #define XIIC_CR_MSMS_MASK 0x04 /* Master starts Txing=1 */
102 #define XIIC_CR_DIR_IS_TX_MASK 0x08 /* Dir of tx. Txing=1 */
103 #define XIIC_CR_NO_ACK_MASK 0x10 /* Tx Ack. NO ack = 1 */
104 #define XIIC_CR_REPEATED_START_MASK 0x20 /* Repeated start = 1 */
105 #define XIIC_CR_GENERAL_CALL_MASK 0x40 /* Gen Call enabled = 1 */
107 /* Status Register masks */
108 #define XIIC_SR_GEN_CALL_MASK 0x01 /* 1=a mstr issued a GC */
109 #define XIIC_SR_ADDR_AS_SLAVE_MASK 0x02 /* 1=when addr as slave */
110 #define XIIC_SR_BUS_BUSY_MASK 0x04 /* 1 = bus is busy */
111 #define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */
112 #define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */
113 #define XIIC_SR_RX_FIFO_FULL_MASK 0x20 /* 1 = Rx FIFO full */
114 #define XIIC_SR_RX_FIFO_EMPTY_MASK 0x40 /* 1 = Rx FIFO empty */
115 #define XIIC_SR_TX_FIFO_EMPTY_MASK 0x80 /* 1 = Tx FIFO empty */
117 /* Interrupt Status Register masks Interrupt occurs when... */
118 #define XIIC_INTR_ARB_LOST_MASK 0x01 /* 1 = arbitration lost */
119 #define XIIC_INTR_TX_ERROR_MASK 0x02 /* 1=Tx error/msg complete */
120 #define XIIC_INTR_TX_EMPTY_MASK 0x04 /* 1 = Tx FIFO/reg empty */
121 #define XIIC_INTR_RX_FULL_MASK 0x08 /* 1=Rx FIFO/reg=OCY level */
122 #define XIIC_INTR_BNB_MASK 0x10 /* 1 = Bus not busy */
123 #define XIIC_INTR_AAS_MASK 0x20 /* 1 = when addr as slave */
124 #define XIIC_INTR_NAAS_MASK 0x40 /* 1 = not addr as slave */
125 #define XIIC_INTR_TX_HALF_MASK 0x80 /* 1 = TX FIFO half empty */
127 /* The following constants specify the depth of the FIFOs */
128 #define IIC_RX_FIFO_DEPTH 16 /* Rx fifo capacity */
129 #define IIC_TX_FIFO_DEPTH 16 /* Tx fifo capacity */
131 /* The following constants specify groups of interrupts that are typically
132 * enabled or disables at the same time
134 #define XIIC_TX_INTERRUPTS \
135 (XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)
137 #define XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS)
139 /* The following constants are used with the following macros to specify the
140 * operation, a read or write operation.
142 #define XIIC_READ_OPERATION 1
143 #define XIIC_WRITE_OPERATION 0
146 * Tx Fifo upper bit masks.
148 #define XIIC_TX_DYN_START_MASK 0x0100 /* 1 = Set dynamic start */
149 #define XIIC_TX_DYN_STOP_MASK 0x0200 /* 1 = Set dynamic stop */
152 * The following constants define the register offsets for the Interrupt
153 * registers. There are some holes in the memory map for reserved addresses
154 * to allow other registers to be added and still match the memory map of the
155 * interrupt controller registers
157 #define XIIC_DGIER_OFFSET 0x1C /* Device Global Interrupt Enable Register */
158 #define XIIC_IISR_OFFSET 0x20 /* Interrupt Status Register */
159 #define XIIC_IIER_OFFSET 0x28 /* Interrupt Enable Register */
160 #define XIIC_RESETR_OFFSET 0x40 /* Reset Register */
162 #define XIIC_RESET_MASK 0xAUL
165 * The following constant is used for the device global interrupt enable
166 * register, to enable all interrupts for the device, this is the only bit
169 #define XIIC_GINTR_ENABLE_MASK 0x80000000UL
171 #define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos)
172 #define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos)
174 static void xiic_start_xfer(struct xiic_i2c
*i2c
);
175 static void __xiic_start_xfer(struct xiic_i2c
*i2c
);
177 static inline void xiic_setreg8(struct xiic_i2c
*i2c
, int reg
, u8 value
)
179 iowrite8(value
, i2c
->base
+ reg
);
182 static inline u8
xiic_getreg8(struct xiic_i2c
*i2c
, int reg
)
184 return ioread8(i2c
->base
+ reg
);
187 static inline void xiic_setreg16(struct xiic_i2c
*i2c
, int reg
, u16 value
)
189 iowrite16(value
, i2c
->base
+ reg
);
192 static inline void xiic_setreg32(struct xiic_i2c
*i2c
, int reg
, int value
)
194 iowrite32(value
, i2c
->base
+ reg
);
197 static inline int xiic_getreg32(struct xiic_i2c
*i2c
, int reg
)
199 return ioread32(i2c
->base
+ reg
);
202 static inline void xiic_irq_dis(struct xiic_i2c
*i2c
, u32 mask
)
204 u32 ier
= xiic_getreg32(i2c
, XIIC_IIER_OFFSET
);
205 xiic_setreg32(i2c
, XIIC_IIER_OFFSET
, ier
& ~mask
);
208 static inline void xiic_irq_en(struct xiic_i2c
*i2c
, u32 mask
)
210 u32 ier
= xiic_getreg32(i2c
, XIIC_IIER_OFFSET
);
211 xiic_setreg32(i2c
, XIIC_IIER_OFFSET
, ier
| mask
);
214 static inline void xiic_irq_clr(struct xiic_i2c
*i2c
, u32 mask
)
216 u32 isr
= xiic_getreg32(i2c
, XIIC_IISR_OFFSET
);
217 xiic_setreg32(i2c
, XIIC_IISR_OFFSET
, isr
& mask
);
220 static inline void xiic_irq_clr_en(struct xiic_i2c
*i2c
, u32 mask
)
222 xiic_irq_clr(i2c
, mask
);
223 xiic_irq_en(i2c
, mask
);
226 static void xiic_clear_rx_fifo(struct xiic_i2c
*i2c
)
229 for (sr
= xiic_getreg8(i2c
, XIIC_SR_REG_OFFSET
);
230 !(sr
& XIIC_SR_RX_FIFO_EMPTY_MASK
);
231 sr
= xiic_getreg8(i2c
, XIIC_SR_REG_OFFSET
))
232 xiic_getreg8(i2c
, XIIC_DRR_REG_OFFSET
);
235 static void xiic_reinit(struct xiic_i2c
*i2c
)
237 xiic_setreg32(i2c
, XIIC_RESETR_OFFSET
, XIIC_RESET_MASK
);
239 /* Set receive Fifo depth to maximum (zero based). */
240 xiic_setreg8(i2c
, XIIC_RFD_REG_OFFSET
, IIC_RX_FIFO_DEPTH
- 1);
243 xiic_setreg8(i2c
, XIIC_CR_REG_OFFSET
, XIIC_CR_TX_FIFO_RESET_MASK
);
245 /* Enable IIC Device, remove Tx Fifo reset & disable general call. */
246 xiic_setreg8(i2c
, XIIC_CR_REG_OFFSET
, XIIC_CR_ENABLE_DEVICE_MASK
);
248 /* make sure RX fifo is empty */
249 xiic_clear_rx_fifo(i2c
);
251 /* Enable interrupts */
252 xiic_setreg32(i2c
, XIIC_DGIER_OFFSET
, XIIC_GINTR_ENABLE_MASK
);
254 xiic_irq_clr_en(i2c
, XIIC_INTR_AAS_MASK
| XIIC_INTR_ARB_LOST_MASK
);
257 static void xiic_deinit(struct xiic_i2c
*i2c
)
261 xiic_setreg32(i2c
, XIIC_RESETR_OFFSET
, XIIC_RESET_MASK
);
263 /* Disable IIC Device. */
264 cr
= xiic_getreg8(i2c
, XIIC_CR_REG_OFFSET
);
265 xiic_setreg8(i2c
, XIIC_CR_REG_OFFSET
, cr
& ~XIIC_CR_ENABLE_DEVICE_MASK
);
268 static void xiic_read_rx(struct xiic_i2c
*i2c
)
273 bytes_in_fifo
= xiic_getreg8(i2c
, XIIC_RFO_REG_OFFSET
) + 1;
275 dev_dbg(i2c
->adap
.dev
.parent
, "%s entry, bytes in fifo: %d, msg: %d"
276 ", SR: 0x%x, CR: 0x%x\n",
277 __func__
, bytes_in_fifo
, xiic_rx_space(i2c
),
278 xiic_getreg8(i2c
, XIIC_SR_REG_OFFSET
),
279 xiic_getreg8(i2c
, XIIC_CR_REG_OFFSET
));
281 if (bytes_in_fifo
> xiic_rx_space(i2c
))
282 bytes_in_fifo
= xiic_rx_space(i2c
);
284 for (i
= 0; i
< bytes_in_fifo
; i
++)
285 i2c
->rx_msg
->buf
[i2c
->rx_pos
++] =
286 xiic_getreg8(i2c
, XIIC_DRR_REG_OFFSET
);
288 xiic_setreg8(i2c
, XIIC_RFD_REG_OFFSET
,
289 (xiic_rx_space(i2c
) > IIC_RX_FIFO_DEPTH
) ?
290 IIC_RX_FIFO_DEPTH
- 1 : xiic_rx_space(i2c
) - 1);
293 static int xiic_tx_fifo_space(struct xiic_i2c
*i2c
)
295 /* return the actual space left in the FIFO */
296 return IIC_TX_FIFO_DEPTH
- xiic_getreg8(i2c
, XIIC_TFO_REG_OFFSET
) - 1;
299 static void xiic_fill_tx_fifo(struct xiic_i2c
*i2c
)
301 u8 fifo_space
= xiic_tx_fifo_space(i2c
);
302 int len
= xiic_tx_space(i2c
);
304 len
= (len
> fifo_space
) ? fifo_space
: len
;
306 dev_dbg(i2c
->adap
.dev
.parent
, "%s entry, len: %d, fifo space: %d\n",
307 __func__
, len
, fifo_space
);
310 u16 data
= i2c
->tx_msg
->buf
[i2c
->tx_pos
++];
311 if ((xiic_tx_space(i2c
) == 0) && (i2c
->nmsgs
== 1)) {
312 /* last message in transfer -> STOP */
313 data
|= XIIC_TX_DYN_STOP_MASK
;
314 dev_dbg(i2c
->adap
.dev
.parent
, "%s TX STOP\n", __func__
);
316 xiic_setreg16(i2c
, XIIC_DTR_REG_OFFSET
, data
);
320 static void xiic_wakeup(struct xiic_i2c
*i2c
, int code
)
329 static void xiic_process(struct xiic_i2c
*i2c
)
334 /* Get the interrupt Status from the IPIF. There is no clearing of
335 * interrupts in the IPIF. Interrupts must be cleared at the source.
336 * To find which interrupts are pending; AND interrupts pending with
339 isr
= xiic_getreg32(i2c
, XIIC_IISR_OFFSET
);
340 ier
= xiic_getreg32(i2c
, XIIC_IIER_OFFSET
);
343 dev_dbg(i2c
->adap
.dev
.parent
, "%s entry, IER: 0x%x, ISR: 0x%x, "
344 "pend: 0x%x, SR: 0x%x, msg: %p, nmsgs: %d\n",
345 __func__
, ier
, isr
, pend
, xiic_getreg8(i2c
, XIIC_SR_REG_OFFSET
),
346 i2c
->tx_msg
, i2c
->nmsgs
);
348 /* Do not processes a devices interrupts if the device has no
354 /* Service requesting interrupt */
355 if ((pend
& XIIC_INTR_ARB_LOST_MASK
) ||
356 ((pend
& XIIC_INTR_TX_ERROR_MASK
) &&
357 !(pend
& XIIC_INTR_RX_FULL_MASK
))) {
358 /* bus arbritration lost, or...
359 * Transmit error _OR_ RX completed
360 * if this happens when RX_FULL is not set
361 * this is probably a TX error
364 dev_dbg(i2c
->adap
.dev
.parent
, "%s error\n", __func__
);
366 /* dynamic mode seem to suffer from problems if we just flushes
367 * fifos and the next message is a TX with len 0 (only addr)
368 * reset the IP instead of just flush fifos
373 xiic_wakeup(i2c
, STATE_ERROR
);
375 } else if (pend
& XIIC_INTR_RX_FULL_MASK
) {
376 /* Receive register/FIFO is full */
378 clr
= XIIC_INTR_RX_FULL_MASK
;
380 dev_dbg(i2c
->adap
.dev
.parent
,
381 "%s unexpexted RX IRQ\n", __func__
);
382 xiic_clear_rx_fifo(i2c
);
387 if (xiic_rx_space(i2c
) == 0) {
388 /* this is the last part of the message */
391 /* also clear TX error if there (RX complete) */
392 clr
|= (isr
& XIIC_INTR_TX_ERROR_MASK
);
394 dev_dbg(i2c
->adap
.dev
.parent
,
395 "%s end of message, nmsgs: %d\n",
396 __func__
, i2c
->nmsgs
);
398 /* send next message if this wasn't the last,
399 * otherwise the transfer will be finialise when
400 * receiving the bus not busy interrupt
402 if (i2c
->nmsgs
> 1) {
405 dev_dbg(i2c
->adap
.dev
.parent
,
406 "%s will start next...\n", __func__
);
408 __xiic_start_xfer(i2c
);
411 } else if (pend
& XIIC_INTR_BNB_MASK
) {
412 /* IIC bus has transitioned to not busy */
413 clr
= XIIC_INTR_BNB_MASK
;
415 /* The bus is not busy, disable BusNotBusy interrupt */
416 xiic_irq_dis(i2c
, XIIC_INTR_BNB_MASK
);
421 if ((i2c
->nmsgs
== 1) && !i2c
->rx_msg
&&
422 xiic_tx_space(i2c
) == 0)
423 xiic_wakeup(i2c
, STATE_DONE
);
425 xiic_wakeup(i2c
, STATE_ERROR
);
427 } else if (pend
& (XIIC_INTR_TX_EMPTY_MASK
| XIIC_INTR_TX_HALF_MASK
)) {
428 /* Transmit register/FIFO is empty or ½ empty */
431 (XIIC_INTR_TX_EMPTY_MASK
| XIIC_INTR_TX_HALF_MASK
);
434 dev_dbg(i2c
->adap
.dev
.parent
,
435 "%s unexpexted TX IRQ\n", __func__
);
439 xiic_fill_tx_fifo(i2c
);
441 /* current message sent and there is space in the fifo */
442 if (!xiic_tx_space(i2c
) && xiic_tx_fifo_space(i2c
) >= 2) {
443 dev_dbg(i2c
->adap
.dev
.parent
,
444 "%s end of message sent, nmsgs: %d\n",
445 __func__
, i2c
->nmsgs
);
446 if (i2c
->nmsgs
> 1) {
449 __xiic_start_xfer(i2c
);
451 xiic_irq_dis(i2c
, XIIC_INTR_TX_HALF_MASK
);
453 dev_dbg(i2c
->adap
.dev
.parent
,
454 "%s Got TX IRQ but no more to do...\n",
457 } else if (!xiic_tx_space(i2c
) && (i2c
->nmsgs
== 1))
458 /* current frame is sent and is last,
459 * make sure to disable tx half
461 xiic_irq_dis(i2c
, XIIC_INTR_TX_HALF_MASK
);
463 /* got IRQ which is not acked */
464 dev_err(i2c
->adap
.dev
.parent
, "%s Got unexpected IRQ\n",
469 dev_dbg(i2c
->adap
.dev
.parent
, "%s clr: 0x%x\n", __func__
, clr
);
471 xiic_setreg32(i2c
, XIIC_IISR_OFFSET
, clr
);
474 static int xiic_bus_busy(struct xiic_i2c
*i2c
)
476 u8 sr
= xiic_getreg8(i2c
, XIIC_SR_REG_OFFSET
);
478 return (sr
& XIIC_SR_BUS_BUSY_MASK
) ? -EBUSY
: 0;
481 static int xiic_busy(struct xiic_i2c
*i2c
)
489 /* for instance if previous transfer was terminated due to TX error
490 * it might be that the bus is on it's way to become available
491 * give it at most 3 ms to wake
493 err
= xiic_bus_busy(i2c
);
494 while (err
&& tries
--) {
496 err
= xiic_bus_busy(i2c
);
502 static void xiic_start_recv(struct xiic_i2c
*i2c
)
505 struct i2c_msg
*msg
= i2c
->rx_msg
= i2c
->tx_msg
;
507 /* Clear and enable Rx full interrupt. */
508 xiic_irq_clr_en(i2c
, XIIC_INTR_RX_FULL_MASK
| XIIC_INTR_TX_ERROR_MASK
);
510 /* we want to get all but last byte, because the TX_ERROR IRQ is used
511 * to inidicate error ACK on the address, and negative ack on the last
512 * received byte, so to not mix them receive all but last.
513 * In the case where there is only one byte to receive
514 * we can check if ERROR and RX full is set at the same time
516 rx_watermark
= msg
->len
;
517 if (rx_watermark
> IIC_RX_FIFO_DEPTH
)
518 rx_watermark
= IIC_RX_FIFO_DEPTH
;
519 xiic_setreg8(i2c
, XIIC_RFD_REG_OFFSET
, rx_watermark
- 1);
521 if (!(msg
->flags
& I2C_M_NOSTART
))
522 /* write the address */
523 xiic_setreg16(i2c
, XIIC_DTR_REG_OFFSET
,
524 (msg
->addr
<< 1) | XIIC_READ_OPERATION
|
525 XIIC_TX_DYN_START_MASK
);
527 xiic_irq_clr_en(i2c
, XIIC_INTR_BNB_MASK
);
529 xiic_setreg16(i2c
, XIIC_DTR_REG_OFFSET
,
530 msg
->len
| ((i2c
->nmsgs
== 1) ? XIIC_TX_DYN_STOP_MASK
: 0));
532 /* very last, enable bus not busy as well */
533 xiic_irq_clr_en(i2c
, XIIC_INTR_BNB_MASK
);
535 /* the message is tx:ed */
536 i2c
->tx_pos
= msg
->len
;
539 static void xiic_start_send(struct xiic_i2c
*i2c
)
541 struct i2c_msg
*msg
= i2c
->tx_msg
;
543 xiic_irq_clr(i2c
, XIIC_INTR_TX_ERROR_MASK
);
545 dev_dbg(i2c
->adap
.dev
.parent
, "%s entry, msg: %p, len: %d, "
546 "ISR: 0x%x, CR: 0x%x\n",
547 __func__
, msg
, msg
->len
, xiic_getreg32(i2c
, XIIC_IISR_OFFSET
),
548 xiic_getreg8(i2c
, XIIC_CR_REG_OFFSET
));
550 if (!(msg
->flags
& I2C_M_NOSTART
)) {
551 /* write the address */
552 u16 data
= ((msg
->addr
<< 1) & 0xfe) | XIIC_WRITE_OPERATION
|
553 XIIC_TX_DYN_START_MASK
;
554 if ((i2c
->nmsgs
== 1) && msg
->len
== 0)
555 /* no data and last message -> add STOP */
556 data
|= XIIC_TX_DYN_STOP_MASK
;
558 xiic_setreg16(i2c
, XIIC_DTR_REG_OFFSET
, data
);
561 xiic_fill_tx_fifo(i2c
);
563 /* Clear any pending Tx empty, Tx Error and then enable them. */
564 xiic_irq_clr_en(i2c
, XIIC_INTR_TX_EMPTY_MASK
| XIIC_INTR_TX_ERROR_MASK
|
568 static irqreturn_t
xiic_isr(int irq
, void *dev_id
)
570 struct xiic_i2c
*i2c
= dev_id
;
572 spin_lock(&i2c
->lock
);
573 /* disable interrupts globally */
574 xiic_setreg32(i2c
, XIIC_DGIER_OFFSET
, 0);
576 dev_dbg(i2c
->adap
.dev
.parent
, "%s entry\n", __func__
);
580 xiic_setreg32(i2c
, XIIC_DGIER_OFFSET
, XIIC_GINTR_ENABLE_MASK
);
581 spin_unlock(&i2c
->lock
);
586 static void __xiic_start_xfer(struct xiic_i2c
*i2c
)
589 int fifo_space
= xiic_tx_fifo_space(i2c
);
590 dev_dbg(i2c
->adap
.dev
.parent
, "%s entry, msg: %p, fifos space: %d\n",
591 __func__
, i2c
->tx_msg
, fifo_space
);
598 i2c
->state
= STATE_START
;
599 while ((fifo_space
>= 2) && (first
|| (i2c
->nmsgs
> 1))) {
607 if (i2c
->tx_msg
->flags
& I2C_M_RD
) {
608 /* we dont date putting several reads in the FIFO */
609 xiic_start_recv(i2c
);
612 xiic_start_send(i2c
);
613 if (xiic_tx_space(i2c
) != 0) {
614 /* the message could not be completely sent */
619 fifo_space
= xiic_tx_fifo_space(i2c
);
622 /* there are more messages or the current one could not be completely
623 * put into the FIFO, also enable the half empty interrupt
625 if (i2c
->nmsgs
> 1 || xiic_tx_space(i2c
))
626 xiic_irq_clr_en(i2c
, XIIC_INTR_TX_HALF_MASK
);
630 static void xiic_start_xfer(struct xiic_i2c
*i2c
)
634 spin_lock_irqsave(&i2c
->lock
, flags
);
636 /* disable interrupts globally */
637 xiic_setreg32(i2c
, XIIC_DGIER_OFFSET
, 0);
638 spin_unlock_irqrestore(&i2c
->lock
, flags
);
640 __xiic_start_xfer(i2c
);
641 xiic_setreg32(i2c
, XIIC_DGIER_OFFSET
, XIIC_GINTR_ENABLE_MASK
);
644 static int xiic_xfer(struct i2c_adapter
*adap
, struct i2c_msg
*msgs
, int num
)
646 struct xiic_i2c
*i2c
= i2c_get_adapdata(adap
);
649 dev_dbg(adap
->dev
.parent
, "%s entry SR: 0x%x\n", __func__
,
650 xiic_getreg8(i2c
, XIIC_SR_REG_OFFSET
));
652 err
= xiic_busy(i2c
);
659 xiic_start_xfer(i2c
);
661 if (wait_event_timeout(i2c
->wait
, (i2c
->state
== STATE_ERROR
) ||
662 (i2c
->state
== STATE_DONE
), HZ
))
663 return (i2c
->state
== STATE_DONE
) ? num
: -EIO
;
672 static u32
xiic_func(struct i2c_adapter
*adap
)
674 return I2C_FUNC_I2C
| I2C_FUNC_SMBUS_EMUL
;
677 static const struct i2c_algorithm xiic_algorithm
= {
678 .master_xfer
= xiic_xfer
,
679 .functionality
= xiic_func
,
682 static struct i2c_adapter xiic_adapter
= {
683 .owner
= THIS_MODULE
,
685 .class = I2C_CLASS_HWMON
| I2C_CLASS_SPD
,
686 .algo
= &xiic_algorithm
,
690 static int xiic_i2c_probe(struct platform_device
*pdev
)
692 struct xiic_i2c
*i2c
;
693 struct xiic_i2c_platform_data
*pdata
;
694 struct resource
*res
;
698 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
700 goto resource_missing
;
702 irq
= platform_get_irq(pdev
, 0);
704 goto resource_missing
;
706 pdata
= (struct xiic_i2c_platform_data
*) pdev
->dev
.platform_data
;
708 i2c
= kzalloc(sizeof(*i2c
), GFP_KERNEL
);
712 if (!request_mem_region(res
->start
, resource_size(res
), pdev
->name
)) {
713 dev_err(&pdev
->dev
, "Memory region busy\n");
715 goto request_mem_failed
;
718 i2c
->base
= ioremap(res
->start
, resource_size(res
));
720 dev_err(&pdev
->dev
, "Unable to map registers\n");
725 /* hook up driver to tree */
726 platform_set_drvdata(pdev
, i2c
);
727 i2c
->adap
= xiic_adapter
;
728 i2c_set_adapdata(&i2c
->adap
, i2c
);
729 i2c
->adap
.dev
.parent
= &pdev
->dev
;
730 i2c
->adap
.dev
.of_node
= pdev
->dev
.of_node
;
734 spin_lock_init(&i2c
->lock
);
735 init_waitqueue_head(&i2c
->wait
);
736 ret
= request_irq(irq
, xiic_isr
, 0, pdev
->name
, i2c
);
738 dev_err(&pdev
->dev
, "Cannot claim IRQ\n");
739 goto request_irq_failed
;
742 /* add i2c adapter to i2c tree */
743 ret
= i2c_add_adapter(&i2c
->adap
);
745 dev_err(&pdev
->dev
, "Failed to add adapter\n");
746 goto add_adapter_failed
;
750 /* add in known devices to the bus */
751 for (i
= 0; i
< pdata
->num_devices
; i
++)
752 i2c_new_device(&i2c
->adap
, pdata
->devices
+ i
);
755 of_i2c_register_devices(&i2c
->adap
);
765 release_mem_region(res
->start
, resource_size(res
));
771 dev_err(&pdev
->dev
, "IRQ or Memory resource is missing\n");
775 static int xiic_i2c_remove(struct platform_device
*pdev
)
777 struct xiic_i2c
*i2c
= platform_get_drvdata(pdev
);
778 struct resource
*res
;
780 /* remove adapter & data */
781 i2c_del_adapter(&i2c
->adap
);
785 free_irq(platform_get_irq(pdev
, 0), i2c
);
789 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
791 release_mem_region(res
->start
, resource_size(res
));
798 #if defined(CONFIG_OF)
799 static const struct of_device_id xiic_of_match
[] = {
800 { .compatible
= "xlnx,xps-iic-2.00.a", },
803 MODULE_DEVICE_TABLE(of
, xiic_of_match
);
806 static struct platform_driver xiic_i2c_driver
= {
807 .probe
= xiic_i2c_probe
,
808 .remove
= xiic_i2c_remove
,
810 .owner
= THIS_MODULE
,
812 .of_match_table
= of_match_ptr(xiic_of_match
),
816 module_platform_driver(xiic_i2c_driver
);
818 MODULE_AUTHOR("info@mocean-labs.com");
819 MODULE_DESCRIPTION("Xilinx I2C bus driver");
820 MODULE_LICENSE("GPL v2");
821 MODULE_ALIAS("platform:"DRIVER_NAME
);