drivers/i2c/busses/i2c-xiic.c

   1 /*
   2  * i2c-xiic.c
   3  * Copyright (c) 2002-2007 Xilinx Inc.
   4  * Copyright (c) 2009-2010 Intel Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18  *
  19  *
  20  * This code was implemented by Mocean Laboratories AB when porting linux
  21  * to the automotive development board Russellville. The copyright holder
  22  * as seen in the header is Intel corporation.
  23  * Mocean Laboratories forked off the GNU/Linux platform work into a
  24  * separate company called Pelagicore AB, which committed the code to the
  25  * kernel.
  26  */
  27
  28 /* Supports:
  29  * Xilinx IIC
  30  */
  31 #include <linux/kernel.h>
  32 #include <linux/module.h>
  33 #include <linux/init.h>
  34 #include <linux/errno.h>
  35 #include <linux/delay.h>
  36 #include <linux/platform_device.h>
  37 #include <linux/i2c.h>
  38 #include <linux/interrupt.h>
  39 #include <linux/wait.h>
  40 #include <linux/i2c-xiic.h>
  41 #include <linux/io.h>
  42 #include <linux/slab.h>
  43 #include <linux/of.h>
  44
  45 #define DRIVER_NAME "xiic-i2c"
  46
  47 enum xilinx_i2c_state {
  48         STATE_DONE,
  49         STATE_ERROR,
  50         STATE_START
  51 };
  52
  53 /**
  54  * struct xiic_i2c - Internal representation of the XIIC I2C bus
  55  * @base:       Memory base of the HW registers
  56  * @wait:       Wait queue for callers
  57  * @adap:       Kernel adapter representation
  58  * @tx_msg:     Messages from above to be sent
  59  * @lock:       Mutual exclusion
  60  * @tx_pos:     Current pos in TX message
  61  * @nmsgs:      Number of messages in tx_msg
  62  * @state:      See STATE_
  63  * @rx_msg:     Current RX message
  64  * @rx_pos:     Position within current RX message
  65  */
  66 struct xiic_i2c {
  67         void __iomem            *base;
  68         wait_queue_head_t       wait;
  69         struct i2c_adapter      adap;
  70         struct i2c_msg          *tx_msg;
  71         spinlock_t              lock;
  72         unsigned int            tx_pos;
  73         unsigned int            nmsgs;
  74         enum xilinx_i2c_state   state;
  75         struct i2c_msg          *rx_msg;
  76         int                     rx_pos;
  77 };
  78
  79
  80 #define XIIC_MSB_OFFSET 0
  81 #define XIIC_REG_OFFSET (0x100+XIIC_MSB_OFFSET)
  82
  83 /*
  84  * Register offsets in bytes from RegisterBase. Three is added to the
  85  * base offset to access LSB (IBM style) of the word
  86  */
  87 #define XIIC_CR_REG_OFFSET   (0x00+XIIC_REG_OFFSET)     /* Control Register   */
  88 #define XIIC_SR_REG_OFFSET   (0x04+XIIC_REG_OFFSET)     /* Status Register    */
  89 #define XIIC_DTR_REG_OFFSET  (0x08+XIIC_REG_OFFSET)     /* Data Tx Register   */
  90 #define XIIC_DRR_REG_OFFSET  (0x0C+XIIC_REG_OFFSET)     /* Data Rx Register   */
  91 #define XIIC_ADR_REG_OFFSET  (0x10+XIIC_REG_OFFSET)     /* Address Register   */
  92 #define XIIC_TFO_REG_OFFSET  (0x14+XIIC_REG_OFFSET)     /* Tx FIFO Occupancy  */
  93 #define XIIC_RFO_REG_OFFSET  (0x18+XIIC_REG_OFFSET)     /* Rx FIFO Occupancy  */
  94 #define XIIC_TBA_REG_OFFSET  (0x1C+XIIC_REG_OFFSET)     /* 10 Bit Address reg */
  95 #define XIIC_RFD_REG_OFFSET  (0x20+XIIC_REG_OFFSET)     /* Rx FIFO Depth reg  */
  96 #define XIIC_GPO_REG_OFFSET  (0x24+XIIC_REG_OFFSET)     /* Output Register    */
  97
  98 /* Control Register masks */
  99 #define XIIC_CR_ENABLE_DEVICE_MASK        0x01  /* Device enable = 1      */
 100 #define XIIC_CR_TX_FIFO_RESET_MASK        0x02  /* Transmit FIFO reset=1  */
 101 #define XIIC_CR_MSMS_MASK                 0x04  /* Master starts Txing=1  */
 102 #define XIIC_CR_DIR_IS_TX_MASK            0x08  /* Dir of tx. Txing=1     */
 103 #define XIIC_CR_NO_ACK_MASK               0x10  /* Tx Ack. NO ack = 1     */
 104 #define XIIC_CR_REPEATED_START_MASK       0x20  /* Repeated start = 1     */
 105 #define XIIC_CR_GENERAL_CALL_MASK         0x40  /* Gen Call enabled = 1   */
 106
 107 /* Status Register masks */
 108 #define XIIC_SR_GEN_CALL_MASK             0x01  /* 1=a mstr issued a GC   */
 109 #define XIIC_SR_ADDR_AS_SLAVE_MASK        0x02  /* 1=when addr as slave   */
 110 #define XIIC_SR_BUS_BUSY_MASK             0x04  /* 1 = bus is busy        */
 111 #define XIIC_SR_MSTR_RDING_SLAVE_MASK     0x08  /* 1=Dir: mstr <-- slave  */
 112 #define XIIC_SR_TX_FIFO_FULL_MASK         0x10  /* 1 = Tx FIFO full       */
 113 #define XIIC_SR_RX_FIFO_FULL_MASK         0x20  /* 1 = Rx FIFO full       */
 114 #define XIIC_SR_RX_FIFO_EMPTY_MASK        0x40  /* 1 = Rx FIFO empty      */
 115 #define XIIC_SR_TX_FIFO_EMPTY_MASK        0x80  /* 1 = Tx FIFO empty      */
 116
 117 /* Interrupt Status Register masks    Interrupt occurs when...       */
 118 #define XIIC_INTR_ARB_LOST_MASK           0x01  /* 1 = arbitration lost   */
 119 #define XIIC_INTR_TX_ERROR_MASK           0x02  /* 1=Tx error/msg complete */
 120 #define XIIC_INTR_TX_EMPTY_MASK           0x04  /* 1 = Tx FIFO/reg empty  */
 121 #define XIIC_INTR_RX_FULL_MASK            0x08  /* 1=Rx FIFO/reg=OCY level */
 122 #define XIIC_INTR_BNB_MASK                0x10  /* 1 = Bus not busy       */
 123 #define XIIC_INTR_AAS_MASK                0x20  /* 1 = when addr as slave */
 124 #define XIIC_INTR_NAAS_MASK               0x40  /* 1 = not addr as slave  */
 125 #define XIIC_INTR_TX_HALF_MASK            0x80  /* 1 = TX FIFO half empty */
 126
 127 /* The following constants specify the depth of the FIFOs */
 128 #define IIC_RX_FIFO_DEPTH         16    /* Rx fifo capacity               */
 129 #define IIC_TX_FIFO_DEPTH         16    /* Tx fifo capacity               */
 130
 131 /* The following constants specify groups of interrupts that are typically
 132  * enabled or disables at the same time
 133  */
 134 #define XIIC_TX_INTERRUPTS                           \
 135 (XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)
 136
 137 #define XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS)
 138
 139 /* The following constants are used with the following macros to specify the
 140  * operation, a read or write operation.
 141  */
 142 #define XIIC_READ_OPERATION  1
 143 #define XIIC_WRITE_OPERATION 0
 144
 145 /*
 146  * Tx Fifo upper bit masks.
 147  */
 148 #define XIIC_TX_DYN_START_MASK            0x0100 /* 1 = Set dynamic start */
 149 #define XIIC_TX_DYN_STOP_MASK             0x0200 /* 1 = Set dynamic stop */
 150
 151 /*
 152  * The following constants define the register offsets for the Interrupt
 153  * registers. There are some holes in the memory map for reserved addresses
 154  * to allow other registers to be added and still match the memory map of the
 155  * interrupt controller registers
 156  */
 157 #define XIIC_DGIER_OFFSET    0x1C /* Device Global Interrupt Enable Register */
 158 #define XIIC_IISR_OFFSET     0x20 /* Interrupt Status Register */
 159 #define XIIC_IIER_OFFSET     0x28 /* Interrupt Enable Register */
 160 #define XIIC_RESETR_OFFSET   0x40 /* Reset Register */
 161
 162 #define XIIC_RESET_MASK             0xAUL
 163
 164 /*
 165  * The following constant is used for the device global interrupt enable
 166  * register, to enable all interrupts for the device, this is the only bit
 167  * in the register
 168  */
 169 #define XIIC_GINTR_ENABLE_MASK      0x80000000UL
 170
 171 #define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos)
 172 #define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos)
 173
 174 static void xiic_start_xfer(struct xiic_i2c *i2c);
 175 static void __xiic_start_xfer(struct xiic_i2c *i2c);
 176
 177 static inline void xiic_setreg8(struct xiic_i2c *i2c, int reg, u8 value)
 178 {
 179         iowrite8(value, i2c->base + reg);
 180 }
 181
 182 static inline u8 xiic_getreg8(struct xiic_i2c *i2c, int reg)
 183 {
 184         return ioread8(i2c->base + reg);
 185 }
 186
 187 static inline void xiic_setreg16(struct xiic_i2c *i2c, int reg, u16 value)
 188 {
 189         iowrite16(value, i2c->base + reg);
 190 }
 191
 192 static inline void xiic_setreg32(struct xiic_i2c *i2c, int reg, int value)
 193 {
 194         iowrite32(value, i2c->base + reg);
 195 }
 196
 197 static inline int xiic_getreg32(struct xiic_i2c *i2c, int reg)
 198 {
 199         return ioread32(i2c->base + reg);
 200 }
 201
 202 static inline void xiic_irq_dis(struct xiic_i2c *i2c, u32 mask)
 203 {
 204         u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
 205         xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier & ~mask);
 206 }
 207
 208 static inline void xiic_irq_en(struct xiic_i2c *i2c, u32 mask)
 209 {
 210         u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
 211         xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier | mask);
 212 }
 213
 214 static inline void xiic_irq_clr(struct xiic_i2c *i2c, u32 mask)
 215 {
 216         u32 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
 217         xiic_setreg32(i2c, XIIC_IISR_OFFSET, isr & mask);
 218 }
 219
 220 static inline void xiic_irq_clr_en(struct xiic_i2c *i2c, u32 mask)
 221 {
 222         xiic_irq_clr(i2c, mask);
 223         xiic_irq_en(i2c, mask);
 224 }
 225
 226 static void xiic_clear_rx_fifo(struct xiic_i2c *i2c)
 227 {
 228         u8 sr;
 229         for (sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET);
 230                 !(sr & XIIC_SR_RX_FIFO_EMPTY_MASK);
 231                 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET))
 232                 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
 233 }
 234
 235 static void xiic_reinit(struct xiic_i2c *i2c)
 236 {
 237         xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK);
 238
 239         /* Set receive Fifo depth to maximum (zero based). */
 240         xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1);
 241
 242         /* Reset Tx Fifo. */
 243         xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK);
 244
 245         /* Enable IIC Device, remove Tx Fifo reset & disable general call. */
 246         xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_ENABLE_DEVICE_MASK);
 247
 248         /* make sure RX fifo is empty */
 249         xiic_clear_rx_fifo(i2c);
 250
 251         /* Enable interrupts */
 252         xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
 253
 254         xiic_irq_clr_en(i2c, XIIC_INTR_AAS_MASK | XIIC_INTR_ARB_LOST_MASK);
 255 }
 256
 257 static void xiic_deinit(struct xiic_i2c *i2c)
 258 {
 259         u8 cr;
 260
 261         xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK);
 262
 263         /* Disable IIC Device. */
 264         cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
 265         xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & ~XIIC_CR_ENABLE_DEVICE_MASK);
 266 }
 267
 268 static void xiic_read_rx(struct xiic_i2c *i2c)
 269 {
 270         u8 bytes_in_fifo;
 271         int i;
 272
 273         bytes_in_fifo = xiic_getreg8(i2c, XIIC_RFO_REG_OFFSET) + 1;
 274
 275         dev_dbg(i2c->adap.dev.parent, "%s entry, bytes in fifo: %d, msg: %d"
 276                 ", SR: 0x%x, CR: 0x%x\n",
 277                 __func__, bytes_in_fifo, xiic_rx_space(i2c),
 278                 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET),
 279                 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
 280
 281         if (bytes_in_fifo > xiic_rx_space(i2c))
 282                 bytes_in_fifo = xiic_rx_space(i2c);
 283
 284         for (i = 0; i < bytes_in_fifo; i++)
 285                 i2c->rx_msg->buf[i2c->rx_pos++] =
 286                         xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
 287
 288         xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET,
 289                 (xiic_rx_space(i2c) > IIC_RX_FIFO_DEPTH) ?
 290                 IIC_RX_FIFO_DEPTH - 1 :  xiic_rx_space(i2c) - 1);
 291 }
 292
 293 static int xiic_tx_fifo_space(struct xiic_i2c *i2c)
 294 {
 295         /* return the actual space left in the FIFO */
 296         return IIC_TX_FIFO_DEPTH - xiic_getreg8(i2c, XIIC_TFO_REG_OFFSET) - 1;
 297 }
 298
 299 static void xiic_fill_tx_fifo(struct xiic_i2c *i2c)
 300 {
 301         u8 fifo_space = xiic_tx_fifo_space(i2c);
 302         int len = xiic_tx_space(i2c);
 303
 304         len = (len > fifo_space) ? fifo_space : len;
 305
 306         dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n",
 307                 __func__, len, fifo_space);
 308
 309         while (len--) {
 310                 u16 data = i2c->tx_msg->buf[i2c->tx_pos++];
 311                 if ((xiic_tx_space(i2c) == 0) && (i2c->nmsgs == 1)) {
 312                         /* last message in transfer -> STOP */
 313                         data |= XIIC_TX_DYN_STOP_MASK;
 314                         dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__);
 315                 }
 316                 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
 317         }
 318 }
 319
 320 static void xiic_wakeup(struct xiic_i2c *i2c, int code)
 321 {
 322         i2c->tx_msg = NULL;
 323         i2c->rx_msg = NULL;
 324         i2c->nmsgs = 0;
 325         i2c->state = code;
 326         wake_up(&i2c->wait);
 327 }
 328
 329 static void xiic_process(struct xiic_i2c *i2c)
 330 {
 331         u32 pend, isr, ier;
 332         u32 clr = 0;
 333
 334         /* Get the interrupt Status from the IPIF. There is no clearing of
 335          * interrupts in the IPIF. Interrupts must be cleared at the source.
 336          * To find which interrupts are pending; AND interrupts pending with
 337          * interrupts masked.
 338          */
 339         isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
 340         ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
 341         pend = isr & ier;
 342
 343         dev_dbg(i2c->adap.dev.parent, "%s entry, IER: 0x%x, ISR: 0x%x, "
 344                 "pend: 0x%x, SR: 0x%x, msg: %p, nmsgs: %d\n",
 345                 __func__, ier, isr, pend, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET),
 346                 i2c->tx_msg, i2c->nmsgs);
 347
 348         /* Do not processes a devices interrupts if the device has no
 349          * interrupts pending
 350          */
 351         if (!pend)
 352                 return;
 353
 354         /* Service requesting interrupt */
 355         if ((pend & XIIC_INTR_ARB_LOST_MASK) ||
 356                 ((pend & XIIC_INTR_TX_ERROR_MASK) &&
 357                 !(pend & XIIC_INTR_RX_FULL_MASK))) {
 358                 /* bus arbritration lost, or...
 359                  * Transmit error _OR_ RX completed
 360                  * if this happens when RX_FULL is not set
 361                  * this is probably a TX error
 362                  */
 363
 364                 dev_dbg(i2c->adap.dev.parent, "%s error\n", __func__);
 365
 366                 /* dynamic mode seem to suffer from problems if we just flushes
 367                  * fifos and the next message is a TX with len 0 (only addr)
 368                  * reset the IP instead of just flush fifos
 369                  */
 370                 xiic_reinit(i2c);
 371
 372                 if (i2c->tx_msg)
 373                         xiic_wakeup(i2c, STATE_ERROR);
 374
 375         } else if (pend & XIIC_INTR_RX_FULL_MASK) {
 376                 /* Receive register/FIFO is full */
 377
 378                 clr = XIIC_INTR_RX_FULL_MASK;
 379                 if (!i2c->rx_msg) {
 380                         dev_dbg(i2c->adap.dev.parent,
 381                                 "%s unexpexted RX IRQ\n", __func__);
 382                         xiic_clear_rx_fifo(i2c);
 383                         goto out;
 384                 }
 385
 386                 xiic_read_rx(i2c);
 387                 if (xiic_rx_space(i2c) == 0) {
 388                         /* this is the last part of the message */
 389                         i2c->rx_msg = NULL;
 390
 391                         /* also clear TX error if there (RX complete) */
 392                         clr |= (isr & XIIC_INTR_TX_ERROR_MASK);
 393
 394                         dev_dbg(i2c->adap.dev.parent,
 395                                 "%s end of message, nmsgs: %d\n",
 396                                 __func__, i2c->nmsgs);
 397
 398                         /* send next message if this wasn't the last,
 399                          * otherwise the transfer will be finialise when
 400                          * receiving the bus not busy interrupt
 401                          */
 402                         if (i2c->nmsgs > 1) {
 403                                 i2c->nmsgs--;
 404                                 i2c->tx_msg++;
 405                                 dev_dbg(i2c->adap.dev.parent,
 406                                         "%s will start next...\n", __func__);
 407
 408                                 __xiic_start_xfer(i2c);
 409                         }
 410                 }
 411         } else if (pend & XIIC_INTR_BNB_MASK) {
 412                 /* IIC bus has transitioned to not busy */
 413                 clr = XIIC_INTR_BNB_MASK;
 414
 415                 /* The bus is not busy, disable BusNotBusy interrupt */
 416                 xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK);
 417
 418                 if (!i2c->tx_msg)
 419                         goto out;
 420
 421                 if ((i2c->nmsgs == 1) && !i2c->rx_msg &&
 422                         xiic_tx_space(i2c) == 0)
 423                         xiic_wakeup(i2c, STATE_DONE);
 424                 else
 425                         xiic_wakeup(i2c, STATE_ERROR);
 426
 427         } else if (pend & (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)) {
 428                 /* Transmit register/FIFO is empty or ½ empty */
 429
 430                 clr = pend &
 431                         (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK);
 432
 433                 if (!i2c->tx_msg) {
 434                         dev_dbg(i2c->adap.dev.parent,
 435                                 "%s unexpexted TX IRQ\n", __func__);
 436                         goto out;
 437                 }
 438
 439                 xiic_fill_tx_fifo(i2c);
 440
 441                 /* current message sent and there is space in the fifo */
 442                 if (!xiic_tx_space(i2c) && xiic_tx_fifo_space(i2c) >= 2) {
 443                         dev_dbg(i2c->adap.dev.parent,
 444                                 "%s end of message sent, nmsgs: %d\n",
 445                                 __func__, i2c->nmsgs);
 446                         if (i2c->nmsgs > 1) {
 447                                 i2c->nmsgs--;
 448                                 i2c->tx_msg++;
 449                                 __xiic_start_xfer(i2c);
 450                         } else {
 451                                 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK);
 452
 453                                 dev_dbg(i2c->adap.dev.parent,
 454                                         "%s Got TX IRQ but no more to do...\n",
 455                                         __func__);
 456                         }
 457                 } else if (!xiic_tx_space(i2c) && (i2c->nmsgs == 1))
 458                         /* current frame is sent and is last,
 459                          * make sure to disable tx half
 460                          */
 461                         xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK);
 462         } else {
 463                 /* got IRQ which is not acked */
 464                 dev_err(i2c->adap.dev.parent, "%s Got unexpected IRQ\n",
 465                         __func__);
 466                 clr = pend;
 467         }
 468 out:
 469         dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr);
 470
 471         xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr);
 472 }
 473
 474 static int xiic_bus_busy(struct xiic_i2c *i2c)
 475 {
 476         u8 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET);
 477
 478         return (sr & XIIC_SR_BUS_BUSY_MASK) ? -EBUSY : 0;
 479 }
 480
 481 static int xiic_busy(struct xiic_i2c *i2c)
 482 {
 483         int tries = 3;
 484         int err;
 485
 486         if (i2c->tx_msg)
 487                 return -EBUSY;
 488
 489         /* for instance if previous transfer was terminated due to TX error
 490          * it might be that the bus is on it's way to become available
 491          * give it at most 3 ms to wake
 492          */
 493         err = xiic_bus_busy(i2c);
 494         while (err && tries--) {
 495                 mdelay(1);
 496                 err = xiic_bus_busy(i2c);
 497         }
 498
 499         return err;
 500 }
 501
 502 static void xiic_start_recv(struct xiic_i2c *i2c)
 503 {
 504         u8 rx_watermark;
 505         struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg;
 506
 507         /* Clear and enable Rx full interrupt. */
 508         xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK);
 509
 510         /* we want to get all but last byte, because the TX_ERROR IRQ is used
 511          * to inidicate error ACK on the address, and negative ack on the last
 512          * received byte, so to not mix them receive all but last.
 513          * In the case where there is only one byte to receive
 514          * we can check if ERROR and RX full is set at the same time
 515          */
 516         rx_watermark = msg->len;
 517         if (rx_watermark > IIC_RX_FIFO_DEPTH)
 518                 rx_watermark = IIC_RX_FIFO_DEPTH;
 519         xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rx_watermark - 1);
 520
 521         if (!(msg->flags & I2C_M_NOSTART))
 522                 /* write the address */
 523                 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET,
 524                         (msg->addr << 1) | XIIC_READ_OPERATION |
 525                         XIIC_TX_DYN_START_MASK);
 526
 527         xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK);
 528
 529         xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET,
 530                 msg->len | ((i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0));
 531         if (i2c->nmsgs == 1)
 532                 /* very last, enable bus not busy as well */
 533                 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK);
 534
 535         /* the message is tx:ed */
 536         i2c->tx_pos = msg->len;
 537 }
 538
 539 static void xiic_start_send(struct xiic_i2c *i2c)
 540 {
 541         struct i2c_msg *msg = i2c->tx_msg;
 542
 543         xiic_irq_clr(i2c, XIIC_INTR_TX_ERROR_MASK);
 544
 545         dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, len: %d, "
 546                 "ISR: 0x%x, CR: 0x%x\n",
 547                 __func__, msg, msg->len, xiic_getreg32(i2c, XIIC_IISR_OFFSET),
 548                 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
 549
 550         if (!(msg->flags & I2C_M_NOSTART)) {
 551                 /* write the address */
 552                 u16 data = ((msg->addr << 1) & 0xfe) | XIIC_WRITE_OPERATION |
 553                         XIIC_TX_DYN_START_MASK;
 554                 if ((i2c->nmsgs == 1) && msg->len == 0)
 555                         /* no data and last message -> add STOP */
 556                         data |= XIIC_TX_DYN_STOP_MASK;
 557
 558                 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
 559         }
 560
 561         xiic_fill_tx_fifo(i2c);
 562
 563         /* Clear any pending Tx empty, Tx Error and then enable them. */
 564         xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_ERROR_MASK |
 565                 XIIC_INTR_BNB_MASK);
 566 }
 567
 568 static irqreturn_t xiic_isr(int irq, void *dev_id)
 569 {
 570         struct xiic_i2c *i2c = dev_id;
 571
 572         spin_lock(&i2c->lock);
 573         /* disable interrupts globally */
 574         xiic_setreg32(i2c, XIIC_DGIER_OFFSET, 0);
 575
 576         dev_dbg(i2c->adap.dev.parent, "%s entry\n", __func__);
 577
 578         xiic_process(i2c);
 579
 580         xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
 581         spin_unlock(&i2c->lock);
 582
 583         return IRQ_HANDLED;
 584 }
 585
 586 static void __xiic_start_xfer(struct xiic_i2c *i2c)
 587 {
 588         int first = 1;
 589         int fifo_space = xiic_tx_fifo_space(i2c);
 590         dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, fifos space: %d\n",
 591                 __func__, i2c->tx_msg, fifo_space);
 592
 593         if (!i2c->tx_msg)
 594                 return;
 595
 596         i2c->rx_pos = 0;
 597         i2c->tx_pos = 0;
 598         i2c->state = STATE_START;
 599         while ((fifo_space >= 2) && (first || (i2c->nmsgs > 1))) {
 600                 if (!first) {
 601                         i2c->nmsgs--;
 602                         i2c->tx_msg++;
 603                         i2c->tx_pos = 0;
 604                 } else
 605                         first = 0;
 606
 607                 if (i2c->tx_msg->flags & I2C_M_RD) {
 608                         /* we dont date putting several reads in the FIFO */
 609                         xiic_start_recv(i2c);
 610                         return;
 611                 } else {
 612                         xiic_start_send(i2c);
 613                         if (xiic_tx_space(i2c) != 0) {
 614                                 /* the message could not be completely sent */
 615                                 break;
 616                         }
 617                 }
 618
 619                 fifo_space = xiic_tx_fifo_space(i2c);
 620         }
 621
 622         /* there are more messages or the current one could not be completely
 623          * put into the FIFO, also enable the half empty interrupt
 624          */
 625         if (i2c->nmsgs > 1 || xiic_tx_space(i2c))
 626                 xiic_irq_clr_en(i2c, XIIC_INTR_TX_HALF_MASK);
 627
 628 }
 629
 630 static void xiic_start_xfer(struct xiic_i2c *i2c)
 631 {
 632         unsigned long flags;
 633
 634         spin_lock_irqsave(&i2c->lock, flags);
 635         xiic_reinit(i2c);
 636         /* disable interrupts globally */
 637         xiic_setreg32(i2c, XIIC_DGIER_OFFSET, 0);
 638         spin_unlock_irqrestore(&i2c->lock, flags);
 639
 640         __xiic_start_xfer(i2c);
 641         xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
 642 }
 643
 644 static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
 645 {
 646         struct xiic_i2c *i2c = i2c_get_adapdata(adap);
 647         int err;
 648
 649         dev_dbg(adap->dev.parent, "%s entry SR: 0x%x\n", __func__,
 650                 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET));
 651
 652         err = xiic_busy(i2c);
 653         if (err)
 654                 return err;
 655
 656         i2c->tx_msg = msgs;
 657         i2c->nmsgs = num;
 658
 659         xiic_start_xfer(i2c);
 660
 661         if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) ||
 662                 (i2c->state == STATE_DONE), HZ))
 663                 return (i2c->state == STATE_DONE) ? num : -EIO;
 664         else {
 665                 i2c->tx_msg = NULL;
 666                 i2c->rx_msg = NULL;
 667                 i2c->nmsgs = 0;
 668                 return -ETIMEDOUT;
 669         }
 670 }
 671
 672 static u32 xiic_func(struct i2c_adapter *adap)
 673 {
 674         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 675 }
 676
 677 static const struct i2c_algorithm xiic_algorithm = {
 678         .master_xfer    = xiic_xfer,
 679         .functionality  = xiic_func,
 680 };
 681
 682 static struct i2c_adapter xiic_adapter = {
 683         .owner          = THIS_MODULE,
 684         .name           = DRIVER_NAME,
 685         .class          = I2C_CLASS_HWMON | I2C_CLASS_SPD,
 686         .algo           = &xiic_algorithm,
 687 };
 688
 689
 690 static int xiic_i2c_probe(struct platform_device *pdev)
 691 {
 692         struct xiic_i2c *i2c;
 693         struct xiic_i2c_platform_data *pdata;
 694         struct resource *res;
 695         int ret, irq;
 696         u8 i;
 697
 698         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 699         if (!res)
 700                 goto resource_missing;
 701
 702         irq = platform_get_irq(pdev, 0);
 703         if (irq < 0)
 704                 goto resource_missing;
 705
 706         pdata = dev_get_platdata(&pdev->dev);
 707
 708         i2c = kzalloc(sizeof(*i2c), GFP_KERNEL);
 709         if (!i2c)
 710                 return -ENOMEM;
 711
 712         if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
 713                 dev_err(&pdev->dev, "Memory region busy\n");
 714                 ret = -EBUSY;
 715                 goto request_mem_failed;
 716         }
 717
 718         i2c->base = ioremap(res->start, resource_size(res));
 719         if (!i2c->base) {
 720                 dev_err(&pdev->dev, "Unable to map registers\n");
 721                 ret = -EIO;
 722                 goto map_failed;
 723         }
 724
 725         /* hook up driver to tree */
 726         platform_set_drvdata(pdev, i2c);
 727         i2c->adap = xiic_adapter;
 728         i2c_set_adapdata(&i2c->adap, i2c);
 729         i2c->adap.dev.parent = &pdev->dev;
 730         i2c->adap.dev.of_node = pdev->dev.of_node;
 731
 732         xiic_reinit(i2c);
 733
 734         spin_lock_init(&i2c->lock);
 735         init_waitqueue_head(&i2c->wait);
 736         ret = request_irq(irq, xiic_isr, 0, pdev->name, i2c);
 737         if (ret) {
 738                 dev_err(&pdev->dev, "Cannot claim IRQ\n");
 739                 goto request_irq_failed;
 740         }
 741
 742         /* add i2c adapter to i2c tree */
 743         ret = i2c_add_adapter(&i2c->adap);
 744         if (ret) {
 745                 dev_err(&pdev->dev, "Failed to add adapter\n");
 746                 goto add_adapter_failed;
 747         }
 748
 749         if (pdata) {
 750                 /* add in known devices to the bus */
 751                 for (i = 0; i < pdata->num_devices; i++)
 752                         i2c_new_device(&i2c->adap, pdata->devices + i);
 753         }
 754
 755         return 0;
 756
 757 add_adapter_failed:
 758         free_irq(irq, i2c);
 759 request_irq_failed:
 760         xiic_deinit(i2c);
 761         iounmap(i2c->base);
 762 map_failed:
 763         release_mem_region(res->start, resource_size(res));
 764 request_mem_failed:
 765         kfree(i2c);
 766
 767         return ret;
 768 resource_missing:
 769         dev_err(&pdev->dev, "IRQ or Memory resource is missing\n");
 770         return -ENOENT;
 771 }
 772
 773 static int xiic_i2c_remove(struct platform_device *pdev)
 774 {
 775         struct xiic_i2c *i2c = platform_get_drvdata(pdev);
 776         struct resource *res;
 777
 778         /* remove adapter & data */
 779         i2c_del_adapter(&i2c->adap);
 780
 781         xiic_deinit(i2c);
 782
 783         free_irq(platform_get_irq(pdev, 0), i2c);
 784
 785         iounmap(i2c->base);
 786
 787         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 788         if (res)
 789                 release_mem_region(res->start, resource_size(res));
 790
 791         kfree(i2c);
 792
 793         return 0;
 794 }
 795
 796 #if defined(CONFIG_OF)
 797 static const struct of_device_id xiic_of_match[] = {
 798         { .compatible = "xlnx,xps-iic-2.00.a", },
 799         {},
 800 };
 801 MODULE_DEVICE_TABLE(of, xiic_of_match);
 802 #endif
 803
 804 static struct platform_driver xiic_i2c_driver = {
 805         .probe   = xiic_i2c_probe,
 806         .remove  = xiic_i2c_remove,
 807         .driver  = {
 808                 .owner = THIS_MODULE,
 809                 .name = DRIVER_NAME,
 810                 .of_match_table = of_match_ptr(xiic_of_match),
 811         },
 812 };
 813
 814 module_platform_driver(xiic_i2c_driver);
 815
 816 MODULE_AUTHOR("info@mocean-labs.com");
 817 MODULE_DESCRIPTION("Xilinx I2C bus driver");
 818 MODULE_LICENSE("GPL v2");
 819 MODULE_ALIAS("platform:"DRIVER_NAME);