1 /* linux/drivers/i2c/busses/i2c-s3c2410.c
3 * Copyright (C) 2004,2005,2009 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * S3C2410 I2C Controller
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #include <linux/kernel.h>
24 #include <linux/module.h>
26 #include <linux/i2c.h>
27 #include <linux/init.h>
28 #include <linux/time.h>
29 #include <linux/interrupt.h>
30 #include <linux/delay.h>
31 #include <linux/errno.h>
32 #include <linux/err.h>
33 #include <linux/platform_device.h>
34 #include <linux/pm_runtime.h>
35 #include <linux/clk.h>
36 #include <linux/cpufreq.h>
37 #include <linux/slab.h>
39 #include <linux/of_i2c.h>
40 #include <linux/of_gpio.h>
41 #include <linux/pinctrl/consumer.h>
45 #include <linux/platform_data/i2c-s3c2410.h>
47 /* see s3c2410x user guide, v1.1, section 9 (p447) for more info */
49 #define S3C2410_IICCON 0x00
50 #define S3C2410_IICSTAT 0x04
51 #define S3C2410_IICADD 0x08
52 #define S3C2410_IICDS 0x0C
53 #define S3C2440_IICLC 0x10
55 #define S3C2410_IICCON_ACKEN (1 << 7)
56 #define S3C2410_IICCON_TXDIV_16 (0 << 6)
57 #define S3C2410_IICCON_TXDIV_512 (1 << 6)
58 #define S3C2410_IICCON_IRQEN (1 << 5)
59 #define S3C2410_IICCON_IRQPEND (1 << 4)
60 #define S3C2410_IICCON_SCALE(x) ((x) & 0xf)
61 #define S3C2410_IICCON_SCALEMASK (0xf)
63 #define S3C2410_IICSTAT_MASTER_RX (2 << 6)
64 #define S3C2410_IICSTAT_MASTER_TX (3 << 6)
65 #define S3C2410_IICSTAT_SLAVE_RX (0 << 6)
66 #define S3C2410_IICSTAT_SLAVE_TX (1 << 6)
67 #define S3C2410_IICSTAT_MODEMASK (3 << 6)
69 #define S3C2410_IICSTAT_START (1 << 5)
70 #define S3C2410_IICSTAT_BUSBUSY (1 << 5)
71 #define S3C2410_IICSTAT_TXRXEN (1 << 4)
72 #define S3C2410_IICSTAT_ARBITR (1 << 3)
73 #define S3C2410_IICSTAT_ASSLAVE (1 << 2)
74 #define S3C2410_IICSTAT_ADDR0 (1 << 1)
75 #define S3C2410_IICSTAT_LASTBIT (1 << 0)
77 #define S3C2410_IICLC_SDA_DELAY0 (0 << 0)
78 #define S3C2410_IICLC_SDA_DELAY5 (1 << 0)
79 #define S3C2410_IICLC_SDA_DELAY10 (2 << 0)
80 #define S3C2410_IICLC_SDA_DELAY15 (3 << 0)
81 #define S3C2410_IICLC_SDA_DELAY_MASK (3 << 0)
83 #define S3C2410_IICLC_FILTER_ON (1 << 2)
85 /* Treat S3C2410 as baseline hardware, anything else is supported via quirks */
86 #define QUIRK_S3C2440 (1 << 0)
87 #define QUIRK_HDMIPHY (1 << 1)
88 #define QUIRK_NO_GPIO (1 << 2)
90 /* Max time to wait for bus to become idle after a xfer (in us) */
91 #define S3C2410_IDLE_TIMEOUT 5000
93 /* i2c controller state */
94 enum s3c24xx_i2c_state
{
103 wait_queue_head_t wait
;
105 unsigned int suspended
:1;
108 unsigned int msg_num
;
109 unsigned int msg_idx
;
110 unsigned int msg_ptr
;
112 unsigned int tx_setup
;
115 enum s3c24xx_i2c_state state
;
116 unsigned long clkrate
;
121 struct i2c_adapter adap
;
123 struct s3c2410_platform_i2c
*pdata
;
125 struct pinctrl
*pctrl
;
126 #ifdef CONFIG_CPU_FREQ
127 struct notifier_block freq_transition
;
131 static struct platform_device_id s3c24xx_driver_ids
[] = {
133 .name
= "s3c2410-i2c",
136 .name
= "s3c2440-i2c",
137 .driver_data
= QUIRK_S3C2440
,
139 .name
= "s3c2440-hdmiphy-i2c",
140 .driver_data
= QUIRK_S3C2440
| QUIRK_HDMIPHY
| QUIRK_NO_GPIO
,
143 MODULE_DEVICE_TABLE(platform
, s3c24xx_driver_ids
);
146 static const struct of_device_id s3c24xx_i2c_match
[] = {
147 { .compatible
= "samsung,s3c2410-i2c", .data
= (void *)0 },
148 { .compatible
= "samsung,s3c2440-i2c", .data
= (void *)QUIRK_S3C2440
},
149 { .compatible
= "samsung,s3c2440-hdmiphy-i2c",
150 .data
= (void *)(QUIRK_S3C2440
| QUIRK_HDMIPHY
| QUIRK_NO_GPIO
) },
151 { .compatible
= "samsung,exynos5440-i2c",
152 .data
= (void *)(QUIRK_S3C2440
| QUIRK_NO_GPIO
) },
155 MODULE_DEVICE_TABLE(of
, s3c24xx_i2c_match
);
158 /* s3c24xx_get_device_quirks
160 * Get controller type either from device tree or platform device variant.
163 static inline unsigned int s3c24xx_get_device_quirks(struct platform_device
*pdev
)
165 if (pdev
->dev
.of_node
) {
166 const struct of_device_id
*match
;
167 match
= of_match_node(s3c24xx_i2c_match
, pdev
->dev
.of_node
);
168 return (unsigned int)match
->data
;
171 return platform_get_device_id(pdev
)->driver_data
;
174 /* s3c24xx_i2c_master_complete
176 * complete the message and wake up the caller, using the given return code,
177 * or zero to mean ok.
180 static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c
*i2c
, int ret
)
182 dev_dbg(i2c
->dev
, "master_complete %d\n", ret
);
194 static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c
*i2c
)
198 tmp
= readl(i2c
->regs
+ S3C2410_IICCON
);
199 writel(tmp
& ~S3C2410_IICCON_ACKEN
, i2c
->regs
+ S3C2410_IICCON
);
202 static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c
*i2c
)
206 tmp
= readl(i2c
->regs
+ S3C2410_IICCON
);
207 writel(tmp
| S3C2410_IICCON_ACKEN
, i2c
->regs
+ S3C2410_IICCON
);
210 /* irq enable/disable functions */
212 static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c
*i2c
)
216 tmp
= readl(i2c
->regs
+ S3C2410_IICCON
);
217 writel(tmp
& ~S3C2410_IICCON_IRQEN
, i2c
->regs
+ S3C2410_IICCON
);
220 static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c
*i2c
)
224 tmp
= readl(i2c
->regs
+ S3C2410_IICCON
);
225 writel(tmp
| S3C2410_IICCON_IRQEN
, i2c
->regs
+ S3C2410_IICCON
);
229 /* s3c24xx_i2c_message_start
231 * put the start of a message onto the bus
234 static void s3c24xx_i2c_message_start(struct s3c24xx_i2c
*i2c
,
237 unsigned int addr
= (msg
->addr
& 0x7f) << 1;
239 unsigned long iiccon
;
242 stat
|= S3C2410_IICSTAT_TXRXEN
;
244 if (msg
->flags
& I2C_M_RD
) {
245 stat
|= S3C2410_IICSTAT_MASTER_RX
;
248 stat
|= S3C2410_IICSTAT_MASTER_TX
;
250 if (msg
->flags
& I2C_M_REV_DIR_ADDR
)
253 /* todo - check for whether ack wanted or not */
254 s3c24xx_i2c_enable_ack(i2c
);
256 iiccon
= readl(i2c
->regs
+ S3C2410_IICCON
);
257 writel(stat
, i2c
->regs
+ S3C2410_IICSTAT
);
259 dev_dbg(i2c
->dev
, "START: %08lx to IICSTAT, %02x to DS\n", stat
, addr
);
260 writeb(addr
, i2c
->regs
+ S3C2410_IICDS
);
262 /* delay here to ensure the data byte has gotten onto the bus
263 * before the transaction is started */
265 ndelay(i2c
->tx_setup
);
267 dev_dbg(i2c
->dev
, "iiccon, %08lx\n", iiccon
);
268 writel(iiccon
, i2c
->regs
+ S3C2410_IICCON
);
270 stat
|= S3C2410_IICSTAT_START
;
271 writel(stat
, i2c
->regs
+ S3C2410_IICSTAT
);
274 static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c
*i2c
, int ret
)
276 unsigned long iicstat
= readl(i2c
->regs
+ S3C2410_IICSTAT
);
278 dev_dbg(i2c
->dev
, "STOP\n");
281 * The datasheet says that the STOP sequence should be:
282 * 1) I2CSTAT.5 = 0 - Clear BUSY (or 'generate STOP')
283 * 2) I2CCON.4 = 0 - Clear IRQPEND
284 * 3) Wait until the stop condition takes effect.
285 * 4*) I2CSTAT.4 = 0 - Clear TXRXEN
287 * Where, step "4*" is only for buses with the "HDMIPHY" quirk.
289 * However, after much experimentation, it appears that:
290 * a) normal buses automatically clear BUSY and transition from
291 * Master->Slave when they complete generating a STOP condition.
292 * Therefore, step (3) can be done in doxfer() by polling I2CCON.4
293 * after starting the STOP generation here.
294 * b) HDMIPHY bus does neither, so there is no way to do step 3.
295 * There is no indication when this bus has finished generating
298 * In fact, we have found that as soon as the IRQPEND bit is cleared in
299 * step 2, the HDMIPHY bus generates the STOP condition, and then
300 * immediately starts transferring another data byte, even though the
301 * bus is supposedly stopped. This is presumably because the bus is
302 * still in "Master" mode, and its BUSY bit is still set.
304 * To avoid these extra post-STOP transactions on HDMI phy devices, we
305 * just disable Serial Output on the bus (I2CSTAT.4 = 0) directly,
306 * instead of first generating a proper STOP condition. This should
307 * float SDA & SCK terminating the transfer. Subsequent transfers
308 * start with a proper START condition, and proceed normally.
310 * The HDMIPHY bus is an internal bus that always has exactly two
311 * devices, the host as Master and the HDMIPHY device as the slave.
312 * Skipping the STOP condition has been tested on this bus and works.
314 if (i2c
->quirks
& QUIRK_HDMIPHY
) {
315 /* Stop driving the I2C pins */
316 iicstat
&= ~S3C2410_IICSTAT_TXRXEN
;
318 /* stop the transfer */
319 iicstat
&= ~S3C2410_IICSTAT_START
;
321 writel(iicstat
, i2c
->regs
+ S3C2410_IICSTAT
);
323 i2c
->state
= STATE_STOP
;
325 s3c24xx_i2c_master_complete(i2c
, ret
);
326 s3c24xx_i2c_disable_irq(i2c
);
329 /* helper functions to determine the current state in the set of
330 * messages we are sending */
334 * returns TRUE if the current message is the last in the set
337 static inline int is_lastmsg(struct s3c24xx_i2c
*i2c
)
339 return i2c
->msg_idx
>= (i2c
->msg_num
- 1);
344 * returns TRUE if we this is the last byte in the current message
347 static inline int is_msglast(struct s3c24xx_i2c
*i2c
)
349 /* msg->len is always 1 for the first byte of smbus block read.
350 * Actual length will be read from slave. More bytes will be
351 * read according to the length then. */
352 if (i2c
->msg
->flags
& I2C_M_RECV_LEN
&& i2c
->msg
->len
== 1)
355 return i2c
->msg_ptr
== i2c
->msg
->len
-1;
360 * returns TRUE if we reached the end of the current message
363 static inline int is_msgend(struct s3c24xx_i2c
*i2c
)
365 return i2c
->msg_ptr
>= i2c
->msg
->len
;
368 /* i2c_s3c_irq_nextbyte
370 * process an interrupt and work out what to do
373 static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c
*i2c
, unsigned long iicstat
)
379 switch (i2c
->state
) {
382 dev_err(i2c
->dev
, "%s: called in STATE_IDLE\n", __func__
);
386 dev_err(i2c
->dev
, "%s: called in STATE_STOP\n", __func__
);
387 s3c24xx_i2c_disable_irq(i2c
);
391 /* last thing we did was send a start condition on the
392 * bus, or started a new i2c message
395 if (iicstat
& S3C2410_IICSTAT_LASTBIT
&&
396 !(i2c
->msg
->flags
& I2C_M_IGNORE_NAK
)) {
397 /* ack was not received... */
399 dev_dbg(i2c
->dev
, "ack was not received\n");
400 s3c24xx_i2c_stop(i2c
, -ENXIO
);
404 if (i2c
->msg
->flags
& I2C_M_RD
)
405 i2c
->state
= STATE_READ
;
407 i2c
->state
= STATE_WRITE
;
409 /* terminate the transfer if there is nothing to do
410 * as this is used by the i2c probe to find devices. */
412 if (is_lastmsg(i2c
) && i2c
->msg
->len
== 0) {
413 s3c24xx_i2c_stop(i2c
, 0);
417 if (i2c
->state
== STATE_READ
)
420 /* fall through to the write state, as we will need to
421 * send a byte as well */
424 /* we are writing data to the device... check for the
425 * end of the message, and if so, work out what to do
428 if (!(i2c
->msg
->flags
& I2C_M_IGNORE_NAK
)) {
429 if (iicstat
& S3C2410_IICSTAT_LASTBIT
) {
430 dev_dbg(i2c
->dev
, "WRITE: No Ack\n");
432 s3c24xx_i2c_stop(i2c
, -ECONNREFUSED
);
439 if (!is_msgend(i2c
)) {
440 byte
= i2c
->msg
->buf
[i2c
->msg_ptr
++];
441 writeb(byte
, i2c
->regs
+ S3C2410_IICDS
);
443 /* delay after writing the byte to allow the
444 * data setup time on the bus, as writing the
445 * data to the register causes the first bit
446 * to appear on SDA, and SCL will change as
447 * soon as the interrupt is acknowledged */
449 ndelay(i2c
->tx_setup
);
451 } else if (!is_lastmsg(i2c
)) {
452 /* we need to go to the next i2c message */
454 dev_dbg(i2c
->dev
, "WRITE: Next Message\n");
460 /* check to see if we need to do another message */
461 if (i2c
->msg
->flags
& I2C_M_NOSTART
) {
463 if (i2c
->msg
->flags
& I2C_M_RD
) {
464 /* cannot do this, the controller
465 * forces us to send a new START
466 * when we change direction */
468 s3c24xx_i2c_stop(i2c
, -EINVAL
);
473 /* send the new start */
474 s3c24xx_i2c_message_start(i2c
, i2c
->msg
);
475 i2c
->state
= STATE_START
;
481 s3c24xx_i2c_stop(i2c
, 0);
486 /* we have a byte of data in the data register, do
487 * something with it, and then work out whether we are
488 * going to do any more read/write
491 byte
= readb(i2c
->regs
+ S3C2410_IICDS
);
492 i2c
->msg
->buf
[i2c
->msg_ptr
++] = byte
;
494 /* Add actual length to read for smbus block read */
495 if (i2c
->msg
->flags
& I2C_M_RECV_LEN
&& i2c
->msg
->len
== 1)
496 i2c
->msg
->len
+= byte
;
498 if (is_msglast(i2c
)) {
499 /* last byte of buffer */
502 s3c24xx_i2c_disable_ack(i2c
);
504 } else if (is_msgend(i2c
)) {
505 /* ok, we've read the entire buffer, see if there
506 * is anything else we need to do */
508 if (is_lastmsg(i2c
)) {
509 /* last message, send stop and complete */
510 dev_dbg(i2c
->dev
, "READ: Send Stop\n");
512 s3c24xx_i2c_stop(i2c
, 0);
514 /* go to the next transfer */
515 dev_dbg(i2c
->dev
, "READ: Next Transfer\n");
526 /* acknowlegde the IRQ and get back on with the work */
529 tmp
= readl(i2c
->regs
+ S3C2410_IICCON
);
530 tmp
&= ~S3C2410_IICCON_IRQPEND
;
531 writel(tmp
, i2c
->regs
+ S3C2410_IICCON
);
538 * top level IRQ servicing routine
541 static irqreturn_t
s3c24xx_i2c_irq(int irqno
, void *dev_id
)
543 struct s3c24xx_i2c
*i2c
= dev_id
;
544 unsigned long status
;
547 status
= readl(i2c
->regs
+ S3C2410_IICSTAT
);
549 if (status
& S3C2410_IICSTAT_ARBITR
) {
550 /* deal with arbitration loss */
551 dev_err(i2c
->dev
, "deal with arbitration loss\n");
554 if (i2c
->state
== STATE_IDLE
) {
555 dev_dbg(i2c
->dev
, "IRQ: error i2c->state == IDLE\n");
557 tmp
= readl(i2c
->regs
+ S3C2410_IICCON
);
558 tmp
&= ~S3C2410_IICCON_IRQPEND
;
559 writel(tmp
, i2c
->regs
+ S3C2410_IICCON
);
563 /* pretty much this leaves us with the fact that we've
564 * transmitted or received whatever byte we last sent */
566 i2c_s3c_irq_nextbyte(i2c
, status
);
573 /* s3c24xx_i2c_set_master
575 * get the i2c bus for a master transaction
578 static int s3c24xx_i2c_set_master(struct s3c24xx_i2c
*i2c
)
580 unsigned long iicstat
;
583 while (timeout
-- > 0) {
584 iicstat
= readl(i2c
->regs
+ S3C2410_IICSTAT
);
586 if (!(iicstat
& S3C2410_IICSTAT_BUSBUSY
))
595 /* s3c24xx_i2c_wait_idle
597 * wait for the i2c bus to become idle.
600 static void s3c24xx_i2c_wait_idle(struct s3c24xx_i2c
*i2c
)
602 unsigned long iicstat
;
607 /* ensure the stop has been through the bus */
609 dev_dbg(i2c
->dev
, "waiting for bus idle\n");
611 start
= now
= ktime_get();
614 * Most of the time, the bus is already idle within a few usec of the
615 * end of a transaction. However, really slow i2c devices can stretch
616 * the clock, delaying STOP generation.
618 * On slower SoCs this typically happens within a very small number of
619 * instructions so busy wait briefly to avoid scheduling overhead.
622 iicstat
= readl(i2c
->regs
+ S3C2410_IICSTAT
);
623 while ((iicstat
& S3C2410_IICSTAT_START
) && --spins
) {
625 iicstat
= readl(i2c
->regs
+ S3C2410_IICSTAT
);
629 * If we do get an appreciable delay as a compromise between idle
630 * detection latency for the normal, fast case, and system load in the
631 * slow device case, use an exponential back off in the polling loop,
632 * up to 1/10th of the total timeout, then continue to poll at a
633 * constant rate up to the timeout.
636 while ((iicstat
& S3C2410_IICSTAT_START
) &&
637 ktime_us_delta(now
, start
) < S3C2410_IDLE_TIMEOUT
) {
638 usleep_range(delay
, 2 * delay
);
639 if (delay
< S3C2410_IDLE_TIMEOUT
/ 10)
642 iicstat
= readl(i2c
->regs
+ S3C2410_IICSTAT
);
645 if (iicstat
& S3C2410_IICSTAT_START
)
646 dev_warn(i2c
->dev
, "timeout waiting for bus idle\n");
649 /* s3c24xx_i2c_doxfer
651 * this starts an i2c transfer
654 static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c
*i2c
,
655 struct i2c_msg
*msgs
, int num
)
657 unsigned long timeout
;
663 ret
= s3c24xx_i2c_set_master(i2c
);
665 dev_err(i2c
->dev
, "cannot get bus (error %d)\n", ret
);
674 i2c
->state
= STATE_START
;
676 s3c24xx_i2c_enable_irq(i2c
);
677 s3c24xx_i2c_message_start(i2c
, msgs
);
679 timeout
= wait_event_timeout(i2c
->wait
, i2c
->msg_num
== 0, HZ
* 5);
683 /* having these next two as dev_err() makes life very
684 * noisy when doing an i2cdetect */
687 dev_dbg(i2c
->dev
, "timeout\n");
689 dev_dbg(i2c
->dev
, "incomplete xfer (%d)\n", ret
);
691 /* For QUIRK_HDMIPHY, bus is already disabled */
692 if (i2c
->quirks
& QUIRK_HDMIPHY
)
695 s3c24xx_i2c_wait_idle(i2c
);
703 * first port of call from the i2c bus code when an message needs
704 * transferring across the i2c bus.
707 static int s3c24xx_i2c_xfer(struct i2c_adapter
*adap
,
708 struct i2c_msg
*msgs
, int num
)
710 struct s3c24xx_i2c
*i2c
= (struct s3c24xx_i2c
*)adap
->algo_data
;
714 pm_runtime_get_sync(&adap
->dev
);
715 clk_prepare_enable(i2c
->clk
);
717 for (retry
= 0; retry
< adap
->retries
; retry
++) {
719 ret
= s3c24xx_i2c_doxfer(i2c
, msgs
, num
);
721 if (ret
!= -EAGAIN
) {
722 clk_disable_unprepare(i2c
->clk
);
723 pm_runtime_put(&adap
->dev
);
727 dev_dbg(i2c
->dev
, "Retrying transmission (%d)\n", retry
);
732 clk_disable_unprepare(i2c
->clk
);
733 pm_runtime_put(&adap
->dev
);
737 /* declare our i2c functionality */
738 static u32
s3c24xx_i2c_func(struct i2c_adapter
*adap
)
740 return I2C_FUNC_I2C
| I2C_FUNC_SMBUS_EMUL
| I2C_FUNC_NOSTART
|
741 I2C_FUNC_PROTOCOL_MANGLING
;
744 /* i2c bus registration info */
746 static const struct i2c_algorithm s3c24xx_i2c_algorithm
= {
747 .master_xfer
= s3c24xx_i2c_xfer
,
748 .functionality
= s3c24xx_i2c_func
,
751 /* s3c24xx_i2c_calcdivisor
753 * return the divisor settings for a given frequency
756 static int s3c24xx_i2c_calcdivisor(unsigned long clkin
, unsigned int wanted
,
757 unsigned int *div1
, unsigned int *divs
)
759 unsigned int calc_divs
= clkin
/ wanted
;
760 unsigned int calc_div1
;
762 if (calc_divs
> (16*16))
767 calc_divs
+= calc_div1
-1;
768 calc_divs
/= calc_div1
;
778 return clkin
/ (calc_divs
* calc_div1
);
781 /* s3c24xx_i2c_clockrate
783 * work out a divisor for the user requested frequency setting,
784 * either by the requested frequency, or scanning the acceptable
785 * range of frequencies until something is found
788 static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c
*i2c
, unsigned int *got
)
790 struct s3c2410_platform_i2c
*pdata
= i2c
->pdata
;
791 unsigned long clkin
= clk_get_rate(i2c
->clk
);
792 unsigned int divs
, div1
;
793 unsigned long target_frequency
;
797 i2c
->clkrate
= clkin
;
798 clkin
/= 1000; /* clkin now in KHz */
800 dev_dbg(i2c
->dev
, "pdata desired frequency %lu\n", pdata
->frequency
);
802 target_frequency
= pdata
->frequency
? pdata
->frequency
: 100000;
804 target_frequency
/= 1000; /* Target frequency now in KHz */
806 freq
= s3c24xx_i2c_calcdivisor(clkin
, target_frequency
, &div1
, &divs
);
808 if (freq
> target_frequency
) {
810 "Unable to achieve desired frequency %luKHz." \
811 " Lowest achievable %dKHz\n", target_frequency
, freq
);
817 iiccon
= readl(i2c
->regs
+ S3C2410_IICCON
);
818 iiccon
&= ~(S3C2410_IICCON_SCALEMASK
| S3C2410_IICCON_TXDIV_512
);
822 iiccon
|= S3C2410_IICCON_TXDIV_512
;
824 writel(iiccon
, i2c
->regs
+ S3C2410_IICCON
);
826 if (i2c
->quirks
& QUIRK_S3C2440
) {
827 unsigned long sda_delay
;
829 if (pdata
->sda_delay
) {
830 sda_delay
= clkin
* pdata
->sda_delay
;
831 sda_delay
= DIV_ROUND_UP(sda_delay
, 1000000);
832 sda_delay
= DIV_ROUND_UP(sda_delay
, 5);
835 sda_delay
|= S3C2410_IICLC_FILTER_ON
;
839 dev_dbg(i2c
->dev
, "IICLC=%08lx\n", sda_delay
);
840 writel(sda_delay
, i2c
->regs
+ S3C2440_IICLC
);
846 #ifdef CONFIG_CPU_FREQ
848 #define freq_to_i2c(_n) container_of(_n, struct s3c24xx_i2c, freq_transition)
850 static int s3c24xx_i2c_cpufreq_transition(struct notifier_block
*nb
,
851 unsigned long val
, void *data
)
853 struct s3c24xx_i2c
*i2c
= freq_to_i2c(nb
);
858 delta_f
= clk_get_rate(i2c
->clk
) - i2c
->clkrate
;
860 /* if we're post-change and the input clock has slowed down
861 * or at pre-change and the clock is about to speed up, then
862 * adjust our clock rate. <0 is slow, >0 speedup.
865 if ((val
== CPUFREQ_POSTCHANGE
&& delta_f
< 0) ||
866 (val
== CPUFREQ_PRECHANGE
&& delta_f
> 0)) {
867 i2c_lock_adapter(&i2c
->adap
);
868 ret
= s3c24xx_i2c_clockrate(i2c
, &got
);
869 i2c_unlock_adapter(&i2c
->adap
);
872 dev_err(i2c
->dev
, "cannot find frequency\n");
874 dev_info(i2c
->dev
, "setting freq %d\n", got
);
880 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c
*i2c
)
882 i2c
->freq_transition
.notifier_call
= s3c24xx_i2c_cpufreq_transition
;
884 return cpufreq_register_notifier(&i2c
->freq_transition
,
885 CPUFREQ_TRANSITION_NOTIFIER
);
888 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c
*i2c
)
890 cpufreq_unregister_notifier(&i2c
->freq_transition
,
891 CPUFREQ_TRANSITION_NOTIFIER
);
895 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c
*i2c
)
900 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c
*i2c
)
906 static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c
*i2c
)
910 if (i2c
->quirks
& QUIRK_NO_GPIO
)
913 for (idx
= 0; idx
< 2; idx
++) {
914 gpio
= of_get_gpio(i2c
->dev
->of_node
, idx
);
915 if (!gpio_is_valid(gpio
)) {
916 dev_err(i2c
->dev
, "invalid gpio[%d]: %d\n", idx
, gpio
);
919 i2c
->gpios
[idx
] = gpio
;
921 ret
= gpio_request(gpio
, "i2c-bus");
923 dev_err(i2c
->dev
, "gpio [%d] request failed\n", gpio
);
931 gpio_free(i2c
->gpios
[idx
]);
935 static void s3c24xx_i2c_dt_gpio_free(struct s3c24xx_i2c
*i2c
)
939 if (i2c
->quirks
& QUIRK_NO_GPIO
)
942 for (idx
= 0; idx
< 2; idx
++)
943 gpio_free(i2c
->gpios
[idx
]);
946 static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c
*i2c
)
951 static void s3c24xx_i2c_dt_gpio_free(struct s3c24xx_i2c
*i2c
)
958 * initialise the controller, set the IO lines and frequency
961 static int s3c24xx_i2c_init(struct s3c24xx_i2c
*i2c
)
963 unsigned long iicon
= S3C2410_IICCON_IRQEN
| S3C2410_IICCON_ACKEN
;
964 struct s3c2410_platform_i2c
*pdata
;
967 /* get the plafrom data */
971 /* write slave address */
973 writeb(pdata
->slave_addr
, i2c
->regs
+ S3C2410_IICADD
);
975 dev_info(i2c
->dev
, "slave address 0x%02x\n", pdata
->slave_addr
);
977 writel(iicon
, i2c
->regs
+ S3C2410_IICCON
);
979 /* we need to work out the divisors for the clock... */
981 if (s3c24xx_i2c_clockrate(i2c
, &freq
) != 0) {
982 writel(0, i2c
->regs
+ S3C2410_IICCON
);
983 dev_err(i2c
->dev
, "cannot meet bus frequency required\n");
987 /* todo - check that the i2c lines aren't being dragged anywhere */
989 dev_info(i2c
->dev
, "bus frequency set to %d KHz\n", freq
);
990 dev_dbg(i2c
->dev
, "S3C2410_IICCON=0x%02lx\n", iicon
);
996 /* s3c24xx_i2c_parse_dt
998 * Parse the device tree node and retreive the platform data.
1002 s3c24xx_i2c_parse_dt(struct device_node
*np
, struct s3c24xx_i2c
*i2c
)
1004 struct s3c2410_platform_i2c
*pdata
= i2c
->pdata
;
1009 pdata
->bus_num
= -1; /* i2c bus number is dynamically assigned */
1010 of_property_read_u32(np
, "samsung,i2c-sda-delay", &pdata
->sda_delay
);
1011 of_property_read_u32(np
, "samsung,i2c-slave-addr", &pdata
->slave_addr
);
1012 of_property_read_u32(np
, "samsung,i2c-max-bus-freq",
1013 (u32
*)&pdata
->frequency
);
1017 s3c24xx_i2c_parse_dt(struct device_node
*np
, struct s3c24xx_i2c
*i2c
)
1023 /* s3c24xx_i2c_probe
1025 * called by the bus driver when a suitable device is found
1028 static int s3c24xx_i2c_probe(struct platform_device
*pdev
)
1030 struct s3c24xx_i2c
*i2c
;
1031 struct s3c2410_platform_i2c
*pdata
= NULL
;
1032 struct resource
*res
;
1035 if (!pdev
->dev
.of_node
) {
1036 pdata
= pdev
->dev
.platform_data
;
1038 dev_err(&pdev
->dev
, "no platform data\n");
1043 i2c
= devm_kzalloc(&pdev
->dev
, sizeof(struct s3c24xx_i2c
), GFP_KERNEL
);
1045 dev_err(&pdev
->dev
, "no memory for state\n");
1049 i2c
->pdata
= devm_kzalloc(&pdev
->dev
, sizeof(*pdata
), GFP_KERNEL
);
1051 dev_err(&pdev
->dev
, "no memory for platform data\n");
1055 i2c
->quirks
= s3c24xx_get_device_quirks(pdev
);
1057 memcpy(i2c
->pdata
, pdata
, sizeof(*pdata
));
1059 s3c24xx_i2c_parse_dt(pdev
->dev
.of_node
, i2c
);
1061 strlcpy(i2c
->adap
.name
, "s3c2410-i2c", sizeof(i2c
->adap
.name
));
1062 i2c
->adap
.owner
= THIS_MODULE
;
1063 i2c
->adap
.algo
= &s3c24xx_i2c_algorithm
;
1064 i2c
->adap
.retries
= 2;
1065 i2c
->adap
.class = I2C_CLASS_HWMON
| I2C_CLASS_SPD
;
1068 init_waitqueue_head(&i2c
->wait
);
1070 /* find the clock and enable it */
1072 i2c
->dev
= &pdev
->dev
;
1073 i2c
->clk
= devm_clk_get(&pdev
->dev
, "i2c");
1074 if (IS_ERR(i2c
->clk
)) {
1075 dev_err(&pdev
->dev
, "cannot get clock\n");
1079 dev_dbg(&pdev
->dev
, "clock source %p\n", i2c
->clk
);
1082 /* map the registers */
1084 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1085 i2c
->regs
= devm_ioremap_resource(&pdev
->dev
, res
);
1087 if (IS_ERR(i2c
->regs
))
1088 return PTR_ERR(i2c
->regs
);
1090 dev_dbg(&pdev
->dev
, "registers %p (%p)\n",
1093 /* setup info block for the i2c core */
1095 i2c
->adap
.algo_data
= i2c
;
1096 i2c
->adap
.dev
.parent
= &pdev
->dev
;
1098 i2c
->pctrl
= devm_pinctrl_get_select_default(i2c
->dev
);
1100 /* inititalise the i2c gpio lines */
1102 if (i2c
->pdata
->cfg_gpio
) {
1103 i2c
->pdata
->cfg_gpio(to_platform_device(i2c
->dev
));
1104 } else if (IS_ERR(i2c
->pctrl
) && s3c24xx_i2c_parse_dt_gpio(i2c
)) {
1108 /* initialise the i2c controller */
1110 clk_prepare_enable(i2c
->clk
);
1111 ret
= s3c24xx_i2c_init(i2c
);
1112 clk_disable_unprepare(i2c
->clk
);
1114 dev_err(&pdev
->dev
, "I2C controller init failed\n");
1117 /* find the IRQ for this unit (note, this relies on the init call to
1118 * ensure no current IRQs pending
1121 i2c
->irq
= ret
= platform_get_irq(pdev
, 0);
1123 dev_err(&pdev
->dev
, "cannot find IRQ\n");
1127 ret
= devm_request_irq(&pdev
->dev
, i2c
->irq
, s3c24xx_i2c_irq
, 0,
1128 dev_name(&pdev
->dev
), i2c
);
1131 dev_err(&pdev
->dev
, "cannot claim IRQ %d\n", i2c
->irq
);
1135 ret
= s3c24xx_i2c_register_cpufreq(i2c
);
1137 dev_err(&pdev
->dev
, "failed to register cpufreq notifier\n");
1141 /* Note, previous versions of the driver used i2c_add_adapter()
1142 * to add the bus at any number. We now pass the bus number via
1143 * the platform data, so if unset it will now default to always
1147 i2c
->adap
.nr
= i2c
->pdata
->bus_num
;
1148 i2c
->adap
.dev
.of_node
= pdev
->dev
.of_node
;
1150 ret
= i2c_add_numbered_adapter(&i2c
->adap
);
1152 dev_err(&pdev
->dev
, "failed to add bus to i2c core\n");
1153 s3c24xx_i2c_deregister_cpufreq(i2c
);
1157 of_i2c_register_devices(&i2c
->adap
);
1158 platform_set_drvdata(pdev
, i2c
);
1160 pm_runtime_enable(&pdev
->dev
);
1161 pm_runtime_enable(&i2c
->adap
.dev
);
1163 dev_info(&pdev
->dev
, "%s: S3C I2C adapter\n", dev_name(&i2c
->adap
.dev
));
1167 /* s3c24xx_i2c_remove
1169 * called when device is removed from the bus
1172 static int s3c24xx_i2c_remove(struct platform_device
*pdev
)
1174 struct s3c24xx_i2c
*i2c
= platform_get_drvdata(pdev
);
1176 pm_runtime_disable(&i2c
->adap
.dev
);
1177 pm_runtime_disable(&pdev
->dev
);
1179 s3c24xx_i2c_deregister_cpufreq(i2c
);
1181 i2c_del_adapter(&i2c
->adap
);
1183 clk_disable_unprepare(i2c
->clk
);
1185 if (pdev
->dev
.of_node
&& IS_ERR(i2c
->pctrl
))
1186 s3c24xx_i2c_dt_gpio_free(i2c
);
1191 #ifdef CONFIG_PM_SLEEP
1192 static int s3c24xx_i2c_suspend_noirq(struct device
*dev
)
1194 struct platform_device
*pdev
= to_platform_device(dev
);
1195 struct s3c24xx_i2c
*i2c
= platform_get_drvdata(pdev
);
1202 static int s3c24xx_i2c_resume(struct device
*dev
)
1204 struct platform_device
*pdev
= to_platform_device(dev
);
1205 struct s3c24xx_i2c
*i2c
= platform_get_drvdata(pdev
);
1208 clk_prepare_enable(i2c
->clk
);
1209 s3c24xx_i2c_init(i2c
);
1210 clk_disable_unprepare(i2c
->clk
);
1217 static const struct dev_pm_ops s3c24xx_i2c_dev_pm_ops
= {
1218 #ifdef CONFIG_PM_SLEEP
1219 .suspend_noirq
= s3c24xx_i2c_suspend_noirq
,
1220 .resume
= s3c24xx_i2c_resume
,
1224 #define S3C24XX_DEV_PM_OPS (&s3c24xx_i2c_dev_pm_ops)
1226 #define S3C24XX_DEV_PM_OPS NULL
1229 /* device driver for platform bus bits */
1231 static struct platform_driver s3c24xx_i2c_driver
= {
1232 .probe
= s3c24xx_i2c_probe
,
1233 .remove
= s3c24xx_i2c_remove
,
1234 .id_table
= s3c24xx_driver_ids
,
1236 .owner
= THIS_MODULE
,
1238 .pm
= S3C24XX_DEV_PM_OPS
,
1239 .of_match_table
= of_match_ptr(s3c24xx_i2c_match
),
1243 static int __init
i2c_adap_s3c_init(void)
1245 return platform_driver_register(&s3c24xx_i2c_driver
);
1247 subsys_initcall(i2c_adap_s3c_init
);
1249 static void __exit
i2c_adap_s3c_exit(void)
1251 platform_driver_unregister(&s3c24xx_i2c_driver
);
1253 module_exit(i2c_adap_s3c_exit
);
1255 MODULE_DESCRIPTION("S3C24XX I2C Bus driver");
1256 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
1257 MODULE_LICENSE("GPL");