?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
inotify: fix race
[linux-2.6.22.y-op.git] / include / asm-x86_64 / apicdef.h
blob1dd40067c67c41b18e92298787cbd219bea8bee7
1 #ifndef __ASM_APICDEF_H
2 #define __ASM_APICDEF_H
3
4 /*
5 * Constants for various Intel APICs. (local APIC, IOAPIC, etc.)
6 *
7 * Alan Cox <Alan.Cox@linux.org>, 1995.
8 * Ingo Molnar <mingo@redhat.com>, 1999, 2000
9 */
10
11 #define APIC_DEFAULT_PHYS_BASE 0xfee00000
12
13 #define APIC_ID 0x20
14 #define APIC_ID_MASK (0xFFu<<24)
15 #define GET_APIC_ID(x) (((x)>>24)&0xFFu)
16 #define SET_APIC_ID(x) (((x)<<24))
17 #define APIC_LVR 0x30
18 #define APIC_LVR_MASK 0xFF00FF
19 #define GET_APIC_VERSION(x) ((x)&0xFFu)
20 #define GET_APIC_MAXLVT(x) (((x)>>16)&0xFFu)
21 #define APIC_INTEGRATED(x) ((x)&0xF0u)
22 #define APIC_TASKPRI 0x80
23 #define APIC_TPRI_MASK 0xFFu
24 #define APIC_ARBPRI 0x90
25 #define APIC_ARBPRI_MASK 0xFFu
26 #define APIC_PROCPRI 0xA0
27 #define APIC_EOI 0xB0
28 #define APIC_EIO_ACK 0x0 /* Write this to the EOI register */
29 #define APIC_RRR 0xC0
30 #define APIC_LDR 0xD0
31 #define APIC_LDR_MASK (0xFFu<<24)
32 #define GET_APIC_LOGICAL_ID(x) (((x)>>24)&0xFFu)
33 #define SET_APIC_LOGICAL_ID(x) (((x)<<24))
34 #define APIC_ALL_CPUS 0xFFu
35 #define APIC_DFR 0xE0
36 #define APIC_DFR_CLUSTER 0x0FFFFFFFul
37 #define APIC_DFR_FLAT 0xFFFFFFFFul
38 #define APIC_SPIV 0xF0
39 #define APIC_SPIV_FOCUS_DISABLED (1<<9)
40 #define APIC_SPIV_APIC_ENABLED (1<<8)
41 #define APIC_ISR 0x100
42 #define APIC_ISR_NR 0x8 /* Number of 32 bit ISR registers. */
43 #define APIC_TMR 0x180
44 #define APIC_IRR 0x200
45 #define APIC_ESR 0x280
46 #define APIC_ESR_SEND_CS 0x00001
47 #define APIC_ESR_RECV_CS 0x00002
48 #define APIC_ESR_SEND_ACC 0x00004
49 #define APIC_ESR_RECV_ACC 0x00008
50 #define APIC_ESR_SENDILL 0x00020
51 #define APIC_ESR_RECVILL 0x00040
52 #define APIC_ESR_ILLREGA 0x00080
53 #define APIC_ICR 0x300
54 #define APIC_DEST_SELF 0x40000
55 #define APIC_DEST_ALLINC 0x80000
56 #define APIC_DEST_ALLBUT 0xC0000
57 #define APIC_ICR_RR_MASK 0x30000
58 #define APIC_ICR_RR_INVALID 0x00000
59 #define APIC_ICR_RR_INPROG 0x10000
60 #define APIC_ICR_RR_VALID 0x20000
61 #define APIC_INT_LEVELTRIG 0x08000
62 #define APIC_INT_ASSERT 0x04000
63 #define APIC_ICR_BUSY 0x01000
64 #define APIC_DEST_LOGICAL 0x00800
65 #define APIC_DEST_PHYSICAL 0x00000
66 #define APIC_DM_FIXED 0x00000
67 #define APIC_DM_LOWEST 0x00100
68 #define APIC_DM_SMI 0x00200
69 #define APIC_DM_REMRD 0x00300
70 #define APIC_DM_NMI 0x00400
71 #define APIC_DM_INIT 0x00500
72 #define APIC_DM_STARTUP 0x00600
73 #define APIC_DM_EXTINT 0x00700
74 #define APIC_VECTOR_MASK 0x000FF
75 #define APIC_ICR2 0x310
76 #define GET_APIC_DEST_FIELD(x) (((x)>>24)&0xFF)
77 #define SET_APIC_DEST_FIELD(x) ((x)<<24)
78 #define APIC_LVTT 0x320
79 #define APIC_LVTTHMR 0x330
80 #define APIC_LVTPC 0x340
81 #define APIC_LVT0 0x350
82 #define APIC_LVT_TIMER_BASE_MASK (0x3<<18)
83 #define GET_APIC_TIMER_BASE(x) (((x)>>18)&0x3)
84 #define SET_APIC_TIMER_BASE(x) (((x)<<18))
85 #define APIC_TIMER_BASE_CLKIN 0x0
86 #define APIC_TIMER_BASE_TMBASE 0x1
87 #define APIC_TIMER_BASE_DIV 0x2
88 #define APIC_LVT_TIMER_PERIODIC (1<<17)
89 #define APIC_LVT_MASKED (1<<16)
90 #define APIC_LVT_LEVEL_TRIGGER (1<<15)
91 #define APIC_LVT_REMOTE_IRR (1<<14)
92 #define APIC_INPUT_POLARITY (1<<13)
93 #define APIC_SEND_PENDING (1<<12)
94 #define APIC_MODE_MASK 0x700
95 #define GET_APIC_DELIVERY_MODE(x) (((x)>>8)&0x7)
96 #define SET_APIC_DELIVERY_MODE(x,y) (((x)&~0x700)|((y)<<8))
97 #define APIC_MODE_FIXED 0x0
98 #define APIC_MODE_NMI 0x4
99 #define APIC_MODE_EXTINT 0x7
100 #define APIC_LVT1 0x360
101 #define APIC_LVTERR 0x370
102 #define APIC_TMICT 0x380
103 #define APIC_TMCCT 0x390
104 #define APIC_TDCR 0x3E0
105 #define APIC_TDR_DIV_TMBASE (1<<2)
106 #define APIC_TDR_DIV_1 0xB
107 #define APIC_TDR_DIV_2 0x0
108 #define APIC_TDR_DIV_4 0x1
109 #define APIC_TDR_DIV_8 0x2
110 #define APIC_TDR_DIV_16 0x3
111 #define APIC_TDR_DIV_32 0x8
112 #define APIC_TDR_DIV_64 0x9
113 #define APIC_TDR_DIV_128 0xA
114
115 #define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
116
117 #define MAX_IO_APICS 128
118 #define MAX_LOCAL_APIC 256
119
120 /*
121 * All x86-64 systems are xAPIC compatible.
122 * In the following, "apicid" is a physical APIC ID.
123 */
124 #define XAPIC_DEST_CPUS_SHIFT 4
125 #define XAPIC_DEST_CPUS_MASK ((1u << XAPIC_DEST_CPUS_SHIFT) - 1)
126 #define XAPIC_DEST_CLUSTER_MASK (XAPIC_DEST_CPUS_MASK << XAPIC_DEST_CPUS_SHIFT)
127 #define APIC_CLUSTER(apicid) ((apicid) & XAPIC_DEST_CLUSTER_MASK)
128 #define APIC_CLUSTERID(apicid) (APIC_CLUSTER(apicid) >> XAPIC_DEST_CPUS_SHIFT)
129 #define APIC_CPUID(apicid) ((apicid) & XAPIC_DEST_CPUS_MASK)
130 #define NUM_APIC_CLUSTERS ((BAD_APICID + 1) >> XAPIC_DEST_CPUS_SHIFT)
131
132 /*
133 * the local APIC register structure, memory mapped. Not terribly well
134 * tested, but we might eventually use this one in the future - the
135 * problem why we cannot use it right now is the P5 APIC, it has an
136 * errata which cannot take 8-bit reads and writes, only 32-bit ones ...
137 */
138 #define u32 unsigned int
139
140 struct local_apic {
141
142 /*000*/ struct { u32 __reserved[4]; } __reserved_01;
143
144 /*010*/ struct { u32 __reserved[4]; } __reserved_02;
145
146 /*020*/ struct { /* APIC ID Register */
147 u32 __reserved_1 : 24,
148 phys_apic_id : 4,
149 __reserved_2 : 4;
150 u32 __reserved[3];
151 } id;
152
153 /*030*/ const
154 struct { /* APIC Version Register */
155 u32 version : 8,
156 __reserved_1 : 8,
157 max_lvt : 8,
158 __reserved_2 : 8;
159 u32 __reserved[3];
160 } version;
161
162 /*040*/ struct { u32 __reserved[4]; } __reserved_03;
163
164 /*050*/ struct { u32 __reserved[4]; } __reserved_04;
165
166 /*060*/ struct { u32 __reserved[4]; } __reserved_05;
167
168 /*070*/ struct { u32 __reserved[4]; } __reserved_06;
169
170 /*080*/ struct { /* Task Priority Register */
171 u32 priority : 8,
172 __reserved_1 : 24;
173 u32 __reserved_2[3];
174 } tpr;
175
176 /*090*/ const
177 struct { /* Arbitration Priority Register */
178 u32 priority : 8,
179 __reserved_1 : 24;
180 u32 __reserved_2[3];
181 } apr;
182
183 /*0A0*/ const
184 struct { /* Processor Priority Register */
185 u32 priority : 8,
186 __reserved_1 : 24;
187 u32 __reserved_2[3];
188 } ppr;
189
190 /*0B0*/ struct { /* End Of Interrupt Register */
191 u32 eoi;
192 u32 __reserved[3];
193 } eoi;
194
195 /*0C0*/ struct { u32 __reserved[4]; } __reserved_07;
196
197 /*0D0*/ struct { /* Logical Destination Register */
198 u32 __reserved_1 : 24,
199 logical_dest : 8;
200 u32 __reserved_2[3];
201 } ldr;
202
203 /*0E0*/ struct { /* Destination Format Register */
204 u32 __reserved_1 : 28,
205 model : 4;
206 u32 __reserved_2[3];
207 } dfr;
208
209 /*0F0*/ struct { /* Spurious Interrupt Vector Register */
210 u32 spurious_vector : 8,
211 apic_enabled : 1,
212 focus_cpu : 1,
213 __reserved_2 : 22;
214 u32 __reserved_3[3];
215 } svr;
216
217 /*100*/ struct { /* In Service Register */
218 /*170*/ u32 bitfield;
219 u32 __reserved[3];
220 } isr [8];
221
222 /*180*/ struct { /* Trigger Mode Register */
223 /*1F0*/ u32 bitfield;
224 u32 __reserved[3];
225 } tmr [8];
226
227 /*200*/ struct { /* Interrupt Request Register */
228 /*270*/ u32 bitfield;
229 u32 __reserved[3];
230 } irr [8];
231
232 /*280*/ union { /* Error Status Register */
233 struct {
234 u32 send_cs_error : 1,
235 receive_cs_error : 1,
236 send_accept_error : 1,
237 receive_accept_error : 1,
238 __reserved_1 : 1,
239 send_illegal_vector : 1,
240 receive_illegal_vector : 1,
241 illegal_register_address : 1,
242 __reserved_2 : 24;
243 u32 __reserved_3[3];
244 } error_bits;
245 struct {
246 u32 errors;
247 u32 __reserved_3[3];
248 } all_errors;
249 } esr;
250
251 /*290*/ struct { u32 __reserved[4]; } __reserved_08;
252
253 /*2A0*/ struct { u32 __reserved[4]; } __reserved_09;
254
255 /*2B0*/ struct { u32 __reserved[4]; } __reserved_10;
256
257 /*2C0*/ struct { u32 __reserved[4]; } __reserved_11;
258
259 /*2D0*/ struct { u32 __reserved[4]; } __reserved_12;
260
261 /*2E0*/ struct { u32 __reserved[4]; } __reserved_13;
262
263 /*2F0*/ struct { u32 __reserved[4]; } __reserved_14;
264
265 /*300*/ struct { /* Interrupt Command Register 1 */
266 u32 vector : 8,
267 delivery_mode : 3,
268 destination_mode : 1,
269 delivery_status : 1,
270 __reserved_1 : 1,
271 level : 1,
272 trigger : 1,
273 __reserved_2 : 2,
274 shorthand : 2,
275 __reserved_3 : 12;
276 u32 __reserved_4[3];
277 } icr1;
278
279 /*310*/ struct { /* Interrupt Command Register 2 */
280 union {
281 u32 __reserved_1 : 24,
282 phys_dest : 4,
283 __reserved_2 : 4;
284 u32 __reserved_3 : 24,
285 logical_dest : 8;
286 } dest;
287 u32 __reserved_4[3];
288 } icr2;
289
290 /*320*/ struct { /* LVT - Timer */
291 u32 vector : 8,
292 __reserved_1 : 4,
293 delivery_status : 1,
294 __reserved_2 : 3,
295 mask : 1,
296 timer_mode : 1,
297 __reserved_3 : 14;
298 u32 __reserved_4[3];
299 } lvt_timer;
300
301 /*330*/ struct { /* LVT - Thermal Sensor */
302 u32 vector : 8,
303 delivery_mode : 3,
304 __reserved_1 : 1,
305 delivery_status : 1,
306 __reserved_2 : 3,
307 mask : 1,
308 __reserved_3 : 15;
309 u32 __reserved_4[3];
310 } lvt_thermal;
311
312 /*340*/ struct { /* LVT - Performance Counter */
313 u32 vector : 8,
314 delivery_mode : 3,
315 __reserved_1 : 1,
316 delivery_status : 1,
317 __reserved_2 : 3,
318 mask : 1,
319 __reserved_3 : 15;
320 u32 __reserved_4[3];
321 } lvt_pc;
322
323 /*350*/ struct { /* LVT - LINT0 */
324 u32 vector : 8,
325 delivery_mode : 3,
326 __reserved_1 : 1,
327 delivery_status : 1,
328 polarity : 1,
329 remote_irr : 1,
330 trigger : 1,
331 mask : 1,
332 __reserved_2 : 15;
333 u32 __reserved_3[3];
334 } lvt_lint0;
335
336 /*360*/ struct { /* LVT - LINT1 */
337 u32 vector : 8,
338 delivery_mode : 3,
339 __reserved_1 : 1,
340 delivery_status : 1,
341 polarity : 1,
342 remote_irr : 1,
343 trigger : 1,
344 mask : 1,
345 __reserved_2 : 15;
346 u32 __reserved_3[3];
347 } lvt_lint1;
348
349 /*370*/ struct { /* LVT - Error */
350 u32 vector : 8,
351 __reserved_1 : 4,
352 delivery_status : 1,
353 __reserved_2 : 3,
354 mask : 1,
355 __reserved_3 : 15;
356 u32 __reserved_4[3];
357 } lvt_error;
358
359 /*380*/ struct { /* Timer Initial Count Register */
360 u32 initial_count;
361 u32 __reserved_2[3];
362 } timer_icr;
363
364 /*390*/ const
365 struct { /* Timer Current Count Register */
366 u32 curr_count;
367 u32 __reserved_2[3];
368 } timer_ccr;
369
370 /*3A0*/ struct { u32 __reserved[4]; } __reserved_16;
371
372 /*3B0*/ struct { u32 __reserved[4]; } __reserved_17;
373
374 /*3C0*/ struct { u32 __reserved[4]; } __reserved_18;
375
376 /*3D0*/ struct { u32 __reserved[4]; } __reserved_19;
377
378 /*3E0*/ struct { /* Timer Divide Configuration Register */
379 u32 divisor : 4,
380 __reserved_1 : 28;
381 u32 __reserved_2[3];
382 } timer_dcr;
383
384 /*3F0*/ struct { u32 __reserved[4]; } __reserved_20;
385
386 } __attribute__ ((packed));
387
388 #undef u32
389
390 #define BAD_APICID 0xFFu
391
392 #endif
linux v2.6.22.y-op