firmware/target/arm/imx31/gigabeat-s/mc13783-imx31.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (c) 2008 by Michael Sevakis
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21 #include "system.h"
  22 #include "cpu.h"
  23 #include "spi-imx31.h"
  24 #include "gpio-imx31.h"
  25 #include "mc13783.h"
  26 #include "debug.h"
  27 #include "kernel.h"
  28
  29 #include "power-imx31.h"
  30 #include "button-target.h"
  31 #include "adc-target.h"
  32 #include "usb-target.h"
  33
  34 #ifdef BOOTLOADER
  35 #define PMIC_DRIVER_CLOSE
  36 #endif
  37
  38 /* This is all based on communicating with the MC13783 PMU which is on
  39  * CSPI2 with the chip select at 0. The LCD controller resides on
  40  * CSPI3 cs1, but we have no idea how to communicate to it */
  41 static struct spi_node mc13783_spi =
  42 {
  43     CSPI2_NUM,                     /* CSPI module 2 */
  44     CSPI_CONREG_CHIP_SELECT_SS0 |  /* Chip select 0 */
  45     CSPI_CONREG_DRCTL_DONT_CARE |  /* Don't care about CSPI_RDY */
  46     CSPI_CONREG_DATA_RATE_DIV_4 |  /* Clock = IPG_CLK/4 - 16.5MHz */
  47     CSPI_BITCOUNT(32-1) |          /* All 32 bits are to be transferred */
  48     CSPI_CONREG_SSPOL |            /* SS active high */
  49     CSPI_CONREG_SSCTL |            /* Negate SS between SPI bursts */
  50     CSPI_CONREG_MODE,              /* Master mode */
  51     0,                             /* SPI clock - no wait states */
  52 };
  53
  54 extern const struct mc13783_event_list mc13783_event_list;
  55
  56 static int mc13783_thread_stack[DEFAULT_STACK_SIZE/sizeof(int)];
  57 static const char *mc13783_thread_name = "pmic";
  58 static struct wakeup mc13783_wake;
  59
  60 /* Tracking for which interrupts are enabled */
  61 static uint32_t pmic_int_enabled[2] =
  62     { 0x00000000, 0x00000000 };
  63
  64 static const unsigned char pmic_intm_regs[2] =
  65     { MC13783_INTERRUPT_MASK0, MC13783_INTERRUPT_MASK1 };
  66
  67 static const unsigned char pmic_ints_regs[2] =
  68     { MC13783_INTERRUPT_STATUS0, MC13783_INTERRUPT_STATUS1 };
  69
  70 #ifdef PMIC_DRIVER_CLOSE
  71 static bool pmic_close = false;
  72 static struct thread_entry *mc13783_thread_p = NULL;
  73 #endif
  74
  75 static void mc13783_interrupt_thread(void)
  76 {
  77     uint32_t pending[2];
  78
  79     /* Enable mc13783 GPIO event */
  80     gpio_enable_event(MC13783_EVENT_ID);
  81
  82     while (1)
  83     {
  84         const struct mc13783_event *event, *event_last;
  85
  86         wakeup_wait(&mc13783_wake, TIMEOUT_BLOCK);
  87
  88 #ifdef PMIC_DRIVER_CLOSE
  89         if (pmic_close)
  90             break;
  91 #endif
  92
  93         mc13783_read_regset(pmic_ints_regs, pending, 2);
  94
  95         /* Only clear interrupts being dispatched */
  96         pending[0] &= pmic_int_enabled[0];
  97         pending[1] &= pmic_int_enabled[1];
  98
  99         mc13783_write_regset(pmic_ints_regs, pending, 2);
 100
 101         event = mc13783_event_list.events;
 102         event_last = event + mc13783_event_list.count;
 103
 104         /* .count is surely expected to be > 0 */
 105         do
 106         {
 107             enum mc13783_event_sets set = event->set;
 108             uint32_t pnd = pending[set];
 109             uint32_t mask = event->mask;
 110
 111             if (pnd & mask)
 112             {
 113                 event->callback();
 114                 pnd &= ~mask;
 115                 pending[set] = pnd;
 116             }
 117
 118             if ((pending[0] | pending[1]) == 0)
 119                 break; /* Teminate early if nothing more to service */
 120         }
 121         while (++event < event_last);
 122     }
 123
 124 #ifdef PMIC_DRIVER_CLOSE
 125     gpio_disable_event(MC13783_EVENT_ID);
 126 #endif
 127 }
 128
 129 /* GPIO interrupt handler for mc13783 */
 130 void mc13783_event(void)
 131 {
 132     MC13783_GPIO_ISR = (1ul << MC13783_GPIO_LINE);
 133     wakeup_signal(&mc13783_wake);
 134 }
 135
 136 void mc13783_init(void)
 137 {
 138     /* Serial interface must have been initialized first! */
 139     wakeup_init(&mc13783_wake);
 140
 141     /* Enable the PMIC SPI module */
 142     spi_enable_module(&mc13783_spi);
 143
 144     /* Mask any PMIC interrupts for now - modules will enable them as
 145      * required */
 146     mc13783_write(MC13783_INTERRUPT_MASK0, 0xffffff);
 147     mc13783_write(MC13783_INTERRUPT_MASK1, 0xffffff);
 148
 149     MC13783_GPIO_ISR = (1ul << MC13783_GPIO_LINE);
 150
 151 #ifdef PMIC_DRIVER_CLOSE
 152     mc13783_thread_p =
 153 #endif
 154         create_thread(mc13783_interrupt_thread,
 155             mc13783_thread_stack, sizeof(mc13783_thread_stack), 0,
 156             mc13783_thread_name IF_PRIO(, PRIORITY_REALTIME) IF_COP(, CPU));
 157 }
 158
 159 #ifdef PMIC_DRIVER_CLOSE
 160 void mc13783_close(void)
 161 {
 162     struct thread_entry *thread = mc13783_thread_p;
 163
 164     if (thread == NULL)
 165         return;
 166
 167     mc13783_thread_p = NULL;
 168
 169     pmic_close = true;
 170     wakeup_signal(&mc13783_wake);
 171     thread_wait(thread);
 172 }
 173 #endif /* PMIC_DRIVER_CLOSE */
 174
 175 bool mc13783_enable_event(enum mc13783_event_ids id)
 176 {
 177     const struct mc13783_event * const event =
 178         &mc13783_event_list.events[id];
 179     int set = event->set;
 180     uint32_t mask = event->mask;
 181
 182     spi_lock(&mc13783_spi);
 183
 184     pmic_int_enabled[set] |= mask;
 185     mc13783_clear(pmic_intm_regs[set], mask);
 186
 187     spi_unlock(&mc13783_spi);
 188
 189     return true;
 190 }
 191
 192 void mc13783_disable_event(enum mc13783_event_ids id)
 193 {
 194     const struct mc13783_event * const event =
 195         &mc13783_event_list.events[id];
 196     int set = event->set;
 197     uint32_t mask = event->mask;
 198
 199     spi_lock(&mc13783_spi);
 200
 201     pmic_int_enabled[set] &= ~mask;
 202     mc13783_set(pmic_intm_regs[set], mask);
 203
 204     spi_unlock(&mc13783_spi);
 205 }
 206
 207 uint32_t mc13783_set(unsigned address, uint32_t bits)
 208 {
 209     spi_lock(&mc13783_spi);
 210
 211     uint32_t data = mc13783_read(address);
 212
 213     if (data != MC13783_DATA_ERROR)
 214         mc13783_write(address, data | bits);
 215
 216     spi_unlock(&mc13783_spi);
 217
 218     return data;
 219 }
 220
 221 uint32_t mc13783_clear(unsigned address, uint32_t bits)
 222 {
 223     spi_lock(&mc13783_spi);
 224
 225     uint32_t data = mc13783_read(address);
 226
 227     if (data != MC13783_DATA_ERROR)
 228         mc13783_write(address, data & ~bits);
 229
 230     spi_unlock(&mc13783_spi);
 231
 232     return data;
 233 }
 234
 235 int mc13783_write(unsigned address, uint32_t data)
 236 {
 237     struct spi_transfer xfer;
 238     uint32_t packet;
 239
 240     if (address >= MC13783_NUM_REGS)
 241         return -1;
 242
 243     packet = (1 << 31) | (address << 25) | (data & 0xffffff);
 244     xfer.txbuf = &packet;
 245     xfer.rxbuf = &packet;
 246     xfer.count = 1;
 247
 248     if (!spi_transfer(&mc13783_spi, &xfer))
 249         return -1;
 250
 251     return 1 - xfer.count;
 252 }
 253
 254 uint32_t mc13783_write_masked(unsigned address, uint32_t data, uint32_t mask)
 255 {
 256     uint32_t old;
 257
 258     spi_lock(&mc13783_spi);
 259
 260     old = mc13783_read(address);
 261
 262     if (old != MC13783_DATA_ERROR)
 263     {
 264         data = (old & ~mask) | (data & mask);
 265
 266         if (mc13783_write(address, data) != 1)
 267             old = MC13783_DATA_ERROR;
 268     }
 269
 270     spi_unlock(&mc13783_spi);
 271
 272     return old;
 273 }
 274
 275 int mc13783_write_regset(const unsigned char *regs, const uint32_t *data,
 276                          int count)
 277 {
 278     int i;
 279     struct spi_transfer xfer;
 280     uint32_t packets[MC13783_NUM_REGS];
 281
 282     if ((unsigned)count > MC13783_NUM_REGS)
 283         return -1;
 284
 285     for (i = 0; i < count; i++)
 286     {
 287         uint32_t reg = regs[i];
 288
 289         if (reg >= MC13783_NUM_REGS)
 290             return -1;
 291
 292         packets[i] = (1 << 31) | (reg << 25) | (data[i] & 0xffffff);
 293     }
 294
 295     xfer.txbuf = packets;
 296     xfer.rxbuf = packets;
 297     xfer.count = count;
 298
 299     if (!spi_transfer(&mc13783_spi, &xfer))
 300         return -1;
 301
 302     return count - xfer.count;
 303 }
 304
 305 uint32_t mc13783_read(unsigned address)
 306 {
 307     uint32_t packet;
 308     struct spi_transfer xfer;
 309
 310     if (address >= MC13783_NUM_REGS)
 311         return MC13783_DATA_ERROR;
 312
 313     packet = address << 25;
 314
 315     xfer.txbuf = &packet;
 316     xfer.rxbuf = &packet;
 317     xfer.count = 1;
 318
 319     if (!spi_transfer(&mc13783_spi, &xfer))
 320         return MC13783_DATA_ERROR;
 321
 322     return packet;
 323 }
 324
 325 int mc13783_read_regset(const unsigned char *regs, uint32_t *buffer,
 326                         int count)
 327 {
 328     int i;
 329     struct spi_transfer xfer;
 330
 331     if ((unsigned)count > MC13783_NUM_REGS)
 332         return -1;
 333
 334     for (i = 0; i < count; i++)
 335     {
 336         unsigned reg = regs[i];
 337
 338         if (reg >= MC13783_NUM_REGS)
 339             return -1;
 340
 341         buffer[i] = reg << 25;
 342     }
 343
 344     xfer.txbuf = buffer;
 345     xfer.rxbuf = buffer;
 346     xfer.count = count;
 347
 348     if (!spi_transfer(&mc13783_spi, &xfer))
 349         return -1;
 350
 351     return count - xfer.count;
 352 }