gdb/sh-stub.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2002 by Linus Nielsen Feltzing
  11  *
  12  * All files in this archive are subject to the GNU General Public License.
  13  * See the file COPYING in the source tree root for full license agreement.
  14  *
  15  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  16  * KIND, either express or implied.
  17  *
  18  ****************************************************************************/
  19 /* sh-stub.c -- debugging stub for the Hitachi-SH.
  20
  21  NOTE!! This code has to be compiled with optimization, otherwise the
  22  function inlining which generates the exception handlers won't work.
  23
  24 */
  25
  26 /*   This is originally based on an m68k software stub written by Glenn
  27      Engel at HP, but has changed quite a bit.
  28
  29      Modifications for the SH by Ben Lee and Steve Chamberlain
  30
  31      Even more modifications for GCC 3.0 and The Rockbox by Linus
  32      Nielsen Feltzing
  33 */
  34
  35 /****************************************************************************
  36
  37                 THIS SOFTWARE IS NOT COPYRIGHTED
  38
  39    HP offers the following for use in the public domain.  HP makes no
  40    warranty with regard to the software or it's performance and the
  41    user accepts the software "AS IS" with all faults.
  42
  43    HP DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD
  44    TO THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  45    OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
  46
  47 ****************************************************************************/
  48
  49
  50 /* Remote communication protocol.
  51
  52    A debug packet whose contents are <data>
  53    is encapsulated for transmission in the form:
  54
  55         $ <data> # CSUM1 CSUM2
  56
  57         <data> must be ASCII alphanumeric and cannot include characters
  58         '$' or '#'.  If <data> starts with two characters followed by
  59         ':', then the existing stubs interpret this as a sequence number.
  60
  61         CSUM1 and CSUM2 are ascii hex representation of an 8-bit
  62         checksum of <data>, the most significant nibble is sent first.
  63         the hex digits 0-9,a-f are used.
  64
  65    Receiver responds with:
  66
  67         +       - if CSUM is correct and ready for next packet
  68         -       - if CSUM is incorrect
  69
  70    <data> is as follows:
  71    All values are encoded in ascii hex digits.
  72
  73         Request         Packet
  74
  75         read registers  g
  76         reply           XX....X         Each byte of register data
  77                                         is described by two hex digits.
  78                                         Registers are in the internal order
  79                                         for GDB, and the bytes in a register
  80                                         are in the same order the machine uses.
  81                         or ENN          for an error.
  82
  83         write regs      GXX..XX         Each byte of register data
  84                                         is described by two hex digits.
  85         reply           OK              for success
  86                         ENN             for an error
  87
  88         write reg       Pn...=r...      Write register n... with value r...,
  89                                         which contains two hex digits for each
  90                                         byte in the register (target byte
  91                                         order).
  92         reply           OK              for success
  93                         ENN             for an error
  94         (not supported by all stubs).
  95
  96         read mem        mAA..AA,LLLL    AA..AA is address, LLLL is length.
  97         reply           XX..XX          XX..XX is mem contents
  98                                         Can be fewer bytes than requested
  99                                         if able to read only part of the data.
 100                         or ENN          NN is errno
 101
 102         write mem       MAA..AA,LLLL:XX..XX
 103                                         AA..AA is address,
 104                                         LLLL is number of bytes,
 105                                         XX..XX is data
 106         reply           OK              for success
 107                         ENN             for an error (this includes the case
 108                                         where only part of the data was
 109                                         written).
 110
 111         cont            cAA..AA         AA..AA is address to resume
 112                                         If AA..AA is omitted,
 113                                         resume at same address.
 114
 115         step            sAA..AA         AA..AA is address to resume
 116                                         If AA..AA is omitted,
 117                                         resume at same address.
 118
 119         last signal     ?               Reply the current reason for stopping.
 120                                         This is the same reply as is generated
 121                                         for step or cont : SAA where AA is the
 122                                         signal number.
 123
 124         There is no immediate reply to step or cont.
 125         The reply comes when the machine stops.
 126         It is           SAA             AA is the "signal number"
 127
 128         or...           TAAn...:r...;n:r...;n...:r...;
 129                                         AA = signal number
 130                                         n... = register number
 131                                         r... = register contents
 132         or...           WAA             The process exited, and AA is
 133                                         the exit status.  This is only
 134                                         applicable for certains sorts of
 135                                         targets.
 136         kill request    k
 137
 138         toggle debug    d               toggle debug flag (see 386 & 68k stubs)
 139         reset           r               reset -- see sparc stub.
 140         reserved        <other>         On other requests, the stub should
 141                                         ignore the request and send an empty
 142                                         response ($#<checksum>).  This way
 143                                         we can extend the protocol and GDB
 144                                         can tell whether the stub it is
 145                                         talking to uses the old or the new.
 146         search          tAA:PP,MM       Search backwards starting at address
 147                                         AA for a match with pattern PP and
 148                                         mask MM.  PP and MM are 4 bytes.
 149                                         Not supported by all stubs.
 150
 151         general query   qXXXX           Request info about XXXX.
 152         general set     QXXXX=yyyy      Set value of XXXX to yyyy.
 153         query sect offs qOffsets        Get section offsets.  Reply is
 154                                         Text=xxx;Data=yyy;Bss=zzz
 155         console output  Otext           Send text to stdout.  Only comes from
 156                                         remote target.
 157
 158         Responses can be run-length encoded to save space.  A '*' means that
 159         the next character is an ASCII encoding giving a repeat count which
 160         stands for that many repititions of the character preceding the '*'.
 161         The encoding is n+29, yielding a printable character where n >=3
 162         (which is where rle starts to win).  Don't use an n > 126.
 163
 164         So
 165         "0* " means the same as "0000".  */
 166
 167 #include "sh7034.h"
 168 #include <string.h>
 169 #include <setjmp.h>
 170 #include <signal.h>
 171
 172 /* We need to undefine this from the sh7034.h file */
 173 #undef GBR
 174
 175 /* Hitachi SH architecture instruction encoding masks */
 176
 177 #define COND_BR_MASK   0xff00
 178 #define UCOND_DBR_MASK 0xe000
 179 #define UCOND_RBR_MASK 0xf0df
 180 #define TRAPA_MASK     0xff00
 181
 182 #define COND_DISP      0x00ff
 183 #define UCOND_DISP     0x0fff
 184 #define UCOND_REG      0x0f00
 185
 186 /* Hitachi SH instruction opcodes */
 187
 188 #define BF_INSTR       0x8b00
 189 #define BT_INSTR       0x8900
 190 #define BRA_INSTR      0xa000
 191 #define BSR_INSTR      0xb000
 192 #define JMP_INSTR      0x402b
 193 #define JSR_INSTR      0x400b
 194 #define RTS_INSTR      0x000b
 195 #define RTE_INSTR      0x002b
 196 #define TRAPA_INSTR    0xc300
 197 #define SSTEP_INSTR    0xc37f
 198
 199 /* Hitachi SH processor register masks */
 200
 201 #define T_BIT_MASK     0x0001
 202
 203 /*
 204  * BUFMAX defines the maximum number of characters in inbound/outbound
 205  * buffers. At least NUMREGBYTES*2 are needed for register packets.
 206  */
 207 #define BUFMAX 1024
 208
 209 /*
 210  * Number of bytes for registers
 211  */
 212 #define NUMREGBYTES 112         /* 92 */
 213
 214 /*
 215  * Forward declarations
 216  */
 217
 218 static int hex (char);
 219 static char *mem2hex (char *mem, char *buf, int count);
 220 static char *hex2mem (char *buf, char *mem, int count);
 221 static int hex2int (char **ptr, int *intValue);
 222 static unsigned char *getpacket (void);
 223 static void putpacket (register char *buffer);
 224 static int computeSignal (int exceptionVector);
 225 void handle_buserror (void);
 226 void handle_exception (int exceptionVector);
 227 void init_serial(void);
 228
 229 void serial_putc (char ch);
 230 char serial_getc (void);
 231
 232 /* These are in the file but in asm statements so the compiler can't see them */
 233 void catch_exception_4 (void);
 234 void catch_exception_5 (void);
 235 void catch_exception_6 (void);
 236 void catch_exception_7 (void);
 237 void catch_exception_8 (void);
 238 void catch_exception_9 (void);
 239 void catch_exception_10 (void);
 240 void catch_exception_11 (void);
 241 void catch_exception_12 (void);
 242 void catch_exception_13 (void);
 243 void catch_exception_14 (void);
 244 void catch_exception_15 (void);
 245 void catch_exception_16 (void);
 246 void catch_exception_17 (void);
 247 void catch_exception_18 (void);
 248 void catch_exception_19 (void);
 249 void catch_exception_20 (void);
 250 void catch_exception_21 (void);
 251 void catch_exception_22 (void);
 252 void catch_exception_23 (void);
 253 void catch_exception_24 (void);
 254 void catch_exception_25 (void);
 255 void catch_exception_26 (void);
 256 void catch_exception_27 (void);
 257 void catch_exception_28 (void);
 258 void catch_exception_29 (void);
 259 void catch_exception_30 (void);
 260 void catch_exception_31 (void);
 261 void catch_exception_32 (void);
 262 void catch_exception_33 (void);
 263 void catch_exception_34 (void);
 264 void catch_exception_35 (void);
 265 void catch_exception_36 (void);
 266 void catch_exception_37 (void);
 267 void catch_exception_38 (void);
 268 void catch_exception_39 (void);
 269 void catch_exception_40 (void);
 270 void catch_exception_41 (void);
 271 void catch_exception_42 (void);
 272 void catch_exception_43 (void);
 273 void catch_exception_44 (void);
 274 void catch_exception_45 (void);
 275 void catch_exception_46 (void);
 276 void catch_exception_47 (void);
 277 void catch_exception_48 (void);
 278 void catch_exception_49 (void);
 279 void catch_exception_50 (void);
 280 void catch_exception_51 (void);
 281 void catch_exception_52 (void);
 282 void catch_exception_53 (void);
 283 void catch_exception_54 (void);
 284 void catch_exception_55 (void);
 285 void catch_exception_56 (void);
 286 void catch_exception_57 (void);
 287 void catch_exception_58 (void);
 288 void catch_exception_59 (void);
 289 void catch_exception_60 (void);
 290 void catch_exception_61 (void);
 291 void catch_exception_62 (void);
 292 void catch_exception_63 (void);
 293 void catch_exception_64 (void);
 294 void catch_exception_65 (void);
 295 void catch_exception_66 (void);
 296 void catch_exception_67 (void);
 297 void catch_exception_68 (void);
 298 void catch_exception_69 (void);
 299 void catch_exception_70 (void);
 300 void catch_exception_71 (void);
 301 void catch_exception_72 (void);
 302 void catch_exception_73 (void);
 303 void catch_exception_74 (void);
 304 void catch_exception_75 (void);
 305 void catch_exception_76 (void);
 306 void catch_exception_77 (void);
 307 void catch_exception_78 (void);
 308 void catch_exception_79 (void);
 309 void catch_exception_80 (void);
 310 void catch_exception_81 (void);
 311 void catch_exception_82 (void);
 312 void catch_exception_83 (void);
 313 void catch_exception_84 (void);
 314 void catch_exception_85 (void);
 315 void catch_exception_86 (void);
 316 void catch_exception_87 (void);
 317 void catch_exception_88 (void);
 318 void catch_exception_89 (void);
 319 void catch_exception_90 (void);
 320 void catch_exception_91 (void);
 321 void catch_exception_92 (void);
 322 void catch_exception_93 (void);
 323 void catch_exception_94 (void);
 324 void catch_exception_95 (void);
 325 void catch_exception_96 (void);
 326 void catch_exception_97 (void);
 327 void catch_exception_98 (void);
 328 void catch_exception_99 (void);
 329 void catch_exception_100 (void);
 330 void catch_exception_101 (void);
 331 void catch_exception_102 (void);
 332 void catch_exception_103 (void);
 333 void catch_exception_104 (void);
 334 void catch_exception_105 (void);
 335 void catch_exception_106 (void);
 336 void catch_exception_107 (void);
 337 void catch_exception_108 (void);
 338 void catch_exception_109 (void);
 339 void catch_exception_110 (void);
 340 void catch_exception_111 (void);
 341 void catch_exception_112 (void);
 342 void catch_exception_113 (void);
 343 void catch_exception_114 (void);
 344 void catch_exception_115 (void);
 345 void catch_exception_116 (void);
 346 void catch_exception_117 (void);
 347 void catch_exception_118 (void);
 348 void catch_exception_119 (void);
 349 void catch_exception_120 (void);
 350 void catch_exception_121 (void);
 351 void catch_exception_122 (void);
 352 void catch_exception_123 (void);
 353 void catch_exception_124 (void);
 354 void catch_exception_125 (void);
 355 void catch_exception_126 (void);
 356 void catch_exception_127 (void);
 357
 358 void breakpoint (void);
 359
 360
 361 //#define stub_stack_size 2*1024
 362
 363 //int stub_stack[stub_stack_size] __attribute__ ((section (".stack"))) = {0};
 364
 365 extern int stub_stack[];
 366
 367 void INIT (void);
 368 void start (void);
 369
 370 #define CPU_BUS_ERROR_VEC  9
 371 #define DMA_BUS_ERROR_VEC 10
 372 #define NMI_VEC           11
 373 #define INVALID_INSN_VEC   4
 374 #define INVALID_SLOT_VEC   6
 375 #define TRAP_VEC          32
 376 #define IO_VEC            33
 377 #define USER_VEC         127
 378
 379 char in_nmi;   /* Set when handling an NMI, so we don't reenter */
 380 int dofault;  /* Non zero, bus errors will raise exception */
 381
 382 int *stub_sp;
 383
 384 /* debug > 0 prints ill-formed commands in valid packets & checksum errors */
 385 int remote_debug;
 386
 387 /* jump buffer used for setjmp/longjmp */
 388 jmp_buf remcomEnv;
 389
 390 enum regnames
 391 {
 392     R0, R1, R2, R3, R4, R5, R6, R7,
 393     R8, R9, R10, R11, R12, R13, R14,
 394     R15, PC, PR, GBR, VBR, MACH, MACL, SR,
 395     TICKS, STALLS, CYCLES, INSTS, PLR
 396 };
 397
 398 typedef struct
 399 {
 400     short *memAddr;
 401     short oldInstr;
 402 }
 403 stepData;
 404
 405 int registers[NUMREGBYTES / 4];
 406 stepData instrBuffer;
 407 char stepped;
 408 static const char hexchars[] = "0123456789abcdef";
 409 static char remcomInBuffer[BUFMAX];
 410 static char remcomOutBuffer[BUFMAX];
 411
 412 #define ATA_NSECTOR     (*((volatile unsigned char*)0x06100102))
 413 #define ATA_COMMAND     (*((volatile unsigned char*)0x06100107))
 414 #define ATA_CONTROL     (*((volatile unsigned char*)0x06200306))
 415 #define ATA_ALT_STATUS  ATA_CONTROL
 416
 417 #define STATUS_BSY      0x80
 418 #define STATUS_RDY      0x40
 419
 420 #define CMD_STANDBY_IMMEDIATE      0xE0
 421 #define CMD_STANDBY                0xE2
 422
 423 void ata_wait_for_bsy(void)
 424 {
 425     while (ATA_ALT_STATUS & STATUS_BSY);
 426 }
 427
 428 int ata_wait_for_rdy(void)
 429 {
 430     ata_wait_for_bsy();
 431     return ATA_ALT_STATUS & STATUS_RDY;
 432 }
 433
 434 int ata_spindown(int time)
 435 {
 436     /* activate ATA */
 437     PADR &= ~0x80;
 438
 439     if(!ata_wait_for_rdy())
 440         return -1;
 441
 442     if ( time == -1 ) {
 443         ATA_COMMAND = CMD_STANDBY_IMMEDIATE;
 444     }
 445     else {
 446         if (time > 255)
 447             return -1;
 448         ATA_NSECTOR = time & 0xff;
 449         ATA_COMMAND = CMD_STANDBY;
 450     }
 451
 452     if (!ata_wait_for_rdy())
 453         return -1;
 454
 455     return 0;
 456 }
 457
 458 void blink(void)
 459 {
 460     while(1)
 461     {
 462         int i;
 463         PBDR ^= 0x40; /* toggle PB6 */
 464         for(i = 0;i < 500000;i++)
 465         {
 466         }
 467     }
 468 }
 469
 470 char highhex(int  x)
 471 {
 472     return hexchars[(x >> 4) & 0xf];
 473 }
 474
 475 char lowhex(int  x)
 476 {
 477     return hexchars[x & 0xf];
 478 }
 479
 480 /*
 481  * Assembly macros
 482  */
 483
 484 #define BREAKPOINT()   asm("trapa       #0x20"::);
 485
 486
 487 /*
 488  * Routines to handle hex data
 489  */
 490
 491 static int hex (char ch)
 492 {
 493     if ((ch >= 'a') && (ch <= 'f'))
 494         return (ch - 'a' + 10);
 495     if ((ch >= '0') && (ch <= '9'))
 496         return (ch - '0');
 497     if ((ch >= 'A') && (ch <= 'F'))
 498         return (ch - 'A' + 10);
 499     return (-1);
 500 }
 501
 502 /* convert the memory, pointed to by mem into hex, placing result in buf */
 503 /* return a pointer to the last char put in buf (null) */
 504 static char *mem2hex (char *mem, char *buf, int count)
 505 {
 506     int i;
 507     int ch;
 508     for (i = 0; i < count; i++)
 509     {
 510         ch = *mem++;
 511         *buf++ = highhex (ch);
 512         *buf++ = lowhex (ch);
 513     }
 514     *buf = 0;
 515     return (buf);
 516 }
 517
 518 /* convert the hex array pointed to by buf into binary, to be placed in mem */
 519 /* return a pointer to the character after the last byte written */
 520 static char *hex2mem (char *buf, char *mem, int count)
 521 {
 522     int i;
 523     unsigned char ch;
 524     for (i = 0; i < count; i++)
 525     {
 526         ch = hex (*buf++) << 4;
 527         ch = ch + hex (*buf++);
 528         *mem++ = ch;
 529     }
 530     return (mem);
 531 }
 532
 533 /**********************************************/
 534 /* WHILE WE FIND NICE HEX CHARS, BUILD AN INT */
 535 /* RETURN NUMBER OF CHARS PROCESSED           */
 536 /**********************************************/
 537 static int hex2int (char **ptr, int *intValue)
 538 {
 539     int numChars = 0;
 540     int hexValue;
 541
 542     *intValue = 0;
 543
 544     while (**ptr)
 545     {
 546         hexValue = hex (**ptr);
 547         if (hexValue >= 0)
 548         {
 549             *intValue = (*intValue << 4) | hexValue;
 550             numChars++;
 551         }
 552         else
 553             break;
 554
 555         (*ptr)++;
 556     }
 557
 558     return (numChars);
 559 }
 560
 561 /*
 562  * Routines to get and put packets
 563  */
 564
 565 /* scan for the sequence $<data>#<checksum>     */
 566
 567 unsigned char *getpacket (void)
 568 {
 569     unsigned char *buffer = &remcomInBuffer[0];
 570     unsigned char checksum;
 571     unsigned char xmitcsum;
 572     int count;
 573     char ch;
 574
 575     while (1)
 576     {
 577         /* wait around for the start character, ignore all other characters */
 578         while ((ch = serial_getc ()) != '$')
 579             ;
 580
 581       retry:
 582         checksum = 0;
 583         xmitcsum = -1;
 584         count = 0;
 585
 586         /* now, read until a # or end of buffer is found */
 587         while (count < BUFMAX)
 588         {
 589             ch = serial_getc ();
 590             if (ch == '$')
 591                 goto retry;
 592             if (ch == '#')
 593                 break;
 594             checksum = checksum + ch;
 595             buffer[count] = ch;
 596             count = count + 1;
 597         }
 598         buffer[count] = 0;
 599
 600         if (ch == '#')
 601         {
 602             ch = serial_getc ();
 603             xmitcsum = hex (ch) << 4;
 604             ch = serial_getc ();
 605             xmitcsum += hex (ch);
 606
 607             if (checksum != xmitcsum)
 608             {
 609                 serial_putc ('-');      /* failed checksum */
 610             }
 611             else
 612             {
 613                 serial_putc ('+');      /* successful transfer */
 614
 615                 /* if a sequence char is present, reply the sequence ID */
 616                 if (buffer[2] == ':')
 617                 {
 618                     serial_putc (buffer[0]);
 619                     serial_putc (buffer[1]);
 620
 621                     return &buffer[3];
 622                 }
 623
 624                 return &buffer[0];
 625             }
 626         }
 627     }
 628 }
 629
 630
 631 /* send the packet in buffer. */
 632
 633 static void putpacket (register char *buffer)
 634 {
 635     register  int checksum;
 636
 637     /*  $<packet info>#<checksum>. */
 638     do
 639     {
 640         char *src = buffer;
 641         serial_putc ('$');
 642         checksum = 0;
 643
 644         while (*src)
 645         {
 646             int runlen;
 647
 648             /* Do run length encoding */
 649             for (runlen = 0; runlen < 100; runlen ++)
 650             {
 651                 if (src[0] != src[runlen])
 652                 {
 653                     if (runlen > 3)
 654                     {
 655                         int encode;
 656                         /* Got a useful amount */
 657                         serial_putc (*src);
 658                         checksum += *src;
 659                         serial_putc ('*');
 660                         checksum += '*';
 661                         checksum += (encode = runlen + ' ' - 4);
 662                         serial_putc (encode);
 663                         src += runlen;
 664                     }
 665                     else
 666                     {
 667                         serial_putc (*src);
 668                         checksum += *src;
 669                         src++;
 670                     }
 671                     break;
 672                 }
 673             }
 674         }
 675
 676
 677         serial_putc ('#');
 678         serial_putc (highhex(checksum));
 679         serial_putc (lowhex(checksum));
 680     }
 681     while  (serial_getc() != '+');
 682 }
 683
 684
 685 /* a bus error has occurred, perform a longjmp
 686    to return execution and allow handling of the error */
 687
 688 void handle_buserror (void)
 689 {
 690     longjmp (remcomEnv, 1);
 691 }
 692
 693 /*
 694  * this function takes the SH-1 exception number and attempts to
 695  * translate this number into a unix compatible signal value
 696  */
 697 static int computeSignal (int exceptionVector)
 698 {
 699     int sigval;
 700     switch (exceptionVector)
 701     {
 702         case INVALID_INSN_VEC:
 703             sigval = SIGILL;
 704             break;
 705         case INVALID_SLOT_VEC:
 706             sigval = SIGILL;
 707             break;
 708         case CPU_BUS_ERROR_VEC:
 709             sigval = SIGBUS;
 710             break;
 711         case DMA_BUS_ERROR_VEC:
 712             sigval = SIGBUS;
 713             break;
 714         case NMI_VEC:
 715             sigval = SIGINT;
 716             break;
 717
 718         case TRAP_VEC:
 719         case USER_VEC:
 720             sigval = SIGTRAP;
 721             break;
 722
 723         default:
 724             sigval = SIGEMT;            /* "software generated"*/
 725             break;
 726     }
 727     return (sigval);
 728 }
 729
 730 void doSStep (void)
 731 {
 732     short *instrMem;
 733     int displacement;
 734     int reg;
 735     unsigned short opcode;
 736
 737     instrMem = (short *) registers[PC];
 738
 739     opcode = *instrMem;
 740     stepped = 1;
 741
 742     if ((opcode & COND_BR_MASK) == BT_INSTR)
 743     {
 744         if (registers[SR] & T_BIT_MASK)
 745         {
 746             displacement = (opcode & COND_DISP) << 1;
 747             if (displacement & 0x80)
 748                 displacement |= 0xffffff00;
 749             /*
 750              * Remember PC points to second instr.
 751              * after PC of branch ... so add 4
 752              */
 753             instrMem = (short *) (registers[PC] + displacement + 4);
 754         }
 755         else
 756             instrMem += 1;
 757     }
 758     else if ((opcode & COND_BR_MASK) == BF_INSTR)
 759     {
 760         if (registers[SR] & T_BIT_MASK)
 761             instrMem += 1;
 762         else
 763         {
 764             displacement = (opcode & COND_DISP) << 1;
 765             if (displacement & 0x80)
 766                 displacement |= 0xffffff00;
 767             /*
 768              * Remember PC points to second instr.
 769              * after PC of branch ... so add 4
 770              */
 771             instrMem = (short *) (registers[PC] + displacement + 4);
 772         }
 773     }
 774     else if ((opcode & UCOND_DBR_MASK) == BRA_INSTR)
 775     {
 776         displacement = (opcode & UCOND_DISP) << 1;
 777         if (displacement & 0x0800)
 778             displacement |= 0xfffff000;
 779
 780         /*
 781          * Remember PC points to second instr.
 782          * after PC of branch ... so add 4
 783          */
 784         instrMem = (short *) (registers[PC] + displacement + 4);
 785     }
 786     else if ((opcode & UCOND_RBR_MASK) == JSR_INSTR)
 787     {
 788         reg = (char) ((opcode & UCOND_REG) >> 8);
 789
 790         instrMem = (short *) registers[reg];
 791     }
 792     else if (opcode == RTS_INSTR)
 793         instrMem = (short *) registers[PR];
 794     else if (opcode == RTE_INSTR)
 795         instrMem = (short *) registers[15];
 796     else if ((opcode & TRAPA_MASK) == TRAPA_INSTR)
 797         instrMem = (short *) ((opcode & ~TRAPA_MASK) << 2);
 798     else
 799         instrMem += 1;
 800
 801     instrBuffer.memAddr = instrMem;
 802     instrBuffer.oldInstr = *instrMem;
 803     *instrMem = SSTEP_INSTR;
 804 }
 805
 806
 807 /* Undo the effect of a previous doSStep.  If we single stepped,
 808    restore the old instruction. */
 809 void undoSStep (void)
 810 {
 811     if (stepped)
 812     {
 813         short *instrMem;
 814         instrMem = instrBuffer.memAddr;
 815         *instrMem = instrBuffer.oldInstr;
 816     }
 817     stepped = 0;
 818 }
 819
 820 /*
 821  * This function does all exception handling.  It only does two things -
 822  * it figures out why it was called and tells gdb, and then it reacts
 823  * to gdb's requests.
 824  *
 825 */
 826 void gdb_handle_exception (int exceptionVector)
 827 {
 828     int sigval, stepping;
 829     int addr, length;
 830     char *ptr;
 831
 832     /* reply to host that an exception has occurred */
 833     sigval = computeSignal (exceptionVector);
 834     remcomOutBuffer[0] = 'S';
 835     remcomOutBuffer[1] = highhex(sigval);
 836     remcomOutBuffer[2] = lowhex (sigval);
 837     remcomOutBuffer[3] = 0;
 838
 839     putpacket (remcomOutBuffer);
 840
 841     /*
 842      * exception 127 indicates a software trap
 843      * inserted in place of code ... so back up
 844      * PC by one instruction, since this instruction
 845      * will later be replaced by its original one!
 846      */
 847     if (exceptionVector == USER_VEC
 848         || exceptionVector == TRAP_VEC)
 849         registers[PC] -= 2;
 850
 851     /*
 852      * Do the things needed to undo
 853      * any stepping we may have done!
 854      */
 855     undoSStep ();
 856
 857     stepping = 0;
 858
 859     while (1)
 860     {
 861         remcomOutBuffer[0] = 0;
 862         ptr = getpacket ();
 863
 864         switch (*ptr++)
 865         {
 866         case '?':
 867             remcomOutBuffer[0] = 'S';
 868             remcomOutBuffer[1] = highhex (sigval);
 869             remcomOutBuffer[2] = lowhex (sigval);
 870             remcomOutBuffer[3] = 0;
 871             break;
 872         case 'd':
 873             remote_debug = !(remote_debug);     /* toggle debug flag */
 874             break;
 875         case 'g':   /* return the value of the CPU registers */
 876             mem2hex ((char *) registers, remcomOutBuffer, NUMREGBYTES);
 877             break;
 878         case 'G':   /* set the value of the CPU registers - return OK */
 879             hex2mem (ptr, (char *) registers, NUMREGBYTES);
 880             strcpy (remcomOutBuffer, "OK");
 881             break;
 882
 883             /* mAA..AA,LLLL  Read LLLL bytes at address AA..AA */
 884         case 'm':
 885             if (setjmp (remcomEnv) == 0)
 886             {
 887                 dofault = 0;
 888                 /* TRY, TO READ %x,%x.  IF SUCCEED, SET PTR = 0 */
 889                 if (hex2int (&ptr, &addr))
 890                     if (*(ptr++) == ',')
 891                         if (hex2int (&ptr, &length))
 892                         {
 893                             ptr = 0;
 894                             mem2hex ((char *) addr, remcomOutBuffer, length);
 895                         }
 896                 if (ptr)
 897                     strcpy (remcomOutBuffer, "E01");
 898             }
 899             else
 900                 strcpy (remcomOutBuffer, "E03");
 901
 902             /* restore handler for bus error */
 903             dofault = 1;
 904             break;
 905
 906             /* MAA..AA,LLLL: Write LLLL bytes at address AA.AA return OK */
 907         case 'M':
 908             if (setjmp (remcomEnv) == 0)
 909             {
 910                 dofault = 0;
 911
 912                 /* TRY, TO READ '%x,%x:'.  IF SUCCEED, SET PTR = 0 */
 913                 if (hex2int (&ptr, &addr))
 914                     if (*(ptr++) == ',')
 915                         if (hex2int (&ptr, &length))
 916                             if (*(ptr++) == ':')
 917                             {
 918                                 hex2mem (ptr, (char *) addr, length);
 919                                 ptr = 0;
 920                                 strcpy (remcomOutBuffer, "OK");
 921                             }
 922                 if (ptr)
 923                     strcpy (remcomOutBuffer, "E02");
 924             }
 925             else
 926                 strcpy (remcomOutBuffer, "E03");
 927
 928             /* restore handler for bus error */
 929             dofault = 1;
 930             break;
 931
 932             /* cAA..AA    Continue at address AA..AA(optional) */
 933             /* sAA..AA   Step one instruction from AA..AA(optional) */
 934         case 's':
 935             stepping = 1;
 936         case 'c':
 937         {
 938             /* tRY, to read optional parameter, pc unchanged if no parm */
 939             if (hex2int (&ptr, &addr))
 940                 registers[PC] = addr;
 941
 942             if (stepping)
 943                 doSStep ();
 944         }
 945
 946         return;
 947         break;
 948
 949         /* kill the program */
 950         case 'k':               /* do nothing */
 951             break;
 952
 953         default:
 954             break;
 955         }                       /* switch */
 956
 957         /* reply to the request */
 958         putpacket (remcomOutBuffer);
 959     }
 960 }
 961
 962
 963 /* We've had an exception - go into the gdb stub */
 964 void handle_exception(int exceptionVector)
 965 {
 966     gdb_handle_exception (exceptionVector);
 967 }
 968
 969 /* This function will generate a breakpoint exception.  It is used at the
 970    beginning of a program to sync up with a debugger and can be used
 971    otherwise as a quick means to stop program execution and "break" into
 972    the debugger. */
 973 void breakpoint (void)
 974 {
 975     BREAKPOINT ();
 976 }
 977
 978 /**** Processor-specific routines start here ****/
 979 /**** Processor-specific routines start here ****/
 980 /**** Processor-specific routines start here ****/
 981
 982 extern int stack[];
 983
 984 /* SH1/SH2 exception vector table format */
 985 typedef struct
 986 {
 987         void (*func_cold) (void);
 988         int *stack_cold;
 989         void (*func_warm) (void);
 990         int *stack_warm;
 991         void (*(handler[128 - 4])) (void);
 992 } vec_type;
 993
 994 /* vectable is the SH1/SH2 vector table. It must be at address 0
 995 ** or wherever your vbr points.
 996 ** Note that we only define the first 128 vectors, since the Jukebox
 997 ** firmware has its entry point at 0x200
 998 */
 999 const vec_type vectable  __attribute__ ((section (".vectors"))) =
1000 {
1001     &start,                             /* 0: Power-on reset PC */
1002     stack,                              /* 1: Power-on reset SP */
1003     &start,                             /* 2: Manual reset PC */
1004     stack,                              /* 3: Manual reset SP */
1005     {
1006         &catch_exception_4,             /* 4: General invalid instruction */
1007         &catch_exception_5,             /* 5: Reserved for system */
1008         &catch_exception_6,             /* 6: Invalid slot instruction */
1009         &catch_exception_7,             /* 7: Reserved for system */
1010         &catch_exception_8,             /* 8: Reserved for system */
1011         &catch_exception_9,             /* 9: CPU bus error */
1012         &catch_exception_10,            /* 10: DMA bus error */
1013         &catch_exception_11,            /* 11: NMI */
1014         &catch_exception_12,            /* 12: User break */
1015         &catch_exception_13,            /* 13: Reserved for system */
1016         &catch_exception_14,            /* 14: Reserved for system */
1017         &catch_exception_15,            /* 15: Reserved for system */
1018         &catch_exception_16,            /* 16: Reserved for system */
1019         &catch_exception_17,            /* 17: Reserved for system */
1020         &catch_exception_18,            /* 18: Reserved for system */
1021         &catch_exception_19,            /* 19: Reserved for system */
1022         &catch_exception_20,            /* 20: Reserved for system */
1023         &catch_exception_21,            /* 21: Reserved for system */
1024         &catch_exception_22,            /* 22: Reserved for system */
1025         &catch_exception_23,            /* 23: Reserved for system */
1026         &catch_exception_24,            /* 24: Reserved for system */
1027         &catch_exception_25,            /* 25: Reserved for system */
1028         &catch_exception_26,            /* 26: Reserved for system */
1029         &catch_exception_27,            /* 27: Reserved for system */
1030         &catch_exception_28,            /* 28: Reserved for system */
1031         &catch_exception_29,            /* 29: Reserved for system */
1032         &catch_exception_30,            /* 30: Reserved for system */
1033         &catch_exception_31,            /* 31: Reserved for system */
1034         &catch_exception_32,            /* 32: Trap instr (user vectors) */
1035         &catch_exception_33,            /* 33: Trap instr (user vectors) */
1036         &catch_exception_34,            /* 34: Trap instr (user vectors) */
1037         &catch_exception_35,            /* 35: Trap instr (user vectors) */
1038         &catch_exception_36,            /* 36: Trap instr (user vectors) */
1039         &catch_exception_37,            /* 37: Trap instr (user vectors) */
1040         &catch_exception_38,            /* 38: Trap instr (user vectors) */
1041         &catch_exception_39,            /* 39: Trap instr (user vectors) */
1042         &catch_exception_40,            /* 40: Trap instr (user vectors) */
1043         &catch_exception_41,            /* 41: Trap instr (user vectors) */
1044         &catch_exception_42,            /* 42: Trap instr (user vectors) */
1045         &catch_exception_43,            /* 43: Trap instr (user vectors) */
1046         &catch_exception_44,            /* 44: Trap instr (user vectors) */
1047         &catch_exception_45,            /* 45: Trap instr (user vectors) */
1048         &catch_exception_46,            /* 46: Trap instr (user vectors) */
1049         &catch_exception_47,            /* 47: Trap instr (user vectors) */
1050         &catch_exception_48,            /* 48: Trap instr (user vectors) */
1051         &catch_exception_49,            /* 49: Trap instr (user vectors) */
1052         &catch_exception_50,            /* 50: Trap instr (user vectors) */
1053         &catch_exception_51,            /* 51: Trap instr (user vectors) */
1054         &catch_exception_52,            /* 52: Trap instr (user vectors) */
1055         &catch_exception_53,            /* 53: Trap instr (user vectors) */
1056         &catch_exception_54,            /* 54: Trap instr (user vectors) */
1057         &catch_exception_55,            /* 55: Trap instr (user vectors) */
1058         &catch_exception_56,            /* 56: Trap instr (user vectors) */
1059         &catch_exception_57,            /* 57: Trap instr (user vectors) */
1060         &catch_exception_58,            /* 58: Trap instr (user vectors) */
1061         &catch_exception_59,            /* 59: Trap instr (user vectors) */
1062         &catch_exception_60,            /* 60: Trap instr (user vectors) */
1063         &catch_exception_61,            /* 61: Trap instr (user vectors) */
1064         &catch_exception_62,            /* 62: Trap instr (user vectors) */
1065         &catch_exception_63,            /* 63: Trap instr (user vectors) */
1066         &catch_exception_64,            /* 64: IRQ0 */
1067         &catch_exception_65,            /* 65: IRQ1 */
1068         &catch_exception_66,            /* 66: IRQ2 */
1069         &catch_exception_67,            /* 67: IRQ3 */
1070         &catch_exception_68,            /* 68: IRQ4 */
1071         &catch_exception_69,            /* 69: IRQ5 */
1072         &catch_exception_70,            /* 70: IRQ6 */
1073         &catch_exception_71,            /* 71: IRQ7 */
1074         &catch_exception_72,
1075         &catch_exception_73,
1076         &catch_exception_74,
1077         &catch_exception_75,
1078         &catch_exception_76,
1079         &catch_exception_77,
1080         &catch_exception_78,
1081         &catch_exception_79,
1082         &catch_exception_80,
1083         &catch_exception_81,
1084         &catch_exception_82,
1085         &catch_exception_83,
1086         &catch_exception_84,
1087         &catch_exception_85,
1088         &catch_exception_86,
1089         &catch_exception_87,
1090         &catch_exception_88,
1091         &catch_exception_89,
1092         &catch_exception_90,
1093         &catch_exception_91,
1094         &catch_exception_92,
1095         &catch_exception_93,
1096         &catch_exception_94,
1097         &catch_exception_95,
1098         &catch_exception_96,
1099         &catch_exception_97,
1100         &catch_exception_98,
1101         &catch_exception_99,
1102         &catch_exception_100,
1103         &catch_exception_101,
1104         &catch_exception_102,
1105         &catch_exception_103,
1106         &catch_exception_104,
1107         &catch_exception_105,
1108         &catch_exception_106,
1109         &catch_exception_107,
1110         &catch_exception_108,
1111         &catch_exception_109,
1112         &catch_exception_110,
1113         &catch_exception_111,
1114         &catch_exception_112,
1115         &catch_exception_113,
1116         &catch_exception_114,
1117         &catch_exception_115,
1118         &catch_exception_116,
1119         &catch_exception_117,
1120         &catch_exception_118,
1121         &catch_exception_119,
1122         &catch_exception_120,
1123         &catch_exception_121,
1124         &catch_exception_122,
1125         &catch_exception_123,
1126         &catch_exception_124,
1127         &catch_exception_125,
1128         &catch_exception_126,
1129         &catch_exception_127}};
1130
1131 void INIT (void)
1132 {
1133     /* Disable all timer interrupts */
1134     TIER0 = 0;
1135     TIER1 = 0;
1136     TIER2 = 0;
1137     TIER3 = 0;
1138     TIER4 = 0;
1139
1140     init_serial();
1141
1142     in_nmi = 0;
1143     dofault = 1;
1144     stepped = 0;
1145
1146     ata_spindown(-1);
1147
1148     stub_sp = stub_stack;
1149     breakpoint ();
1150
1151     /* We should never come here */
1152     blink();
1153 }
1154
1155 void sr(void)
1156 {
1157     /* Calling Reset does the same as pressing the button */
1158     asm (".global _Reset\n"
1159          "        .global _WarmReset\n"
1160          "_Reset:\n"
1161          "_WarmReset:\n"
1162          "         mov.l L_sp,r15\n"
1163          "         bra   _INIT\n"
1164          "         nop\n"
1165          "         .align 2\n"
1166          "L_sp:    .long _stack");
1167
1168     asm("saveRegisters:\n");
1169     asm(" mov.l @(L_reg, pc), r0\n"
1170         "       mov.l   @r15+, r1               ! pop R0\n"
1171         "       mov.l   r2, @(0x08, r0)         ! save R2\n"
1172         "       mov.l   r1, @r0                 ! save R0\n"
1173         "       mov.l   @r15+, r1               ! pop R1\n"
1174         "       mov.l   r3, @(0x0c, r0)         ! save R3\n"
1175         "       mov.l   r1, @(0x04, r0)         ! save R1\n"
1176         "       mov.l   r4, @(0x10, r0)         ! save R4\n"
1177         "       mov.l   r5, @(0x14, r0)         ! save R5\n"
1178         "       mov.l   r6, @(0x18, r0)         ! save R6\n"
1179         "       mov.l   r7, @(0x1c, r0)         ! save R7\n"
1180         "       mov.l   r8, @(0x20, r0)         ! save R8\n"
1181         "       mov.l   r9, @(0x24, r0)         ! save R9\n"
1182         "       mov.l   r10, @(0x28, r0)        ! save R10\n"
1183         "       mov.l   r11, @(0x2c, r0)        ! save R11\n"
1184         "       mov.l   r12, @(0x30, r0)        ! save R12\n"
1185         "       mov.l   r13, @(0x34, r0)        ! save R13\n"
1186         "       mov.l   r14, @(0x38, r0)        ! save R14\n"
1187         "       mov.l   @r15+, r4               ! save arg to handleException\n"
1188         "       add     #8, r15                 ! hide PC/SR values on stack\n"
1189         "       mov.l   r15, @(0x3c, r0)        ! save R15\n"
1190         "       add     #-8, r15                ! save still needs old SP value\n"
1191         "       add     #92, r0                 ! readjust register pointer\n"
1192         "       mov     r15, r2\n"
1193         "       add     #4, r2\n"
1194         "       mov.l   @r2, r2                 ! R2 has SR\n"
1195         "       mov.l   @r15, r1                ! R1 has PC\n"
1196         "       mov.l   r2, @-r0                ! save SR\n"
1197         "       sts.l   macl, @-r0              ! save MACL\n"
1198         "       sts.l   mach, @-r0              ! save MACH\n"
1199         "       stc.l   vbr, @-r0               ! save VBR\n"
1200         "       stc.l   gbr, @-r0               ! save GBR\n"
1201         "       sts.l   pr, @-r0                ! save PR\n"
1202         "       mov.l   @(L_stubstack, pc), r2\n"
1203         "       mov.l   @(L_hdl_except, pc), r3\n"
1204         "       mov.l   @r2, r15\n"
1205         "       jsr     @r3\n"
1206         "       mov.l   r1, @-r0                ! save PC\n"
1207         "       mov.l   @(L_stubstack, pc), r0\n"
1208         "       mov.l   @(L_reg, pc), r1\n"
1209         "       bra     restoreRegisters\n"
1210         "       mov.l   r15, @r0                ! save __stub_stack\n"
1211
1212         "       .align 2\n"
1213         "L_reg:\n"
1214         "       .long   _registers\n"
1215         "L_stubstack:\n"
1216         "       .long   _stub_sp\n"
1217         "L_hdl_except:\n"
1218         "       .long   _handle_exception");
1219 }
1220
1221 void rr(void)
1222 {
1223     asm("       .align 2        \n"
1224         "        .global _resume\n"
1225         "_resume:\n"
1226         "       mov     r4,r1\n"
1227         "restoreRegisters:\n"
1228         "       add     #8, r1                  ! skip to R2\n"
1229         "       mov.l   @r1+, r2                ! restore R2\n"
1230         "       mov.l   @r1+, r3                ! restore R3\n"
1231         "       mov.l   @r1+, r4                ! restore R4\n"
1232         "       mov.l   @r1+, r5                ! restore R5\n"
1233         "       mov.l   @r1+, r6                ! restore R6\n"
1234         "       mov.l   @r1+, r7                ! restore R7\n"
1235         "       mov.l   @r1+, r8                ! restore R8\n"
1236         "       mov.l   @r1+, r9                ! restore R9\n"
1237         "       mov.l   @r1+, r10               ! restore R10\n"
1238         "       mov.l   @r1+, r11               ! restore R11\n"
1239         "       mov.l   @r1+, r12               ! restore R12\n"
1240         "       mov.l   @r1+, r13               ! restore R13\n"
1241         "       mov.l   @r1+, r14               ! restore R14\n"
1242         "       mov.l   @r1+, r15               ! restore programs stack\n"
1243         "       mov.l   @r1+, r0\n"
1244         "       add     #-8, r15                ! uncover PC/SR on stack \n"
1245         "       mov.l   r0, @r15                ! restore PC onto stack\n"
1246         "       lds.l   @r1+, pr                ! restore PR\n"
1247         "       ldc.l   @r1+, gbr               ! restore GBR\n"
1248         "       ldc.l   @r1+, vbr               ! restore VBR\n"
1249         "       lds.l   @r1+, mach              ! restore MACH\n"
1250         "       lds.l   @r1+, macl              ! restore MACL\n"
1251         "       mov.l   @r1, r0 \n"
1252         "       add     #-88, r1                ! readjust reg pointer to R1\n"
1253         "       mov.l   r0, @(4, r15)           ! restore SR onto stack+4\n"
1254         "       mov.l   r2, @-r15\n"
1255         "       mov.l   L_in_nmi, r0\n"
1256         "       mov             #0, r2\n"
1257         "       mov.b   r2, @r0\n"
1258         "       mov.l   @r15+, r2\n"
1259         "       mov.l   @r1+, r0                ! restore R0\n"
1260         "       rte\n"
1261         "       mov.l   @r1, r1                 ! restore R1");
1262 }
1263
1264 static inline void code_for_catch_exception(unsigned int n)
1265 {
1266     asm("               .globl  _catch_exception_%O0" : : "X" (n) );
1267     asm("       _catch_exception_%O0:" :: "X" (n) );
1268
1269     asm("               add     #-4, r15        ! reserve spot on stack ");
1270     asm("               mov.l   r1, @-r15       ! push R1               ");
1271
1272     if (n == NMI_VEC)
1273     {
1274         /* Special case for NMI - make sure that they don't nest */
1275         asm("   mov.l   r0, @-r15       ! push R0");
1276         asm("   mov.l   L_in_nmi, r0");
1277         asm("   tas.b   @r0             ! Fend off against addtnl NMIs");
1278         asm("   bt              noNMI");
1279         asm("   mov.l   @r15+, r0");
1280         asm("   mov.l   @r15+, r1");
1281         asm("   add             #4, r15");
1282         asm("   rte");
1283         asm("   nop");
1284         asm(".align 2");
1285         asm("L_in_nmi: .long    _in_nmi");
1286         asm("noNMI:");
1287     }
1288     else
1289     {
1290
1291         if (n == CPU_BUS_ERROR_VEC)
1292         {
1293             /* Exception 9 (bus errors) are disasbleable - so that you
1294                can probe memory and get zero instead of a fault.
1295                Because the vector table may be in ROM we don't revector
1296                the interrupt like all the other stubs, we check in here
1297             */
1298             asm("mov.l  L_dofault,r1");
1299             asm("mov.l  @r1,r1");
1300             asm("tst    r1,r1");
1301             asm("bf     faultaway");
1302             asm("bsr    _handle_buserror");
1303             asm(".align 2");
1304             asm("L_dofault: .long _dofault");
1305             asm("faultaway:");
1306         }
1307         asm("           mov     #15<<4, r1                              ");
1308         asm("           ldc     r1, sr          ! disable interrupts    ");
1309         asm("           mov.l   r0, @-r15       ! push R0               ");
1310     }
1311
1312     /* Prepare for saving context, we've already pushed r0 and r1, stick
1313        exception number into the frame */
1314     asm("               mov     r15, r0                         ");
1315     asm("               add     #8, r0                          ");
1316     asm("               mov     %0,r1" :: "X" (n));
1317     asm("               extu.b  r1,r1                           ");
1318     asm("               bra     saveRegisters   ! save register values  ");
1319     asm("               mov.l   r1, @r0         ! save exception #      ");
1320 }
1321
1322 /* Here we call all defined exceptions, so the inline assembler gets
1323    generated */
1324 void exceptions (void)
1325 {
1326     code_for_catch_exception (4);
1327     code_for_catch_exception (5);
1328     code_for_catch_exception (6);
1329     code_for_catch_exception (7);
1330     code_for_catch_exception (8);
1331     code_for_catch_exception (9);
1332     code_for_catch_exception (10);
1333     code_for_catch_exception (11);
1334     code_for_catch_exception (12);
1335     code_for_catch_exception (13);
1336     code_for_catch_exception (14);
1337     code_for_catch_exception (15);
1338     code_for_catch_exception (16);
1339     code_for_catch_exception (17);
1340     code_for_catch_exception (18);
1341     code_for_catch_exception (19);
1342     code_for_catch_exception (20);
1343     code_for_catch_exception (21);
1344     code_for_catch_exception (22);
1345     code_for_catch_exception (23);
1346     code_for_catch_exception (24);
1347     code_for_catch_exception (25);
1348     code_for_catch_exception (26);
1349     code_for_catch_exception (27);
1350     code_for_catch_exception (28);
1351     code_for_catch_exception (29);
1352     code_for_catch_exception (30);
1353     code_for_catch_exception (31);
1354     code_for_catch_exception (32);
1355     code_for_catch_exception (33);
1356     code_for_catch_exception (34);
1357     code_for_catch_exception (35);
1358     code_for_catch_exception (36);
1359     code_for_catch_exception (37);
1360     code_for_catch_exception (38);
1361     code_for_catch_exception (39);
1362     code_for_catch_exception (40);
1363     code_for_catch_exception (41);
1364     code_for_catch_exception (42);
1365     code_for_catch_exception (43);
1366     code_for_catch_exception (44);
1367     code_for_catch_exception (45);
1368     code_for_catch_exception (46);
1369     code_for_catch_exception (47);
1370     code_for_catch_exception (48);
1371     code_for_catch_exception (49);
1372     code_for_catch_exception (50);
1373     code_for_catch_exception (51);
1374     code_for_catch_exception (52);
1375     code_for_catch_exception (53);
1376     code_for_catch_exception (54);
1377     code_for_catch_exception (55);
1378     code_for_catch_exception (56);
1379     code_for_catch_exception (57);
1380     code_for_catch_exception (58);
1381     code_for_catch_exception (59);
1382     code_for_catch_exception (60);
1383     code_for_catch_exception (61);
1384     code_for_catch_exception (62);
1385     code_for_catch_exception (63);
1386     code_for_catch_exception (64);
1387     code_for_catch_exception (65);
1388     code_for_catch_exception (66);
1389     code_for_catch_exception (67);
1390     code_for_catch_exception (68);
1391     code_for_catch_exception (69);
1392     code_for_catch_exception (70);
1393     code_for_catch_exception (71);
1394     code_for_catch_exception (72);
1395     code_for_catch_exception (73);
1396     code_for_catch_exception (74);
1397     code_for_catch_exception (75);
1398     code_for_catch_exception (76);
1399     code_for_catch_exception (77);
1400     code_for_catch_exception (78);
1401     code_for_catch_exception (79);
1402     code_for_catch_exception (80);
1403     code_for_catch_exception (81);
1404     code_for_catch_exception (82);
1405     code_for_catch_exception (83);
1406     code_for_catch_exception (84);
1407     code_for_catch_exception (85);
1408     code_for_catch_exception (86);
1409     code_for_catch_exception (87);
1410     code_for_catch_exception (88);
1411     code_for_catch_exception (89);
1412     code_for_catch_exception (90);
1413     code_for_catch_exception (91);
1414     code_for_catch_exception (92);
1415     code_for_catch_exception (93);
1416     code_for_catch_exception (94);
1417     code_for_catch_exception (95);
1418     code_for_catch_exception (96);
1419     code_for_catch_exception (97);
1420     code_for_catch_exception (98);
1421     code_for_catch_exception (99);
1422     code_for_catch_exception (100);
1423     code_for_catch_exception (101);
1424     code_for_catch_exception (102);
1425     code_for_catch_exception (103);
1426     code_for_catch_exception (104);
1427     code_for_catch_exception (105);
1428     code_for_catch_exception (106);
1429     code_for_catch_exception (107);
1430     code_for_catch_exception (108);
1431     code_for_catch_exception (109);
1432     code_for_catch_exception (110);
1433     code_for_catch_exception (111);
1434     code_for_catch_exception (112);
1435     code_for_catch_exception (113);
1436     code_for_catch_exception (114);
1437     code_for_catch_exception (115);
1438     code_for_catch_exception (116);
1439     code_for_catch_exception (117);
1440     code_for_catch_exception (118);
1441     code_for_catch_exception (119);
1442     code_for_catch_exception (120);
1443     code_for_catch_exception (121);
1444     code_for_catch_exception (122);
1445     code_for_catch_exception (123);
1446     code_for_catch_exception (124);
1447     code_for_catch_exception (125);
1448     code_for_catch_exception (126);
1449     code_for_catch_exception (127);
1450 }
1451
1452 /*
1453  * Port B Control Register (PBCR1)
1454  */
1455 #define PB15MD1         0x8000
1456 #define PB15MD0         0x4000
1457 #define PB14MD1         0x2000
1458 #define PB14MD0         0x1000
1459 #define PB13MD1         0x0800
1460 #define PB13MD0         0x0400
1461 #define PB12MD1         0x0200
1462 #define PB12MD0         0x0100
1463 #define PB11MD1         0x0080
1464 #define PB11MD0         0x0040
1465 #define PB10MD1         0x0020
1466 #define PB10MD0         0x0010
1467 #define PB9MD1          0x0008
1468 #define PB9MD0          0x0004
1469 #define PB8MD1          0x0002
1470 #define PB8MD0          0x0001
1471
1472 #define PB15MD          PB15MD1|PB14MD0
1473 #define PB14MD          PB14MD1|PB14MD0
1474 #define PB13MD          PB13MD1|PB13MD0
1475 #define PB12MD          PB12MD1|PB12MD0
1476 #define PB11MD          PB11MD1|PB11MD0
1477 #define PB10MD          PB10MD1|PB10MD0
1478 #define PB9MD           PB9MD1|PB9MD0
1479 #define PB8MD           PB8MD1|PB8MD0
1480
1481 #define PB_TXD1         PB11MD1
1482 #define PB_RXD1         PB10MD1
1483 #define PB_TXD0         PB9MD1
1484 #define PB_RXD0         PB8MD1
1485
1486 #define PB7MD   PB7MD1|PB7MD0
1487 #define PB6MD   PB6MD1|PB6MD0
1488 #define PB5MD   PB5MD1|PB5MD0
1489 #define PB4MD   PB4MD1|PB4MD0
1490 #define PB3MD   PB3MD1|PB3MD0
1491 #define PB2MD   PB2MD1|PB2MD0
1492 #define PB1MD   PB1MD1|PB1MD0
1493 #define PB0MD   PB0MD1|PB0MD0
1494
1495
1496 void handleError (char theSSR);
1497
1498 void nop (void)
1499 {
1500 }
1501
1502 void init_serial (void)
1503 {
1504     int i;
1505
1506     /* Clear Channel 1's SCR   */
1507     SCR1 = 0;
1508
1509     /* Set communication to be async, 8-bit data,
1510        no parity, 1 stop bit and use internal clock */
1511     SMR1 = 0;
1512 /*    BRR1 = SYSCLOCK / (9600 * 32) - 1;*/
1513     BRR1 = 9; /* 38400 */
1514
1515     SCR1 &= ~(SCI_CKE1 | SCI_CKE0);
1516
1517     /* let the hardware settle */
1518     for (i = 0; i < 1000; i++)
1519         nop ();
1520
1521     /* Turn on in and out */
1522     SCR1 |= SCI_RE | SCI_TE;
1523
1524     /* Set the PFC to make RXD1 (pin PB8) an input pin
1525        and TXD1 (pin PB9) an output pin */
1526     PBCR1 &= ~(PB_TXD1 | PB_RXD1);
1527     PBCR1 |= PB_TXD1 | PB_RXD1;
1528 }
1529
1530
1531 int serial_waitc(void)
1532 {
1533     char mySSR;
1534     mySSR = SSR1 & ( SCI_PER | SCI_FER | SCI_ORER );
1535     if ( mySSR )
1536         handleError ( mySSR );
1537     return SSR1 & SCI_RDRF ;
1538 }
1539
1540 char serial_getc (void)
1541 {
1542     char ch;
1543     char mySSR;
1544
1545     while ( ! serial_waitc())
1546         ;
1547
1548     ch = RDR1;
1549     SSR1 &= ~SCI_RDRF;
1550
1551     mySSR = SSR1 & (SCI_PER | SCI_FER | SCI_ORER);
1552
1553     if (mySSR)
1554         handleError (mySSR);
1555
1556     return ch;
1557 }
1558
1559 void serial_putc (char ch)
1560 {
1561     while (!(SSR1 & SCI_TDRE))
1562     {
1563         ;
1564     }
1565
1566     /*
1567      * Write data into TDR and clear TDRE
1568      */
1569     TDR1 = ch;
1570     SSR1 &= ~SCI_TDRE;
1571 }
1572
1573 void handleError (char theSSR)
1574 {
1575     /* Clear all error bits, otherwise the receiver will stop */
1576     SSR1 &= ~(SCI_ORER | SCI_PER | SCI_FER);
1577 }