firmware/target/arm/usb-drv-pp502x.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id:  $
   9  *
  10  * Driver for ARC USBOTG Device Controller
  11  *
  12  * Copyright (C) 2007 by Björn Stenberg
  13  *
  14  * All files in this archive are subject to the GNU General Public License.
  15  * See the file COPYING in the source tree root for full license agreement.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21
  22 #include "system.h"
  23 #include "string.h"
  24 #include "usb_ch9.h"
  25 #include "usb_core.h"
  26 //#define LOGF_ENABLE
  27 #include "logf.h"
  28
  29 /* USB device mode registers (Little Endian) */
  30
  31 #define REG_ID               (*(volatile unsigned int *)(USB_BASE+0x000))
  32 #define REG_HWGENERAL        (*(volatile unsigned int *)(USB_BASE+0x004))
  33 #define REG_CAPLENGTH        (*(volatile unsigned char*)(USB_BASE+0x100))
  34 #define REG_DCIVERSION       (*(volatile unsigned int *)(USB_BASE+0x120))
  35 #define REG_DCCPARAMS        (*(volatile unsigned int *)(USB_BASE+0x124))
  36 #define REG_USBCMD           (*(volatile unsigned int *)(USB_BASE+0x140))
  37 #define REG_USBSTS           (*(volatile unsigned int *)(USB_BASE+0x144))
  38 #define REG_USBINTR          (*(volatile unsigned int *)(USB_BASE+0x148))
  39 #define REG_FRINDEX          (*(volatile unsigned int *)(USB_BASE+0x14c))
  40 #define REG_DEVICEADDR       (*(volatile unsigned int *)(USB_BASE+0x154))
  41 #define REG_ENDPOINTLISTADDR (*(volatile unsigned int *)(USB_BASE+0x158))
  42 #define REG_BURSTSIZE        (*(volatile unsigned int *)(USB_BASE+0x160))
  43 #define REG_CONFIGFLAG       (*(volatile unsigned int *)(USB_BASE+0x180))
  44 #define REG_PORTSC1          (*(volatile unsigned int *)(USB_BASE+0x184))
  45 #define REG_OTGSC            (*(volatile unsigned int *)(USB_BASE+0x1a4))
  46 #define REG_USBMODE          (*(volatile unsigned int *)(USB_BASE+0x1a8))
  47 #define REG_ENDPTSETUPSTAT   (*(volatile unsigned int *)(USB_BASE+0x1ac))
  48 #define REG_ENDPTPRIME       (*(volatile unsigned int *)(USB_BASE+0x1b0))
  49 #define REG_ENDPTFLUSH       (*(volatile unsigned int *)(USB_BASE+0x1b4))
  50 #define REG_ENDPTSTATUS      (*(volatile unsigned int *)(USB_BASE+0x1b8))
  51 #define REG_ENDPTCOMPLETE    (*(volatile unsigned int *)(USB_BASE+0x1bc))
  52 #define REG_ENDPTCTRL0       (*(volatile unsigned int *)(USB_BASE+0x1c0))
  53 #define REG_ENDPTCTRL1       (*(volatile unsigned int *)(USB_BASE+0x1c4))
  54 #define REG_ENDPTCTRL2       (*(volatile unsigned int *)(USB_BASE+0x1c8))
  55 #define REG_ENDPTCTRL(_x_)   (*(volatile unsigned int *)(USB_BASE+0x1c0+4*(_x_)))
  56
  57 /* Frame Index Register Bit Masks */
  58 #define USB_FRINDEX_MASKS                      (0x3fff)
  59
  60 /* USB CMD  Register Bit Masks */
  61 #define USBCMD_RUN                            (0x00000001)
  62 #define USBCMD_CTRL_RESET                     (0x00000002)
  63 #define USBCMD_PERIODIC_SCHEDULE_EN           (0x00000010)
  64 #define USBCMD_ASYNC_SCHEDULE_EN              (0x00000020)
  65 #define USBCMD_INT_AA_DOORBELL                (0x00000040)
  66 #define USBCMD_ASP                            (0x00000300)
  67 #define USBCMD_ASYNC_SCH_PARK_EN              (0x00000800)
  68 #define USBCMD_SUTW                           (0x00002000)
  69 #define USBCMD_ATDTW                          (0x00004000)
  70 #define USBCMD_ITC                            (0x00FF0000)
  71
  72 /* bit 15,3,2 are frame list size */
  73 #define USBCMD_FRAME_SIZE_1024                (0x00000000)
  74 #define USBCMD_FRAME_SIZE_512                 (0x00000004)
  75 #define USBCMD_FRAME_SIZE_256                 (0x00000008)
  76 #define USBCMD_FRAME_SIZE_128                 (0x0000000C)
  77 #define USBCMD_FRAME_SIZE_64                  (0x00008000)
  78 #define USBCMD_FRAME_SIZE_32                  (0x00008004)
  79 #define USBCMD_FRAME_SIZE_16                  (0x00008008)
  80 #define USBCMD_FRAME_SIZE_8                   (0x0000800C)
  81
  82 /* bit 9-8 are async schedule park mode count */
  83 #define USBCMD_ASP_00                         (0x00000000)
  84 #define USBCMD_ASP_01                         (0x00000100)
  85 #define USBCMD_ASP_10                         (0x00000200)
  86 #define USBCMD_ASP_11                         (0x00000300)
  87 #define USBCMD_ASP_BIT_POS                    (8)
  88
  89 /* bit 23-16 are interrupt threshold control */
  90 #define USBCMD_ITC_NO_THRESHOLD               (0x00000000)
  91 #define USBCMD_ITC_1_MICRO_FRM                (0x00010000)
  92 #define USBCMD_ITC_2_MICRO_FRM                (0x00020000)
  93 #define USBCMD_ITC_4_MICRO_FRM                (0x00040000)
  94 #define USBCMD_ITC_8_MICRO_FRM                (0x00080000)
  95 #define USBCMD_ITC_16_MICRO_FRM               (0x00100000)
  96 #define USBCMD_ITC_32_MICRO_FRM               (0x00200000)
  97 #define USBCMD_ITC_64_MICRO_FRM               (0x00400000)
  98 #define USBCMD_ITC_BIT_POS                    (16)
  99
 100 /* USB STS Register Bit Masks */
 101 #define USBSTS_INT                            (0x00000001)
 102 #define USBSTS_ERR                            (0x00000002)
 103 #define USBSTS_PORT_CHANGE                    (0x00000004)
 104 #define USBSTS_FRM_LST_ROLL                   (0x00000008)
 105 #define USBSTS_SYS_ERR                        (0x00000010) /* not used */
 106 #define USBSTS_IAA                            (0x00000020)
 107 #define USBSTS_RESET                          (0x00000040)
 108 #define USBSTS_SOF                            (0x00000080)
 109 #define USBSTS_SUSPEND                        (0x00000100)
 110 #define USBSTS_HC_HALTED                      (0x00001000)
 111 #define USBSTS_RCL                            (0x00002000)
 112 #define USBSTS_PERIODIC_SCHEDULE              (0x00004000)
 113 #define USBSTS_ASYNC_SCHEDULE                 (0x00008000)
 114
 115 /* USB INTR Register Bit Masks */
 116 #define USBINTR_INT_EN                        (0x00000001)
 117 #define USBINTR_ERR_INT_EN                    (0x00000002)
 118 #define USBINTR_PTC_DETECT_EN                 (0x00000004)
 119 #define USBINTR_FRM_LST_ROLL_EN               (0x00000008)
 120 #define USBINTR_SYS_ERR_EN                    (0x00000010)
 121 #define USBINTR_ASYN_ADV_EN                   (0x00000020)
 122 #define USBINTR_RESET_EN                      (0x00000040)
 123 #define USBINTR_SOF_EN                        (0x00000080)
 124 #define USBINTR_DEVICE_SUSPEND                (0x00000100)
 125
 126 /* Device Address bit masks */
 127 #define USBDEVICEADDRESS_MASK                 (0xFE000000)
 128 #define USBDEVICEADDRESS_BIT_POS              (25)
 129
 130 /* endpoint list address bit masks */
 131 #define USB_EP_LIST_ADDRESS_MASK               (0xfffff800)
 132
 133 /* PORTSCX  Register Bit Masks */
 134 #define PORTSCX_CURRENT_CONNECT_STATUS         (0x00000001)
 135 #define PORTSCX_CONNECT_STATUS_CHANGE          (0x00000002)
 136 #define PORTSCX_PORT_ENABLE                    (0x00000004)
 137 #define PORTSCX_PORT_EN_DIS_CHANGE             (0x00000008)
 138 #define PORTSCX_OVER_CURRENT_ACT               (0x00000010)
 139 #define PORTSCX_OVER_CURRENT_CHG               (0x00000020)
 140 #define PORTSCX_PORT_FORCE_RESUME              (0x00000040)
 141 #define PORTSCX_PORT_SUSPEND                   (0x00000080)
 142 #define PORTSCX_PORT_RESET                     (0x00000100)
 143 #define PORTSCX_LINE_STATUS_BITS               (0x00000C00)
 144 #define PORTSCX_PORT_POWER                     (0x00001000)
 145 #define PORTSCX_PORT_INDICTOR_CTRL             (0x0000C000)
 146 #define PORTSCX_PORT_TEST_CTRL                 (0x000F0000)
 147 #define PORTSCX_WAKE_ON_CONNECT_EN             (0x00100000)
 148 #define PORTSCX_WAKE_ON_CONNECT_DIS            (0x00200000)
 149 #define PORTSCX_WAKE_ON_OVER_CURRENT           (0x00400000)
 150 #define PORTSCX_PHY_LOW_POWER_SPD              (0x00800000)
 151 #define PORTSCX_PORT_FORCE_FULL_SPEED          (0x01000000)
 152 #define PORTSCX_PORT_SPEED_MASK                (0x0C000000)
 153 #define PORTSCX_PORT_WIDTH                     (0x10000000)
 154 #define PORTSCX_PHY_TYPE_SEL                   (0xC0000000)
 155
 156 /* bit 11-10 are line status */
 157 #define PORTSCX_LINE_STATUS_SE0                (0x00000000)
 158 #define PORTSCX_LINE_STATUS_JSTATE             (0x00000400)
 159 #define PORTSCX_LINE_STATUS_KSTATE             (0x00000800)
 160 #define PORTSCX_LINE_STATUS_UNDEF              (0x00000C00)
 161 #define PORTSCX_LINE_STATUS_BIT_POS            (10)
 162
 163 /* bit 15-14 are port indicator control */
 164 #define PORTSCX_PIC_OFF                        (0x00000000)
 165 #define PORTSCX_PIC_AMBER                      (0x00004000)
 166 #define PORTSCX_PIC_GREEN                      (0x00008000)
 167 #define PORTSCX_PIC_UNDEF                      (0x0000C000)
 168 #define PORTSCX_PIC_BIT_POS                    (14)
 169
 170 /* bit 19-16 are port test control */
 171 #define PORTSCX_PTC_DISABLE                    (0x00000000)
 172 #define PORTSCX_PTC_JSTATE                     (0x00010000)
 173 #define PORTSCX_PTC_KSTATE                     (0x00020000)
 174 #define PORTSCX_PTC_SEQNAK                     (0x00030000)
 175 #define PORTSCX_PTC_PACKET                     (0x00040000)
 176 #define PORTSCX_PTC_FORCE_EN                   (0x00050000)
 177 #define PORTSCX_PTC_BIT_POS                    (16)
 178
 179 /* bit 27-26 are port speed */
 180 #define PORTSCX_PORT_SPEED_FULL                (0x00000000)
 181 #define PORTSCX_PORT_SPEED_LOW                 (0x04000000)
 182 #define PORTSCX_PORT_SPEED_HIGH                (0x08000000)
 183 #define PORTSCX_PORT_SPEED_UNDEF               (0x0C000000)
 184 #define PORTSCX_SPEED_BIT_POS                  (26)
 185
 186 /* bit 28 is parallel transceiver width for UTMI interface */
 187 #define PORTSCX_PTW                            (0x10000000)
 188 #define PORTSCX_PTW_8BIT                       (0x00000000)
 189 #define PORTSCX_PTW_16BIT                      (0x10000000)
 190
 191 /* bit 31-30 are port transceiver select */
 192 #define PORTSCX_PTS_UTMI                       (0x00000000)
 193 #define PORTSCX_PTS_ULPI                       (0x80000000)
 194 #define PORTSCX_PTS_FSLS                       (0xC0000000)
 195 #define PORTSCX_PTS_BIT_POS                    (30)
 196
 197 /* USB MODE Register Bit Masks */
 198 #define USBMODE_CTRL_MODE_IDLE                (0x00000000)
 199 #define USBMODE_CTRL_MODE_DEVICE              (0x00000002)
 200 #define USBMODE_CTRL_MODE_HOST                (0x00000003)
 201 #define USBMODE_CTRL_MODE_RSV                 (0x00000001)
 202 #define USBMODE_SETUP_LOCK_OFF                (0x00000008)
 203 #define USBMODE_STREAM_DISABLE                (0x00000010)
 204
 205 /* Endpoint Flush Register */
 206 #define EPFLUSH_TX_OFFSET                      (0x00010000)
 207 #define EPFLUSH_RX_OFFSET                      (0x00000000)
 208
 209 /* Endpoint Setup Status bit masks */
 210 #define EPSETUP_STATUS_MASK                   (0x0000003F)
 211 #define EPSETUP_STATUS_EP0                    (0x00000001)
 212
 213 /* ENDPOINTCTRLx  Register Bit Masks */
 214 #define EPCTRL_TX_ENABLE                       (0x00800000)
 215 #define EPCTRL_TX_DATA_TOGGLE_RST              (0x00400000)    /* Not EP0 */
 216 #define EPCTRL_TX_DATA_TOGGLE_INH              (0x00200000)    /* Not EP0 */
 217 #define EPCTRL_TX_TYPE                         (0x000C0000)
 218 #define EPCTRL_TX_DATA_SOURCE                  (0x00020000)    /* Not EP0 */
 219 #define EPCTRL_TX_EP_STALL                     (0x00010000)
 220 #define EPCTRL_RX_ENABLE                       (0x00000080)
 221 #define EPCTRL_RX_DATA_TOGGLE_RST              (0x00000040)    /* Not EP0 */
 222 #define EPCTRL_RX_DATA_TOGGLE_INH              (0x00000020)    /* Not EP0 */
 223 #define EPCTRL_RX_TYPE                         (0x0000000C)
 224 #define EPCTRL_RX_DATA_SINK                    (0x00000002)    /* Not EP0 */
 225 #define EPCTRL_RX_EP_STALL                     (0x00000001)
 226
 227 /* bit 19-18 and 3-2 are endpoint type */
 228 #define EPCTRL_EP_TYPE_CONTROL                 (0)
 229 #define EPCTRL_EP_TYPE_ISO                     (1)
 230 #define EPCTRL_EP_TYPE_BULK                    (2)
 231 #define EPCTRL_EP_TYPE_INTERRUPT               (3)
 232 #define EPCTRL_TX_EP_TYPE_SHIFT                (18)
 233 #define EPCTRL_RX_EP_TYPE_SHIFT                (2)
 234
 235 /* pri_ctrl Register Bit Masks */
 236 #define PRI_CTRL_PRI_LVL1                      (0x0000000C)
 237 #define PRI_CTRL_PRI_LVL0                      (0x00000003)
 238
 239 /* si_ctrl Register Bit Masks */
 240 #define SI_CTRL_ERR_DISABLE                    (0x00000010)
 241 #define SI_CTRL_IDRC_DISABLE                   (0x00000008)
 242 #define SI_CTRL_RD_SAFE_EN                     (0x00000004)
 243 #define SI_CTRL_RD_PREFETCH_DISABLE            (0x00000002)
 244 #define SI_CTRL_RD_PREFEFETCH_VAL              (0x00000001)
 245
 246 /* control Register Bit Masks */
 247 #define USB_CTRL_IOENB                         (0x00000004)
 248 #define USB_CTRL_ULPI_INT0EN                   (0x00000001)
 249
 250 #define QH_MULT_POS                            (30)
 251 #define QH_ZLT_SEL                             (0x20000000)
 252 #define QH_MAX_PKT_LEN_POS                     (16)
 253 #define QH_IOS                                 (0x00008000)
 254 #define QH_NEXT_TERMINATE                      (0x00000001)
 255 #define QH_IOC                                 (0x00008000)
 256 #define QH_MULTO                               (0x00000C00)
 257 #define QH_STATUS_HALT                         (0x00000040)
 258 #define QH_STATUS_ACTIVE                       (0x00000080)
 259 #define EP_QUEUE_CURRENT_OFFSET_MASK         (0x00000FFF)
 260 #define EP_QUEUE_HEAD_NEXT_POINTER_MASK      (0xFFFFFFE0)
 261 #define EP_QUEUE_FRINDEX_MASK                (0x000007FF)
 262 #define EP_MAX_LENGTH_TRANSFER               (0x4000)
 263
 264 #define DTD_NEXT_TERMINATE                   (0x00000001)
 265 #define DTD_IOC                              (0x00008000)
 266 #define DTD_STATUS_ACTIVE                    (0x00000080)
 267 #define DTD_STATUS_HALTED                    (0x00000040)
 268 #define DTD_STATUS_DATA_BUFF_ERR             (0x00000020)
 269 #define DTD_STATUS_TRANSACTION_ERR           (0x00000008)
 270 #define DTD_RESERVED_FIELDS                  (0x80007300)
 271 #define DTD_ADDR_MASK                        (0xFFFFFFE0)
 272 #define DTD_PACKET_SIZE                      (0x7FFF0000)
 273 #define DTD_LENGTH_BIT_POS                   (16)
 274 #define DTD_ERROR_MASK                       (DTD_STATUS_HALTED | \
 275                                                DTD_STATUS_DATA_BUFF_ERR | \
 276                                                DTD_STATUS_TRANSACTION_ERR)
 277
 278 /*-------------------------------------------------------------------------*/
 279
 280 /* manual: 32.13.2 Endpoint Transfer Descriptor (dTD) */
 281 struct transfer_descriptor {
 282     unsigned int next_td_ptr;           /* Next TD pointer(31-5), T(0) set
 283                                            indicate invalid */
 284     unsigned int size_ioc_sts;          /* Total bytes (30-16), IOC (15),
 285                                            MultO(11-10), STS (7-0)  */
 286     unsigned int buff_ptr0;             /* Buffer pointer Page 0 */
 287     unsigned int buff_ptr1;             /* Buffer pointer Page 1 */
 288     unsigned int buff_ptr2;             /* Buffer pointer Page 2 */
 289     unsigned int buff_ptr3;             /* Buffer pointer Page 3 */
 290     unsigned int buff_ptr4;             /* Buffer pointer Page 4 */
 291     unsigned int reserved;
 292 } __attribute__ ((packed));
 293
 294 static struct transfer_descriptor _td_array[NUM_ENDPOINTS*2] __attribute((aligned (32)));
 295 static struct transfer_descriptor* td_array;
 296
 297 /* manual: 32.13.1 Endpoint Queue Head (dQH) */
 298 struct queue_head {
 299     unsigned int max_pkt_length;    /* Mult(31-30) , Zlt(29) , Max Pkt len
 300                                        and IOS(15) */
 301     unsigned int curr_dtd_ptr;      /* Current dTD Pointer(31-5) */
 302     struct transfer_descriptor dtd; /* dTD overlay */
 303     unsigned int setup_buffer[2];   /* Setup data 8 bytes */
 304     unsigned int reserved[4];
 305 } __attribute__((packed));
 306
 307 static struct queue_head _qh_array[NUM_ENDPOINTS*2] __attribute((aligned (2048)));
 308 static struct queue_head* qh_array;
 309
 310
 311 static const unsigned int pipe2mask[NUM_ENDPOINTS*2] = {
 312     0x01, 0x010000,
 313     0x02, 0x020000,
 314     0x04, 0x040000,
 315 };
 316
 317 /*-------------------------------------------------------------------------*/
 318 static void transfer_completed(void);
 319 static void prime_transfer(int endpoint, void* ptr, int len, bool send);
 320 static void bus_reset(void);
 321 static void init_queue_heads(void);
 322 static void init_endpoints(void);
 323 /*-------------------------------------------------------------------------*/
 324
 325
 326 /* manual: 32.14.1 Device Controller Initialization */
 327 void usb_drv_init(void)
 328 {
 329     REG_USBCMD &= ~USBCMD_RUN;
 330     udelay(50000);
 331     REG_USBCMD |= USBCMD_CTRL_RESET;
 332     while (REG_USBCMD & USBCMD_CTRL_RESET);
 333
 334     REG_USBMODE = USBMODE_CTRL_MODE_DEVICE;
 335
 336     td_array = (struct transfer_descriptor*)UNCACHED_ADDR(&_td_array);
 337     qh_array = (struct queue_head*)UNCACHED_ADDR(&_qh_array);
 338     init_queue_heads();
 339     memset(td_array, 0, sizeof _td_array);
 340
 341     REG_ENDPOINTLISTADDR = (unsigned int)qh_array;
 342     REG_DEVICEADDR = 0;
 343
 344     /* enable USB interrupts */
 345     REG_USBINTR =
 346         USBINTR_INT_EN |
 347         USBINTR_ERR_INT_EN |
 348         USBINTR_PTC_DETECT_EN |
 349         USBINTR_RESET_EN |
 350         USBINTR_SYS_ERR_EN;
 351
 352     /* enable USB IRQ in CPU */
 353     CPU_INT_EN |= USB_MASK;
 354
 355     /* go go go */
 356     REG_USBCMD |= USBCMD_RUN;
 357
 358     logf("usb_drv_init() finished");
 359     logf("usb id %x", REG_ID);
 360     logf("usb dciversion %x", REG_DCIVERSION);
 361     logf("usb dccparams %x", REG_DCCPARAMS);
 362
 363     /* now a bus reset will occur. see bus_reset() */
 364 }
 365
 366 void usb_drv_exit(void)
 367 {
 368     /* disable interrupts */
 369     REG_USBINTR = 0;
 370
 371     /* stop usb controller */
 372     REG_USBCMD &= ~USBCMD_RUN;
 373 }
 374
 375 void usb_drv_int(void)
 376 {
 377     unsigned int status = REG_USBSTS;
 378
 379 #if 0
 380     if (status & USBSTS_INT) logf("int: usb ioc");
 381     if (status & USBSTS_ERR) logf("int: usb err");
 382     if (status & USBSTS_PORT_CHANGE) logf("int: portchange");
 383     if (status & USBSTS_RESET) logf("int: reset");
 384     if (status & USBSTS_SYS_ERR) logf("int: syserr");
 385 #endif
 386
 387     /* usb transaction interrupt */
 388     if (status & USBSTS_INT) {
 389         REG_USBSTS |= USBSTS_INT;
 390
 391         /* a control packet? */
 392         if (REG_ENDPTSETUPSTAT & EPSETUP_STATUS_EP0) {
 393             /* copy setup data from packet */
 394             unsigned int tmp[2];
 395             tmp[0] = qh_array[0].setup_buffer[0];
 396             tmp[1] = qh_array[0].setup_buffer[1];
 397
 398             /* acknowledge packet recieved */
 399             REG_ENDPTSETUPSTAT |= EPSETUP_STATUS_EP0;
 400
 401             usb_core_control_request((struct usb_ctrlrequest*)tmp);
 402         }
 403
 404         if (REG_ENDPTCOMPLETE)
 405             transfer_completed();
 406     }
 407
 408     /* error interrupt */
 409     if (status & USBSTS_ERR) {
 410         REG_USBSTS |= USBSTS_ERR;
 411         logf("usb error int");
 412     }
 413
 414     /* reset interrupt */
 415     if (status & USBSTS_RESET) {
 416         REG_USBSTS |= USBSTS_RESET;
 417         bus_reset();
 418         usb_core_bus_reset(); /* tell mom */
 419     }
 420
 421     /* port change */
 422     if (status & USBSTS_PORT_CHANGE) {
 423         REG_USBSTS |= USBSTS_PORT_CHANGE;
 424     }
 425 }
 426
 427 void usb_drv_stall(int endpoint, bool stall)
 428 {
 429     logf("%sstall %d", stall?"":"un", endpoint);
 430
 431     if (stall) {
 432         REG_ENDPTCTRL(endpoint) |= EPCTRL_RX_EP_STALL;
 433         REG_ENDPTCTRL(endpoint) |= EPCTRL_TX_EP_STALL;
 434     }
 435     else {
 436         REG_ENDPTCTRL(endpoint) &= ~EPCTRL_RX_EP_STALL;
 437         REG_ENDPTCTRL(endpoint) &= ~EPCTRL_TX_EP_STALL;
 438     }
 439 }
 440
 441 void usb_drv_send(int endpoint, void* ptr, int length)
 442 {
 443     prime_transfer(endpoint, ptr, length, true);
 444 }
 445
 446 void usb_drv_recv(int endpoint, void* ptr, int length)
 447 {
 448     //logf("usbrecv(%x, %d)", ptr, length);
 449     prime_transfer(endpoint, ptr, length, false);
 450 }
 451
 452 void usb_drv_wait(int endpoint, bool send)
 453 {
 454     int pipe = endpoint * 2 + (send ? 1 : 0);
 455     struct queue_head* qh = &qh_array[pipe];
 456
 457     while (qh->dtd.size_ioc_sts & QH_STATUS_ACTIVE) {
 458         if (REG_USBSTS & USBSTS_RESET)
 459             break;
 460     }
 461 }
 462
 463
 464 void usb_drv_set_address(int address)
 465 {
 466     REG_DEVICEADDR = address << USBDEVICEADDRESS_BIT_POS;
 467     init_endpoints();
 468 }
 469
 470 void usb_drv_reset_endpoint(int endpoint, bool send)
 471 {
 472     int pipe = endpoint * 2 + (send ? 1 : 0);
 473     unsigned int mask = pipe2mask[pipe];
 474     REG_ENDPTFLUSH = mask;
 475     while (REG_ENDPTFLUSH & mask);
 476 }
 477
 478 /*-------------------------------------------------------------------------*/
 479
 480 /* manual: 32.14.5.2 */
 481 static void prime_transfer(int endpoint, void* ptr, int len, bool send)
 482 {
 483     int timeout;
 484     int pipe = endpoint * 2 + (send ? 1 : 0);
 485     unsigned int mask = pipe2mask[pipe];
 486     struct transfer_descriptor* td = &td_array[pipe];
 487     struct queue_head* qh = &qh_array[pipe];
 488
 489     if (send && endpoint > EP_CONTROL) {
 490         logf("usb: sent %d bytes", len);
 491     }
 492
 493     memset(td, 0, sizeof(struct transfer_descriptor));
 494     td->next_td_ptr = DTD_NEXT_TERMINATE;
 495     td->size_ioc_sts = (len << DTD_LENGTH_BIT_POS) |
 496         DTD_STATUS_ACTIVE | DTD_IOC;
 497     td->buff_ptr0 = (unsigned int)ptr;
 498     td->buff_ptr1 = (unsigned int)ptr + 0x1000;
 499     td->buff_ptr2 = (unsigned int)ptr + 0x2000;
 500     td->buff_ptr3 = (unsigned int)ptr + 0x3000;
 501     td->buff_ptr4 = (unsigned int)ptr + 0x4000;
 502     td->reserved = len;
 503     qh->dtd.next_td_ptr = (unsigned int)td;
 504     qh->dtd.size_ioc_sts &= ~(QH_STATUS_HALT | QH_STATUS_ACTIVE);
 505
 506     REG_ENDPTPRIME |= mask;
 507
 508     timeout = 10000;
 509     while ((REG_ENDPTPRIME & mask) && --timeout) {
 510         if (REG_USBSTS & USBSTS_RESET)
 511             break;
 512     }
 513     if (!timeout) {
 514         logf("prime timeout");
 515     }
 516
 517     if (!(REG_ENDPTSTATUS & mask)) {
 518         logf("no prime! %d %d %x", endpoint, pipe, qh->dtd.size_ioc_sts & 0xff );
 519     }
 520
 521     if (send) {
 522         /* wait for transfer to finish */
 523         timeout = 100000;
 524         while ((td->size_ioc_sts & DTD_STATUS_ACTIVE) && --timeout) {
 525             if (REG_ENDPTCOMPLETE & mask)
 526                 REG_ENDPTCOMPLETE |= mask;
 527
 528             if (REG_USBSTS & USBSTS_RESET)
 529                 return;
 530         }
 531         if (!timeout) {
 532             logf("td never finished");
 533             return;
 534         }
 535     }
 536 }
 537
 538 static void transfer_completed(void)
 539 {
 540     int i;
 541     unsigned int mask = REG_ENDPTCOMPLETE;
 542     REG_ENDPTCOMPLETE |= mask;
 543
 544     //logf("usb comp %x", mask);
 545
 546     for (i=0; i<NUM_ENDPOINTS; i++) {
 547         int x;
 548         for (x=0; x<2; x++) {
 549             int pipe = i * 2 + x;
 550             if (mask & pipe2mask[pipe])
 551                 usb_core_transfer_complete(i, x ? true : false);
 552
 553             if ((mask & pipe2mask[pipe]) &&
 554                 (td_array[pipe].size_ioc_sts & DTD_ERROR_MASK)) {
 555                 logf("pipe %d err %x", pipe, td_array[pipe].size_ioc_sts & DTD_ERROR_MASK);
 556             }
 557         }
 558     }
 559 }
 560
 561 /* manual: 32.14.2.1 Bus Reset */
 562 static void bus_reset(void)
 563 {
 564     int i;
 565     logf("usb bus_reset");
 566
 567     REG_DEVICEADDR = 0;
 568     REG_ENDPTSETUPSTAT = REG_ENDPTSETUPSTAT;
 569     REG_ENDPTCOMPLETE  = REG_ENDPTCOMPLETE;
 570
 571     for (i=0; i<100; i++) {
 572         if (!REG_ENDPTPRIME)
 573             break;
 574
 575         if (REG_USBSTS & USBSTS_RESET) {
 576             logf("usb: double reset");
 577             return;
 578         }
 579
 580         udelay(100);
 581     }
 582     if (REG_ENDPTPRIME) {
 583         logf("usb: short reset timeout");
 584     }
 585
 586     REG_ENDPTFLUSH = ~0;
 587     //while (REG_ENDPTFLUSH);
 588
 589     if (!(REG_PORTSC1 & PORTSCX_PORT_RESET)) {
 590         logf("usb: slow reset!");
 591     }
 592 }
 593
 594 /* manual: 32.14.4.1 Queue Head Initialization */
 595 static void init_queue_heads(void)
 596 {
 597     memset(qh_array, 0, sizeof _qh_array);
 598
 599     /*** control ***/
 600     qh_array[EP_CONTROL].max_pkt_length = 512 << QH_MAX_PKT_LEN_POS | QH_IOS;
 601     qh_array[EP_CONTROL].dtd.next_td_ptr = QH_NEXT_TERMINATE;
 602     qh_array[EP_CONTROL+1].max_pkt_length = 512 << QH_MAX_PKT_LEN_POS;
 603     qh_array[EP_CONTROL+1].dtd.next_td_ptr = QH_NEXT_TERMINATE;
 604
 605     /*** bulk ***/
 606     qh_array[EP_RX*2].max_pkt_length = 512 << QH_MAX_PKT_LEN_POS;
 607     qh_array[EP_RX*2].dtd.next_td_ptr = QH_NEXT_TERMINATE;
 608     qh_array[EP_TX*2+1].max_pkt_length = 512 << QH_MAX_PKT_LEN_POS;
 609     qh_array[EP_TX*2+1].dtd.next_td_ptr = QH_NEXT_TERMINATE;
 610 }
 611
 612 static void init_endpoints(void)
 613 {
 614     /* bulk */
 615     REG_ENDPTCTRL(EP_RX) =
 616         EPCTRL_RX_DATA_TOGGLE_RST | EPCTRL_RX_ENABLE |
 617         (EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT) |
 618         (EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT);
 619
 620     REG_ENDPTCTRL(EP_TX) =
 621         EPCTRL_TX_DATA_TOGGLE_RST | EPCTRL_TX_ENABLE |
 622         (EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT) |
 623         (EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT);
 624 }