firmware/drivers/uda1380.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2005 by Andy Young
  11  *
  12  * All files in this archive are subject to the GNU General Public License.
  13  * See the file COPYING in the source tree root for full license agreement.
  14  *
  15  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  16  * KIND, either express or implied.
  17  *
  18  ****************************************************************************/
  19 #include "lcd.h"
  20 #include "cpu.h"
  21 #include "kernel.h"
  22 #include "thread.h"
  23 #include "power.h"
  24 #include "debug.h"
  25 #include "system.h"
  26 #include "sprintf.h"
  27 #include "button.h"
  28 #include "string.h"
  29 #include "file.h"
  30 #include "buffer.h"
  31 #include "audio.h"
  32 #include "logf.h"
  33
  34 #include "i2c-coldfire.h"
  35 #include "uda1380.h"
  36 #include "pcf50606.h"
  37
  38 /* ------------------------------------------------- */
  39 /* Local functions and variables */
  40 /* ------------------------------------------------- */
  41
  42 int uda1380_write_reg(unsigned char reg, unsigned short value);
  43 unsigned short uda1380_regs[0x30];
  44 short recgain_mic;
  45 short recgain_line;
  46
  47 /* Definition of a playback configuration to start with */
  48
  49 #define NUM_DEFAULT_REGS 13
  50 unsigned short uda1380_defaults[2*NUM_DEFAULT_REGS] =
  51 {
  52    REG_0,          EN_DAC | EN_INT | EN_DEC | SYSCLK_256FS | WSPLL_25_50,
  53    REG_I2S,        I2S_IFMT_IIS,
  54    REG_PWR,        PON_BIAS,
  55                    /* PON_HP & PON_DAC is enabled later */
  56    REG_AMIX,       AMIX_RIGHT(0x3f) | AMIX_LEFT(0x3f),
  57                    /* 00=max, 3f=mute */
  58    REG_MASTER_VOL, MASTER_VOL_LEFT(0x20) | MASTER_VOL_RIGHT(0x20),
  59                    /* 00=max, ff=mute */
  60    REG_MIX_VOL,    MIX_VOL_CH_1(0) | MIX_VOL_CH_2(0xff),
  61                    /* 00=max, ff=mute */
  62    REG_EQ,         EQ_MODE_MAX,
  63                    /* Bass and tremble = 0 dB */
  64    REG_MUTE,       MUTE_MASTER | MUTE_CH2,
  65                    /* Mute everything to start with */
  66    REG_MIX_CTL,    MIX_CTL_MIX,
  67                    /* Enable mixer */
  68    REG_DEC_VOL,    0,
  69    REG_PGA,        MUTE_ADC,
  70    REG_ADC,        SKIP_DCFIL,
  71    REG_AGC,        0
  72 };
  73
  74
  75
  76 /* Returns 0 if register was written or -1 if write failed */
  77 int uda1380_write_reg(unsigned char reg, unsigned short value)
  78 {
  79     unsigned char data[4];
  80
  81     data[0] = UDA1380_ADDR;
  82     data[1] = reg;
  83     data[2] = value >> 8;
  84     data[3] = value & 0xff;
  85
  86     if (i2c_write(1, data, 4) != 4)
  87     {
  88         DEBUGF("uda1380 error reg=0x%x", reg);
  89         return -1;
  90     }
  91
  92     uda1380_regs[reg] = value;
  93
  94     return 0;
  95 }
  96
  97 /**
  98  * Sets left and right master volume  (0(max) to 252(muted))
  99  */
 100 int uda1380_set_master_vol(int vol_l, int vol_r)
 101 {
 102     return uda1380_write_reg(REG_MASTER_VOL,
 103                              MASTER_VOL_LEFT(vol_l) | MASTER_VOL_RIGHT(vol_r));
 104 }
 105
 106 /**
 107  * Sets mixer volume for both channels (0(max) to 228(muted))
 108  */
 109 int uda1380_set_mixer_vol(int channel1, int channel2)
 110 {
 111     return uda1380_write_reg(REG_MIX_VOL,
 112                              MIX_VOL_CH_1(channel1) | MIX_VOL_CH_2(channel2));
 113 }
 114
 115 /**
 116  * Sets the bass value (0-12)
 117  */
 118 void uda1380_set_bass(int value)
 119 {
 120     uda1380_write_reg(REG_EQ, (uda1380_regs[REG_EQ] & ~BASS_MASK)
 121                               | BASSL(value) | BASSR(value));
 122 }
 123
 124 /**
 125  * Sets the treble value (0-3)
 126  */
 127 void uda1380_set_treble(int value)
 128 {
 129     uda1380_write_reg(REG_EQ, (uda1380_regs[REG_EQ] & ~TREBLE_MASK)
 130                               | TREBLEL(value) | TREBLER(value));
 131 }
 132
 133 /**
 134  * Mute (mute=1) or enable sound (mute=0)
 135  *
 136  */
 137 int uda1380_mute(int mute)
 138 {
 139     unsigned int value = uda1380_regs[REG_MUTE];
 140
 141     if (mute)
 142         value = value | MUTE_MASTER;
 143     else
 144         value = value & ~MUTE_MASTER;
 145
 146     return uda1380_write_reg(REG_MUTE, value);
 147 }
 148
 149 /* Returns 0 if successful or -1 if some register failed */
 150 int uda1380_set_regs(void)
 151 {
 152     int i;
 153     memset(uda1380_regs, 0, sizeof(uda1380_regs));
 154
 155     /* Initialize all registers */
 156     for (i=0; i<NUM_DEFAULT_REGS; i++)
 157     {
 158         unsigned char reg = uda1380_defaults[i*2+0];
 159         unsigned short value = uda1380_defaults[i*2+1];
 160
 161         if (uda1380_write_reg(reg, value) == -1)
 162             return -1;
 163     }
 164
 165     return 0;
 166 }
 167
 168 /* Silently enable / disable audio output */
 169 void uda1380_enable_output(bool enable)
 170 {
 171     if (enable) {
 172         uda1380_write_reg(REG_PWR, uda1380_regs[REG_PWR] | PON_DAC | PON_HP);
 173     } else {
 174         uda1380_write_reg(REG_MUTE, MUTE_MASTER);
 175         uda1380_write_reg(REG_PWR, uda1380_regs[REG_PWR] & ~PON_DAC);
 176     }
 177 }
 178
 179 void uda1380_reset(void)
 180 {
 181 #ifdef IRIVER_H300_SERIES
 182     int mask = set_irq_level(HIGHEST_IRQ_LEVEL);
 183     pcf50606_write(0x3b, 0x00);  /* GPOOD2 high Z */
 184     pcf50606_write(0x3b, 0x07);  /* GPOOD2 low */
 185     set_irq_level(mask);
 186 #else
 187     /* RESET signal */
 188     or_l(1<<29, &GPIO_OUT);
 189     or_l(1<<29, &GPIO_ENABLE);
 190     or_l(1<<29, &GPIO_FUNCTION);
 191     sleep(HZ/100);
 192     and_l(~(1<<29), &GPIO_OUT);
 193 #endif
 194 }
 195
 196 /* Initialize UDA1380 codec with default register values (uda1380_defaults) */
 197 int uda1380_init(void)
 198 {
 199     recgain_mic = 0;
 200     recgain_line = 0;
 201
 202     uda1380_reset();
 203
 204     if (uda1380_set_regs() == -1)
 205         return -1;
 206
 207     return 0;
 208 }
 209
 210 /* Nice shutdown of UDA1380 codec */
 211 void uda1380_close(void)
 212 {
 213     /* First enable mute and sleep a while */
 214     uda1380_write_reg(REG_MUTE, MUTE_MASTER);
 215     sleep(HZ/8);
 216
 217     /* Then power off the rest of the chip */
 218     uda1380_write_reg(REG_PWR, 0);
 219     uda1380_write_reg(REG_0, 0);    /* Disable codec    */
 220 }
 221
 222 /**
 223  * Calling this function enables the UDA1380 to send
 224  * sound samples over the I2S bus, which is connected
 225  * to the processor's IIS1 interface.
 226  *
 227  * source_mic: true=record from microphone, false=record from line-in (or radio)
 228  */
 229 void uda1380_enable_recording(bool source_mic)
 230 {
 231     uda1380_write_reg(REG_0, uda1380_regs[REG_0] | EN_ADC);
 232
 233     if (source_mic)
 234     {
 235         /* VGA_GAIN: 0=0 dB, F=30dB */
 236         uda1380_write_reg(REG_PWR, uda1380_regs[REG_PWR] | PON_LNA | PON_ADCL);
 237         uda1380_write_reg(REG_ADC, (uda1380_regs[REG_ADC] & VGA_GAIN_MASK)
 238                                    | SEL_LNA | SEL_MIC | EN_DCFIL);
 239         uda1380_write_reg(REG_PGA, 0);
 240     } else
 241     {
 242         /* PGA_GAIN: 0=0 dB, F=24dB */
 243         uda1380_write_reg(REG_PWR, uda1380_regs[REG_PWR] | PON_PGAL | PON_ADCL
 244                                    | PON_PGAR | PON_ADCR);
 245         uda1380_write_reg(REG_ADC, EN_DCFIL);
 246         uda1380_write_reg(REG_PGA, (uda1380_regs[REG_PGA] & PGA_GAIN_MASK)
 247                                    | PGA_GAINL(0) | PGA_GAINR(0));
 248     }
 249
 250     sleep(HZ/8);
 251
 252     uda1380_write_reg(REG_I2S,     uda1380_regs[REG_I2S] | I2S_MODE_MASTER);
 253     uda1380_write_reg(REG_MIX_CTL, MIX_MODE(1));
 254
 255 }
 256
 257 /**
 258  * Stop sending samples on the I2S bus
 259  */
 260 void uda1380_disable_recording(void)
 261 {
 262     uda1380_write_reg(REG_PGA, MUTE_ADC);
 263     sleep(HZ/8);
 264
 265     uda1380_write_reg(REG_I2S, I2S_IFMT_IIS);
 266     uda1380_write_reg(REG_PWR, uda1380_regs[REG_PWR] & ~(PON_LNA | PON_ADCL
 267                                                          | PON_ADCR | PON_PGAL
 268                                                          | PON_PGAR));
 269     uda1380_write_reg(REG_0,   uda1380_regs[REG_0] & ~EN_ADC);
 270     uda1380_write_reg(REG_ADC, SKIP_DCFIL);
 271 }
 272
 273 /**
 274  * Set recording gain and volume
 275  *
 276  * type:                params:        ranges:
 277  * AUDIO_GAIN_MIC:      left           -128 .. 108 -> -64 .. 54 dB gain
 278  * AUDIO_GAIN_LINEIN    left & right   -128 ..  96 -> -64 .. 48 dB gain
 279  *
 280  * Note: - For all types the value 0 gives 0 dB gain.
 281  *       - order of setting both values determines if the small glitch will
 282            be a peak or a dip. The small glitch is caused by the time between
 283            setting the two gains
 284  */
 285 void uda1380_set_recvol(int left, int right, int type)
 286 {
 287     int left_ag, right_ag;
 288
 289     switch (type)
 290     {
 291         case AUDIO_GAIN_MIC:
 292             left_ag = MIN(MAX(0, left / 4), 15);
 293             left -= left_ag * 4;
 294
 295             if(left < recgain_mic)
 296             {
 297                 uda1380_write_reg(REG_DEC_VOL, DEC_VOLL(left)
 298                                                    | DEC_VOLR(left));
 299                 uda1380_write_reg(REG_ADC, (uda1380_regs[REG_ADC]
 300                                                & ~VGA_GAIN_MASK)
 301                                             | VGA_GAIN(left_ag));
 302             }
 303             else
 304             {
 305                 uda1380_write_reg(REG_ADC, (uda1380_regs[REG_ADC]
 306                                                & ~VGA_GAIN_MASK)
 307                                             | VGA_GAIN(left_ag));
 308                 uda1380_write_reg(REG_DEC_VOL, DEC_VOLL(left)
 309                                                    | DEC_VOLR(left));
 310             }
 311             recgain_mic = left;
 312             logf("Mic: %dA/%dD", left_ag, left);
 313             break;
 314
 315         case AUDIO_GAIN_LINEIN:
 316             left_ag = MIN(MAX(0, left / 6), 8);
 317             left -= left_ag * 6;
 318             right_ag = MIN(MAX(0, right / 6), 8);
 319             right -= right_ag * 6;
 320
 321             if(left < recgain_line)
 322             {
 323                 /* for this order we can combine both registers,
 324                     making the glitch even smaller */
 325                 unsigned char data[6];
 326                 unsigned short value_dec;
 327                 unsigned short value_pga;
 328                 value_dec = DEC_VOLL(left) | DEC_VOLR(right);
 329                 value_pga = (uda1380_regs[REG_PGA] & ~PGA_GAIN_MASK)
 330                                 | PGA_GAINL(left_ag) | PGA_GAINR(right_ag);
 331
 332                 data[0] = UDA1380_ADDR;
 333                 data[1] = REG_DEC_VOL;
 334                 data[2] = value_dec >> 8;
 335                 data[3] = value_dec & 0xff;
 336                 data[4] = value_pga >> 8;
 337                 data[5] = value_pga & 0xff;
 338
 339                 if (i2c_write(1, data, 6) != 6)
 340                 {
 341                     DEBUGF("uda1380 error reg=combi rec gain");
 342                 }
 343                 else
 344                 {
 345                     uda1380_regs[REG_DEC_VOL] = value_dec;
 346                     uda1380_regs[REG_PGA] = value_pga;
 347                 }
 348             }
 349             else
 350             {
 351                 uda1380_write_reg(REG_PGA, (uda1380_regs[REG_PGA]
 352                                                & ~PGA_GAIN_MASK)
 353                                             | PGA_GAINL(left_ag)
 354                                             | PGA_GAINR(right_ag));
 355                 uda1380_write_reg(REG_DEC_VOL, DEC_VOLL(left)
 356                                                    | DEC_VOLR(right));
 357             }
 358
 359             recgain_line = left;
 360             logf("Line L: %dA/%dD", left_ag, left);
 361             logf("Line R: %dA/%dD", right_ag, right);
 362             break;
 363     }
 364 }
 365
 366
 367 /**
 368  * Enable or disable recording monitor (so one can listen to the recording)
 369  *
 370  */
 371 void uda1380_set_monitor(int enable)
 372 {
 373     if (enable)    /* enable channel 2 */
 374         uda1380_write_reg(REG_MUTE, uda1380_regs[REG_MUTE] & ~MUTE_CH2);
 375     else           /* mute channel 2 */
 376         uda1380_write_reg(REG_MUTE, uda1380_regs[REG_MUTE] | MUTE_CH2);
 377 }
 378
 379 /* Change the order of the noise chaper,
 380    5th order is recommended above 32kHz */
 381 void uda1380_set_nsorder(int order)
 382 {
 383     switch(order)
 384     {
 385     case 5:
 386         uda1380_write_reg(REG_MIX_CTL, uda1380_regs[REG_MIX_CTL]
 387                                        | MIX_CTL_SEL_NS);
 388         break;
 389     case 3:
 390     default:
 391         uda1380_write_reg(REG_MIX_CTL, uda1380_regs[REG_MIX_CTL]
 392                                        & ~MIX_CTL_SEL_NS);
 393     }
 394 }