firmware/target/arm/as3525/debug-as3525.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright © 2008 Rafaël Carré
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21
  22 #include <stdbool.h>
  23 #include "debug-target.h"
  24 #include "button.h"
  25 #include "lcd.h"
  26 #include "font.h"
  27 #include "system.h"
  28 #include "sprintf.h"
  29 #include "cpu.h"
  30 #include "pl180.h"
  31 #include "ascodec-target.h"
  32 #include "adc.h"
  33 #include "storage.h"
  34
  35 #define ON "Enabled"
  36 #define OFF "Disabled"
  37
  38 #define CP15_MMU (1<<0)            /* mmu off/on */
  39 #define CP15_DC  (1<<2)            /* dcache off/on */
  40 #define CP15_IC  (1<<12)           /* icache off/on */
  41
  42 #define CLK_MAIN         24000000     /* 24 MHz  */
  43
  44 #define CLK_PLLA             0
  45 #define CLK_PLLB             1
  46 #define CLK_PROC             2
  47 #define CLK_FCLK             3
  48 #define CLK_EXTMEM           4
  49 #define CLK_PCLK             5
  50 #define CLK_IDE              6
  51 #define CLK_I2C              7
  52 #define CLK_I2SI             8
  53 #define CLK_I2SO             9
  54 #define CLK_DBOP             10
  55 #define CLK_SD_MCLK_NAND     11
  56 #define CLK_SD_MCLK_MSD      12
  57 #define CLK_USB              13
  58
  59 #define I2C2_CPSR0      *((volatile unsigned int *)(I2C_AUDIO_BASE + 0x1C))
  60 #define I2C2_CPSR1      *((volatile unsigned int *)(I2C_AUDIO_BASE + 0x20))
  61 #define MCI_NAND        *((volatile unsigned long *)(NAND_FLASH_BASE + 0x04))
  62 #define MCI_SD          *((volatile unsigned long *)(SD_MCI_BASE + 0x04))
  63
  64 extern bool sd_enabled;
  65
  66 /* FIXME: target tree is including ./debug-target.h rather than the one in
  67  * sansa-fuze/, even though deps contains the correct one
  68  * if I put the below into a sansa-fuze/debug-target.h, it doesn't work*/
  69 #if defined(SANSA_FUZE) || defined(SANSA_E200V2) || defined(SANSA_C200V2)
  70 #define DEBUG_DBOP
  71 #include "dbop-as3525.h"
  72 #endif
  73
  74 static inline unsigned read_cp15 (void)
  75 {
  76     unsigned cp15_value;
  77     asm volatile (
  78         "mrc p15, 0, %0, c1, c0, 0   @ read control reg\n" : "=r"(cp15_value));
  79     return (cp15_value);
  80 }
  81
  82 static int calc_freq(int clk)
  83 {
  84     unsigned int prediv = ((unsigned int)CGU_PROC>>2) & 0x3;
  85     unsigned int postdiv = ((unsigned int)CGU_PROC>>4) & 0xf;
  86 #if CONFIG_CPU == AS3525
  87     int out_div;
  88
  89     switch(clk) {
  90         /* clk_main = clk_int = 24MHz oscillator */
  91         case CLK_PLLA:
  92             if(CGU_PLLASUP & (1<<3))
  93                 return 0;
  94
  95                  /*assume 24MHz oscillator only input available */
  96             out_div = ((CGU_PLLA>>13) & 0x3);         /* bits 13:14 */
  97             if (out_div == 3)                         /* for 11 NO=4  */
  98                 out_div=4;
  99             if(out_div)                               /*  NO = 0 not allowed */
 100                 return ((2 * (CGU_PLLA & 0xff))*CLK_MAIN)/
 101                                                (((CGU_PLLA>>8) & 0x1f)*out_div);
 102             return 0;
 103        case CLK_PLLB:
 104             if(CGU_PLLBSUP & (1<<3))
 105                 return 0;
 106
 107                  /*assume 24MHz oscillator only input available */
 108             out_div = ((CGU_PLLB>>13) & 0x3);         /* bits 13:14 */
 109             if (out_div == 3)                         /* for 11 NO=4  */
 110                 out_div=4;
 111             if(out_div)                               /*  NO = 0 not allowed */
 112                 return ((2 * (CGU_PLLB & 0xff))*CLK_MAIN)/
 113                                                (((CGU_PLLB>>8) & 0x1f)*out_div);
 114             return 0;
 115 #else
 116     /* AS3525v2  */
 117     switch(clk) {
 118         /*  we're using a known setting for PLLA = 240 MHz and PLLB inop  */
 119         case CLK_PLLA:
 120             return 240000000;
 121
 122         case CLK_PLLB:
 123             return 0;
 124 #endif
 125         case CLK_PROC:
 126 #if CONFIG_CPU == AS3525 /* not in arm926-ejs */
 127             if (!(read_cp15()>>30))                 /* fastbus */
 128                 return calc_freq(CLK_PCLK);
 129             else                                    /* Synch or Asynch bus*/
 130 #endif /* CONFIG_CPU == AS3525 */
 131                 return calc_freq(CLK_FCLK);
 132         case CLK_FCLK:
 133             switch(CGU_PROC & 3) {
 134                 case 0:
 135                     return (CLK_MAIN * (8 - prediv)) / (8 * (postdiv + 1));
 136                 case 1:
 137                     return (calc_freq(CLK_PLLA) * (8 - prediv)) /
 138                                                             (8 * (postdiv + 1));
 139                 case 2:
 140                     return (calc_freq(CLK_PLLB) * (8 - prediv)) /
 141                                                             (8 * (postdiv + 1));
 142                 default:
 143                     return 0;
 144             }
 145         case CLK_EXTMEM:
 146         /* bits 1:0 of CGU_PERI always read as 0 and we assume source = PLLA */
 147 #if CONFIG_CPU == AS3525
 148             switch(CGU_PERI & 3) {
 149 #else
 150         /* bits 1:0 of CGU_PERI always read as 0 and we assume source = PLLA */
 151             switch(1) {
 152 #endif
 153                 case 0:
 154                     return CLK_MAIN/(((CGU_PERI>>2)& 0xf)+1);
 155                 case 1:
 156                     return calc_freq(CLK_PLLA)/(((CGU_PERI>>2)& 0xf)+1);
 157                 case 2:
 158                     return calc_freq(CLK_PLLB)/(((CGU_PERI>>2)& 0xf)+1);
 159                 case 3:
 160                 default:
 161                     return calc_freq(CLK_FCLK)/(((CGU_PERI>>2)& 0xf)+1);
 162             }
 163         case CLK_PCLK:
 164             return calc_freq(CLK_EXTMEM)/(((CGU_PERI>>6)& 0x1)+1);
 165         case CLK_IDE:
 166             switch(CGU_IDE & 3) {
 167                 case 0:
 168                     return CLK_MAIN/(((CGU_IDE>>2)& 0xf)+1);
 169                 case 1:
 170                     return calc_freq(CLK_PLLA)/(((CGU_IDE>>2)& 0xf)+1);
 171                 case 2:
 172                     return calc_freq(CLK_PLLB)/(((CGU_IDE>>2)& 0xf)+1);
 173                 default:
 174                     return 0;
 175             }
 176         case CLK_I2C:
 177             return calc_freq(CLK_PCLK)/AS3525_I2C_PRESCALER;
 178         case CLK_I2SI:
 179             switch((CGU_AUDIO>>12) & 3) {
 180                 case 0:
 181                     return CLK_MAIN/(((CGU_AUDIO>>14) & 0x1ff)+1);
 182                 case 1:
 183                     return calc_freq(CLK_PLLA)/(((CGU_AUDIO>>14) & 0x1ff)+1);
 184                 case 2:
 185                     return calc_freq(CLK_PLLB)/(((CGU_AUDIO>>14) & 0x1ff)+1);
 186                 default:
 187                     return 0;
 188             }
 189         case CLK_I2SO:
 190             switch(CGU_AUDIO & 3) {
 191                 case 0:
 192                     return CLK_MAIN/(((CGU_AUDIO>>2) & 0x1ff)+1);
 193                 case 1:
 194                     return calc_freq(CLK_PLLA)/(((CGU_AUDIO>>2) & 0x1ff)+1);
 195                 case 2:
 196                     return calc_freq(CLK_PLLB)/(((CGU_AUDIO>>2) & 0x1ff)+1);
 197                 default:
 198                     return 0;
 199             }
 200         case CLK_DBOP:
 201             return calc_freq(CLK_PCLK)/((CGU_DBOP & 7)+1);
 202 #if CONFIG_CPU == AS3525
 203         case CLK_SD_MCLK_NAND:
 204             if(!(MCI_NAND & (1<<8)))
 205                 return 0;
 206             else if(MCI_NAND & (1<<10))
 207                 return calc_freq(CLK_IDE);
 208             else
 209                 return calc_freq(CLK_IDE)/(((MCI_NAND & 0xff)+1)*2);
 210         case CLK_SD_MCLK_MSD:
 211             if(!(MCI_SD & (1<<8)))
 212                 return 0;
 213             else if(MCI_SD & (1<<10))
 214                 return calc_freq(CLK_PCLK);
 215             else
 216             return calc_freq(CLK_PCLK)/(((MCI_SD & 0xff)+1)*2);
 217 #endif
 218         case CLK_USB:
 219             switch(CGU_USB & 3) {     /* 0-> div=1  other->div=1/(2*n)  */
 220                 case 0:
 221                     if (!((CGU_USB>>2) & 0x7))
 222                         return CLK_MAIN;
 223                     else
 224                         return CLK_MAIN/(2*((CGU_USB>>2) & 0x7));
 225                 case 1:
 226                     if (!((CGU_USB>>2) & 0x7))
 227                         return calc_freq(CLK_PLLA);
 228                     else
 229                         return calc_freq(CLK_PLLA)/(2*((CGU_USB>>2) & 0x7));
 230                 case 2:
 231                     if (!((CGU_USB>>2) & 0x7))
 232                         return calc_freq(CLK_PLLB);
 233                     else
 234                         return calc_freq(CLK_PLLB)/(2*((CGU_USB>>2) & 0x7));
 235                 default:
 236                     return 0;
 237             }
 238         default:
 239             return 0;
 240         }
 241 }
 242
 243 bool __dbg_hw_info(void)
 244 {
 245     int line;
 246 #if CONFIG_CPU == AS3525
 247     int last_nand = 0;
 248 #ifdef HAVE_MULTIDRIVE
 249     int last_sd = 0;
 250 #endif
 251 #endif /* CONFIG_CPU == AS3525 */
 252
 253     lcd_clear_display();
 254     lcd_setfont(FONT_SYSFIXED);
 255
 256     while(1)
 257     {
 258         while(1)
 259         {
 260         lcd_clear_display();
 261         line = 0;
 262         lcd_puts(0, line++, "[Clock Frequencies:]");
 263         lcd_puts(0, line++, "     SET       ACTUAL");
 264 #if CONFIG_CPU == AS3525
 265         lcd_putsf(0, line++, "922T:%s     %3dMHz",
 266                                         (!(read_cp15()>>30)) ? "FAST " :
 267                                         (read_cp15()>>31) ? "ASYNC" : "SYNC ",
 268 #else
 269         lcd_putsf(0, line++, "926ejs:        %3dMHz",
 270 #endif
 271                                          calc_freq(CLK_PROC)/1000000);
 272         lcd_putsf(0, line++, "PLLA:%3dMHz    %3dMHz", AS3525_PLLA_FREQ/1000000,
 273                                                    calc_freq(CLK_PLLA)/1000000);
 274         lcd_putsf(0, line++, "PLLB:          %3dMHz", calc_freq(CLK_PLLB)/1000000);
 275         lcd_putsf(0, line++, "FCLK:          %3dMHz", calc_freq(CLK_FCLK)/1000000);
 276         lcd_putsf(0, line++, "DRAM:%3dMHz    %3dMHz", AS3525_PCLK_FREQ/1000000,
 277                                                  calc_freq(CLK_EXTMEM)/1000000);
 278         lcd_putsf(0, line++, "PCLK:%3dMHz    %3dMHz", AS3525_PCLK_FREQ/1000000,
 279                                                    calc_freq(CLK_PCLK)/1000000);
 280
 281 #if LCD_HEIGHT < 176  /* clip  */
 282         lcd_update();
 283         int btn = button_get_w_tmo(HZ/10);
 284         if(btn == (DEBUG_CANCEL|BUTTON_REL))
 285             goto end;
 286         else if(btn == (BUTTON_DOWN|BUTTON_REL))
 287             break;
 288         }
 289         while(1)
 290         {
 291         lcd_clear_display();
 292         line = 0;
 293 #endif  /*  LCD_HEIGHT < 176 */
 294
 295         lcd_putsf(0, line++, "IDE :%3dMHz    %3dMHz", AS3525_IDE_FREQ/1000000,
 296                                                     calc_freq(CLK_IDE)/1000000);
 297         lcd_putsf(0, line++, "DBOP:%3dMHz    %3dMHz", AS3525_DBOP_FREQ/1000000,
 298                                                    calc_freq(CLK_DBOP)/1000000);
 299         lcd_putsf(0, line++, "I2C :%3dkHz    %3dkHz", AS3525_I2C_FREQ/1000,
 300                                                        calc_freq(CLK_I2C)/1000);
 301         lcd_putsf(0, line++, "I2SI: %s      %3dMHz", (CGU_AUDIO & (1<<23)) ?
 302                                    "on " : "off" , calc_freq(CLK_I2SI)/1000000);
 303         lcd_putsf(0, line++, "I2SO: %s      %3dMHz", (CGU_AUDIO & (1<<11)) ?
 304                                     "on " : "off", calc_freq(CLK_I2SO)/1000000);
 305 #if CONFIG_CPU == AS3525
 306         /* If disabled, enable SD cards so we can read the registers */
 307         if(sd_enabled == false)
 308         {
 309             sd_enable(true);
 310             last_nand = MCI_NAND;
 311 #ifdef HAVE_MULTIDRIVE
 312             last_sd = MCI_SD;
 313 #endif
 314             sd_enable(false);
 315         }
 316
 317         lcd_putsf(0, line++, "SD  :%3dMHz    %3dMHz",
 318             ((AS3525_IDE_FREQ/ 1000000) /
 319             ((last_nand & MCI_CLOCK_BYPASS)? 1:(((last_nand & 0xff)+1) * 2))),
 320             calc_freq(CLK_SD_MCLK_NAND)/1000000);
 321 #ifdef HAVE_MULTIDRIVE
 322         lcd_putsf(0, line++, "uSD :%3dMHz    %3dMHz",
 323             ((AS3525_PCLK_FREQ/ 1000000) /
 324             ((last_sd & MCI_CLOCK_BYPASS) ? 1: (((last_sd & 0xff) + 1) * 2))),
 325             calc_freq(CLK_SD_MCLK_MSD)/1000000);
 326 #endif
 327 #endif  /* CONFIG_CPU == AS3525 */
 328         lcd_putsf(0, line++, "USB :          %3dMHz", calc_freq(CLK_USB)/1000000);
 329
 330 #if LCD_HEIGHT < 176  /* clip  */
 331         lcd_update();
 332         int btn = button_get_w_tmo(HZ/10);
 333         if(btn == (DEBUG_CANCEL|BUTTON_REL))
 334             goto end;
 335         else if(btn == (BUTTON_DOWN|BUTTON_REL))
 336             break;
 337         }
 338         while(1)
 339         {
 340         lcd_clear_display();
 341         line = 0;
 342 #endif  /*  LCD_HEIGHT < 176 */
 343
 344         lcd_putsf(0, line++, "MMU :  %s CVDDP:%4d", (read_cp15() & CP15_MMU) ?
 345                                         " on" : "off", adc_read(ADC_CVDD) * 25);
 346         lcd_putsf(0, line++, "Icache:%s Dcache:%s",
 347                                       (read_cp15() & CP15_IC)  ? " on" : "off",
 348                                       (read_cp15() & CP15_DC)  ? " on" : "off");
 349
 350         lcd_update();
 351         int btn = button_get_w_tmo(HZ/10);
 352         if(btn == (DEBUG_CANCEL|BUTTON_REL))
 353             goto end;
 354         else if(btn == (BUTTON_DOWN|BUTTON_REL))
 355             break;
 356         }
 357         while(1)
 358         {
 359         lcd_clear_display();
 360         line = 0;
 361
 362         lcd_putsf(0, line++, "CGU_PLLA  :%8x", (unsigned int)(CGU_PLLA));
 363         lcd_putsf(0, line++, "CGU_PLLB  :%8x", (unsigned int)(CGU_PLLB));
 364         lcd_putsf(0, line++, "CGU_PROC  :%8x", (unsigned int)(CGU_PROC));
 365         lcd_putsf(0, line++, "CGU_PERI  :%8x", (unsigned int)(CGU_PERI));
 366         lcd_putsf(0, line++, "CGU_IDE   :%8x", (unsigned int)(CGU_IDE));
 367         lcd_putsf(0, line++, "CGU_DBOP  :%8x", (unsigned int)(CGU_DBOP));
 368         lcd_putsf(0, line++, "CGU_AUDIO :%8x", (unsigned int)(CGU_AUDIO));
 369         lcd_putsf(0, line++, "CGU_USB   :%8x", (unsigned int)(CGU_USB));
 370
 371 #if LCD_HEIGHT < 176  /* clip  */
 372         lcd_update();
 373         int btn = button_get_w_tmo(HZ/10);
 374         if(btn == (DEBUG_CANCEL|BUTTON_REL))
 375             goto end;
 376         else if(btn == (BUTTON_DOWN|BUTTON_REL))
 377             break;
 378         }
 379         while(1)
 380         {
 381         lcd_clear_display();
 382         line = 0;
 383 #endif  /*  LCD_HEIGHT < 176 */
 384
 385         lcd_putsf(0, line++, "I2C2_CPSR :%8x", (unsigned int)(I2C2_CPSR1<<8 |
 386                                                        I2C2_CPSR0));
 387 #if CONFIG_CPU == AS3525
 388         lcd_putsf(0, line++, "MCI_NAND  :%8x", (unsigned int)(MCI_NAND));
 389         lcd_putsf(0, line++, "MCI_SD    :%8x", (unsigned int)(MCI_SD));
 390 #else
 391         lcd_putsf(0, line++, "CGU_MEMSTK:%8x", (unsigned int)(CGU_MEMSTICK));
 392         lcd_putsf(0, line++, "CGU_SDSLOT:%8x", (unsigned int)(CGU_SDSLOT));
 393 #endif
 394
 395         lcd_update();
 396         int btn = button_get_w_tmo(HZ/10);
 397         if(btn == (DEBUG_CANCEL|BUTTON_REL))
 398             goto end;
 399         else if(btn == (BUTTON_DOWN|BUTTON_REL))
 400             break;
 401         }
 402     }
 403
 404 end:
 405     lcd_setfont(FONT_UI);
 406     return false;
 407 }
 408
 409 bool __dbg_ports(void)
 410 {
 411     int line;
 412
 413     lcd_clear_display();
 414     lcd_setfont(FONT_SYSFIXED);
 415
 416     while(1)
 417     {
 418         line = 0;
 419         lcd_puts(0, line++, "[GPIO Values and Directions]");
 420         lcd_putsf(0, line++, "GPIOA: %2x DIR: %2x", GPIOA_DATA, GPIOA_DIR);
 421         lcd_putsf(0, line++, "GPIOB: %2x DIR: %2x", GPIOB_DATA, GPIOB_DIR);
 422         lcd_putsf(0, line++, "GPIOC: %2x DIR: %2x", GPIOC_DATA, GPIOC_DIR);
 423         lcd_putsf(0, line++, "GPIOD: %2x DIR: %2x", GPIOD_DATA, GPIOD_DIR);
 424 #ifdef DEBUG_DBOP
 425         line++;
 426         lcd_puts(0, line++, "[DBOP_DIN]");
 427         lcd_putsf(0, line++, "DBOP_DIN: %4x", dbop_debug());
 428 #endif
 429         line++;
 430         lcd_puts(0, line++, "[CP15]");
 431         lcd_putsf(0, line++, "CP15: 0x%8x", read_cp15());
 432         lcd_update();
 433         if (button_get_w_tmo(HZ/10) == (DEBUG_CANCEL|BUTTON_REL))
 434             break;
 435     }
 436     lcd_setfont(FONT_UI);
 437     return false;
 438 }