firmware/target/mips/ingenic_jz47xx/system-target.h

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2008 by Maurus Cuelenaere
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21
  22 #ifndef __SYSTEM_TARGET_H_
  23 #define __SYSTEM_TARGET_H_
  24
  25 #include "config.h"
  26 #include "jz4740.h"
  27 #include "mipsregs.h"
  28
  29 #define CACHE_SIZE       16*1024
  30 #define CACHE_LINE_SIZE  32
  31 #include "mmu-mips.h"
  32
  33 /* This one returns the old status */
  34 static inline int set_interrupt_status(int status, int mask)
  35 {
  36         unsigned int res, oldstatus;
  37
  38         res = oldstatus = read_c0_status();
  39         res &= ~mask;
  40         res |= (status & mask);
  41         write_c0_status(res);
  42
  43         return oldstatus;
  44 }
  45
  46 static inline void enable_interrupt(void)
  47 {
  48     /* Set IE bit */
  49     set_c0_status(ST0_IE);
  50 }
  51
  52 static inline void disable_interrupt(void)
  53 {
  54     /* Clear IE bit */
  55     clear_c0_status(ST0_IE);
  56 }
  57
  58 static inline int disable_interrupt_save(int mask)
  59 {
  60     return set_interrupt_status(0, mask);
  61 }
  62
  63 static inline void restore_interrupt(int status)
  64 {
  65     write_c0_status(status);
  66 }
  67
  68 #define disable_irq() disable_interrupt()
  69 #define enable_irq()  enable_interrupt()
  70 #define HIGHEST_IRQ_LEVEL 0
  71 #define set_irq_level(status)  set_interrupt_status((status), ST0_IE)
  72 #define disable_irq_save()     disable_interrupt_save(ST0_IE)
  73 #define restore_irq(c0_status) restore_interrupt(c0_status)
  74
  75 #define swap16(x) (((x) & 0xff) << 8 | ((x) >> 8) & 0xff)
  76 #define swap32(x) (((x) & 0xff) << 24 | ((x) & 0xff00) << 8 | \
  77                    ((x) & 0xff0000) >> 8 | ((x) >> 24) & 0xff)
  78
  79 #define UNCACHED_ADDRESS(addr)    ((unsigned int)(addr) | 0xA0000000)
  80 #define UNCACHED_ADDR(x)          UNCACHED_ADDRESS((x))
  81 #define PHYSADDR(x)               ((x) & 0x1fffffff)
  82
  83 void system_enable_irq(unsigned int irq);
  84 void udelay(unsigned int usec);
  85 void mdelay(unsigned int msec);
  86 void power_off(void);
  87 void system_reboot(void);
  88 void dma_enable(void);
  89 void dma_disable(void);
  90
  91 #define DMA_LCD_CHANNEL    0
  92 #define DMA_NAND_CHANNEL   1
  93 #define DMA_USB_CHANNEL    2
  94 #define DMA_AIC_TX_CHANNEL 3
  95
  96 #define XDMA_CALLBACK(n) DMA ## n
  97 #define DMA_CALLBACK(n)  XDMA_CALLBACK(n)
  98
  99 #define DMA_IRQ(n)      (IRQ_DMA_0 + n)
 100
 101 #endif /* __SYSTEM_TARGET_H_ */