firmware/target/arm/as3525/sd-as3525v2.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2006 Daniel Ankers
  11  * Copyright © 2008-2009 Rafaël Carré
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License
  15  * as published by the Free Software Foundation; either version 2
  16  * of the License, or (at your option) any later version.
  17  *
  18  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  19  * KIND, either express or implied.
  20  *
  21  ****************************************************************************/
  22
  23 #include "config.h" /* for HAVE_MULTIVOLUME */
  24 #include "fat.h"
  25 #include "thread.h"
  26 #include "hotswap.h"
  27 #include "system.h"
  28 #include "kernel.h"
  29 #include "cpu.h"
  30 #include <stdio.h>
  31 #include <stdlib.h>
  32 #include <string.h>
  33 #include "as3525v2.h"
  34 #include "pl081.h"  /* DMA controller */
  35 #include "dma-target.h" /* DMA request lines */
  36 #include "clock-target.h"
  37 #include "panic.h"
  38 #include "stdbool.h"
  39 #include "ata_idle_notify.h"
  40 #include "sd.h"
  41
  42 #ifdef HAVE_HOTSWAP
  43 #include "disk.h"
  44 #endif
  45
  46 #include "lcd.h"
  47 #include <stdarg.h>
  48 #include "sysfont.h"
  49
  50 #define     INTERNAL_AS3525  0   /* embedded SD card */
  51 #define     SD_SLOT_AS3525   1   /* SD slot if present */
  52
  53 /* command flags */
  54 #define MCI_NO_RESP     (0<<0)
  55 #define MCI_RESP        (1<<0)
  56 #define MCI_LONG_RESP   (1<<1)
  57
  58 /* controller registers */
  59 #define SD_BASE 0xC6070000
  60
  61 #define SD_REG(x)       (*(volatile unsigned long *) (SD_BASE+x))
  62
  63 #define MCI_CTRL        SD_REG(0x00)
  64
  65 /* control bits */
  66 #define CTRL_RESET      (1<<0)
  67 #define FIFO_RESET      (1<<1)
  68 #define DMA_RESET       (1<<2)
  69 #define INT_ENABLE      (1<<4)
  70 #define DMA_ENABLE      (1<<5)
  71 #define READ_WAIT       (1<<6)
  72 #define SEND_IRQ_RESP   (1<<7)
  73 #define ABRT_READ_DATA  (1<<8)
  74 #define SEND_CCSD       (1<<9)
  75 #define SEND_AS_CCSD    (1<<10)
  76 #define EN_OD_PULLUP    (1<<24)
  77
  78
  79 #define MCI_PWREN       SD_REG(0x04)    /* power enable */
  80
  81 #define PWR_CRD_0       (1<<0)
  82 #define PWR_CRD_1       (1<<1)
  83 #define PWR_CRD_2       (1<<2)
  84 #define PWR_CRD_3       (1<<3)
  85
  86 #define MCI_CLKDIV      SD_REG(0x08)    /* clock divider */
  87 /* CLK_DIV_0 :    bits 7:0
  88  * CLK_DIV_1 :    bits 15:8
  89  * CLK_DIV_2 :    bits 23:16
  90  * CLK_DIV_3 :    bits 31:24
  91  */
  92
  93 #define MCI_CLKSRC      SD_REG(0x0C)    /* clock source */
  94 /* CLK_SRC_CRD0:  bits 1:0
  95  * CLK_SRC_CRD1:  bits 3:2
  96  * CLK_SRC_CRD2:  bits 5:4
  97  * CLK_SRC_CRD3:  bits 7:6
  98  */
  99
 100 #define MCI_CLKENA      SD_REG(0x10)    /* clock enable */
 101
 102 #define CCLK_ENA_CRD0   (1<<0)
 103 #define CCLK_ENA_CRD1   (1<<1)
 104 #define CCLK_ENA_CRD2   (1<<2)
 105 #define CCLK_ENA_CRD3   (1<<3)
 106 #define CCLK_LP_CRD0    (1<<16)         /* LP --> Low Power Mode? */
 107 #define CCLK_LP_CRD1    (1<<17)
 108 #define CCLK_LP_CRD2    (1<<18)
 109 #define CCLK_LP_CRD3    (1<<19)
 110
 111 #define MCI_TMOUT       SD_REG(0x14)    /* timeout */
 112 /* response timeout bits 0:7
 113  * data timeout bits     8:31
 114  */
 115
 116 #define MCI_CTYPE       SD_REG(0x18)    /* card type */
 117                                         /* 1 bit per card, set = wide bus */
 118 #define WIDTH4_CRD0     (1<<0)
 119 #define WIDTH4_CRD1     (1<<1)
 120 #define WIDTH4_CRD2     (1<<2)
 121 #define WIDTH4_CRD3     (1<<3)
 122
 123 #define MCI_BLKSIZ      SD_REG(0x1C)    /* block size  bits 0:15*/
 124 #define MCI_BYTCNT      SD_REG(0x20)    /* byte count  bits 0:31*/
 125 #define MCI_MASK        SD_REG(0x24)    /* interrupt mask */
 126
 127
 128
 129 #define MCI_ARGUMENT    SD_REG(0x28)
 130 #define MCI_COMMAND     SD_REG(0x2C)
 131
 132 /* command bits (bits 5:0 are the command index) */
 133 #define CMD_RESP_EXP_BIT        (1<<6)
 134 #define CMD_RESP_LENGTH_BIT     (1<<7)
 135 #define CMD_CHECK_CRC_BIT       (1<<8)
 136 #define CMD_DATA_EXP_BIT        (1<<9)
 137 #define CMD_RW_BIT              (1<<10)
 138 #define CMD_TRANSMODE_BIT       (1<<11)
 139 #define CMD_SENT_AUTO_STOP_BIT  (1<<12)
 140 #define CMD_WAIT_PRV_DAT_BIT    (1<<13)
 141 #define CMD_ABRT_CMD_BIT        (1<<14)
 142 #define CMD_SEND_INIT_BIT       (1<<15)
 143 #define CMD_CARD_NO(x)          ((x)<<16)         /* 5 bits wide  */
 144 #define CMD_SEND_CLK_ONLY       (1<<21)
 145 #define CMD_READ_CEATA          (1<<22)
 146 #define CMD_CCS_EXPECTED        (1<<23)
 147 #define CMD_DONE_BIT            (1<<31)
 148
 149
 150 #define MCI_RESP0       SD_REG(0x30)
 151 #define MCI_RESP1       SD_REG(0x34)
 152 #define MCI_RESP2       SD_REG(0x38)
 153 #define MCI_RESP3       SD_REG(0x3C)
 154
 155 #define MCI_MASK_STATUS SD_REG(0x40)    /* masked interrupt status */
 156 #define MCI_RAW_STATUS  SD_REG(0x44)    /* raw interrupt status, also used as
 157                                          * status clear */
 158
 159 /* interrupt bits */
 160 #define MCI_INT_CRDDET  (1<<0)      /* card detect */
 161 #define MCI_INT_RE      (1<<1)      /* response error */
 162 #define MCI_INT_CD      (1<<2)      /* command done */
 163 #define MCI_INT_DTO     (1<<3)      /* data transfer over */
 164 #define MCI_INT_TXDR    (1<<4)      /* tx fifo data request */
 165 #define MCI_INT_RXDR    (1<<5)      /* rx fifo data request */
 166 #define MCI_INT_RCRC    (1<<6)      /* response crc error */
 167 #define MCI_INT_DCRC    (1<<7)      /* data crc error */
 168 #define MCI_INT_RTO     (1<<8)      /* response timeout */
 169 #define MCI_INT_DRTO    (1<<9)      /* data read timeout */
 170 #define MCI_INT_HTO     (1<<10)     /* data starv timeout */
 171 #define MCI_INT_FRUN    (1<<11)     /* fifo over/underrun */
 172 #define MCI_INT_HLE     (1<<12)     /* hw locked while error */
 173 #define MCI_INT_SBE     (1<<13)     /* start bit error */
 174 #define MCI_INT_ACD     (1<<14)     /* auto command done */
 175 #define MCI_INT_EBE     (1<<15)     /* end bit error */
 176 #define MCI_INT_SDIO    (0xf<<16)
 177
 178 /*
 179  *  STATUS register
 180  *  & 0xBA80    = MCI_INT_DCRC | MCI_INT_DRTO | MCI_INT_FRUN | \
 181  *                  MCI_INT_HLE | MCI_INT_SBE | MCI_INT_EBE
 182  *  & 8         = MCI_INT_DTO
 183  *  & 0x428     = MCI_INT_DTO | MCI_INT_RXDR | MCI_INT_HTO
 184  *  & 0x418     = MCI_INT_DTO | MCI_INT_TXDR | MCI_INT_HTO
 185  */
 186
 187 #define MCI_ERROR   (MCI_INT_RE | MCI_INT_RCRC | MCI_INT_DCRC /*| MCI_INT_RTO*/ \
 188                    | MCI_INT_DRTO | MCI_INT_HTO | MCI_INT_FRUN | MCI_INT_HLE \
 189                    | MCI_INT_SBE | MCI_INT_EBE)
 190
 191 #define MCI_STATUS      SD_REG(0x48)
 192
 193 #define FIFO_RX_WM              (1<<0)
 194 #define FIFO_TX_WM              (1<<1)
 195 #define FIFO_EMPTY              (1<<2)
 196 #define FIFO_FULL               (1<<3)
 197 #define CMD_FSM_STATE_B0        (1<<4)
 198 #define CMD_FSM_STATE_B1        (1<<5)
 199 #define CMD_FSM_STATE_B2        (1<<6)
 200 #define CMD_FSM_STATE_B3        (1<<7)
 201 #define DATA_3_STAT             (1<<8)
 202 #define DATA_BUSY               (1<<9)
 203 #define DATA_STAT_MC_BUSY       (1<<10)
 204 #define RESP_IDX_B0             (1<<11)
 205 #define RESP_IDX_B1             (1<<12)
 206 #define RESP_IDX_B2             (1<<13)
 207 #define RESP_IDX_B3             (1<<14)
 208 #define RESP_IDX_B4             (1<<15)
 209 #define RESP_IDX_B5             (1<<16)
 210 #define FIFO_CNT_B00            (1<<17)
 211 #define FIFO_CNT_B01            (1<<18)
 212 #define FIFO_CNT_B02            (1<<19)
 213 #define FIFO_CNT_B03            (1<<20)
 214 #define FIFO_CNT_B04            (1<<21)
 215 #define FIFO_CNT_B05            (1<<22)
 216 #define FIFO_CNT_B06            (1<<23)
 217 #define FIFO_CNT_B07            (1<<24)
 218 #define FIFO_CNT_B08            (1<<25)
 219 #define FIFO_CNT_B09            (1<<26)
 220 #define FIFO_CNT_B10            (1<<27)
 221 #define FIFO_CNT_B11            (1<<28)
 222 #define FIFO_CNT_B12            (1<<29)
 223 #define DMA_ACK                 (1<<30)
 224 #define START_CMD               (1<<31)
 225
 226 #define MCI_FIFOTH      SD_REG(0x4C)    /* FIFO threshold */
 227 /* TX watermark :    bits 11:0
 228  * RX watermark :    bits 27:16
 229  * DMA MTRANS SIZE : bits 30:28
 230  * bits 31, 15:12 : unused
 231  */
 232 #define MCI_FIFOTH_MASK 0x8000f000
 233
 234 #define MCI_CDETECT     SD_REG(0x50)    /* card detect */
 235
 236 #define CDETECT_CRD_0   (1<<0)
 237 #define CDETECT_CRD_1   (1<<1)
 238 #define CDETECT_CRD_2   (1<<2)
 239 #define CDETECT_CRD_3   (1<<3)
 240
 241 #define MCI_WRTPRT      SD_REG(0x54)    /* write protect */
 242 #define MCI_GPIO        SD_REG(0x58)
 243 #define MCI_TCBCNT      SD_REG(0x5C)    /* transferred CIU byte count (card)*/
 244 #define MCI_TBBCNT      SD_REG(0x60)    /* transferred host/DMA to/from bytes (FIFO)*/
 245 #define MCI_DEBNCE      SD_REG(0x64)    /* card detect debounce  bits 23:0*/
 246 #define MCI_USRID       SD_REG(0x68)    /* user id */
 247 #define MCI_VERID       SD_REG(0x6C)    /* version id */
 248
 249 #define MCI_HCON        SD_REG(0x70)    /* hardware config */
 250 /* bit  0       : card type
 251  * bits 5:1     : maximum card index
 252  * bit  6       : BUS TYPE
 253  * bits 9:7     : DATA WIDTH
 254  * bits 15:10   : ADDR WIDTH
 255  * bits 17:16   : DMA IF
 256  * bits 20:18   : DMA WIDTH
 257  * bit  21      : FIFO RAM INSIDE
 258  * bit  22      : IMPL HOLD REG
 259  * bit  23      : SET CLK FALSE
 260  * bits 25:24   : MAX CLK DIV IDX
 261  * bit  26      : AREA OPTIM
 262  */
 263
 264 #define MCI_BMOD        SD_REG(0x80)    /* bus mode */
 265 /* bit  0       : SWR
 266  * bit  1       : FB
 267  * bits 6:2     : DSL
 268  * bit  7       : DE
 269  * bit  10:8    : PBL
 270  */
 271
 272 #define MCI_PLDMND      SD_REG(0x84)    /* poll demand */
 273 #define MCI_DBADDR      SD_REG(0x88)    /* descriptor base address */
 274 #define MCI_IDSTS       SD_REG(0x8C)    /* internal DMAC status */
 275 /* bit  0       : TI
 276  * bit  1       : RI
 277  * bit  2       : FBE
 278  * bit  3       : unused
 279  * bit  4       : DU
 280  * bit  5       : CES
 281  * bits 7:6     : unused
 282  * bits 8       : NIS
 283  * bit  9       : AIS
 284  * bits 12:10   : EB
 285  * bits 16:13   : FSM
 286  */
 287
 288 #define MCI_IDINTEN     SD_REG(0x90)    /* internal DMAC interrupt enable */
 289 /* bit  0       : TI
 290  * bit  1       : RI
 291  * bit  2       : FBE
 292  * bit  3       : unused
 293  * bit  4       : DU
 294  * bit  5       : CES
 295  * bits 7:6     : unused
 296  * bits 8       : NI
 297  * bit  9       : AI
 298  */
 299 #define MCI_DSCADDR     SD_REG(0x94)    /* current host descriptor address */
 300 #define MCI_BUFADDR     SD_REG(0x98)    /* current host buffer address */
 301
 302 #define MCI_FIFO        ((unsigned long *) (SD_BASE+0x100))
 303
 304 #define UNALIGNED_NUM_SECTORS 10
 305 static unsigned char aligned_buffer[UNALIGNED_NUM_SECTORS* SD_BLOCK_SIZE] __attribute__((aligned(32)));   /* align on cache line size */
 306 static unsigned char *uncached_buffer = UNCACHED_ADDR(&aligned_buffer[0]);
 307
 308 static void init_controller(void);
 309
 310 static tCardInfo card_info[NUM_DRIVES];
 311
 312 /* for compatibility */
 313 static long last_disk_activity = -1;
 314
 315 #define MIN_YIELD_PERIOD 5  /* ticks */
 316 static long next_yield = 0;
 317
 318 static long sd_stack [(DEFAULT_STACK_SIZE*2 + 0x200)/sizeof(long)];
 319 static const char         sd_thread_name[] = "ata/sd";
 320 static struct mutex       sd_mtx SHAREDBSS_ATTR;
 321 static struct event_queue sd_queue;
 322 #ifndef BOOTLOADER
 323 bool sd_enabled = false;
 324 #endif
 325
 326 static struct wakeup transfer_completion_signal;
 327 static volatile bool retry;
 328 static volatile bool data_transfer = false;
 329
 330 #if defined(HAVE_MULTIDRIVE)
 331 int active_card = 0;
 332 #endif
 333
 334 static inline void mci_delay(void) { int i = 0xffff; while(i--) ; }
 335
 336 void INT_NAND(void)
 337 {
 338     MCI_CTRL &= ~INT_ENABLE;
 339     const int status = MCI_MASK_STATUS;
 340
 341     MCI_RAW_STATUS = status;    /* clear status */
 342
 343     if(status & MCI_ERROR)
 344         retry = true;
 345
 346     if(data_transfer && status & (MCI_INT_DTO|MCI_ERROR))
 347         wakeup_signal(&transfer_completion_signal);
 348
 349     MCI_CTRL |= INT_ENABLE;
 350 }
 351
 352 static inline bool card_detect_target(void)
 353 {
 354 #if defined(HAVE_MULTIDRIVE)
 355     return !(GPIOA_PIN(2));
 356 #else
 357     return false;
 358 #endif
 359 }
 360
 361 static bool send_cmd(const int drive, const int cmd, const int arg, const int flags,
 362         unsigned long *response)
 363 {
 364 #if defined(HAVE_MULTIDRIVE)
 365     /*  Check to see if we need to switch cards  */
 366     if(sd_present(SD_SLOT_AS3525))
 367          if(active_card != drive)
 368         {
 369             GPIOB_PIN(5) = (1-drive) << 5;
 370             active_card = drive;
 371         }
 372
 373     MCI_COMMAND = cmd | CMD_CARD_NO(drive);
 374 #else
 375     (void) drive;
 376     MCI_COMMAND = cmd;
 377 #endif
 378
 379     if(flags & MCI_RESP)
 380     {
 381         MCI_COMMAND |= CMD_RESP_EXP_BIT;
 382         if(flags & MCI_LONG_RESP)
 383             MCI_COMMAND |= CMD_RESP_LENGTH_BIT;
 384     }
 385
 386     if(cmd == SD_READ_MULTIPLE_BLOCK || cmd == SD_WRITE_MULTIPLE_BLOCK)
 387     {
 388         MCI_COMMAND |= CMD_WAIT_PRV_DAT_BIT | CMD_DATA_EXP_BIT;
 389         if(cmd == SD_WRITE_MULTIPLE_BLOCK)
 390             MCI_COMMAND |= CMD_RW_BIT | CMD_CHECK_CRC_BIT;
 391     }
 392
 393     MCI_CLKENA &= (1 << drive);
 394
 395     MCI_ARGUMENT = arg;
 396     MCI_COMMAND |= CMD_DONE_BIT;
 397
 398     int max = 0x40000;
 399     while(MCI_COMMAND & CMD_DONE_BIT)
 400     {
 401         if(--max == 0)  /* timeout */
 402         {
 403             MCI_CLKENA |= (1 << drive);
 404             return false;
 405         }
 406     }
 407
 408     MCI_CLKENA |= (1 << drive);
 409
 410     if(flags & MCI_RESP)
 411     {
 412         int i = 0xff; while(i--) ;
 413         /* if we read the response too fast we might read the response
 414          * of the previous command instead */
 415
 416         if(flags & MCI_LONG_RESP)
 417         {
 418             response[3] = MCI_RESP3;
 419             response[2] = MCI_RESP2;
 420             response[1] = MCI_RESP1;
 421         }
 422         response[0] = MCI_RESP0;
 423     }
 424     return true;
 425 }
 426
 427 static int sd_init_card(const int drive)
 428 {
 429     unsigned long response;
 430     long init_timeout;
 431     bool sd_v2 = false;
 432
 433     /*  assume 24 MHz clock / 60 = 400 kHz  */
 434     MCI_CLKDIV = (MCI_CLKDIV & ~(0xFF)) | 0x3C;    /* CLK_DIV_0 : bits 7:0  */
 435
 436     /* 100 - 400kHz clock required for Identification Mode  */
 437     /*  Start of Card Identification Mode ************************************/
 438
 439     /* CMD0 Go Idle  */
 440     if(!send_cmd(drive, SD_GO_IDLE_STATE, 0, MCI_NO_RESP, NULL))
 441         return -1;
 442     mci_delay();
 443
 444     /* CMD8 Check for v2 sd card.  Must be sent before using ACMD41
 445       Non v2 cards will not respond to this command*/
 446     if(send_cmd(drive, SD_SEND_IF_COND, 0x1AA, MCI_RESP, &response))
 447         if((response & 0xFFF) == 0x1AA)
 448             sd_v2 = true;
 449
 450     /* timeout for initialization is 1sec, from SD Specification 2.00 */
 451     init_timeout = current_tick + HZ;
 452
 453     do {
 454         /* this timeout is the only valid error for this loop*/
 455         if(TIME_AFTER(current_tick, init_timeout))
 456             return -2;
 457
 458         /* app_cmd */
 459         send_cmd(drive, SD_APP_CMD, 0, MCI_RESP, &response);
 460
 461          /* ACMD41 For v2 cards set HCS bit[30] & send host voltage range to all */
 462         if(!send_cmd(drive, SD_APP_OP_COND, (0x00FF8000 | (sd_v2 ? 1<<30 : 0)),
 463                         MCI_RESP, &card_info[drive].ocr))
 464             return -3;
 465     } while(!(card_info[drive].ocr & (1<<31)) );
 466
 467     /* CMD2 send CID */
 468     if(!send_cmd(drive, SD_ALL_SEND_CID, 0, MCI_RESP|MCI_LONG_RESP, card_info[drive].cid))
 469         return -4;
 470
 471     /* CMD3 send RCA */
 472     if(!send_cmd(drive, SD_SEND_RELATIVE_ADDR, 0, MCI_RESP, &card_info[drive].rca))
 473         return -5;
 474
 475 #ifdef HAVE_MULTIDRIVE
 476     /* Make sure we have 2 unique rca numbers */
 477     if(card_info[INTERNAL_AS3525].rca == card_info[SD_SLOT_AS3525].rca)
 478         if(!send_cmd(drive, SD_SEND_RELATIVE_ADDR, 0, MCI_RESP, &card_info[drive].rca))
 479             return -6;
 480 #endif
 481     /*  End of Card Identification Mode   ************************************/
 482
 483     /* CMD9 send CSD */
 484     if(!send_cmd(drive, SD_SEND_CSD, card_info[drive].rca,
 485                  MCI_RESP|MCI_LONG_RESP, card_info[drive].csd))
 486         return -7;
 487
 488     sd_parse_csd(&card_info[drive]);
 489
 490     /*  Card back to full speed  */
 491     MCI_CLKDIV &= ~(0xFF);    /* CLK_DIV_0 : bits 7:0 = 0x00 */
 492
 493 #ifndef HAVE_MULTIDRIVE
 494     /*  CMD7 w/rca: Select card to put it in TRAN state */
 495     if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_NO_RESP, NULL))
 496         return -8;
 497 #endif
 498
 499     card_info[drive].initialized = 1;
 500
 501     return 0;
 502 }
 503
 504 static void sd_thread(void) __attribute__((noreturn));
 505 static void sd_thread(void)
 506 {
 507     struct queue_event ev;
 508     bool idle_notified = false;
 509
 510     while (1)
 511     {
 512         queue_wait_w_tmo(&sd_queue, &ev, HZ);
 513
 514         switch ( ev.id )
 515         {
 516 #ifdef HAVE_HOTSWAP
 517         case SYS_HOTSWAP_INSERTED:
 518         case SYS_HOTSWAP_EXTRACTED:
 519         {
 520             int microsd_init = 1;
 521             fat_lock();          /* lock-out FAT activity first -
 522                                     prevent deadlocking via disk_mount that
 523                                     would cause a reverse-order attempt with
 524                                     another thread */
 525             mutex_lock(&sd_mtx); /* lock-out card activity - direct calls
 526                                     into driver that bypass the fat cache */
 527
 528             /* We now have exclusive control of fat cache and ata */
 529
 530             disk_unmount(SD_SLOT_AS3525);     /* release "by force", ensure file
 531                                     descriptors aren't leaked and any busy
 532                                     ones are invalid if mounting */
 533             /* Force card init for new card, re-init for re-inserted one or
 534              * clear if the last attempt to init failed with an error. */
 535             card_info[SD_SLOT_AS3525].initialized = 0;
 536
 537             if (ev.id == SYS_HOTSWAP_INSERTED)
 538             {
 539                 sd_enable(true);
 540                 microsd_init = sd_init_card(SD_SLOT_AS3525);
 541                 if (microsd_init < 0) /* initialisation failed */
 542                     panicf("microSD init failed : %d", microsd_init);
 543
 544                 microsd_init = disk_mount(SD_SLOT_AS3525); /* 0 if fail */
 545             }
 546
 547             /*
 548              * Mount succeeded, or this was an EXTRACTED event,
 549              * in both cases notify the system about the changed filesystems
 550              */
 551             if (microsd_init)
 552                 queue_broadcast(SYS_FS_CHANGED, 0);
 553             /* Access is now safe */
 554             mutex_unlock(&sd_mtx);
 555             fat_unlock();
 556             sd_enable(false);
 557         }
 558             break;
 559 #endif
 560         case SYS_TIMEOUT:
 561             if (TIME_BEFORE(current_tick, last_disk_activity+(3*HZ)))
 562             {
 563                 idle_notified = false;
 564             }
 565             else
 566             {
 567                 /* never let a timer wrap confuse us */
 568                 next_yield = current_tick;
 569
 570                 if (!idle_notified)
 571                 {
 572                     call_storage_idle_notifys(false);
 573                     idle_notified = true;
 574                 }
 575             }
 576             break;
 577 #if 0
 578         case SYS_USB_CONNECTED:
 579             usb_acknowledge(SYS_USB_CONNECTED_ACK);
 580             /* Wait until the USB cable is extracted again */
 581             usb_wait_for_disconnect(&sd_queue);
 582
 583             break;
 584         case SYS_USB_DISCONNECTED:
 585             usb_acknowledge(SYS_USB_DISCONNECTED_ACK);
 586             break;
 587 #endif
 588         }
 589     }
 590 }
 591
 592 static void init_controller(void)
 593 {
 594     int hcon_numcards = ((MCI_HCON>>1) & 0x1F) + 1;
 595     int card_mask = (1 << hcon_numcards) - 1;
 596
 597     MCI_PWREN &= ~card_mask;               /*  power off all cards  */
 598
 599     MCI_CLKSRC = 0x00;                     /* All CLK_SRC_CRD set to 0*/
 600     MCI_CLKDIV = 0x00;                     /* CLK_DIV_0 : bits 7:0  */
 601
 602     MCI_PWREN |= card_mask;                /*  power up cards  */
 603     mci_delay();
 604
 605     MCI_CTRL |= CTRL_RESET;
 606     while(MCI_CTRL & CTRL_RESET)
 607         ;
 608
 609     MCI_RAW_STATUS = 0xffffffff;
 610
 611     MCI_TMOUT = 0xffffffff;             /*  data b31:8, response b7:0 */
 612
 613     MCI_CTYPE = 0x0;                    /*  all cards 1 bit bus for now */
 614
 615     MCI_CLKENA = card_mask;
 616
 617     MCI_ARGUMENT = 0;
 618     MCI_COMMAND = CMD_DONE_BIT|CMD_SEND_CLK_ONLY|CMD_WAIT_PRV_DAT_BIT;
 619     while(MCI_COMMAND & CMD_DONE_BIT)
 620         ;
 621
 622     MCI_DEBNCE = 0xfffff;   /* default value */
 623
 624     MCI_FIFOTH &= MCI_FIFOTH_MASK;
 625     MCI_FIFOTH |= 0x503f0080;
 626
 627     MCI_MASK = 0xffffffff & ~(MCI_INT_ACD|MCI_INT_CRDDET);
 628
 629     GPIOB_DIR |= (1<<5);         /* Pin B5 output  */
 630
 631     MCI_CTRL |= INT_ENABLE;
 632 }
 633
 634 int sd_init(void)
 635 {
 636     int ret;
 637     CGU_PERI |= CGU_MCI_CLOCK_ENABLE;
 638
 639     CGU_IDE =   (1<<7)  /* AHB interface enable */  |
 640                 (1<<6)  /* interface enable */      |
 641                 ((CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1) << 2) |
 642                 1;       /* clock source = PLLA */
 643
 644     CGU_MEMSTICK = (1<<8) | (1<<7) |
 645         ((CLK_DIV(AS3525_PLLA_FREQ, AS3525_MS_FREQ) -1) << 2) | 1;
 646
 647     *(volatile int*)(CGU_BASE+0x3C) = (1<<7) |
 648         (CLK_DIV(AS3525_PLLA_FREQ, 24000000) -1)<<2 | 1;
 649
 650     wakeup_init(&transfer_completion_signal);
 651
 652 #ifdef HAVE_MULTIDRIVE
 653     /* setup isr for microsd monitoring */
 654     VIC_INT_ENABLE = (INTERRUPT_GPIOA);
 655     /* clear previous irq */
 656     GPIOA_IC = (1<<2);
 657     /* enable edge detecting */
 658     GPIOA_IS &= ~(1<<2);
 659     /* detect both raising and falling edges */
 660     GPIOA_IBE |= (1<<2);
 661 #endif
 662
 663     VIC_INT_ENABLE = INTERRUPT_NAND;
 664
 665     init_controller();
 666     ret = sd_init_card(INTERNAL_AS3525);
 667     if(ret < 0)
 668         return ret;
 669
 670     /* init mutex */
 671     mutex_init(&sd_mtx);
 672
 673     queue_init(&sd_queue, true);
 674     create_thread(sd_thread, sd_stack, sizeof(sd_stack), 0,
 675             sd_thread_name IF_PRIO(, PRIORITY_USER_INTERFACE) IF_COP(, CPU));
 676
 677 #ifndef BOOTLOADER
 678     sd_enabled = true;
 679     sd_enable(false);
 680 #endif
 681     return 0;
 682 }
 683
 684 static int sd_wait_for_state(const int drive, unsigned int state)
 685 {
 686     unsigned long response;
 687     unsigned int timeout = 100; /* ticks */
 688     long t = current_tick;
 689
 690     while (1)
 691     {
 692         long tick;
 693
 694         if(!send_cmd(drive, SD_SEND_STATUS, card_info[drive].rca,
 695                     MCI_RESP, &response))
 696             return -1;
 697
 698         if (((response >> 9) & 0xf) == state)
 699             return 0;
 700
 701         if(TIME_AFTER(current_tick, t + timeout))
 702             return -10 * ((response >> 9) & 0xf);
 703
 704         if (TIME_AFTER((tick = current_tick), next_yield))
 705         {
 706             yield();
 707             timeout += current_tick - tick;
 708             next_yield = tick + MIN_YIELD_PERIOD;
 709         }
 710     }
 711 }
 712
 713 static int sd_transfer_sectors(IF_MD2(int drive,) unsigned long start,
 714                                 int count, void* buf, bool write)
 715 {
 716     int ret = 0;
 717 #ifndef HAVE_MULTIDRIVE
 718     const int drive = 0;
 719 #endif
 720
 721     /* skip SanDisk OF */
 722     if (drive == INTERNAL_AS3525)
 723         start += 0xf000;
 724
 725     mutex_lock(&sd_mtx);
 726 #ifndef BOOTLOADER
 727     sd_enable(true);
 728 #endif
 729
 730     if (card_info[drive].initialized <= 0)
 731     {
 732         ret = sd_init_card(drive);
 733         if (!(card_info[drive].initialized))
 734         {
 735             panicf("card not initialised (%d)", ret);
 736             goto sd_transfer_error;
 737         }
 738     }
 739
 740 #ifdef HAVE_MULTIDRIVE
 741     /*  CMD7 w/rca: Select card to put it in TRAN state */
 742     if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_NO_RESP, NULL))
 743         return -6;
 744 #endif
 745
 746     last_disk_activity = current_tick;
 747     dma_retain();
 748
 749     const int cmd = write ? SD_WRITE_MULTIPLE_BLOCK : SD_READ_MULTIPLE_BLOCK;
 750
 751     /* Interrupt handler might set this to true during transfer */
 752     do
 753     {
 754         void *dma_buf = aligned_buffer;
 755         unsigned int transfer = count;
 756         if(transfer > UNALIGNED_NUM_SECTORS)
 757             transfer = UNALIGNED_NUM_SECTORS;
 758
 759         if(write)
 760             memcpy(uncached_buffer, buf, transfer * SD_BLOCK_SIZE);
 761
 762         retry = false;
 763
 764         MCI_BLKSIZ = SD_BLOCK_SIZE;
 765         MCI_BYTCNT = transfer * SD_BLOCK_SIZE;
 766
 767         MCI_CTRL |= (FIFO_RESET|DMA_RESET);
 768         while(MCI_CTRL & (FIFO_RESET|DMA_RESET))
 769             ;
 770
 771         ret = sd_wait_for_state(drive, SD_TRAN);
 772         if (ret < 0)
 773         {
 774             static const char *st[9] = {
 775                 "IDLE", "RDY", "IDENT", "STBY", "TRAN", "DATA", "RCV",
 776                                                                 "PRG", "DIS"};
 777             if(ret <= -10)
 778                 panicf("wait for TRAN state failed (%s) %d",
 779                                                     st[(-ret / 10) % 9], drive);
 780             else
 781                 panicf("wait for state failed");
 782             goto sd_transfer_error;
 783         }
 784
 785         MCI_CTRL |= DMA_ENABLE;
 786         MCI_MASK = MCI_INT_CD|MCI_INT_DTO|MCI_INT_DCRC|MCI_INT_DRTO| \
 787             MCI_INT_HTO|MCI_INT_FRUN|MCI_INT_HLE|MCI_INT_SBE|MCI_INT_EBE;
 788
 789         MCI_FIFOTH &= MCI_FIFOTH_MASK;
 790         MCI_FIFOTH |= 0x503f0080;
 791
 792
 793         int arg = start;
 794         if(!(card_info[drive].ocr & (1<<30))) /* not SDHC */
 795             arg *= SD_BLOCK_SIZE;
 796
 797         if(!send_cmd(drive, cmd, arg, MCI_NO_RESP, NULL))
 798             panicf("%s multiple blocks failed", write ? "write" : "read");
 799
 800         if(write)
 801             dma_enable_channel(0, dma_buf, MCI_FIFO, DMA_PERI_SD,
 802                 DMAC_FLOWCTRL_PERI_MEM_TO_PERI, true, false, 0, DMA_S8, NULL);
 803         else
 804             dma_enable_channel(0, MCI_FIFO, dma_buf, DMA_PERI_SD,
 805                 DMAC_FLOWCTRL_PERI_PERI_TO_MEM, false, true, 0, DMA_S8, NULL);
 806
 807         data_transfer = true;
 808         wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK);
 809         data_transfer = false;
 810
 811         last_disk_activity = current_tick;
 812
 813         if(!send_cmd(drive, SD_STOP_TRANSMISSION, 0, MCI_NO_RESP, NULL))
 814         {
 815             ret = -666;
 816             panicf("STOP TRANSMISSION failed");
 817             goto sd_transfer_error;
 818         }
 819
 820         if(!retry)
 821         {
 822             if(!write)
 823                 memcpy(buf, uncached_buffer, transfer * SD_BLOCK_SIZE);
 824             buf += transfer * SD_BLOCK_SIZE;
 825             start += transfer;
 826             count -= transfer;
 827         }
 828     } while(retry || count);
 829
 830     dma_release();
 831
 832 #ifdef HAVE_MULTIDRIVE
 833     /* CMD lines are separate, not common, so we need to actively deselect */
 834     /*  CMD7 w/rca =0 : deselects card & puts it in STBY state */
 835     if(!send_cmd(drive, SD_DESELECT_CARD, 0, MCI_NO_RESP, NULL))
 836         return -6;
 837 #endif
 838
 839 #ifndef BOOTLOADER
 840     sd_enable(false);
 841 #endif
 842     mutex_unlock(&sd_mtx);
 843     return 0;
 844
 845 sd_transfer_error:
 846     panicf("transfer error : %d",ret);
 847     card_info[drive].initialized = 0;
 848     return ret;
 849 }
 850
 851 int sd_read_sectors(IF_MD2(int drive,) unsigned long start, int count,
 852                     void* buf)
 853 {
 854     return sd_transfer_sectors(IF_MD2(drive,) start, count, buf, false);
 855 }
 856
 857 int sd_write_sectors(IF_MD2(int drive,) unsigned long start, int count,
 858                      const void* buf)
 859 {
 860 #if 1 /* disabled until stable*/ \
 861     || defined(BOOTLOADER) /* we don't need write support in bootloader */
 862 #ifdef HAVE_MULTIDRIVE
 863     (void) drive;
 864 #endif
 865     (void) start;
 866     (void) count;
 867     (void) buf;
 868     return -1;
 869 #else
 870     return sd_transfer_sectors(IF_MD2(drive,) start, count, (void*)buf, true);
 871 #endif
 872 }
 873
 874 #ifndef BOOTLOADER
 875 long sd_last_disk_activity(void)
 876 {
 877     return last_disk_activity;
 878 }
 879
 880 void sd_enable(bool on)
 881 {
 882     /* TODO */
 883     if(on)
 884         CCU_IO |= (1<<2);              /* XPD is SD-MCI interface (b3:2 = 01) */
 885     else
 886         CCU_IO &= ~(1<<2);             /* XPD is general purpose IO (b3:2 = 00) */
 887     return;
 888 }
 889
 890 tCardInfo *card_get_info_target(int card_no)
 891 {
 892     return &card_info[card_no];
 893 }
 894 #endif /* BOOTLOADER */
 895
 896 #ifdef HAVE_HOTSWAP
 897 bool sd_removable(IF_MD_NONVOID(int drive))
 898 {
 899     return (drive==1);
 900 }
 901
 902 bool sd_present(IF_MD_NONVOID(int drive))
 903 {
 904     return (drive == 0) ? true : card_detect_target();
 905 }
 906
 907 static int sd1_oneshot_callback(struct timeout *tmo)
 908 {
 909     (void)tmo;
 910
 911     /* This is called only if the state was stable for 300ms - check state
 912  *      * and post appropriate event. */
 913     if (card_detect_target())
 914     {
 915         queue_broadcast(SYS_HOTSWAP_INSERTED, 0);
 916     }
 917     else
 918         queue_broadcast(SYS_HOTSWAP_EXTRACTED, 0);
 919
 920     return 0;
 921 }
 922
 923 void INT_GPIOA(void)
 924 {
 925     static struct timeout sd1_oneshot;
 926     /* acknowledge interrupt */
 927     GPIOA_IC = (1<<2);
 928     timeout_register(&sd1_oneshot, sd1_oneshot_callback, (3*HZ/10), 0);
 929 }
 930
 931 void card_enable_monitoring_target(bool on)
 932 {
 933     if (on) /* enable interrupt */
 934         GPIOA_IE |= (1<<2);
 935     else    /* disable interrupt */
 936         GPIOA_IE &= ~(1<<2);
 937 }
 938 #endif /* HAVE_HOTSWAP */
 939
 940 #ifdef CONFIG_STORAGE_MULTI
 941 int sd_num_drives(int first_drive)
 942 {
 943     /* We don't care which logical drive number(s) we have been assigned */
 944     (void)first_drive;
 945
 946     return NUM_DRIVES;
 947 }
 948 #endif /* CONFIG_STORAGE_MULTI */