firmware/target/arm/as3525/system-as3525.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2007 by Rob Purchase
  11  * Copyright © 2008 Rafaël Carré
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License
  15  * as published by the Free Software Foundation; either version 2
  16  * of the License, or (at your option) any later version.
  17  *
  18  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  19  * KIND, either express or implied.
  20  *
  21  ****************************************************************************/
  22
  23 #include "config.h"
  24 #include "kernel.h"
  25 #include "system.h"
  26 #include "panic.h"
  27 #include "ascodec-target.h"
  28 #include "adc.h"
  29 #include "dma-target.h"
  30 #include "clock-target.h"
  31 #include "fmradio_i2c.h"
  32 #include "button-target.h"
  33 #ifndef BOOTLOADER
  34 #include "mmu-arm.h"
  35 #endif
  36 #include "backlight-target.h"
  37
  38 #define default_interrupt(name) \
  39   extern __attribute__((weak,alias("UIRQ"))) void name (void)
  40
  41 void irq_handler(void) __attribute__((interrupt ("IRQ"), naked));
  42 void fiq_handler(void) __attribute__((interrupt ("FIQ"), naked));
  43
  44 default_interrupt(INT_WATCHDOG);
  45 default_interrupt(INT_TIMER1);
  46 default_interrupt(INT_TIMER2);
  47 default_interrupt(INT_USB);
  48 default_interrupt(INT_DMAC);
  49 default_interrupt(INT_NAND);
  50 default_interrupt(INT_IDE);
  51 default_interrupt(INT_MCI0);
  52 default_interrupt(INT_MCI1);
  53 default_interrupt(INT_AUDIO);
  54 default_interrupt(INT_SSP);
  55 default_interrupt(INT_I2C_MS);
  56 default_interrupt(INT_I2C_AUDIO);
  57 default_interrupt(INT_I2SIN);
  58 default_interrupt(INT_I2SOUT);
  59 default_interrupt(INT_UART);
  60 default_interrupt(INT_GPIOD);
  61 default_interrupt(RESERVED1); /* Interrupt 17 : unused */
  62 default_interrupt(INT_CGU);
  63 default_interrupt(INT_MEMORY_STICK);
  64 default_interrupt(INT_DBOP);
  65 default_interrupt(RESERVED2); /* Interrupt 21 : unused */
  66 default_interrupt(RESERVED3); /* Interrupt 22 : unused */
  67 default_interrupt(RESERVED4); /* Interrupt 23 : unused */
  68 default_interrupt(RESERVED5); /* Interrupt 24 : unused */
  69 default_interrupt(RESERVED6); /* Interrupt 25 : unused */
  70 default_interrupt(RESERVED7); /* Interrupt 26 : unused */
  71 default_interrupt(RESERVED8); /* Interrupt 27 : unused */
  72 default_interrupt(RESERVED9); /* Interrupt 28 : unused */
  73 default_interrupt(INT_GPIOA);
  74 default_interrupt(INT_GPIOB);
  75 default_interrupt(INT_GPIOC);
  76
  77 static const char * const irqname[] =
  78 {
  79     "INT_WATCHDOG", "INT_TIMER1", "INT_TIMER2", "INT_USB", "INT_DMAC", "INT_NAND",
  80     "INT_IDE", "INT_MCI0", "INT_MCI1", "INT_AUDIO", "INT_SSP", "INT_I2C_MS",
  81     "INT_I2C_AUDIO", "INT_I2SIN", "INT_I2SOUT", "INT_UART", "INT_GPIOD", "RESERVED1",
  82     "INT_CGU", "INT_MEMORY_STICK", "INT_DBOP", "RESERVED2", "RESERVED3", "RESERVED4",
  83     "RESERVED5", "RESERVED6", "RESERVED7", "RESERVED8", "RESERVED9", "INT_GPIOA",
  84     "INT_GPIOB", "INT_GPIOC"
  85 };
  86
  87 static void UIRQ(void)
  88 {
  89     unsigned int irq_no = 0;
  90     int status = VIC_IRQ_STATUS;
  91
  92     if(status == 0)
  93         panicf("Unhandled IRQ (source unknown!)");
  94
  95     while((status >>= 1))
  96         irq_no++;
  97
  98     panicf("Unhandled IRQ %02X: %s", irq_no, irqname[irq_no]);
  99 }
 100
 101 struct vec_int_src
 102 {
 103     int source;
 104     void (*isr) (void);
 105 };
 106
 107 /* Vectored interrupts (16 available) */
 108 struct vec_int_src vec_int_srcs[] =
 109 {
 110     { INT_SRC_TIMER1, INT_TIMER1 },
 111     { INT_SRC_TIMER2, INT_TIMER2 },
 112     { INT_SRC_DMAC, INT_DMAC },
 113     { INT_SRC_NAND, INT_NAND },
 114 #ifdef HAVE_MULTIDRIVE
 115     { INT_SRC_MCI0, INT_MCI0 },
 116 #endif
 117 #ifdef HAVE_HOTSWAP
 118     { INT_SRC_GPIOA, INT_GPIOA, },
 119 #endif
 120 #ifdef HAVE_RECORDING
 121     { INT_SRC_I2SIN, INT_I2SIN, },
 122 #endif
 123 };
 124
 125 static void setup_vic(void)
 126 {
 127     volatile unsigned long *vic_vect_addrs = VIC_VECT_ADDRS;
 128     volatile unsigned long *vic_vect_cntls = VIC_VECT_CNTLS;
 129     const unsigned int n = sizeof(vec_int_srcs)/sizeof(vec_int_srcs[0]);
 130     unsigned int i;
 131
 132     CGU_PERI |= CGU_VIC_CLOCK_ENABLE; /* enable VIC */
 133     VIC_INT_EN_CLEAR = 0xffffffff; /* disable all interrupt lines */
 134     VIC_INT_SELECT = 0; /* only IRQ, no FIQ */
 135
 136     VIC_DEF_VECT_ADDR = (unsigned long)UIRQ;
 137
 138     for(i = 0; i < n; i++)
 139     {
 140         vic_vect_addrs[i] = (unsigned long)vec_int_srcs[i].isr;
 141         vic_vect_cntls[i] = (1<<5) | vec_int_srcs[i].source;
 142     }
 143 }
 144
 145 void irq_handler(void)
 146 {
 147     asm volatile(   "stmfd  sp!, {r0-r5,ip,lr}      \n" /* Store context */
 148                     "ldr    r5, =0xC6010030         \n" /* VIC_VECT_ADDR */
 149                     "mov    lr, pc                  \n" /* Return from ISR */
 150                     "ldr    pc, [r5]                \n" /* execute ISR */
 151                     "str    r0, [r5]                \n" /* Ack interrupt */
 152                     "ldmfd  sp!, {r0-r5,ip,lr}      \n" /* Restore context */
 153                     "subs   pc, lr, #4              \n" /* Return from IRQ */
 154             );
 155 }
 156
 157 void fiq_handler(void)
 158 {
 159     asm volatile (
 160         "subs   pc, lr, #4   \r\n"
 161     );
 162 }
 163
 164 #ifdef BOOTLOADER
 165 static void sdram_delay(void)
 166 {
 167     int delay = 1024; /* arbitrary */
 168     while (delay--) ;
 169 }
 170
 171 /* Use the same initialization than OF */
 172 static void sdram_init(void)
 173 {
 174     CGU_PERI |= (1<<26)|(1<<27); /* extmem & extmem intf clocks */
 175
 176     MPMC_CONTROL = 0x1; /* enable MPMC */
 177
 178     MPMC_DYNAMIC_CONTROL = 0x183; /* SDRAM NOP, all clocks high */
 179     sdram_delay();
 180
 181     MPMC_DYNAMIC_CONTROL = 0x103; /* SDRAM PALL, all clocks high */
 182     sdram_delay();
 183
 184     MPMC_DYNAMIC_REFRESH = 0x138; /* 0x138 * 16 HCLK ticks between SDRAM refresh cycles */
 185
 186     MPMC_CONFIG = 0; /* little endian, HCLK:MPMCCLKOUT[3:0] ratio = 1:1 */
 187
 188     if(MPMC_PERIPH_ID2 & 0xf0)
 189         MPMC_DYNAMIC_READ_CONFIG = 0x1; /* command delayed, clock out not delayed */
 190
 191     /* timings */
 192     MPMC_DYNAMIC_tRP    = 2;
 193     MPMC_DYNAMIC_tRAS   = 4;
 194     MPMC_DYNAMIC_tSREX  = 5;
 195     MPMC_DYNAMIC_tAPR   = 0;
 196     MPMC_DYNAMIC_tDAL   = 4;
 197     MPMC_DYNAMIC_tWR    = 2;
 198     MPMC_DYNAMIC_tRC    = 5;
 199     MPMC_DYNAMIC_tRFC   = 5;
 200     MPMC_DYNAMIC_tXSR   = 5;
 201     MPMC_DYNAMIC_tRRD   = 2;
 202     MPMC_DYNAMIC_tMRD   = 2;
 203
 204 #if defined(SANSA_CLIP) || defined(SANSA_M200V4) || defined(SANSA_C200V2)
 205 /* 16 bits external bus, low power SDRAM, 16 Mbits = 2 Mbytes */
 206 #define MEMORY_MODEL 0x21
 207
 208 #elif defined(SANSA_E200V2) || defined(SANSA_FUZE)
 209 /* 16 bits external bus, high performance SDRAM, 64 Mbits = 8 Mbytes */
 210 #define MEMORY_MODEL 0x5
 211
 212 #else
 213 #error "The external memory in your player is unknown"
 214 #endif
 215
 216     MPMC_DYNAMIC_RASCAS_0 = (2<<8)|2; /* CAS & RAS latency = 2 clock cycles */
 217     MPMC_DYNAMIC_CONFIG_0 = (MEMORY_MODEL << 7);
 218
 219     MPMC_DYNAMIC_RASCAS_1 = MPMC_DYNAMIC_CONFIG_1 =
 220     MPMC_DYNAMIC_RASCAS_2 = MPMC_DYNAMIC_CONFIG_2 =
 221     MPMC_DYNAMIC_RASCAS_3 = MPMC_DYNAMIC_CONFIG_3 = 0;
 222
 223     MPMC_DYNAMIC_CONTROL = 0x82; /* SDRAM MODE, MPMCCLKOUT runs continuously */
 224
 225     /* program the SDRAM mode register */
 226     /* FIXME: details the exact settings of mode register */
 227     asm volatile(
 228         "ldr r4, [%0]\n"
 229         : : "p"(0x30000000+0x2300*MEM) : "r4");
 230
 231     MPMC_DYNAMIC_CONTROL = 0x2; /* SDRAM NORMAL, MPMCCLKOUT runs continuously */
 232
 233     MPMC_DYNAMIC_CONFIG_0 |= (1<<19); /* buffer enable */
 234 }
 235 #else
 236 void memory_init(void)
 237 {
 238     ttb_init();
 239     /* map every region to itself, uncached */
 240     map_section(0, 0, 4096, CACHE_NONE);
 241
 242     /* IRAM */
 243     map_section(0, IRAM_ORIG, 1, CACHE_ALL);
 244     map_section(0, UNCACHED_ADDR(IRAM_ORIG), 1, CACHE_NONE);
 245
 246     /* DRAM */
 247     map_section(0x30000000, DRAM_ORIG, MEMORYSIZE, CACHE_ALL);
 248     map_section(0x30000000, UNCACHED_ADDR(DRAM_ORIG), MEMORYSIZE, CACHE_NONE);
 249
 250     /* map 1st mbyte of DRAM at 0x0 to have exception vectors available */
 251     map_section(0x30000000, 0, 1, CACHE_ALL);
 252
 253     enable_mmu();
 254 }
 255 #endif
 256
 257 void system_init(void)
 258 {
 259     unsigned int reset_loops = 640;
 260
 261     CCU_SRC = 0x1fffff0
 262         & ~(1<<18); /* FIXME */
 263     while(reset_loops--)
 264         CCU_SRL = CCU_SRL_MAGIC_NUMBER;
 265     CCU_SRC = CCU_SRL = 0;
 266
 267     CCU_SCON = 1; /* AHB master's priority configuration :
 268                      TIC (Test Interface Controller) > DMA > USB > IDE > ARM */
 269
 270     CGU_PROC = 0;           /* fclk 24 MHz */
 271     CGU_PERI &= ~0x7f;      /* pclk 24 MHz */
 272
 273     CGU_PLLA = AS3525_PLLA_SETTING;
 274     while(!(CGU_INTCTRL & (1<<0)));           /* wait until PLLA is locked */
 275
 276     /*  Set FCLK frequency */
 277     CGU_PROC = ((AS3525_FCLK_POSTDIV << 4) |
 278                 (AS3525_FCLK_PREDIV  << 2) |
 279                  AS3525_FCLK_SEL);
 280     /*  Set PCLK frequency */
 281     CGU_PERI = ((CGU_PERI & 0xffffff80)  |    /* reset divider bits 0:6 */
 282                  (AS3525_PCLK_DIV0 << 2) |
 283                  (AS3525_PCLK_DIV1 << 6) |
 284                   AS3525_PCLK_SEL);
 285
 286     asm volatile(
 287         "mrc p15, 0, r0, c1, c0   \n"      /* control register */
 288         "bic r0, r0, #3<<30       \n"      /* clears bus bits : sets fastbus */
 289         "mcr p15, 0, r0, c1, c0   \n"
 290         : : : "r0" );
 291
 292 #ifdef BOOTLOADER
 293     sdram_init();
 294 #endif  /* BOOTLOADER */
 295
 296 #if 0 /* the GPIO clock is already enabled by the dualboot function */
 297     CGU_PERI |= CGU_GPIO_CLOCK_ENABLE;
 298 #endif
 299
 300     /* enable timer interface for TIMER1 & TIMER2 */
 301     CGU_PERI |= CGU_TIMERIF_CLOCK_ENABLE;
 302
 303     setup_vic();
 304
 305     dma_init();
 306
 307     ascodec_init();
 308
 309 #ifndef BOOTLOADER
 310     /*  Initialize power management settings */
 311     ascodec_write(AS3514_CVDD_DCDC3, AS314_CP_DCDC3_SETTING);
 312 #ifdef CONFIG_TUNER
 313     fmradio_i2c_init();
 314 #endif
 315 #endif /* !BOOTLOADER */
 316 }
 317
 318 void system_reboot(void)
 319 {
 320     _backlight_off();
 321     /* use watchdog to reset */
 322     CGU_PERI |= (CGU_WDOCNT_CLOCK_ENABLE | CGU_WDOIF_CLOCK_ENABLE);
 323     WDT_LOAD = 1; /* set counter to 1 */
 324     WDT_CONTROL = 3; /* enable watchdog counter & reset */
 325     while(1);
 326 }
 327
 328 void system_exception_wait(void)
 329 {
 330     while(!button_read_device());
 331 }
 332
 333 int system_memory_guard(int newmode)
 334 {
 335     (void)newmode;
 336     return 0;
 337 }
 338
 339 #ifndef BOOTLOADER
 340 #ifdef HAVE_ADJUSTABLE_CPU_FREQ
 341 void set_cpu_frequency(long frequency)
 342 {
 343     if(frequency == CPUFREQ_MAX)
 344     {
 345         /* Increasing frequency so boost voltage before change */
 346         ascodec_write(AS3514_CVDD_DCDC3, (AS314_CP_DCDC3_SETTING | CVDD_1_20));
 347
 348         /* Some players run a bit low so use 1.175 volts instead of 1.20  */
 349         /* Wait for voltage to be at least 1.175v before making fclk > 200 MHz */
 350         while(adc_read(ADC_CVDD) < 470); /* 470 * .0025 = 1.175V */
 351
 352         asm volatile(
 353             "mrc p15, 0, r0, c1, c0  \n"
 354
 355 #ifdef ASYNCHRONOUS_BUS
 356             "orr r0, r0, #3<<30      \n"   /* asynchronous bus clocking */
 357 #else
 358             "bic r0, r0, #3<<30      \n"   /* clear bus bits */
 359             "orr r0, r0, #1<<30      \n"   /* synchronous bus clocking */
 360 #endif
 361
 362             "mcr p15, 0, r0, c1, c0  \n"
 363             : : : "r0" );
 364
 365         cpu_frequency = CPUFREQ_MAX;
 366     }
 367     else
 368     {
 369         asm volatile(
 370             "mrc p15, 0, r0, c1, c0  \n"
 371             "bic r0, r0, #3<<30      \n"     /* fastbus clocking */
 372             "mcr p15, 0, r0, c1, c0  \n"
 373             : : : "r0" );
 374
 375         /* Decreasing frequency so reduce voltage after change */
 376         ascodec_write(AS3514_CVDD_DCDC3, (AS314_CP_DCDC3_SETTING | CVDD_1_10));
 377
 378         cpu_frequency = CPUFREQ_NORMAL;
 379     }
 380 }
 381 #endif /* HAVE_ADJUSTABLE_CPU_FREQ */
 382 #endif /* !BOOTLOADER */