firmware/export/tlv320.h

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2005 by Christian Gmeiner
  11  *
  12  * All files in this archive are subject to the GNU General Public License.
  13  * See the file COPYING in the source tree root for full license agreement.
  14  *
  15  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  16  * KIND, either express or implied.
  17  *
  18  ****************************************************************************/
  19
  20 #ifndef _TLV320_H_
  21 #define _TLV320_H_
  22
  23 #define VOLUME_MIN -730
  24 #define VOLUME_MAX  60
  25
  26 extern int tenthdb2master(int db);
  27
  28 /*** definitions ***/
  29
  30 /**
  31  * Sets internal sample rate for DAC and ADC relative to MCLK
  32  * Selection for frequency:
  33  * Fs:        tlv:   with:
  34  * 11025: 0 = MCLK/2 MCLK/2  SCLK, LRCK: Audio Clk / 16
  35  * 22050: 0 = MCLK/2 MCLK    SCLK, LRCK: Audio Clk / 8
  36  * 44100: 1 = MCLK   MCLK    SCLK, LRCK: Audio Clk / 4 (default)
  37  * 88200: 2 = MCLK*2 MCLK    SCLK, LRCK: Audio Clk / 2
  38  */
  39 extern void audiohw_set_frequency(unsigned fsel);
  40 extern void audiohw_set_headphone_vol(int vol_l, int vol_r);
  41
  42 #define HEADPHONE_MUTE 0x30 /* 0110000 = -73db */
  43
  44 /* ToDo: samplerates */
  45
  46 /* registers */
  47 /* REG_LLIV: Left line input channel volume control */
  48 #define REG_LLIV        0x0
  49 #define LLIV_LRS        (1 << 8)    /* simultaneous volume/mute update  */
  50 #define LLIV_LIM        (1 << 7)    /* Left line input mute             */
  51 #define LLIV_LIV(x)     ((x) & 0x1f)/* Left line input volume control   */
  52
  53 /* REG_RLIV: Right line input channel volume control */
  54 #define REG_RLIV        0x1
  55 #define RLIV_RLS        (1 << 8)    /* simultaneous volume/mute update  */
  56 #define RLIV_RIM        (1 << 7)    /* Right line input mute            */
  57 #define RLIV_RIV(x)     ((x) & 0x1f)/* Right line input volume control  */
  58
  59 /* REG_LHV: Left Channel Headphone Volume Control */
  60 #define REG_LHV         0x2
  61 #define LHV_LRS         (1 << 8)    /* simultaneous volume/mute update */
  62 #define LHV_LZC         (1 << 7)    /* Left-channel zero-cross detect  */
  63 #define LHV_LHV(x)      ((x) & 0x7f)/* Left headphone volume control    */
  64
  65 /* REG_RHV: Right Channel Headphone Volume Control */
  66 #define REG_RHV         0x3
  67 #define RHV_LRS         (1 << 8)    /* simultaneous volume/mute update  */
  68 #define RHV_RZC         (1 << 7)    /* Right-channel zero-cross detect  */
  69 #define RHV_RHV(x)      ((x) & 0x7f)/* Right headphone volume control   */
  70
  71 /* REG_AAP: Analog Audio Path Control */
  72 #define REG_AAP         0x4
  73 #define AAP_DAC         (1 << 4)    /* DAC select           */
  74 #define AAP_BYPASS      (1 << 3)    /* bypass               */
  75 #define AAP_INSEL       (1 << 2)    /* Input select for ADC */
  76 #define AAP_MICM        (1 << 1)    /* Microphone mute      */
  77 #define AAP_MICB        (1 << 0)    /* Microphone boost     */
  78
  79 /* REG_DAP: Digital Audio Path Control */
  80 #define REG_DAP         0x5
  81 #define DAP_DACM        (1 << 3)    /* DAC soft mute                    */
  82 #define DAP_DEEMP_32    (1 << 1)    /* De-emphasis control: 32 kHz      */
  83 #define DAP_DEEMP_44    (2 << 1)    /* De-emphasis control: 44.1 kHz    */
  84 #define DAP_DEEMP_48    (3 << 1)    /* De-emphasis control: 48 kHz      */
  85 #define DAP_ADCHP       (1 << 0)    /* ADC high-pass filter             */
  86
  87 /* REG_PC: Power Down Control */
  88 #define REG_PC          0x6
  89 #define PC_OFF          (1 << 7)    /* Device power     */
  90 #define PC_CLK          (1 << 6)    /* Clock            */
  91 #define PC_OSC          (1 << 5)    /* Oscillator       */
  92 #define PC_OUT          (1 << 4)    /* Outputs          */
  93 #define PC_DAC          (1 << 3)    /* DAC              */
  94 #define PC_ADC          (1 << 2)    /* ADC              */
  95 #define PC_MIC          (1 << 1)    /* Microphone input */
  96 #define PC_LINE         (1 << 0)    /* Line input       */
  97
  98 /* REG_DAIF: Digital Audio Interface Format */
  99 #define REG_DAIF        0x7
 100 #define DAIF_MS         (1 << 6)    /* Master/slave mode                        */
 101 #define DAIF_LRSWAP     (1 << 5)    /* DAC left/right swap                      */
 102 #define DAIF_LRP        (1 << 4)    /* DAC left/right phase                     */
 103 #define DAIF_IWL_16     (0 << 2)    /* Input bit length: 16 bit                 */
 104 #define DAIF_IWL_20     (1 << 2)    /* Input bit length: 20 bit                 */
 105 #define DAIF_IWL_24     (2 << 2)    /* Input bit length: 24 bit                 */
 106 #define DAIF_IWL_32     (3 << 2)    /* Input bit length: 32 bit                 */
 107 #define DAIF_FOR_DSP    (3 << 0)    /* Data format: DSP                         */
 108 #define DAIF_FOR_I2S    (2 << 0)    /* Data format: I2S                         */
 109 #define DAIF_FOR_MSBL   (1 << 0)    /* Data format: MSB first, left aligned     */
 110 #define DAIF_FOR_MSBR   (0 << 0)    /* Data format: MSB first, right aligned    */
 111
 112 /* REG_SRC: Sample Rate Control */
 113 #define REG_SRC         0x8
 114 #define SRC_CLKIN       (1 << 6)    /* Clock input divider                          */
 115 #define SRC_CLKOUT      (1 << 7)    /* Clock output divider                         */
 116 /*#define SRC_SR        ()*/
 117 #define SRC_BOSR        (1 << 1)    /* Base oversampling rate, depends on SRC_USB   */
 118 #define SRC_USB         (1 << 0)    /* Clock mode select                            */
 119
 120 /* REG_DIA: Digital Interface Activation */
 121 #define REG_DIA         0x9
 122 #define DIA_ACT         (1 << 0)    /* Activate interface */
 123
 124 /* REG_RR: Reset Register */
 125 #define REG_RR          0xf
 126 #define RR_RESET        0           /* Reset */
 127
 128 #endif /*_TLV320_H_*/