1 /***************************************************************************
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
10 * Copyright © 2008 Rafaël Carré
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
20 ****************************************************************************/
25 #include "dma-target.h"
28 static int dma_used
= 0;
29 static void (*dma_callback
[2])(void); /* 2 channels */
35 CGU_PERI
|= CGU_DMA_CLOCK_ENABLE
;
36 DMAC_CONFIGURATION
|= (1<<0);
40 void dma_release(void)
44 DMAC_CONFIGURATION
&= ~(1<<0);
45 CGU_PERI
&= ~CGU_DMA_CLOCK_ENABLE
;
51 DMAC_SYNC
= 0xffff; /* disable synchronisation logic */
52 VIC_INT_ENABLE
= INTERRUPT_DMAC
;
55 inline void dma_disable_channel(int channel
)
57 DMAC_CH_CONFIGURATION(channel
) &= ~(1<<0);
60 void dma_enable_channel(int channel
, void *src
, void *dst
, int peri
,
61 int flow_controller
, bool src_inc
, bool dst_inc
,
62 size_t size
, int nwords
, void (*callback
)(void))
64 dma_callback
[channel
] = callback
;
66 /* Clear any pending interrupts leftover from previous operation */
67 DMAC_INT_TC_CLEAR
= (1<<channel
);
68 DMAC_INT_ERR_CLEAR
= (1<<channel
);
70 DMAC_CH_SRC_ADDR(channel
) = (int)src
;
71 DMAC_CH_DST_ADDR(channel
) = (int)dst
;
73 /* When LLI is 0 channel is disabled upon transfer completion */
74 DMAC_CH_LLI(channel
) = 0;
76 /* Channel Control Register */
77 DMAC_CH_CONTROL(channel
) =
78 ((1<<31) /* LLI triggers terminal count interrupt */
79 /* | (1<<30) */ /* cacheable = 1, non = 0 */
80 /* | (1<<29) */ /* bufferable = 1, non = 0 */
81 /* | (1<<28) */ /* privileged = 1, user = 0 */
82 | (dst_inc
? (1<<27): 0) /* specify address increment */
83 | (src_inc
? (1<<26): 0) /* specify address increment */
84 /* [25:24] */ /* undefined */
85 | (2<<21) /* dst width = word, 32bit */
86 | (2<<18) /* src width = word, 32bit */
87 /* OF uses transfers of 4 * 32 bits words on memory, i2sin, i2sout */
88 /* OF uses transfers of 8 * 32 bits words on SD */
89 | (nwords
<<15) /* dst size */
90 | (nwords
<<12) /* src size */
91 | ((size
& 0x7ff)<<0)); /* transfer size */
93 /* Channel Config Register */
94 DMAC_CH_CONFIGURATION(channel
) =
95 /* [31:19] */ /* Read undefined. Write as zero */
96 /* (0<<18) */ /* Halt Bit */
97 /* (0<<17) */ /* Active Bit */
98 /* (0<<16) */ /* Lock Bit */
99 (1<<15) /* terminal count interrupt mask */
100 | (1<<14) /* interrupt error mask */
101 | (flow_controller
<<11) /* flow controller is peripheral or SDMAC */
102 /* we set the same peripheral as source and destination because we
103 * always use memory-to-peripheral or peripheral-to-memory transfers */
104 | (peri
<<6) /* dst peripheral */
105 | (peri
<<1) /* src peripheral */
106 | (1<<0); /* enable channel */
112 unsigned int channel
;
114 /* SD channel is serviced first */
115 for(channel
= 0; channel
< 2; channel
++)
116 if(DMAC_INT_STATUS
& (1<<channel
))
118 if(DMAC_INT_ERROR_STATUS
& (1<<channel
))
119 panicf("DMA error, channel %d", channel
);
121 /* clear terminal count interrupt */
122 DMAC_INT_TC_CLEAR
= (1<<channel
);
124 if(dma_callback
[channel
])
125 dma_callback
[channel
]();