1 /***************************************************************************
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
10 * Copyright (C) 2007 by Rob Purchase
11 * Copyright © 2008 Rafaël Carré
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version 2
16 * of the License, or (at your option) any later version.
18 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
19 * KIND, either express or implied.
21 ****************************************************************************/
27 #include "ascodec-target.h"
29 #include "dma-target.h"
30 #include "clock-target.h"
31 #include "fmradio_i2c.h"
32 #include "button-target.h"
36 #include "backlight-target.h"
38 #define default_interrupt(name) \
39 extern __attribute__((weak,alias("UIRQ"))) void name (void)
41 void irq_handler(void) __attribute__((interrupt ("IRQ"), naked
));
42 void fiq_handler(void) __attribute__((interrupt ("FIQ"), naked
));
44 default_interrupt(INT_WATCHDOG
);
45 default_interrupt(INT_TIMER1
);
46 default_interrupt(INT_TIMER2
);
47 default_interrupt(INT_USB
);
48 default_interrupt(INT_DMAC
);
49 default_interrupt(INT_NAND
);
50 default_interrupt(INT_IDE
);
51 default_interrupt(INT_MCI0
);
52 default_interrupt(INT_MCI1
);
53 default_interrupt(INT_AUDIO
);
54 default_interrupt(INT_SSP
);
55 default_interrupt(INT_I2C_MS
);
56 default_interrupt(INT_I2C_AUDIO
);
57 default_interrupt(INT_I2SIN
);
58 default_interrupt(INT_I2SOUT
);
59 default_interrupt(INT_UART
);
60 default_interrupt(INT_GPIOD
);
61 default_interrupt(RESERVED1
); /* Interrupt 17 : unused */
62 default_interrupt(INT_CGU
);
63 default_interrupt(INT_MEMORY_STICK
);
64 default_interrupt(INT_DBOP
);
65 default_interrupt(RESERVED2
); /* Interrupt 21 : unused */
66 default_interrupt(RESERVED3
); /* Interrupt 22 : unused */
67 default_interrupt(RESERVED4
); /* Interrupt 23 : unused */
68 default_interrupt(RESERVED5
); /* Interrupt 24 : unused */
69 default_interrupt(RESERVED6
); /* Interrupt 25 : unused */
70 default_interrupt(RESERVED7
); /* Interrupt 26 : unused */
71 default_interrupt(RESERVED8
); /* Interrupt 27 : unused */
72 default_interrupt(RESERVED9
); /* Interrupt 28 : unused */
73 default_interrupt(INT_GPIOA
);
74 default_interrupt(INT_GPIOB
);
75 default_interrupt(INT_GPIOC
);
77 static const char * const irqname
[] =
79 "INT_WATCHDOG", "INT_TIMER1", "INT_TIMER2", "INT_USB", "INT_DMAC", "INT_NAND",
80 "INT_IDE", "INT_MCI0", "INT_MCI1", "INT_AUDIO", "INT_SSP", "INT_I2C_MS",
81 "INT_I2C_AUDIO", "INT_I2SIN", "INT_I2SOUT", "INT_UART", "INT_GPIOD", "RESERVED1",
82 "INT_CGU", "INT_MEMORY_STICK", "INT_DBOP", "RESERVED2", "RESERVED3", "RESERVED4",
83 "RESERVED5", "RESERVED6", "RESERVED7", "RESERVED8", "RESERVED9", "INT_GPIOA",
84 "INT_GPIOB", "INT_GPIOC"
87 static void UIRQ(void)
89 unsigned int irq_no
= 0;
90 int status
= VIC_IRQ_STATUS
;
93 panicf("Unhandled IRQ (source unknown!)");
98 panicf("Unhandled IRQ %02X: %s", irq_no
, irqname
[irq_no
]);
107 /* Vectored interrupts (16 available) */
108 struct vec_int_src vec_int_srcs
[] =
110 { INT_SRC_TIMER1
, INT_TIMER1
},
111 { INT_SRC_TIMER2
, INT_TIMER2
},
112 { INT_SRC_DMAC
, INT_DMAC
},
113 { INT_SRC_NAND
, INT_NAND
},
114 { INT_SRC_I2C_AUDIO
, INT_I2C_AUDIO
},
115 { INT_SRC_AUDIO
, INT_AUDIO
},
116 #ifdef HAVE_MULTIDRIVE
117 { INT_SRC_MCI0
, INT_MCI0
},
120 { INT_SRC_GPIOA
, INT_GPIOA
, },
122 #ifdef HAVE_RECORDING
123 { INT_SRC_I2SIN
, INT_I2SIN
, },
127 static void setup_vic(void)
129 volatile unsigned long *vic_vect_addrs
= VIC_VECT_ADDRS
;
130 volatile unsigned long *vic_vect_cntls
= VIC_VECT_CNTLS
;
131 const unsigned int n
= sizeof(vec_int_srcs
)/sizeof(vec_int_srcs
[0]);
134 CGU_PERI
|= CGU_VIC_CLOCK_ENABLE
; /* enable VIC */
135 VIC_INT_EN_CLEAR
= 0xffffffff; /* disable all interrupt lines */
136 VIC_INT_SELECT
= 0; /* only IRQ, no FIQ */
138 VIC_DEF_VECT_ADDR
= (unsigned long)UIRQ
;
140 for(i
= 0; i
< n
; i
++)
142 vic_vect_addrs
[i
] = (unsigned long)vec_int_srcs
[i
].isr
;
143 vic_vect_cntls
[i
] = (1<<5) | vec_int_srcs
[i
].source
;
147 void irq_handler(void)
149 asm volatile( "stmfd sp!, {r0-r5,ip,lr} \n" /* Store context */
150 "ldr r5, =0xC6010030 \n" /* VIC_VECT_ADDR */
151 "mov lr, pc \n" /* Return from ISR */
152 "ldr pc, [r5] \n" /* execute ISR */
153 "str r0, [r5] \n" /* Ack interrupt */
154 "ldmfd sp!, {r0-r5,ip,lr} \n" /* Restore context */
155 "subs pc, lr, #4 \n" /* Return from IRQ */
159 void fiq_handler(void)
162 "subs pc, lr, #4 \r\n"
166 #if defined(BOOTLOADER)
167 static void sdram_delay(void)
169 int delay
= 1024; /* arbitrary */
173 /* Use the same initialization than OF */
174 static void sdram_init(void)
176 CGU_PERI
|= (CGU_EXTMEM_CLOCK_ENABLE
|CGU_EXTMEMIF_CLOCK_ENABLE
);
178 MPMC_CONTROL
= 0x1; /* enable MPMC */
180 MPMC_DYNAMIC_CONTROL
= 0x183; /* SDRAM NOP, all clocks high */
183 MPMC_DYNAMIC_CONTROL
= 0x103; /* SDRAM PALL, all clocks high */
186 MPMC_DYNAMIC_REFRESH
= 0x138; /* 0x138 * 16 HCLK ticks between SDRAM refresh cycles */
188 MPMC_CONFIG
= 0; /* little endian, HCLK:MPMCCLKOUT[3:0] ratio = 1:1 */
190 if(MPMC_PERIPH_ID2
& 0xf0)
191 MPMC_DYNAMIC_READ_CONFIG
= 0x1; /* command delayed, clock out not delayed */
194 MPMC_DYNAMIC_tRP
= 2;
195 MPMC_DYNAMIC_tRAS
= 4;
196 MPMC_DYNAMIC_tSREX
= 5;
197 MPMC_DYNAMIC_tAPR
= 0;
198 MPMC_DYNAMIC_tDAL
= 4;
199 MPMC_DYNAMIC_tWR
= 2;
200 MPMC_DYNAMIC_tRC
= 5;
201 MPMC_DYNAMIC_tRFC
= 5;
202 MPMC_DYNAMIC_tXSR
= 5;
203 MPMC_DYNAMIC_tRRD
= 2;
204 MPMC_DYNAMIC_tMRD
= 2;
206 #if defined(SANSA_CLIP) || defined(SANSA_M200V4) || defined(SANSA_C200V2)
207 /* 16 bits external bus, low power SDRAM, 16 Mbits = 2 Mbytes */
208 #define MEMORY_MODEL 0x21
210 #elif defined(SANSA_E200V2) || defined(SANSA_FUZE) || defined(SANSA_CLIPV2) \
211 || defined(SANSA_CLIPPLUS) || defined(SANSA_FUZEV2)
212 /* 16 bits external bus, high performance SDRAM, 64 Mbits = 8 Mbytes */
213 #define MEMORY_MODEL 0x5
216 #error "The external memory in your player is unknown"
219 MPMC_DYNAMIC_RASCAS_0
= (2<<8)|2; /* CAS & RAS latency = 2 clock cycles */
220 MPMC_DYNAMIC_CONFIG_0
= (MEMORY_MODEL
<< 7);
222 MPMC_DYNAMIC_RASCAS_1
= MPMC_DYNAMIC_CONFIG_1
=
223 MPMC_DYNAMIC_RASCAS_2
= MPMC_DYNAMIC_CONFIG_2
=
224 MPMC_DYNAMIC_RASCAS_3
= MPMC_DYNAMIC_CONFIG_3
= 0;
226 MPMC_DYNAMIC_CONTROL
= 0x82; /* SDRAM MODE, MPMCCLKOUT runs continuously */
228 /* program the SDRAM mode register */
229 /* FIXME: details the exact settings of mode register */
232 : : "p"(0x30000000+0x2300*MEM
) : "r4");
234 MPMC_DYNAMIC_CONTROL
= 0x2; /* SDRAM NORMAL, MPMCCLKOUT runs continuously */
236 MPMC_DYNAMIC_CONFIG_0
|= (1<<19); /* buffer enable */
238 #endif /* BOOTLOADER */
240 void system_init(void)
242 #if CONFIG_CPU == AS3525v2
246 & ~CCU_SRC_IDE_EN
; /* FIXME */
249 unsigned int reset_loops
= 640;
251 CCU_SRL
= CCU_SRL_MAGIC_NUMBER
;
252 CCU_SRC
= CCU_SRL
= 0;
254 CCU_SCON
= 1; /* AHB master's priority configuration :
255 TIC (Test Interface Controller) > DMA > USB > IDE > ARM */
257 CGU_PERI
&= ~0x7f; /* pclk 24 MHz */
260 "mrc p15, 0, r0, c1, c0 \n" /* control register */
261 "bic r0, r0, #3<<30 \n" /* clears bus bits : sets fastbus */
262 "mcr p15, 0, r0, c1, c0 \n"
265 CGU_PLLASUP
= 0; /* enable PLLA */
266 CGU_PLLA
= AS3525_PLLA_SETTING
;
267 while(!(CGU_INTCTRL
& (1<<0))); /* wait until PLLA is locked */
269 #if (AS3525_MCLK_SEL == AS3525_CLK_PLLB)
270 CGU_PLLBSUP
= 0; /* enable PLLB */
271 CGU_PLLB
= AS3525_PLLB_SETTING
;
272 while(!(CGU_INTCTRL
& (1<<1))); /* wait until PLLB is locked */
275 /* Set FCLK frequency */
276 CGU_PROC
= ((AS3525_FCLK_POSTDIV
<< 4) |
277 (AS3525_FCLK_PREDIV
<< 2) |
280 /* Set PCLK frequency */
281 CGU_PERI
= ((CGU_PERI
& ~0x7F) | /* reset divider & clksel bits */
282 (AS3525_PCLK_DIV0
<< 2) |
283 (AS3525_PCLK_DIV1
<< 6) |
288 #endif /* BOOTLOADER */
290 #if 0 /* the GPIO clock is already enabled by the dualboot function */
291 CGU_PERI
|= CGU_GPIO_CLOCK_ENABLE
;
294 /* enable timer interface for TIMER1 & TIMER2 */
295 CGU_PERI
|= CGU_TIMERIF_CLOCK_ENABLE
;
304 /* Initialize power management settings */
305 ascodec_write(AS3514_CVDD_DCDC3
, AS314_CP_DCDC3_SETTING
);
309 #endif /* !BOOTLOADER */
312 void system_reboot(void)
315 /* use watchdog to reset */
316 CGU_PERI
|= (CGU_WDOCNT_CLOCK_ENABLE
| CGU_WDOIF_CLOCK_ENABLE
);
317 WDT_LOAD
= 1; /* set counter to 1 */
318 WDT_CONTROL
= 3; /* enable watchdog counter & reset */
322 void system_exception_wait(void)
324 /* wait until button release (if a button is pressed) */
325 while(button_read_device());
326 /* then wait until next button press */
327 while(!button_read_device());
330 int system_memory_guard(int newmode
)
337 #ifdef HAVE_ADJUSTABLE_CPU_FREQ
338 void set_cpu_frequency(long frequency
)
340 if(frequency
== CPUFREQ_MAX
)
342 #ifdef HAVE_ADJUSTABLE_CPU_VOLTAGE
343 /* Increasing frequency so boost voltage before change */
344 ascodec_write(AS3514_CVDD_DCDC3
, (AS314_CP_DCDC3_SETTING
| CVDD_1_20
));
346 /* Some players run a bit low so use 1.175 volts instead of 1.20 */
347 /* Wait for voltage to be at least 1.175v before making fclk > 200 MHz */
348 while(adc_read(ADC_CVDD
) < 470); /* 470 * .0025 = 1.175V */
349 #endif /* HAVE_ADJUSTABLE_CPU_VOLTAGE */
352 "mrc p15, 0, r0, c1, c0 \n"
354 #ifdef ASYNCHRONOUS_BUS
355 "orr r0, r0, #3<<30 \n" /* asynchronous bus clocking */
357 "bic r0, r0, #3<<30 \n" /* clear bus bits */
358 "orr r0, r0, #1<<30 \n" /* synchronous bus clocking */
361 "mcr p15, 0, r0, c1, c0 \n"
364 cpu_frequency
= CPUFREQ_MAX
;
369 "mrc p15, 0, r0, c1, c0 \n"
370 "bic r0, r0, #3<<30 \n" /* fastbus clocking */
371 "mcr p15, 0, r0, c1, c0 \n"
374 #ifdef HAVE_ADJUSTABLE_CPU_VOLTAGE
375 /* Decreasing frequency so reduce voltage after change */
376 ascodec_write(AS3514_CVDD_DCDC3
, (AS314_CP_DCDC3_SETTING
| CVDD_1_10
));
377 #endif /* HAVE_ADJUSTABLE_CPU_VOLTAGE */
379 cpu_frequency
= CPUFREQ_NORMAL
;
382 #endif /* HAVE_ADJUSTABLE_CPU_FREQ */
383 #endif /* !BOOTLOADER */