firmware/system.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2002 by Alan Korr
  11  *
  12  * All files in this archive are subject to the GNU General Public License.
  13  * See the file COPYING in the source tree root for full license agreement.
  14  *
  15  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  16  * KIND, either express or implied.
  17  *
  18  ****************************************************************************/
  19 #include <stdio.h>
  20 #include "config.h"
  21 #include <stdbool.h>
  22
  23 #if CONFIG_CPU == MCF5249
  24
  25 #define default_interrupt(name) \
  26   extern __attribute__((weak,alias("UIE"))) void name (void);
  27
  28 static const char* const irqname[] = {
  29     "", "", "AccessErr","AddrErr","IllInstr", "", "","",
  30     "PrivVio","Trace","Line-A", "Line-F","Debug","","FormErr","Uninit",
  31     "","","","","","","","",
  32     "Spurious","Level1","Level2","Level3","Level4","Level5","Level6","Level7",
  33     "Trap0","Trap1","Trap2","Trap3","Trap4","Trap5","Trap6","Trap7",
  34     "Trap8","Trap9","Trap10","Trap11","Trap12","Trap13","Trap14","Trap15",
  35     "SWT","Timer0","Timer1","I2C","UART1","UART2","DMA0","DMA1",
  36     "DMA2","DMA3","QSPI","","","","","",
  37     "PDIR1FULL","PDIR2FULL","EBUTXEMPTY","IIS2TXEMPTY",
  38     "IIS1TXEMPTY","PDIR3FULL","PDIR3RESYN","UQ2CHANERR",
  39     "AUDIOTICK","PDIR2RESYN","PDIR2UNOV","PDIR1RESYN",
  40     "PDIR1UNOV","UQ1CHANERR","IEC2BUFATTEN","IEC2PARERR",
  41     "IEC2VALNOGOOD","IEC2CNEW","IEC1BUFATTEN","UCHANTXNF",
  42     "UCHANTXUNDER","UCHANTXEMPTY","PDIR3UNOV","IEC1PARERR",
  43     "IEC1VALNOGOOD","IEC1CNEW","EBUTXRESYN","EBUTXUNOV",
  44     "IIS2TXRESYN","IIS2TXUNOV","IIS1TXRESYN","IIS1TXUNOV",
  45     "GPIO0","GPI1","GPI2","GPI3","GPI4","GPI5","GPI6","GPI7",
  46     "","","","","","","","SOFTINT0",
  47     "SOFTINT1","SOFTINT2","SOFTINT3","",
  48     "","CDROMCRCERR","CDROMNOSYNC","CDROMILSYNC",
  49     "CDROMNEWBLK","","","","","","","",
  50     "","","","","","","","",
  51     "","","","","","","","",
  52     "","","","","","","","",
  53     "","","","","","","","",
  54     "","","","","","","","",
  55     "","","","","","","","",
  56     "","","","","","","","",
  57     "","","","","","","",""
  58 };
  59
  60 default_interrupt (TRAP0); /* Trap #0 */
  61 default_interrupt (TRAP1); /* Trap #1 */
  62 default_interrupt (TRAP2); /* Trap #2 */
  63 default_interrupt (TRAP3); /* Trap #3 */
  64 default_interrupt (TRAP4); /* Trap #4 */
  65 default_interrupt (TRAP5); /* Trap #5 */
  66 default_interrupt (TRAP6); /* Trap #6 */
  67 default_interrupt (TRAP7); /* Trap #7 */
  68 default_interrupt (TRAP8); /* Trap #8 */
  69 default_interrupt (TRAP9); /* Trap #9 */
  70 default_interrupt (TRAP10); /* Trap #10 */
  71 default_interrupt (TRAP11); /* Trap #11 */
  72 default_interrupt (TRAP12); /* Trap #12 */
  73 default_interrupt (TRAP13); /* Trap #13 */
  74 default_interrupt (TRAP14); /* Trap #14 */
  75 default_interrupt (TRAP15); /* Trap #15 */
  76 default_interrupt (SWT); /* Software Watchdog Timer */
  77 default_interrupt (TIMER0); /* Timer 0 */
  78 default_interrupt (TIMER1); /* Timer 1 */
  79 default_interrupt (I2C); /* I2C */
  80 default_interrupt (UART1); /* UART 1 */
  81 default_interrupt (UART2); /* UART 2 */
  82 default_interrupt (DMA0); /* DMA 0 */
  83 default_interrupt (DMA1); /* DMA 1 */
  84 default_interrupt (DMA2); /* DMA 2 */
  85 default_interrupt (DMA3); /* DMA 3 */
  86 default_interrupt (QSPI); /* QSPI */
  87
  88 default_interrupt (PDIR1FULL); /* Processor data in 1 full */
  89 default_interrupt (PDIR2FULL); /* Processor data in 2 full */
  90 default_interrupt (EBUTXEMPTY); /* EBU transmit FIFO empty */
  91 default_interrupt (IIS2TXEMPTY); /* IIS2 transmit FIFO empty */
  92 default_interrupt (IIS1TXEMPTY); /* IIS1 transmit FIFO empty */
  93 default_interrupt (PDIR3FULL); /* Processor data in 3 full */
  94 default_interrupt (PDIR3RESYN); /* Processor data in 3 resync */
  95 default_interrupt (UQ2CHANERR); /* IEC958-2 Rx U/Q channel error */
  96 default_interrupt (AUDIOTICK); /* "tick" interrupt */
  97 default_interrupt (PDIR2RESYN); /* Processor data in 2 resync */
  98 default_interrupt (PDIR2UNOV); /* Processor data in 2 under/overrun */
  99 default_interrupt (PDIR1RESYN); /* Processor data in 1 resync */
 100 default_interrupt (PDIR1UNOV); /* Processor data in 1 under/overrun */
 101 default_interrupt (UQ1CHANERR); /* IEC958-1 Rx U/Q channel error */
 102 default_interrupt (IEC2BUFATTEN);/* IEC958-2 channel buffer full */
 103 default_interrupt (IEC2PARERR); /* IEC958-2 Rx parity or symbol error */
 104 default_interrupt (IEC2VALNOGOOD);/* IEC958-2 flag not good */
 105 default_interrupt (IEC2CNEW); /* IEC958-2 New C-channel received */
 106 default_interrupt (IEC1BUFATTEN);/* IEC958-1 channel buffer full */
 107 default_interrupt (UCHANTXNF); /* U channel Tx reg next byte is first */
 108 default_interrupt (UCHANTXUNDER);/* U channel Tx reg underrun */
 109 default_interrupt (UCHANTXEMPTY);/* U channel Tx reg is empty */
 110 default_interrupt (PDIR3UNOV); /* Processor data in 3 under/overrun */
 111 default_interrupt (IEC1PARERR); /* IEC958-1 Rx parity or symbol error */
 112 default_interrupt (IEC1VALNOGOOD);/* IEC958-1 flag not good */
 113 default_interrupt (IEC1CNEW); /* IEC958-1 New C-channel received */
 114 default_interrupt (EBUTXRESYN); /* EBU Tx FIFO resync */
 115 default_interrupt (EBUTXUNOV); /* EBU Tx FIFO under/overrun */
 116 default_interrupt (IIS2TXRESYN); /* IIS2 Tx FIFO resync */
 117 default_interrupt (IIS2TXUNOV); /* IIS2 Tx FIFO under/overrun */
 118 default_interrupt (IIS1TXRESYN); /* IIS1 Tx FIFO resync */
 119 default_interrupt (IIS1TXUNOV); /* IIS1 Tx FIFO under/overrun */
 120 default_interrupt (GPI0); /* GPIO interrupt 0 */
 121 default_interrupt (GPI1); /* GPIO interrupt 1 */
 122 default_interrupt (GPI2); /* GPIO interrupt 2 */
 123 default_interrupt (GPI3); /* GPIO interrupt 3 */
 124 default_interrupt (GPI4); /* GPIO interrupt 4 */
 125 default_interrupt (GPI5); /* GPIO interrupt 5 */
 126 default_interrupt (GPI6); /* GPIO interrupt 6 */
 127 default_interrupt (GPI7); /* GPIO interrupt 7 */
 128
 129 default_interrupt (SOFTINT0); /* Software interrupt 0 */
 130 default_interrupt (SOFTINT1); /* Software interrupt 1 */
 131 default_interrupt (SOFTINT2); /* Software interrupt 2 */
 132 default_interrupt (SOFTINT3); /* Software interrupt 3 */
 133
 134 default_interrupt (CDROMCRCERR); /* CD-ROM CRC error */
 135 default_interrupt (CDROMNOSYNC); /* CD-ROM No sync */
 136 default_interrupt (CDROMILSYNC); /* CD-ROM Illegal sync */
 137 default_interrupt (CDROMNEWBLK); /* CD-ROM New block */
 138
 139 void UIE (void) /* Unexpected Interrupt or Exception */
 140 {
 141     unsigned int format_vector, pc;
 142     int vector;
 143
 144     asm volatile ("move.l (0,%%sp),%0": "=r"(format_vector));
 145     asm volatile ("move.l (4,%%sp),%0": "=r"(pc));
 146
 147     vector = (format_vector >> 16) & 0xff;
 148
 149     while (1)
 150     {
 151     }
 152 }
 153
 154 /* reset vectors are handled in crt0.S */
 155 void (* const vbr[]) (void) __attribute__ ((section (".vectors"))) =
 156 {
 157     UIE,UIE,UIE,UIE,UIE,UIE,
 158     UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
 159     UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
 160     UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
 161
 162     TRAP0,TRAP1,TRAP2,TRAP3,TRAP4,TRAP5,TRAP6,TRAP7,
 163     TRAP8,TRAP9,TRAP10,TRAP11,TRAP12,TRAP13,TRAP14,TRAP15,
 164
 165     SWT,TIMER0,TIMER1,I2C,UART1,UART2,DMA0,DMA1,
 166     DMA2,DMA3,QSPI,UIE,UIE,UIE,UIE,UIE,
 167     PDIR1FULL,PDIR2FULL,EBUTXEMPTY,IIS2TXEMPTY,
 168     IIS1TXEMPTY,PDIR3FULL,PDIR3RESYN,UQ2CHANERR,
 169     AUDIOTICK,PDIR2RESYN,PDIR2UNOV,PDIR1RESYN,
 170     PDIR1UNOV,UQ1CHANERR,IEC2BUFATTEN,IEC2PARERR,
 171     IEC2VALNOGOOD,IEC2CNEW,IEC1BUFATTEN,UCHANTXNF,
 172     UCHANTXUNDER,UCHANTXEMPTY,PDIR3UNOV,IEC1PARERR,
 173     IEC1VALNOGOOD,IEC1CNEW,EBUTXRESYN,EBUTXUNOV,
 174     IIS2TXRESYN,IIS2TXUNOV,IIS1TXRESYN,IIS1TXUNOV,
 175     GPI0,GPI1,GPI2,GPI3,GPI4,GPI5,GPI6,GPI7,
 176     UIE,UIE,UIE,UIE,UIE,UIE,UIE,SOFTINT0,
 177     SOFTINT1,SOFTINT2,SOFTINT3,UIE,
 178     UIE,CDROMCRCERR,CDROMNOSYNC,CDROMILSYNC,
 179     CDROMNEWBLK,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
 180
 181     UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
 182     UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
 183     UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
 184     UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
 185     UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
 186     UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
 187     UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,
 188     UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE,UIE
 189 };
 190
 191 void system_init(void)
 192 {
 193 }
 194
 195 #elif CONFIG_CPU == SH7034
 196 #include "lcd.h"
 197 #include "font.h"
 198 #include "led.h"
 199 #include "system.h"
 200 #include "rolo.h"
 201
 202 #define default_interrupt(name,number) \
 203   extern __attribute__((weak,alias("UIE" #number))) void name (void); void UIE##number (void)
 204 #define reserve_interrupt(number) \
 205   void UIE##number (void)
 206
 207 static const char* const irqname[] = {
 208     "", "", "", "", "IllInstr", "", "IllSltIn","","",
 209     "CPUAdrEr", "DMAAdrEr", "NMI", "UserBrk",
 210     "","","","","","","","","","","","","","","","","","","",
 211     "Trap32","Trap33","Trap34","Trap35","Trap36","Trap37","Trap38","Trap39",
 212     "Trap40","Trap41","Trap42","Trap43","Trap44","Trap45","Trap46","Trap47",
 213     "Trap48","Trap49","Trap50","Trap51","Trap52","Trap53","Trap54","Trap55",
 214     "Trap56","Trap57","Trap58","Trap59","Trap60","Trap61","Trap62","Trap63",
 215     "Irq0","Irq1","Irq2","Irq3","Irq4","Irq5","Irq6","Irq7",
 216     "Dma0","","Dma1","","Dma2","","Dma3","",
 217     "IMIA0","IMIB0","OVI0","", "IMIA1","IMIB1","OVI1","",
 218     "IMIA2","IMIB2","OVI2","", "IMIA3","IMIB3","OVI3","",
 219     "IMIA4","IMIB4","OVI4","",
 220     "Ser0Err","Ser0Rx","Ser0Tx","Ser0TE",
 221     "Ser1Err","Ser1Rx","Ser1Tx","Ser1TE",
 222     "ParityEr","A/D conv","","","Watchdog","DRAMRefr"
 223 };
 224
 225 reserve_interrupt (          0);
 226 reserve_interrupt (          1);
 227 reserve_interrupt (          2);
 228 reserve_interrupt (          3);
 229 default_interrupt (GII,      4);
 230 reserve_interrupt (          5);
 231 default_interrupt (ISI,      6);
 232 reserve_interrupt (          7);
 233 reserve_interrupt (          8);
 234 default_interrupt (CPUAE,    9);
 235 default_interrupt (DMAAE,   10);
 236 default_interrupt (NMI,     11);
 237 default_interrupt (UB,      12);
 238 reserve_interrupt (         13);
 239 reserve_interrupt (         14);
 240 reserve_interrupt (         15);
 241 reserve_interrupt (         16); /* TCB #0 */
 242 reserve_interrupt (         17); /* TCB #1 */
 243 reserve_interrupt (         18); /* TCB #2 */
 244 reserve_interrupt (         19); /* TCB #3 */
 245 reserve_interrupt (         20); /* TCB #4 */
 246 reserve_interrupt (         21); /* TCB #5 */
 247 reserve_interrupt (         22); /* TCB #6 */
 248 reserve_interrupt (         23); /* TCB #7 */
 249 reserve_interrupt (         24); /* TCB #8 */
 250 reserve_interrupt (         25); /* TCB #9 */
 251 reserve_interrupt (         26); /* TCB #10 */
 252 reserve_interrupt (         27); /* TCB #11 */
 253 reserve_interrupt (         28); /* TCB #12 */
 254 reserve_interrupt (         29); /* TCB #13 */
 255 reserve_interrupt (         30); /* TCB #14 */
 256 reserve_interrupt (         31); /* TCB #15 */
 257 default_interrupt (TRAPA32, 32);
 258 default_interrupt (TRAPA33, 33);
 259 default_interrupt (TRAPA34, 34);
 260 default_interrupt (TRAPA35, 35);
 261 default_interrupt (TRAPA36, 36);
 262 default_interrupt (TRAPA37, 37);
 263 default_interrupt (TRAPA38, 38);
 264 default_interrupt (TRAPA39, 39);
 265 default_interrupt (TRAPA40, 40);
 266 default_interrupt (TRAPA41, 41);
 267 default_interrupt (TRAPA42, 42);
 268 default_interrupt (TRAPA43, 43);
 269 default_interrupt (TRAPA44, 44);
 270 default_interrupt (TRAPA45, 45);
 271 default_interrupt (TRAPA46, 46);
 272 default_interrupt (TRAPA47, 47);
 273 default_interrupt (TRAPA48, 48);
 274 default_interrupt (TRAPA49, 49);
 275 default_interrupt (TRAPA50, 50);
 276 default_interrupt (TRAPA51, 51);
 277 default_interrupt (TRAPA52, 52);
 278 default_interrupt (TRAPA53, 53);
 279 default_interrupt (TRAPA54, 54);
 280 default_interrupt (TRAPA55, 55);
 281 default_interrupt (TRAPA56, 56);
 282 default_interrupt (TRAPA57, 57);
 283 default_interrupt (TRAPA58, 58);
 284 default_interrupt (TRAPA59, 59);
 285 default_interrupt (TRAPA60, 60);
 286 default_interrupt (TRAPA61, 61);
 287 default_interrupt (TRAPA62, 62);
 288 default_interrupt (TRAPA63, 63);
 289 default_interrupt (IRQ0,    64);
 290 default_interrupt (IRQ1,    65);
 291 default_interrupt (IRQ2,    66);
 292 default_interrupt (IRQ3,    67);
 293 default_interrupt (IRQ4,    68);
 294 default_interrupt (IRQ5,    69);
 295 default_interrupt (IRQ6,    70);
 296 default_interrupt (IRQ7,    71);
 297 default_interrupt (DEI0,    72);
 298 reserve_interrupt (         73);
 299 default_interrupt (DEI1,    74);
 300 reserve_interrupt (         75);
 301 default_interrupt (DEI2,    76);
 302 reserve_interrupt (         77);
 303 default_interrupt (DEI3,    78);
 304 reserve_interrupt (         79);
 305 default_interrupt (IMIA0,   80);
 306 default_interrupt (IMIB0,   81);
 307 default_interrupt (OVI0,    82);
 308 reserve_interrupt (         83);
 309 default_interrupt (IMIA1,   84);
 310 default_interrupt (IMIB1,   85);
 311 default_interrupt (OVI1,    86);
 312 reserve_interrupt (         87);
 313 default_interrupt (IMIA2,   88);
 314 default_interrupt (IMIB2,   89);
 315 default_interrupt (OVI2,    90);
 316 reserve_interrupt (         91);
 317 default_interrupt (IMIA3,   92);
 318 default_interrupt (IMIB3,   93);
 319 default_interrupt (OVI3,    94);
 320 reserve_interrupt (         95);
 321 default_interrupt (IMIA4,   96);
 322 default_interrupt (IMIB4,   97);
 323 default_interrupt (OVI4,    98);
 324 reserve_interrupt (         99);
 325 default_interrupt (REI0,   100);
 326 default_interrupt (RXI0,   101);
 327 default_interrupt (TXI0,   102);
 328 default_interrupt (TEI0,   103);
 329 default_interrupt (REI1,   104);
 330 default_interrupt (RXI1,   105);
 331 default_interrupt (TXI1,   106);
 332 default_interrupt (TEI1,   107);
 333 reserve_interrupt (        108);
 334 default_interrupt (ADITI,  109);
 335
 336 /* reset vectors are handled in crt0.S */
 337 void (*vbr[]) (void) __attribute__ ((section (".vectors"))) =
 338 {
 339     /*** 4 General Illegal Instruction ***/
 340
 341     GII,
 342
 343     /*** 5 Reserved ***/
 344
 345     UIE5,
 346
 347     /*** 6 Illegal Slot Instruction ***/
 348
 349     ISI,
 350
 351     /*** 7-8 Reserved ***/
 352
 353     UIE7,UIE8,
 354
 355     /*** 9 CPU Address Error ***/
 356
 357     CPUAE,
 358
 359     /*** 10 DMA Address Error ***/
 360
 361     DMAAE,
 362
 363     /*** 11 NMI ***/
 364
 365     NMI,
 366
 367     /*** 12 User Break ***/
 368
 369     UB,
 370
 371     /*** 13-31 Reserved ***/
 372
 373     UIE13,UIE14,UIE15,UIE16,UIE17,UIE18,UIE19,UIE20,UIE21,UIE22,UIE23,UIE24,UIE25,UIE26,UIE27,UIE28,UIE29,UIE30,UIE31,
 374
 375     /*** 32-63 TRAPA #20...#3F ***/
 376
 377     TRAPA32,TRAPA33,TRAPA34,TRAPA35,TRAPA36,TRAPA37,TRAPA38,TRAPA39,TRAPA40,TRAPA41,TRAPA42,TRAPA43,TRAPA44,TRAPA45,TRAPA46,TRAPA47,TRAPA48,TRAPA49,TRAPA50,TRAPA51,TRAPA52,TRAPA53,TRAPA54,TRAPA55,TRAPA56,TRAPA57,TRAPA58,TRAPA59,TRAPA60,TRAPA61,TRAPA62,TRAPA63,
 378
 379     /*** 64-71 IRQ0-7 ***/
 380
 381     IRQ0,IRQ1,IRQ2,IRQ3,IRQ4,IRQ5,IRQ6,IRQ7,
 382
 383     /*** 72 DMAC0 ***/
 384
 385     DEI0,
 386
 387     /*** 73 Reserved ***/
 388
 389     UIE73,
 390
 391     /*** 74 DMAC1 ***/
 392
 393     DEI1,
 394
 395     /*** 75 Reserved ***/
 396
 397     UIE75,
 398
 399     /*** 76 DMAC2 ***/
 400
 401     DEI2,
 402
 403     /*** 77 Reserved ***/
 404
 405     UIE77,
 406
 407     /*** 78 DMAC3 ***/
 408
 409     DEI3,
 410
 411     /*** 79 Reserved ***/
 412
 413     UIE79,
 414
 415     /*** 80-82 ITU0 ***/
 416
 417     IMIA0,IMIB0,OVI0,
 418
 419     /*** 83 Reserved ***/
 420
 421     UIE83,
 422
 423     /*** 84-86 ITU1 ***/
 424
 425     IMIA1,IMIB1,OVI1,
 426
 427     /*** 87 Reserved ***/
 428
 429     UIE87,
 430
 431     /*** 88-90 ITU2 ***/
 432
 433     IMIA2,IMIB2,OVI2,
 434
 435     /*** 91 Reserved ***/
 436
 437     UIE91,
 438
 439     /*** 92-94 ITU3 ***/
 440
 441     IMIA3,IMIB3,OVI3,
 442
 443     /*** 95 Reserved ***/
 444
 445     UIE95,
 446
 447     /*** 96-98 ITU4 ***/
 448
 449     IMIA4,IMIB4,OVI4,
 450
 451     /*** 99 Reserved ***/
 452
 453     UIE99,
 454
 455     /*** 100-103 SCI0 ***/
 456
 457     REI0,RXI0,TXI0,TEI0,
 458
 459     /*** 104-107 SCI1 ***/
 460
 461     REI1,RXI1,TXI1,TEI1,
 462
 463     /*** 108 Parity Control Unit ***/
 464
 465     UIE108,
 466
 467     /*** 109 AD Converter ***/
 468
 469     ADITI
 470
 471 };
 472
 473
 474 void system_reboot (void)
 475 {
 476     set_irq_level(HIGHEST_IRQ_LEVEL);
 477
 478     asm volatile ("ldc\t%0,vbr" : : "r"(0));
 479
 480     PACR2 |= 0x4000; /* for coldstart detection */
 481     IPRA = 0;
 482     IPRB = 0;
 483     IPRC = 0;
 484     IPRD = 0;
 485     IPRE = 0;
 486     ICR = 0;
 487
 488     asm volatile ("jmp @%0; mov.l @%1,r15" : :
 489                   "r"(*(int*)0),"r"(4));
 490 }
 491
 492 void UIE (unsigned int pc) /* Unexpected Interrupt or Exception */
 493 {
 494     bool state = true;
 495     unsigned int n;
 496     char str[32];
 497
 498     asm volatile ("sts\tpr,%0" : "=r"(n));
 499
 500     /* clear screen */
 501     lcd_clear_display ();
 502 #ifdef HAVE_LCD_BITMAP
 503     lcd_setfont(FONT_SYSFIXED);
 504 #endif
 505     /* output exception */
 506     n = (n - (unsigned)UIE0 - 4)>>2; /* get exception or interrupt number */
 507     snprintf(str,sizeof(str),"I%02x:%s",n,irqname[n]);
 508     lcd_puts(0,0,str);
 509     snprintf(str,sizeof(str),"at %08x",pc);
 510     lcd_puts(0,1,str);
 511
 512 #ifdef HAVE_LCD_BITMAP
 513     lcd_update ();
 514 #endif
 515
 516     while (1)
 517     {
 518         volatile int i;
 519         led (state);
 520         state = state?false:true;
 521
 522         for (i = 0; i < 240000; ++i);
 523
 524         /* try to restart firmware if ON is pressed */
 525 #ifdef HAVE_LCD_CHARCELLS
 526         if (!(PADR & 0x20))
 527             rolo_load("/archos.mod");
 528 #else
 529         if (!(PBDR & PBDR_BTN_ON))
 530             rolo_load("/ajbrec.ajz");
 531 #endif
 532     }
 533 }
 534
 535 asm (
 536     "_UIE0:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 537     "_UIE1:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 538     "_UIE2:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 539     "_UIE3:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 540     "_UIE4:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 541     "_UIE5:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 542     "_UIE6:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 543     "_UIE7:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 544     "_UIE8:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 545     "_UIE9:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 546     "_UIE10:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 547     "_UIE11:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 548     "_UIE12:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 549     "_UIE13:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 550     "_UIE14:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 551     "_UIE15:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 552     "_UIE16:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 553     "_UIE17:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 554     "_UIE18:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 555     "_UIE19:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 556     "_UIE20:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 557     "_UIE21:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 558     "_UIE22:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 559     "_UIE23:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 560     "_UIE24:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 561     "_UIE25:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 562     "_UIE26:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 563     "_UIE27:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 564     "_UIE28:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 565     "_UIE29:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 566     "_UIE30:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 567     "_UIE31:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 568     "_UIE32:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 569     "_UIE33:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 570     "_UIE34:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 571     "_UIE35:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 572     "_UIE36:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 573     "_UIE37:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 574     "_UIE38:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 575     "_UIE39:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 576     "_UIE40:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 577     "_UIE41:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 578     "_UIE42:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 579     "_UIE43:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 580     "_UIE44:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 581     "_UIE45:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 582     "_UIE46:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 583     "_UIE47:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 584     "_UIE48:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 585     "_UIE49:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 586     "_UIE50:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 587     "_UIE51:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 588     "_UIE52:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 589     "_UIE53:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 590     "_UIE54:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 591     "_UIE55:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 592     "_UIE56:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 593     "_UIE57:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 594     "_UIE58:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 595     "_UIE59:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 596     "_UIE60:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 597     "_UIE61:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 598     "_UIE62:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 599     "_UIE63:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 600     "_UIE64:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 601     "_UIE65:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 602     "_UIE66:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 603     "_UIE67:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 604     "_UIE68:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 605     "_UIE69:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 606     "_UIE70:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 607     "_UIE71:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 608     "_UIE72:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 609     "_UIE73:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 610     "_UIE74:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 611     "_UIE75:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 612     "_UIE76:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 613     "_UIE77:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 614     "_UIE78:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 615     "_UIE79:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 616     "_UIE80:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 617     "_UIE81:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 618     "_UIE82:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 619     "_UIE83:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 620     "_UIE84:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 621     "_UIE85:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 622     "_UIE86:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 623     "_UIE87:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 624     "_UIE88:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 625     "_UIE89:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 626     "_UIE90:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 627     "_UIE91:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 628     "_UIE92:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 629     "_UIE93:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 630     "_UIE94:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 631     "_UIE95:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 632     "_UIE96:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 633     "_UIE97:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 634     "_UIE98:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 635     "_UIE99:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 636     "_UIE100:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 637     "_UIE101:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 638     "_UIE102:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 639     "_UIE103:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 640     "_UIE104:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 641     "_UIE105:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 642     "_UIE106:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 643     "_UIE107:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 644     "_UIE108:\tbsr\t_UIE\n\tmov.l\t@r15+,r4\t\n"
 645     "_UIE109:\tbsr\t_UIE\n\tmov.l\t@r15+,r4");
 646
 647 void system_init(void)
 648 {
 649     /* Disable all interrupts */
 650     IPRA = 0;
 651     IPRB = 0;
 652     IPRC = 0;
 653     IPRD = 0;
 654     IPRE = 0;
 655
 656     /* NMI level low, falling edge on all interrupts */
 657     ICR = 0;
 658
 659     /* Enable burst and RAS down mode on DRAM */
 660     DCR |= 0x5000;
 661
 662     /* Activate Warp mode (simultaneous internal and external mem access) */
 663     BCR |= 0x2000;
 664
 665     /* Bus state controller initializations. These are only necessary when
 666        running from flash. */
 667     WCR1 = 0x40FD; /* Long wait states for CS6 (ATA), short for the rest. */
 668     WCR3 = 0x8000; /* WAIT is pulled up, 1 state inserted for CS6 */
 669 }
 670
 671 /* Utilize the user break controller to catch invalid memory accesses. */
 672 int system_memory_guard(int newmode)
 673 {
 674     static const struct {
 675         unsigned long  addr;
 676         unsigned long  mask;
 677         unsigned short bbr;
 678     } modes[MAXMEMGUARD] = {
 679         /* catch nothing */
 680         { 0x00000000, 0x00000000, 0x0000 },
 681         /* catch writes to area 02 (flash ROM) */
 682         { 0x02000000, 0x00FFFFFF, 0x00F8 },
 683         /* catch all accesses to areas 00 (internal ROM) and 01 (free) */
 684         { 0x00000000, 0x01FFFFFF, 0x00FC }
 685     };
 686
 687     int oldmode = MEMGUARD_NONE;
 688     int i;
 689
 690     /* figure out the old mode from what is in the UBC regs. If the register
 691        values don't match any mode, assume MEMGUARD_NONE */
 692     for (i = MEMGUARD_NONE; i < MAXMEMGUARD; i++)
 693     {
 694         if (BAR == modes[i].addr && BAMR == modes[i].mask &&
 695             BBR == modes[i].bbr)
 696         {
 697             oldmode = i;
 698             break;
 699         }
 700     }
 701
 702     if (newmode == MEMGUARD_KEEP)
 703         newmode = oldmode;
 704
 705     BBR = 0;  /* switch off everything first */
 706
 707     /* always set the UBC according to the mode, in case the old settings
 708        didn't match any valid mode */
 709     BAR  = modes[newmode].addr;
 710     BAMR = modes[newmode].mask;
 711     BBR  = modes[newmode].bbr;
 712
 713     return oldmode;
 714 }
 715 #endif