firmware/export/usb-s3c6400x.h

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2009 Michael Sparmann
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21 #ifndef USB_S3C6400X_H
  22 #define USB_S3C6400X_H
  23
  24
  25
  26
  27 /*** OTG PHY CONTROL REGISTERS ***/
  28 #define OPHYPWR     (*((uint32_t volatile*)(PHYBASE + 0x000)))
  29 #define OPHYCLK     (*((uint32_t volatile*)(PHYBASE + 0x004)))
  30 #define ORSTCON     (*((uint32_t volatile*)(PHYBASE + 0x008)))
  31 #define OPHYUNK3    (*((uint32_t volatile*)(PHYBASE + 0x018)))
  32 #define OPHYUNK1    (*((uint32_t volatile*)(PHYBASE + 0x01c)))
  33 #define OPHYUNK2    (*((uint32_t volatile*)(PHYBASE + 0x044)))
  34
  35 /*** OTG LINK CORE REGISTERS ***/
  36 /* Core Global Registers */
  37 #define GOTGCTL     (*((uint32_t volatile*)(OTGBASE + 0x000)))
  38 #define GOTGINT     (*((uint32_t volatile*)(OTGBASE + 0x004)))
  39 #define GAHBCFG     (*((uint32_t volatile*)(OTGBASE + 0x008)))
  40 #define GUSBCFG     (*((uint32_t volatile*)(OTGBASE + 0x00C)))
  41 #define GRSTCTL     (*((uint32_t volatile*)(OTGBASE + 0x010)))
  42 #define GINTSTS     (*((uint32_t volatile*)(OTGBASE + 0x014)))
  43 #define GINTMSK     (*((uint32_t volatile*)(OTGBASE + 0x018)))
  44 #define GRXSTSR     (*((uint32_t volatile*)(OTGBASE + 0x01C)))
  45 #define GRXSTSP     (*((uint32_t volatile*)(OTGBASE + 0x020)))
  46 #define GRXFSIZ     (*((uint32_t volatile*)(OTGBASE + 0x024)))
  47 #define GNPTXFSIZ   (*((uint32_t volatile*)(OTGBASE + 0x028)))
  48 #define GNPTXSTS    (*((uint32_t volatile*)(OTGBASE + 0x02C)))
  49 #define HPTXFSIZ    (*((uint32_t volatile*)(OTGBASE + 0x100)))
  50 #define DPTXFSIZ(x) (*((uint32_t volatile*)(OTGBASE + 0x100 + 4 * (x))))
  51 #define DPTXFSIZ1   (*((uint32_t volatile*)(OTGBASE + 0x104)))
  52 #define DPTXFSIZ2   (*((uint32_t volatile*)(OTGBASE + 0x108)))
  53 #define DPTXFSIZ3   (*((uint32_t volatile*)(OTGBASE + 0x10C)))
  54 #define DPTXFSIZ4   (*((uint32_t volatile*)(OTGBASE + 0x110)))
  55 #define DPTXFSIZ5   (*((uint32_t volatile*)(OTGBASE + 0x114)))
  56 #define DPTXFSIZ6   (*((uint32_t volatile*)(OTGBASE + 0x118)))
  57 #define DPTXFSIZ7   (*((uint32_t volatile*)(OTGBASE + 0x11C)))
  58 #define DPTXFSIZ8   (*((uint32_t volatile*)(OTGBASE + 0x120)))
  59 #define DPTXFSIZ9   (*((uint32_t volatile*)(OTGBASE + 0x124)))
  60 #define DPTXFSIZ10  (*((uint32_t volatile*)(OTGBASE + 0x128)))
  61 #define DPTXFSIZ11  (*((uint32_t volatile*)(OTGBASE + 0x12C)))
  62 #define DPTXFSIZ12  (*((uint32_t volatile*)(OTGBASE + 0x130)))
  63 #define DPTXFSIZ13  (*((uint32_t volatile*)(OTGBASE + 0x134)))
  64 #define DPTXFSIZ14  (*((uint32_t volatile*)(OTGBASE + 0x138)))
  65 #define DPTXFSIZ15  (*((uint32_t volatile*)(OTGBASE + 0x13C)))
  66
  67 /*** HOST MODE REGISTERS ***/
  68 /* Host Global Registers */
  69 #define HCFG        (*((uint32_t volatile*)(OTGBASE + 0x400)))
  70 #define HFIR        (*((uint32_t volatile*)(OTGBASE + 0x404)))
  71 #define HFNUM       (*((uint32_t volatile*)(OTGBASE + 0x408)))
  72 #define HPTXSTS     (*((uint32_t volatile*)(OTGBASE + 0x410)))
  73 #define HAINT       (*((uint32_t volatile*)(OTGBASE + 0x414)))
  74 #define HAINTMSK    (*((uint32_t volatile*)(OTGBASE + 0x418)))
  75
  76 /* Host Port Control and Status Registers */
  77 #define HPRT        (*((uint32_t volatile*)(OTGBASE + 0x440)))
  78
  79 /* Host Channel-Specific Registers */
  80 #define HCCHAR(x)   (*((uint32_t volatile*)(OTGBASE + 0x500 + 0x20 * (x))))
  81 #define HCSPLT(x)   (*((uint32_t volatile*)(OTGBASE + 0x504 + 0x20 * (x))))
  82 #define HCINT(x)    (*((uint32_t volatile*)(OTGBASE + 0x508 + 0x20 * (x))))
  83 #define HCINTMSK(x) (*((uint32_t volatile*)(OTGBASE + 0x50C + 0x20 * (x))))
  84 #define HCTSIZ(x)   (*((uint32_t volatile*)(OTGBASE + 0x510 + 0x20 * (x))))
  85 #define HCDMA(x)    (*((uint32_t volatile*)(OTGBASE + 0x514 + 0x20 * (x))))
  86 #define HCCHAR0     (*((uint32_t volatile*)(OTGBASE + 0x500)))
  87 #define HCSPLT0     (*((uint32_t volatile*)(OTGBASE + 0x504)))
  88 #define HCINT0      (*((uint32_t volatile*)(OTGBASE + 0x508)))
  89 #define HCINTMSK0   (*((uint32_t volatile*)(OTGBASE + 0x50C)))
  90 #define HCTSIZ0     (*((uint32_t volatile*)(OTGBASE + 0x510)))
  91 #define HCDMA0      (*((uint32_t volatile*)(OTGBASE + 0x514)))
  92 #define HCCHAR1     (*((uint32_t volatile*)(OTGBASE + 0x520)))
  93 #define HCSPLT1     (*((uint32_t volatile*)(OTGBASE + 0x524)))
  94 #define HCINT1      (*((uint32_t volatile*)(OTGBASE + 0x528)))
  95 #define HCINTMSK1   (*((uint32_t volatile*)(OTGBASE + 0x52C)))
  96 #define HCTSIZ1     (*((uint32_t volatile*)(OTGBASE + 0x530)))
  97 #define HCDMA1      (*((uint32_t volatile*)(OTGBASE + 0x534)))
  98 #define HCCHAR2     (*((uint32_t volatile*)(OTGBASE + 0x540)))
  99 #define HCSPLT2     (*((uint32_t volatile*)(OTGBASE + 0x544)))
 100 #define HCINT2      (*((uint32_t volatile*)(OTGBASE + 0x548)))
 101 #define HCINTMSK2   (*((uint32_t volatile*)(OTGBASE + 0x54C)))
 102 #define HCTSIZ2     (*((uint32_t volatile*)(OTGBASE + 0x550)))
 103 #define HCDMA2      (*((uint32_t volatile*)(OTGBASE + 0x554)))
 104 #define HCCHAR3     (*((uint32_t volatile*)(OTGBASE + 0x560)))
 105 #define HCSPLT3     (*((uint32_t volatile*)(OTGBASE + 0x564)))
 106 #define HCINT3      (*((uint32_t volatile*)(OTGBASE + 0x568)))
 107 #define HCINTMSK3   (*((uint32_t volatile*)(OTGBASE + 0x56C)))
 108 #define HCTSIZ3     (*((uint32_t volatile*)(OTGBASE + 0x570)))
 109 #define HCDMA3      (*((uint32_t volatile*)(OTGBASE + 0x574)))
 110 #define HCCHAR4     (*((uint32_t volatile*)(OTGBASE + 0x580)))
 111 #define HCSPLT4     (*((uint32_t volatile*)(OTGBASE + 0x584)))
 112 #define HCINT4      (*((uint32_t volatile*)(OTGBASE + 0x588)))
 113 #define HCINTMSK4   (*((uint32_t volatile*)(OTGBASE + 0x58C)))
 114 #define HCTSIZ4     (*((uint32_t volatile*)(OTGBASE + 0x590)))
 115 #define HCDMA4      (*((uint32_t volatile*)(OTGBASE + 0x594)))
 116 #define HCCHAR5     (*((uint32_t volatile*)(OTGBASE + 0x5A0)))
 117 #define HCSPLT5     (*((uint32_t volatile*)(OTGBASE + 0x5A4)))
 118 #define HCINT5      (*((uint32_t volatile*)(OTGBASE + 0x5A8)))
 119 #define HCINTMSK5   (*((uint32_t volatile*)(OTGBASE + 0x5AC)))
 120 #define HCTSIZ5     (*((uint32_t volatile*)(OTGBASE + 0x5B0)))
 121 #define HCDMA5      (*((uint32_t volatile*)(OTGBASE + 0x5B4)))
 122 #define HCCHAR6     (*((uint32_t volatile*)(OTGBASE + 0x5C0)))
 123 #define HCSPLT6     (*((uint32_t volatile*)(OTGBASE + 0x5C4)))
 124 #define HCINT6      (*((uint32_t volatile*)(OTGBASE + 0x5C8)))
 125 #define HCINTMSK6   (*((uint32_t volatile*)(OTGBASE + 0x5CC)))
 126 #define HCTSIZ6     (*((uint32_t volatile*)(OTGBASE + 0x5D0)))
 127 #define HCDMA6      (*((uint32_t volatile*)(OTGBASE + 0x5D4)))
 128 #define HCCHAR7     (*((uint32_t volatile*)(OTGBASE + 0x5E0)))
 129 #define HCSPLT7     (*((uint32_t volatile*)(OTGBASE + 0x5E4)))
 130 #define HCINT7      (*((uint32_t volatile*)(OTGBASE + 0x5E8)))
 131 #define HCINTMSK7   (*((uint32_t volatile*)(OTGBASE + 0x5EC)))
 132 #define HCTSIZ7     (*((uint32_t volatile*)(OTGBASE + 0x5F0)))
 133 #define HCDMA7      (*((uint32_t volatile*)(OTGBASE + 0x5F4)))
 134 #define HCCHAR8     (*((uint32_t volatile*)(OTGBASE + 0x600)))
 135 #define HCSPLT8     (*((uint32_t volatile*)(OTGBASE + 0x604)))
 136 #define HCINT8      (*((uint32_t volatile*)(OTGBASE + 0x608)))
 137 #define HCINTMSK8   (*((uint32_t volatile*)(OTGBASE + 0x60C)))
 138 #define HCTSIZ8     (*((uint32_t volatile*)(OTGBASE + 0x610)))
 139 #define HCDMA8      (*((uint32_t volatile*)(OTGBASE + 0x614)))
 140 #define HCCHAR9     (*((uint32_t volatile*)(OTGBASE + 0x620)))
 141 #define HCSPLT9     (*((uint32_t volatile*)(OTGBASE + 0x624)))
 142 #define HCINT9      (*((uint32_t volatile*)(OTGBASE + 0x628)))
 143 #define HCINTMSK9   (*((uint32_t volatile*)(OTGBASE + 0x62C)))
 144 #define HCTSIZ9     (*((uint32_t volatile*)(OTGBASE + 0x630)))
 145 #define HCDMA9      (*((uint32_t volatile*)(OTGBASE + 0x634)))
 146 #define HCCHAR10    (*((uint32_t volatile*)(OTGBASE + 0x640)))
 147 #define HCSPLT10    (*((uint32_t volatile*)(OTGBASE + 0x644)))
 148 #define HCINT10     (*((uint32_t volatile*)(OTGBASE + 0x648)))
 149 #define HCINTMSK10  (*((uint32_t volatile*)(OTGBASE + 0x64C)))
 150 #define HCTSIZ10    (*((uint32_t volatile*)(OTGBASE + 0x650)))
 151 #define HCDMA10     (*((uint32_t volatile*)(OTGBASE + 0x654)))
 152 #define HCCHAR11    (*((uint32_t volatile*)(OTGBASE + 0x660)))
 153 #define HCSPLT11    (*((uint32_t volatile*)(OTGBASE + 0x664)))
 154 #define HCINT11     (*((uint32_t volatile*)(OTGBASE + 0x668)))
 155 #define HCINTMSK11  (*((uint32_t volatile*)(OTGBASE + 0x66C)))
 156 #define HCTSIZ11    (*((uint32_t volatile*)(OTGBASE + 0x670)))
 157 #define HCDMA11     (*((uint32_t volatile*)(OTGBASE + 0x674)))
 158 #define HCCHAR12    (*((uint32_t volatile*)(OTGBASE + 0x680)))
 159 #define HCSPLT12    (*((uint32_t volatile*)(OTGBASE + 0x684)))
 160 #define HCINT12     (*((uint32_t volatile*)(OTGBASE + 0x688)))
 161 #define HCINTMSK12  (*((uint32_t volatile*)(OTGBASE + 0x68C)))
 162 #define HCTSIZ12    (*((uint32_t volatile*)(OTGBASE + 0x690)))
 163 #define HCDMA12     (*((uint32_t volatile*)(OTGBASE + 0x694)))
 164 #define HCCHAR13    (*((uint32_t volatile*)(OTGBASE + 0x6A0)))
 165 #define HCSPLT13    (*((uint32_t volatile*)(OTGBASE + 0x6A4)))
 166 #define HCINT13     (*((uint32_t volatile*)(OTGBASE + 0x6A8)))
 167 #define HCINTMSK13  (*((uint32_t volatile*)(OTGBASE + 0x6AC)))
 168 #define HCTSIZ13    (*((uint32_t volatile*)(OTGBASE + 0x6B0)))
 169 #define HCDMA13     (*((uint32_t volatile*)(OTGBASE + 0x6B4)))
 170 #define HCCHAR14    (*((uint32_t volatile*)(OTGBASE + 0x6C0)))
 171 #define HCSPLT14    (*((uint32_t volatile*)(OTGBASE + 0x6C4)))
 172 #define HCINT14     (*((uint32_t volatile*)(OTGBASE + 0x6C8)))
 173 #define HCINTMSK14  (*((uint32_t volatile*)(OTGBASE + 0x6CC)))
 174 #define HCTSIZ14    (*((uint32_t volatile*)(OTGBASE + 0x6D0)))
 175 #define HCDMA14     (*((uint32_t volatile*)(OTGBASE + 0x6D4)))
 176 #define HCCHAR15    (*((uint32_t volatile*)(OTGBASE + 0x6E0)))
 177 #define HCSPLT15    (*((uint32_t volatile*)(OTGBASE + 0x6E4)))
 178 #define HCINT15     (*((uint32_t volatile*)(OTGBASE + 0x6E8)))
 179 #define HCINTMSK15  (*((uint32_t volatile*)(OTGBASE + 0x6EC)))
 180 #define HCTSIZ15    (*((uint32_t volatile*)(OTGBASE + 0x6F0)))
 181 #define HCDMA15     (*((uint32_t volatile*)(OTGBASE + 0x6F4)))
 182
 183 /*** DEVICE MODE REGISTERS ***/
 184 /* Device Global Registers */
 185 #define DCFG        (*((uint32_t volatile*)(OTGBASE + 0x800)))
 186 #define DCTL        (*((uint32_t volatile*)(OTGBASE + 0x804)))
 187 #define DSTS        (*((uint32_t volatile*)(OTGBASE + 0x808)))
 188 #define DIEPMSK     (*((uint32_t volatile*)(OTGBASE + 0x810)))
 189 #define DOEPMSK     (*((uint32_t volatile*)(OTGBASE + 0x814)))
 190 #define DAINT       (*((uint32_t volatile*)(OTGBASE + 0x818)))
 191 #define DAINTMSK    (*((uint32_t volatile*)(OTGBASE + 0x81C)))
 192 #define DTKNQR1     (*((uint32_t volatile*)(OTGBASE + 0x820)))
 193 #define DTKNQR2     (*((uint32_t volatile*)(OTGBASE + 0x824)))
 194 #define DVBUSDIS    (*((uint32_t volatile*)(OTGBASE + 0x828)))
 195 #define DVBUSPULSE  (*((uint32_t volatile*)(OTGBASE + 0x82C)))
 196 #define DTKNQR3     (*((uint32_t volatile*)(OTGBASE + 0x830)))
 197 #define DTKNQR4     (*((uint32_t volatile*)(OTGBASE + 0x834)))
 198
 199 /* Device Logical IN Endpoint-Specific Registers */
 200 #define DIEPCTL(x)  (*((uint32_t volatile*)(OTGBASE + 0x900 + 0x20 * (x))))
 201 #define DIEPINT(x)  (*((uint32_t volatile*)(OTGBASE + 0x908 + 0x20 * (x))))
 202 #define DIEPTSIZ(x) (*((uint32_t volatile*)(OTGBASE + 0x910 + 0x20 * (x))))
 203 #define DIEPDMA(x)  (*((const void* volatile*)(OTGBASE + 0x914 + 0x20 * (x))))
 204 #define DIEPCTL0    (*((uint32_t volatile*)(OTGBASE + 0x900)))
 205 #define DIEPINT0    (*((uint32_t volatile*)(OTGBASE + 0x908)))
 206 #define DIEPTSIZ0   (*((uint32_t volatile*)(OTGBASE + 0x910)))
 207 #define DIEPDMA0    (*((const void* volatile*)(OTGBASE + 0x914)))
 208 #define DIEPCTL1    (*((uint32_t volatile*)(OTGBASE + 0x920)))
 209 #define DIEPINT1    (*((uint32_t volatile*)(OTGBASE + 0x928)))
 210 #define DIEPTSIZ1   (*((uint32_t volatile*)(OTGBASE + 0x930)))
 211 #define DIEPDMA1    (*((const void* volatile*)(OTGBASE + 0x934)))
 212 #define DIEPCTL2    (*((uint32_t volatile*)(OTGBASE + 0x940)))
 213 #define DIEPINT2    (*((uint32_t volatile*)(OTGBASE + 0x948)))
 214 #define DIEPTSIZ2   (*((uint32_t volatile*)(OTGBASE + 0x950)))
 215 #define DIEPDMA2    (*((const void* volatile*)(OTGBASE + 0x954)))
 216 #define DIEPCTL3    (*((uint32_t volatile*)(OTGBASE + 0x960)))
 217 #define DIEPINT3    (*((uint32_t volatile*)(OTGBASE + 0x968)))
 218 #define DIEPTSIZ3   (*((uint32_t volatile*)(OTGBASE + 0x970)))
 219 #define DIEPDMA3    (*((const void* volatile*)(OTGBASE + 0x974)))
 220 #define DIEPCTL4    (*((uint32_t volatile*)(OTGBASE + 0x980)))
 221 #define DIEPINT4    (*((uint32_t volatile*)(OTGBASE + 0x988)))
 222 #define DIEPTSIZ4   (*((uint32_t volatile*)(OTGBASE + 0x990)))
 223 #define DIEPDMA4    (*((const void* volatile*)(OTGBASE + 0x994)))
 224 #define DIEPCTL5    (*((uint32_t volatile*)(OTGBASE + 0x9A0)))
 225 #define DIEPINT5    (*((uint32_t volatile*)(OTGBASE + 0x9A8)))
 226 #define DIEPTSIZ5   (*((uint32_t volatile*)(OTGBASE + 0x9B0)))
 227 #define DIEPDMA5    (*((const void* volatile*)(OTGBASE + 0x9B4)))
 228 #define DIEPCTL6    (*((uint32_t volatile*)(OTGBASE + 0x9C0)))
 229 #define DIEPINT6    (*((uint32_t volatile*)(OTGBASE + 0x9C8)))
 230 #define DIEPTSIZ6   (*((uint32_t volatile*)(OTGBASE + 0x9D0)))
 231 #define DIEPDMA6    (*((const void* volatile*)(OTGBASE + 0x9D4)))
 232 #define DIEPCTL7    (*((uint32_t volatile*)(OTGBASE + 0x9E0)))
 233 #define DIEPINT7    (*((uint32_t volatile*)(OTGBASE + 0x9E8)))
 234 #define DIEPTSIZ7   (*((uint32_t volatile*)(OTGBASE + 0x9F0)))
 235 #define DIEPDMA7    (*((const void* volatile*)(OTGBASE + 0x9F4)))
 236 #define DIEPCTL8    (*((uint32_t volatile*)(OTGBASE + 0xA00)))
 237 #define DIEPINT8    (*((uint32_t volatile*)(OTGBASE + 0xA08)))
 238 #define DIEPTSIZ8   (*((uint32_t volatile*)(OTGBASE + 0xA10)))
 239 #define DIEPDMA8    (*((const void* volatile*)(OTGBASE + 0xA14)))
 240 #define DIEPCTL9    (*((uint32_t volatile*)(OTGBASE + 0xA20)))
 241 #define DIEPINT9    (*((uint32_t volatile*)(OTGBASE + 0xA28)))
 242 #define DIEPTSIZ9   (*((uint32_t volatile*)(OTGBASE + 0xA30)))
 243 #define DIEPDMA9    (*((const void* volatile*)(OTGBASE + 0xA34)))
 244 #define DIEPCTL10   (*((uint32_t volatile*)(OTGBASE + 0xA40)))
 245 #define DIEPINT10   (*((uint32_t volatile*)(OTGBASE + 0xA48)))
 246 #define DIEPTSIZ10  (*((uint32_t volatile*)(OTGBASE + 0xA50)))
 247 #define DIEPDMA10   (*((const void* volatile*)(OTGBASE + 0xA54)))
 248 #define DIEPCTL11   (*((uint32_t volatile*)(OTGBASE + 0xA60)))
 249 #define DIEPINT11   (*((uint32_t volatile*)(OTGBASE + 0xA68)))
 250 #define DIEPTSIZ11  (*((uint32_t volatile*)(OTGBASE + 0xA70)))
 251 #define DIEPDMA11   (*((const void* volatile*)(OTGBASE + 0xA74)))
 252 #define DIEPCTL12   (*((uint32_t volatile*)(OTGBASE + 0xA80)))
 253 #define DIEPINT12   (*((uint32_t volatile*)(OTGBASE + 0xA88)))
 254 #define DIEPTSIZ12  (*((uint32_t volatile*)(OTGBASE + 0xA90)))
 255 #define DIEPDMA12   (*((const void* volatile*)(OTGBASE + 0xA94)))
 256 #define DIEPCTL13   (*((uint32_t volatile*)(OTGBASE + 0xAA0)))
 257 #define DIEPINT13   (*((uint32_t volatile*)(OTGBASE + 0xAA8)))
 258 #define DIEPTSIZ13  (*((uint32_t volatile*)(OTGBASE + 0xAB0)))
 259 #define DIEPDMA13   (*((const void* volatile*)(OTGBASE + 0xAB4)))
 260 #define DIEPCTL14   (*((uint32_t volatile*)(OTGBASE + 0xAC0)))
 261 #define DIEPINT14   (*((uint32_t volatile*)(OTGBASE + 0xAC8)))
 262 #define DIEPTSIZ14  (*((uint32_t volatile*)(OTGBASE + 0xAD0)))
 263 #define DIEPDMA14   (*((const void* volatile*)(OTGBASE + 0xAD4)))
 264 #define DIEPCTL15   (*((uint32_t volatile*)(OTGBASE + 0xAE0)))
 265 #define DIEPINT15   (*((uint32_t volatile*)(OTGBASE + 0xAE8)))
 266 #define DIEPTSIZ15  (*((uint32_t volatile*)(OTGBASE + 0xAF0)))
 267 #define DIEPDMA15   (*((const void* volatile*)(OTGBASE + 0xAF4)))
 268
 269 /* Device Logical OUT Endpoint-Specific Registers */
 270 #define DOEPCTL(x)  (*((uint32_t volatile*)(OTGBASE + 0xB00 + 0x20 * (x))))
 271 #define DOEPINT(x)  (*((uint32_t volatile*)(OTGBASE + 0xB08 + 0x20 * (x))))
 272 #define DOEPTSIZ(x) (*((uint32_t volatile*)(OTGBASE + 0xB10 + 0x20 * (x))))
 273 #define DOEPDMA(x)  (*((void* volatile*)(OTGBASE + 0xB14 + 0x20 * (x))))
 274 #define DOEPCTL0    (*((uint32_t volatile*)(OTGBASE + 0xB00)))
 275 #define DOEPINT0    (*((uint32_t volatile*)(OTGBASE + 0xB08)))
 276 #define DOEPTSIZ0   (*((uint32_t volatile*)(OTGBASE + 0xB10)))
 277 #define DOEPDMA0    (*((void* volatile*)(OTGBASE + 0xB14)))
 278 #define DOEPCTL1    (*((uint32_t volatile*)(OTGBASE + 0xB20)))
 279 #define DOEPINT1    (*((uint32_t volatile*)(OTGBASE + 0xB28)))
 280 #define DOEPTSIZ1   (*((uint32_t volatile*)(OTGBASE + 0xB30)))
 281 #define DOEPDMA1    (*((void* volatile*)(OTGBASE + 0xB34)))
 282 #define DOEPCTL2    (*((uint32_t volatile*)(OTGBASE + 0xB40)))
 283 #define DOEPINT2    (*((uint32_t volatile*)(OTGBASE + 0xB48)))
 284 #define DOEPTSIZ2   (*((uint32_t volatile*)(OTGBASE + 0xB50)))
 285 #define DOEPDMA2    (*((void* volatile*)(OTGBASE + 0xB54)))
 286 #define DOEPCTL3    (*((uint32_t volatile*)(OTGBASE + 0xB60)))
 287 #define DOEPINT3    (*((uint32_t volatile*)(OTGBASE + 0xB68)))
 288 #define DOEPTSIZ3   (*((uint32_t volatile*)(OTGBASE + 0xB70)))
 289 #define DOEPDMA3    (*((void* volatile*)(OTGBASE + 0xB74)))
 290 #define DOEPCTL4    (*((uint32_t volatile*)(OTGBASE + 0xB80)))
 291 #define DOEPINT4    (*((uint32_t volatile*)(OTGBASE + 0xB88)))
 292 #define DOEPTSIZ4   (*((uint32_t volatile*)(OTGBASE + 0xB90)))
 293 #define DOEPDMA4    (*((void* volatile*)(OTGBASE + 0xB94)))
 294 #define DOEPCTL5    (*((uint32_t volatile*)(OTGBASE + 0xBA0)))
 295 #define DOEPINT5    (*((uint32_t volatile*)(OTGBASE + 0xBA8)))
 296 #define DOEPTSIZ5   (*((uint32_t volatile*)(OTGBASE + 0xBB0)))
 297 #define DOEPDMA5    (*((void* volatile*)(OTGBASE + 0xBB4)))
 298 #define DOEPCTL6    (*((uint32_t volatile*)(OTGBASE + 0xBC0)))
 299 #define DOEPINT6    (*((uint32_t volatile*)(OTGBASE + 0xBC8)))
 300 #define DOEPTSIZ6   (*((uint32_t volatile*)(OTGBASE + 0xBD0)))
 301 #define DOEPDMA6    (*((void* volatile*)(OTGBASE + 0xBD4)))
 302 #define DOEPCTL7    (*((uint32_t volatile*)(OTGBASE + 0xBE0)))
 303 #define DOEPINT7    (*((uint32_t volatile*)(OTGBASE + 0xBE8)))
 304 #define DOEPTSIZ7   (*((uint32_t volatile*)(OTGBASE + 0xBF0)))
 305 #define DOEPDMA7    (*((void* volatile*)(OTGBASE + 0xBF4)))
 306 #define DOEPCTL8    (*((uint32_t volatile*)(OTGBASE + 0xC00)))
 307 #define DOEPINT8    (*((uint32_t volatile*)(OTGBASE + 0xC08)))
 308 #define DOEPTSIZ8   (*((uint32_t volatile*)(OTGBASE + 0xC10)))
 309 #define DOEPDMA8    (*((void* volatile*)(OTGBASE + 0xC14)))
 310 #define DOEPCTL9    (*((uint32_t volatile*)(OTGBASE + 0xC20)))
 311 #define DOEPINT9    (*((uint32_t volatile*)(OTGBASE + 0xC28)))
 312 #define DOEPTSIZ9   (*((uint32_t volatile*)(OTGBASE + 0xC30)))
 313 #define DOEPDMA9    (*((void* volatile*)(OTGBASE + 0xC34)))
 314 #define DOEPCTL10   (*((uint32_t volatile*)(OTGBASE + 0xC40)))
 315 #define DOEPINT10   (*((uint32_t volatile*)(OTGBASE + 0xC48)))
 316 #define DOEPTSIZ10  (*((uint32_t volatile*)(OTGBASE + 0xC50)))
 317 #define DOEPDMA10   (*((void* volatile*)(OTGBASE + 0xC54)))
 318 #define DOEPCTL11   (*((uint32_t volatile*)(OTGBASE + 0xC60)))
 319 #define DOEPINT11   (*((uint32_t volatile*)(OTGBASE + 0xC68)))
 320 #define DOEPTSIZ11  (*((uint32_t volatile*)(OTGBASE + 0xC70)))
 321 #define DOEPDMA11   (*((void* volatile*)(OTGBASE + 0xC74)))
 322 #define DOEPCTL12   (*((uint32_t volatile*)(OTGBASE + 0xC80)))
 323 #define DOEPINT12   (*((uint32_t volatile*)(OTGBASE + 0xC88)))
 324 #define DOEPTSIZ12  (*((uint32_t volatile*)(OTGBASE + 0xC90)))
 325 #define DOEPDMA12   (*((void* volatile*)(OTGBASE + 0xC94)))
 326 #define DOEPCTL13   (*((uint32_t volatile*)(OTGBASE + 0xCA0)))
 327 #define DOEPINT13   (*((uint32_t volatile*)(OTGBASE + 0xCA8)))
 328 #define DOEPTSIZ13  (*((uint32_t volatile*)(OTGBASE + 0xCB0)))
 329 #define DOEPDMA13   (*((void* volatile*)(OTGBASE + 0xCB4)))
 330 #define DOEPCTL14   (*((uint32_t volatile*)(OTGBASE + 0xCC0)))
 331 #define DOEPINT14   (*((uint32_t volatile*)(OTGBASE + 0xCC8)))
 332 #define DOEPTSIZ14  (*((uint32_t volatile*)(OTGBASE + 0xCD0)))
 333 #define DOEPDMA14   (*((void* volatile*)(OTGBASE + 0xCD4)))
 334 #define DOEPCTL15   (*((uint32_t volatile*)(OTGBASE + 0xCE0)))
 335 #define DOEPINT15   (*((uint32_t volatile*)(OTGBASE + 0xCE8)))
 336 #define DOEPTSIZ15  (*((uint32_t volatile*)(OTGBASE + 0xCF0)))
 337 #define DOEPDMA15   (*((void* volatile*)(OTGBASE + 0xCF4)))
 338
 339 /* Power and Clock Gating Register */
 340 #define PCGCCTL     (*((uint32_t volatile*)(OTGBASE + 0xE00)))
 341
 342
 343 #endif /* USB_S3C6400X_H */