firmware/target/arm/tms320dm320/system-dm320.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2007 by Karl Kurbjun
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21 #include "cpu.h"
  22 #include "mmu-arm.h"
  23 #include "kernel.h"
  24 #include "system.h"
  25 #include "panic.h"
  26 #include "uart-target.h"
  27 #include "system-arm.h"
  28 #include "spi.h"
  29 #ifdef CREATIVE_ZVx
  30 #include "dma-target.h"
  31 #endif
  32
  33 #define default_interrupt(name) \
  34   extern __attribute__((weak,alias("UIRQ"))) void name (void)
  35
  36 void irq_handler(void) __attribute__((interrupt ("IRQ"), naked));
  37 void fiq_handler(void) __attribute__((interrupt ("FIQ"), naked));
  38
  39 default_interrupt(TIMER0);
  40 default_interrupt(TIMER1);
  41 default_interrupt(TIMER2);
  42 default_interrupt(TIMER3);
  43 default_interrupt(CCD_VD0);
  44 default_interrupt(CCD_VD1);
  45 default_interrupt(CCD_WEN);
  46 default_interrupt(VENC);
  47 default_interrupt(SERIAL0);
  48 default_interrupt(SERIAL1);
  49 default_interrupt(EXT_HOST);
  50 default_interrupt(DSPHINT);
  51 default_interrupt(UART0);
  52 default_interrupt(UART1);
  53 default_interrupt(USB_DMA);
  54 default_interrupt(USB_CORE);
  55 default_interrupt(VLYNQ);
  56 default_interrupt(MTC0);
  57 default_interrupt(MTC1);
  58 default_interrupt(SD_MMC);
  59 default_interrupt(SDIO_MS);
  60 default_interrupt(GIO0);
  61 default_interrupt(GIO1);
  62 default_interrupt(GIO2);
  63 default_interrupt(GIO3);
  64 default_interrupt(GIO4);
  65 default_interrupt(GIO5);
  66 default_interrupt(GIO6);
  67 default_interrupt(GIO7);
  68 default_interrupt(GIO8);
  69 default_interrupt(GIO9);
  70 default_interrupt(GIO10);
  71 default_interrupt(GIO11);
  72 default_interrupt(GIO12);
  73 default_interrupt(GIO13);
  74 default_interrupt(GIO14);
  75 default_interrupt(GIO15);
  76 default_interrupt(PREVIEW0);
  77 default_interrupt(PREVIEW1);
  78 default_interrupt(WATCHDOG);
  79 default_interrupt(I2C);
  80 default_interrupt(CLKC);
  81 default_interrupt(ICE);
  82 default_interrupt(ARMCOM_RX);
  83 default_interrupt(ARMCOM_TX);
  84 default_interrupt(RESERVED);
  85
  86 /* The entry address is equal to base address plus an offset.
  87  * The offset is based on the priority of the interrupt. So if
  88  * the priority of an interrupt is changed, the user should also
  89  * change the offset for the interrupt in the entry table.
  90  */
  91
  92 static const unsigned short const irqpriority[] =
  93 {
  94     IRQ_TIMER0,IRQ_TIMER1,IRQ_TIMER2,IRQ_TIMER3,IRQ_CCD_VD0,IRQ_CCD_VD1,
  95     IRQ_CCD_WEN,IRQ_VENC,IRQ_SERIAL0,IRQ_SERIAL1,IRQ_EXT_HOST,IRQ_DSPHINT,
  96     IRQ_UART0,IRQ_UART1,IRQ_USB_DMA,IRQ_USB_CORE,IRQ_VLYNQ,IRQ_MTC0,IRQ_MTC1,
  97     IRQ_SD_MMC,IRQ_SDIO_MS,IRQ_GIO0,IRQ_GIO1,IRQ_GIO2,IRQ_GIO3,IRQ_GIO4,IRQ_GIO5,
  98     IRQ_GIO6,IRQ_GIO7,IRQ_GIO8,IRQ_GIO9,IRQ_GIO10,IRQ_GIO11,IRQ_GIO12,IRQ_GIO13,
  99     IRQ_GIO14,IRQ_GIO15,IRQ_PREVIEW0,IRQ_PREVIEW1,IRQ_WATCHDOG,IRQ_I2C,IRQ_CLKC,
 100     IRQ_ICE,IRQ_ARMCOM_RX,IRQ_ARMCOM_TX,IRQ_RESERVED
 101 }; /* IRQ priorities, ranging from highest to lowest */
 102
 103 static void (* const irqvector[])(void) =
 104 {
 105     TIMER0,TIMER1,TIMER2,TIMER3,CCD_VD0,CCD_VD1,
 106     CCD_WEN,VENC,SERIAL0,SERIAL1,EXT_HOST,DSPHINT,
 107     UART0,UART1,USB_DMA,USB_CORE,VLYNQ,MTC0,MTC1,
 108     SD_MMC,SDIO_MS,GIO0,GIO1,GIO2,GIO3,GIO4,GIO5,
 109     GIO6,GIO7,GIO8,GIO9,GIO10,GIO11,GIO12,GIO13,
 110     GIO14,GIO15,PREVIEW0,PREVIEW1,WATCHDOG,I2C,CLKC,
 111     ICE,ARMCOM_RX,ARMCOM_TX,RESERVED
 112 };
 113
 114 static const char * const irqname[] =
 115 {
 116     "TIMER0","TIMER1","TIMER2","TIMER3","CCD_VD0","CCD_VD1",
 117     "CCD_WEN","VENC","SERIAL0","SERIAL1","EXT_HOST","DSPHINT",
 118     "UART0","UART1","USB_DMA","USB_CORE","VLYNQ","MTC0","MTC1",
 119     "SD_MMC","SDIO_MS","GIO0","GIO1","GIO2","GIO3","GIO4","GIO5",
 120     "GIO6","GIO7","GIO8","GIO9","GIO10","GIO11","GIO12","GIO13",
 121     "GIO14","GIO15","PREVIEW0","PREVIEW1","WATCHDOG","I2C","CLKC",
 122     "ICE","ARMCOM_RX","ARMCOM_TX","RESERVED"
 123 };
 124
 125 static void UIRQ(void)
 126 {
 127     unsigned int offset = (IO_INTC_IRQENTRY0>>2)-1;
 128     panicf("Unhandled IRQ %02X: %s", offset, irqname[offset]);
 129 }
 130
 131 void irq_handler(void)
 132 {
 133     /*
 134      * Based on: linux/arch/arm/kernel/entry-armv.S and system-meg-fx.c
 135      */
 136
 137     asm volatile(   "stmfd sp!, {r0-r7, ip, lr} \n"   /* Store context */
 138                     "sub   sp, sp, #8           \n"); /* Reserve stack */
 139     unsigned short addr = IO_INTC_IRQENTRY0>>2;
 140     if(addr != 0)
 141     {
 142         addr--;
 143         irqvector[addr]();
 144     }
 145     asm volatile(   "add   sp, sp, #8           \n"   /* Cleanup stack   */
 146                     "ldmfd sp!, {r0-r7, ip, lr} \n"   /* Restore context */
 147                     "subs  pc, lr, #4           \n"); /* Return from IRQ */
 148 }
 149
 150 void fiq_handler(void)
 151 {
 152     /*
 153      * Based on: linux/arch/arm/kernel/entry-armv.S and system-meg-fx.c
 154      */
 155
 156     asm volatile (
 157         "sub    lr, lr, #4            \r\n"
 158         "stmfd  sp!, {r0-r3, ip, lr}  \r\n"
 159         "mov    r0, #0x00030000       \r\n"
 160         "ldr    r0, [r0, #0x510]      \r\n" /* Fetch value from IO_INTC_FIQENTRY0 */
 161         "sub    r0, r0, #1            \r\n"
 162         "ldr    r1, =irqvector        \r\n"
 163         "ldr    r1, [r1, r0, lsl #2]  \r\n" /* Divide value by 4 (TBA0/TBA1 is set to 0) and load appropriate pointer from the vector list */
 164         "blx    r1                    \r\n" /* Jump to handler */
 165         "ldmfd  sp!, {r0-r3, ip, pc}^ \r\n" /* Return from FIQ */
 166     );
 167 }
 168
 169 void system_reboot(void)
 170 {
 171     /* Code taken from linux/include/asm-arm/arch-itdm320-20/system.h at NeuroSVN */
 172     __asm__ __volatile__(
 173         "mov     ip, #0                                             \n"
 174         "mcr     p15, 0, ip, c7, c7, 0           @ invalidate cache \n"
 175         "mcr     p15, 0, ip, c7, c10,4           @ drain WB         \n"
 176         "mcr     p15, 0, ip, c8, c7, 0           @ flush TLB (v4)   \n"
 177         "mrc     p15, 0, ip, c1, c0, 0           @ get ctrl register\n"
 178         "bic     ip, ip, #0x000f                 @ ............wcam \n"
 179         "bic     ip, ip, #0x2100                 @ ..v....s........ \n"
 180         "mcr     p15, 0, ip, c1, c0, 0           @ ctrl register    \n"
 181         "mov     ip, #0xFF000000                                    \n"
 182         "orr     pc, ip, #0xFF0000               @ ip = 0xFFFF0000  \n"
 183         :
 184         :
 185         : "cc"
 186     );
 187 }
 188
 189 void system_exception_wait(void)
 190 {
 191     /* Mask all Interrupts. */
 192     IO_INTC_EINT0 = 0;
 193     IO_INTC_EINT1 = 0;
 194     IO_INTC_EINT2 = 0;
 195     while ((IO_GIO_BITSET0&0x01) != 0); /* Wait for power button */
 196 }
 197
 198 void system_init(void)
 199 {
 200     /* taken from linux/arch/arm/mach-itdm320-20/irq.c */
 201
 202     /* Clearing all FIQs and IRQs. */
 203     IO_INTC_IRQ0 = 0xFFFF;
 204     IO_INTC_IRQ1 = 0xFFFF;
 205     IO_INTC_IRQ2 = 0xFFFF;
 206
 207     IO_INTC_FIQ0 = 0xFFFF;
 208     IO_INTC_FIQ1 = 0xFFFF;
 209     IO_INTC_FIQ2 = 0xFFFF;
 210
 211     /* Masking all Interrupts. */
 212     IO_INTC_EINT0 = 0;
 213     IO_INTC_EINT1 = 0;
 214     IO_INTC_EINT2 = 0;
 215
 216     /* Setting INTC to all IRQs. */
 217     IO_INTC_FISEL0 = 0;
 218     IO_INTC_FISEL1 = 0;
 219     IO_INTC_FISEL2 = 0;
 220
 221     /* setup the clocks */
 222     IO_CLK_DIV0=0x0003;
 223     IO_CLK_DIV1=0x0102;
 224     IO_CLK_DIV2=0x021F;
 225     IO_CLK_DIV3=0x1FFF;
 226     IO_CLK_DIV4=0x1F00;
 227
 228     IO_CLK_PLLA=0x80A0;
 229     IO_CLK_PLLB=0x80C0;
 230
 231     IO_CLK_SEL0=0x017E;
 232     IO_CLK_SEL1=0x1000;
 233     IO_CLK_SEL2=0x1001;
 234
 235     /* need to wait before bypassing */
 236
 237     IO_CLK_BYP=0x0000;
 238
 239     /* turn off some unneeded modules */
 240     IO_CLK_MOD0 &=  ~0x0018;
 241     IO_CLK_MOD1 =   0x0918;
 242     IO_CLK_MOD2 =   ~0x7C58;
 243
 244     /* IRQENTRY only reflects enabled interrupts */
 245     IO_INTC_RAW = 0;
 246
 247     IO_INTC_ENTRY_TBA0 = 0;
 248     IO_INTC_ENTRY_TBA1 = 0;
 249
 250     int i;
 251     /* Set interrupt priorities to predefined values */
 252     for(i = 0; i < 23; i++)
 253         DM320_REG(0x0540+i*2) = ((irqpriority[i*2+1] & 0x3F) << 8) | (irqpriority[i*2] & 0x3F); /* IO_INTC_PRIORITYx */
 254
 255     /* Turn off all timers */
 256     IO_TIMER0_TMMD = CONFIG_TIMER0_TMMD_STOP;
 257     IO_TIMER1_TMMD = CONFIG_TIMER1_TMMD_STOP;
 258     IO_TIMER2_TMMD = CONFIG_TIMER2_TMMD_STOP;
 259     IO_TIMER3_TMMD = CONFIG_TIMER3_TMMD_STOP;
 260
 261 #ifndef CREATIVE_ZVx
 262     /* set GIO26 (reset pin) to output and low */
 263     IO_GIO_BITCLR1=(1<<10);
 264     IO_GIO_DIR1&=~(1<<10);
 265 #endif
 266
 267     uart_init();
 268     spi_init();
 269
 270 #ifdef CREATIVE_ZVx
 271     dma_init();
 272 #endif
 273
 274     /* MMU initialization (Starts data and instruction cache) */
 275     ttb_init();
 276     /* Make sure everything is mapped on itself */
 277     map_section(0, 0, 0x1000, CACHE_NONE);
 278     /* Enable caching for RAM */
 279     map_section(CONFIG_SDRAM_START, CONFIG_SDRAM_START, MEM, CACHE_ALL);
 280     /* enable buffered writing for the framebuffer */
 281     map_section((int)FRAME, (int)FRAME, 1, BUFFERED);
 282 #ifdef CREATIVE_ZVx
 283     /* mimic OF */
 284     map_section(0x00100000, 0x00100000,  4, CACHE_NONE);
 285     map_section(0x04700000, 0x04700000,  2,   BUFFERED);
 286     map_section(0x40000000, 0x40000000, 16, CACHE_NONE);
 287     map_section(0x50000000, 0x50000000, 16, CACHE_NONE);
 288     map_section(0x60000000, 0x60000000, 16, CACHE_NONE);
 289     map_section(0x80000000, 0x80000000,  1, CACHE_NONE);
 290 #endif
 291     enable_mmu();
 292 }
 293
 294 int system_memory_guard(int newmode)
 295 {
 296     (void)newmode;
 297     return 0;
 298 }
 299
 300 #ifdef HAVE_ADJUSTABLE_CPU_FREQ
 301 void set_cpu_frequency(long frequency)
 302 {
 303     if (frequency == CPUFREQ_MAX) {
 304         IO_CLK_DIV0 = 0x0101;  /* 175 MHz ARM */
 305     } else {
 306         IO_CLK_DIV0 = 0x0003; /* 87.5 MHz ARM - not much savings, about 3 mA */
 307     }
 308 }
 309 #endif
 310