firmware/target/arm/system-pp5002.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2002 by Alan Korr
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21 #include "system.h"
  22
  23 #ifndef BOOTLOADER
  24 #include "adc-target.h"
  25 #include "button-target.h"
  26
  27 extern void TIMER1(void);
  28 extern void TIMER2(void);
  29
  30 void irq(void)
  31 {
  32     if(CURRENT_CORE == CPU)
  33     {
  34         if (CPU_INT_STAT & TIMER1_MASK)
  35             TIMER1();
  36         else if (CPU_INT_STAT & TIMER2_MASK)
  37             TIMER2();
  38         else if (CPU_INT_STAT & GPIO_MASK)
  39         {
  40             if (GPIOA_INT_STAT)
  41                 ipod_3g_button_int();
  42 #ifdef IPOD_1G2G
  43             if (GPIOB_INT_STAT & 0x04)
  44                 ipod_2g_adc_int();
  45 #endif
  46         }
  47     }
  48     else
  49     {
  50         if (COP_INT_STAT & TIMER2_MASK)
  51             TIMER2();
  52     }
  53 }
  54
  55 #endif
  56
  57 /* TODO: The following two function have been lifted straight from IPL, and
  58    hence have a lot of numeric addresses used straight. I'd like to use
  59    #defines for these, but don't know what most of them are for or even what
  60    they should be named. Because of this I also have no way of knowing how
  61    to extend the funtions to do alternate cache configurations and/or
  62    some other CPU frequency scaling. */
  63
  64 #ifndef BOOTLOADER
  65 void flush_icache(void) ICODE_ATTR;
  66 void flush_icache(void)
  67 {
  68     intptr_t b, e;
  69
  70     for (b = (intptr_t)&CACHE_FLUSH_BASE, e = b + CACHE_SIZE;
  71          b < e; b += 16) {
  72         outl(0x0, b);
  73     }
  74 }
  75
  76 void invalidate_icache(void) ICODE_ATTR;
  77 void invalidate_icache(void)
  78 {
  79     intptr_t b, e;
  80
  81     /* Flush */
  82     for (b = (intptr_t)&CACHE_FLUSH_BASE, e = b + CACHE_SIZE;
  83          b < e; b += 16) {
  84         outl(0x0, b);
  85     }
  86
  87     /* Invalidate */
  88     for (b = (intptr_t)&CACHE_INVALIDATE_BASE, e = b + CACHE_SIZE;
  89          b < e; b += 16) {
  90         outl(0x0, b);
  91     }
  92 }
  93
  94 static void ipod_init_cache(void)
  95 {
  96     intptr_t b, e;
  97
  98 /* Initialising the cache in the iPod bootloader prevents Rockbox from starting */
  99     PROC_STAT &= ~0x700;
 100     outl(0x4000, 0xcf004020);
 101
 102     CACHE_CTL = CACHE_INIT;
 103
 104     for (b = (intptr_t)&CACHE_INVALIDATE_BASE, e = b + CACHE_SIZE;
 105          b < e; b += 16) {
 106         outl(0x0, b);
 107     }
 108
 109     /* Cache if (addr & mask) >> 16 == (mask & match) >> 16:
 110      * yes: 0x00000000 - 0x03ffffff
 111      *  no: 0x04000000 - 0x1fffffff
 112      * yes: 0x20000000 - 0x23ffffff
 113      *  no: 0x24000000 - 0x3fffffff <= range containing uncached alias
 114      */
 115     CACHE_MASK = 0x00001c00;
 116     CACHE_OPERATION = 0x3fc0;
 117
 118     CACHE_CTL = CACHE_INIT | CACHE_RUN;
 119 }
 120
 121 #ifdef HAVE_ADJUSTABLE_CPU_FREQ
 122 void set_cpu_frequency(long frequency)
 123 #else
 124 static void pp_set_cpu_frequency(long frequency)
 125 #endif
 126 {
 127     cpu_frequency = frequency;
 128
 129     PLL_CONTROL |= 0x6000;     /* make sure some enable bits are set */
 130     CLOCK_ENABLE = 0x01;       /* select source #1 */
 131
 132     switch (frequency)
 133     {
 134       case CPUFREQ_MAX:
 135         PLL_UNLOCK   = 0xd19b; /* unlock frequencies > 66MHz */
 136         CLOCK_SOURCE = 0xa9;   /* source #1: 24 Mhz, source #2..#4: PLL */
 137         PLL_CONTROL  = 0xe000; /* PLL enabled */
 138         PLL_DIV      = 3;      /* 10/3 * 24MHz */
 139         PLL_MULT     = 10;
 140         udelay(200);           /* wait for relock */
 141         break;
 142
 143       case CPUFREQ_NORMAL:
 144         CLOCK_SOURCE = 0xa9;   /* source #1: 24 Mhz, source #2..#4: PLL */
 145         PLL_CONTROL  = 0xe000; /* PLL enabled */
 146         PLL_DIV      = 4;      /* 5/4 * 24MHz */
 147         PLL_MULT     = 5;
 148         udelay(200);           /* wait for relock */
 149         break;
 150
 151       case CPUFREQ_SLEEP:
 152         CLOCK_SOURCE = 0x51;   /* source #2: 32kHz, #1, #2, #4: 24MHz */
 153         PLL_CONTROL  = 0x6000; /* PLL disabled */
 154         udelay(10000);         /* let 32kHz source stabilize? */
 155         break;
 156
 157       default:
 158         CLOCK_SOURCE = 0x55;   /* source #1..#4: 24 Mhz */
 159         PLL_CONTROL  = 0x6000; /* PLL disabled */
 160         cpu_frequency = CPUFREQ_DEFAULT;
 161         break;
 162     }
 163     CLOCK_ENABLE = 0x02;       /* select source #2 */
 164 }
 165 #endif /* !BOOTLOADER */
 166
 167 void system_init(void)
 168 {
 169 #ifndef BOOTLOADER
 170     if (CURRENT_CORE == CPU)
 171     {
 172         /* Remap the flash ROM on CPU, keep hidden from COP:
 173          * 0x00000000-0x03ffffff = 0x20000000-0x23ffffff */
 174         MMAP1_LOGICAL  = 0x20003c00;
 175         MMAP1_PHYSICAL = 0x00003f84;
 176
 177 #if defined(IPOD_1G2G) || defined(IPOD_3G)
 178         DEV_EN = 0x0b9f; /* don't clock unused PP5002 hardware components */
 179         outl(0x0035, 0xcf005004);  /* DEV_EN2 ? */
 180 #endif
 181
 182         INT_FORCED_CLR = -1;
 183         CPU_INT_DIS    = -1;
 184         COP_INT_DIS    = -1;
 185
 186         GPIOA_INT_EN   = 0;
 187         GPIOB_INT_EN   = 0;
 188         GPIOC_INT_EN   = 0;
 189         GPIOD_INT_EN   = 0;
 190
 191 #ifdef HAVE_ADJUSTABLE_CPU_FREQ
 192 #if NUM_CORES > 1
 193         cpu_boost_init();
 194 #endif
 195 #else
 196         pp_set_cpu_frequency(CPUFREQ_MAX);
 197 #endif
 198     }
 199     ipod_init_cache();
 200 #endif
 201 }
 202
 203 void system_reboot(void)
 204 {
 205     DEV_RS |= 4;
 206 }
 207
 208 int system_memory_guard(int newmode)
 209 {
 210     (void)newmode;
 211     return 0;
 212 }