firmware/target/arm/tms320dm320/dsp-dm320.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2007 Catalin Patulea <cat@vv.carleton.ca>
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21 #include "config.h"
  22 #include "cpu.h"
  23 #include "system.h"
  24 #include "debug.h"
  25 #include "string.h"
  26 #include "file.h"
  27 #include "dsp-target.h"
  28 #include "dsp/ipc.h"
  29
  30 #ifdef DEBUG
  31 static void dsp_status(void)
  32 {
  33     unsigned short hpib_ctl = IO_DSPC_HPIB_CONTROL;
  34     unsigned short hpib_stat = IO_DSPC_HPIB_STATUS;
  35     char buffer1[80], buffer2[80];
  36
  37     DEBUGF("dsp_status(): clkc_hpib=%u clkc_dsp=%u",
  38            !!(IO_CLK_MOD0 & (1 << 11)), !!(IO_CLK_MOD0 & (1 << 10)));
  39
  40     DEBUGF("dsp_status(): irq_dsphint=%u 7fff=%04x scratch_status=%04x"
  41            " acked=%04x",
  42            (IO_INTC_IRQ0 >> IRQ_DSPHINT) & 1, DSP_(0x7fff), DSP_(_status),
  43            DSP_(_acked));
  44 #define B(f,w,b,m) if ((w & (1 << b)) == 0) \
  45                        strcat(f, "!"); \
  46                        strcat(f, #m "|");
  47     strcpy(buffer1, "");
  48     B(buffer1, hpib_ctl, 0, EN);
  49     B(buffer1, hpib_ctl, 3, NMI);
  50     B(buffer1, hpib_ctl, 5, EXCHG);
  51     B(buffer1, hpib_ctl, 7, DINT0);
  52     B(buffer1, hpib_ctl, 8, DRST);
  53     B(buffer1, hpib_ctl, 9, DHOLD);
  54     B(buffer1, hpib_ctl, 10, BIO);
  55
  56     strcpy(buffer2, "");
  57     B(buffer2, hpib_stat, 8, HOLDA);
  58     B(buffer2, hpib_stat, 12, DXF);
  59
  60     DEBUGF("dsp_status(): hpib: ctl=%s stat=%s", buffer1, buffer2);
  61 #undef B
  62 }
  63 #endif
  64
  65 void dsp_reset(void)
  66 {
  67     DSP_(0x7fff) = 0xdead;
  68
  69     IO_DSPC_HPIB_CONTROL &= ~(1 << 8);
  70     /* HPIB bus cycles will lock up the ARM in here. Don't touch DSP RAM. */
  71     nop; nop;
  72     IO_DSPC_HPIB_CONTROL |= 1 << 8;
  73
  74     /* TODO: Timeout. */
  75     while (DSP_(0x7fff) != 0);
  76 }
  77
  78 void dsp_wake(void)
  79 {
  80     /* If this is called concurrently, we may overlap setting and resetting the
  81        bit, which causes lost interrupts to the DSP. */
  82     int old_level = disable_irq_save();
  83
  84     /* The first time you INT0 the DSP, the ROM loader will branch to your RST
  85        handler. Subsequent times, your INT0 handler will get executed. */
  86     IO_DSPC_HPIB_CONTROL &= ~(1 << 7);
  87     nop; nop;
  88     IO_DSPC_HPIB_CONTROL |= 1 << 7;
  89
  90     restore_irq(old_level);
  91 }
  92
  93 void dsp_load(const struct dsp_section *im)
  94 {
  95     while (im->raw_data_size_half) {
  96         volatile unsigned short *data_ptr = &DSP_(im->physical_addr);
  97         unsigned int i;
  98
  99         /* Use 16-bit writes. */
 100         if (im->raw_data) {
 101             DEBUGF("dsp_load(): loading %u words at 0x%04x (0x%08lx)",
 102                    im->raw_data_size_half, im->physical_addr,
 103                    (unsigned long)data_ptr);
 104
 105             for (i = 0; i < im->raw_data_size_half; i++) {
 106                 data_ptr[i] = im->raw_data[i];
 107             }
 108         } else {
 109             DEBUGF("dsp_load(): clearing %u words at 0x%04x (0x%08lx)",
 110                    im->raw_data_size_half, im->physical_addr,
 111                    (unsigned long)data_ptr);
 112
 113             for (i = 0; i < im->raw_data_size_half; i++) {
 114                 data_ptr[i] = 0;
 115             }
 116         }
 117
 118         im++;
 119     }
 120 }
 121