Unconditionally boost cpu and remove CNAK retry panic
[kugel-rb.git] / firmware / target / arm / as3525 / usb-drv-as3525.c
blob90a1c931f79d15f3cffc7266417f2b351b4ee801
1 /***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
10 * Copyright © 2010 Tobias Diedrich
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
20 ****************************************************************************/
22 #include "system.h"
23 #include "usb.h"
24 #include "usb_drv.h"
25 #include "as3525.h"
26 #include "clock-target.h"
27 #include "ascodec.h"
28 #include "as3514.h"
29 #include <stdbool.h>
30 #include "panic.h"
31 /*#define LOGF_ENABLE*/
32 #include "logf.h"
33 #include "usb_ch9.h"
34 #include "usb_core.h"
35 #include "string.h"
37 #if defined(USE_ROCKBOX_USB)
39 #include "usb-drv-as3525.h"
41 static struct usb_endpoint endpoints[USB_NUM_EPS][2];
42 static int got_set_configuration = 0;
45 * dma/setup descriptors and buffers should avoid sharing
46 * a cacheline with other data.
47 * dmadescs may share with each other, since we only access them uncached.
49 static struct usb_dev_dma_desc dmadescs[USB_NUM_EPS][2] __attribute__((aligned(32)));
50 /* reuse unused EP2 OUT descriptor here */
51 static struct usb_dev_setup_buf *setup_desc = (void*)&dmadescs[2][1];
53 #if AS3525_MCLK_SEL != AS3525_CLK_PLLB
54 static inline void usb_enable_pll(void)
56 CGU_COUNTB = CGU_LOCK_CNT;
57 CGU_PLLB = AS3525_PLLB_SETTING;
58 CGU_PLLBSUP = 0; /* enable PLLB */
59 while(!(CGU_INTCTRL & CGU_PLLB_LOCK)); /* wait until PLLB is locked */
62 static inline void usb_disable_pll(void)
64 CGU_PLLBSUP = CGU_PLL_POWERDOWN;
66 #else
67 static inline void usb_enable_pll(void)
71 static inline void usb_disable_pll(void)
74 #endif /* AS3525_MCLK_SEL != AS3525_CLK_PLLB */
76 void usb_attach(void)
78 usb_enable(true);
81 static void usb_tick(void);
83 static void usb_phy_on(void)
85 /* PHY clock */
86 CGU_USB = 1<<5 /* enable */
87 | (CLK_DIV(AS3525_PLLB_FREQ, 48000000) / 2) << 2
88 | 2; /* source = PLLB */
90 /* UVDD on */
91 ascodec_write(AS3515_USB_UTIL, ascodec_read(AS3515_USB_UTIL) | (1<<4));
92 mdelay(100);
94 /* reset */
95 CCU_SRC = CCU_SRC_USB_AHB_EN|CCU_SRC_USB_PHY_EN;
96 CCU_SRL = CCU_SRL_MAGIC_NUMBER;
97 mdelay(1);
98 CCU_SRC = CCU_SRC_USB_AHB_EN;
99 mdelay(1);
100 CCU_SRC = CCU_SRL = 0;
102 USB_GPIO_CSR = USB_GPIO_TX_ENABLE_N
103 | USB_GPIO_TX_BIT_STUFF_EN
104 | USB_GPIO_XO_ON
105 | USB_GPIO_CLK_SEL10; /* 0x06180000; */
108 static void usb_phy_suspend(void)
110 USB_GPIO_CSR |= USB_GPIO_ASESSVLD_EXT |
111 USB_GPIO_BSESSVLD_EXT |
112 USB_GPIO_VBUS_VLD_EXT;
113 mdelay(3);
114 USB_GPIO_CSR |= USB_GPIO_VBUS_VLD_EXT_SEL;
115 mdelay(10);
118 static void usb_phy_resume(void)
120 USB_GPIO_CSR &= ~(USB_GPIO_ASESSVLD_EXT |
121 USB_GPIO_BSESSVLD_EXT |
122 USB_GPIO_VBUS_VLD_EXT);
123 mdelay(3);
124 USB_GPIO_CSR &= ~USB_GPIO_VBUS_VLD_EXT_SEL;
125 mdelay(10);
128 static void setup_desc_init(struct usb_dev_setup_buf *desc)
130 struct usb_dev_setup_buf *uc_desc = AS3525_UNCACHED_ADDR(desc);
132 uc_desc->status = USB_DMA_DESC_BS_HST_RDY;
133 uc_desc->resv = 0xffffffff;
134 uc_desc->data1 = 0xffffffff;
135 uc_desc->data2 = 0xffffffff;
138 static void dma_desc_init(int ep, int dir)
140 struct usb_dev_dma_desc *desc = &dmadescs[ep][dir];
141 struct usb_dev_dma_desc *uc_desc = AS3525_UNCACHED_ADDR(desc);
143 endpoints[ep][dir].uc_desc = uc_desc;
145 uc_desc->status = USB_DMA_DESC_BS_DMA_DONE | \
146 USB_DMA_DESC_LAST | \
147 USB_DMA_DESC_ZERO_LEN;
148 uc_desc->resv = 0xffffffff;
149 uc_desc->data_ptr = 0;
150 uc_desc->next_desc = 0;
153 static void reset_endpoints(int init)
155 int i;
158 * OUT EP 2 is an alias for OUT EP 0 on this HW!
160 * Resonates with "3 bidirectional- plus 1 in-endpoints in device mode"
161 * from the datasheet, but why ep2 and not ep3?
163 * Reserve it here so we will skip over it in request_endpoint().
165 endpoints[2][1].state |= EP_STATE_ALLOCATED;
167 for(i = 0; i < USB_NUM_EPS; i++) {
169 * MPS sizes depending on speed:
170 * LS: 8 (control), no bulk available
171 * FS: 64 (control), 64 (bulk)
172 * HS: 64 (control), 512 (bulk)
174 * We don't need to handle LS since there is no low-speed only
175 * host AFAIK.
177 int mps = i == 0 ? 64 : (usb_drv_port_speed() ? 512 : 64);
179 if (init) {
180 if (endpoints[i][0].state & EP_STATE_BUSY) {
181 if (endpoints[i][0].state & EP_STATE_ASYNC) {
182 endpoints[i][0].rc = -1;
183 wakeup_signal(&endpoints[i][0].complete);
184 } else {
185 usb_core_transfer_complete(i, USB_DIR_IN, -1, 0);
188 endpoints[i][0].state = 0;
189 wakeup_init(&endpoints[i][0].complete);
191 if (i != 2) { /* Skip the OUT EP0 alias */
192 if (endpoints[i][1].state & EP_STATE_BUSY)
193 usb_core_transfer_complete(i, USB_DIR_OUT, -1, 0);
194 endpoints[i][1].state = 0;
195 wakeup_init(&endpoints[i][1].complete);
196 USB_OEP_SUP_PTR(i) = 0;
200 dma_desc_init(i, 0);
201 USB_IEP_CTRL (i) = USB_EP_CTRL_FLUSH|USB_EP_CTRL_SNAK;
202 USB_IEP_MPS (i) = mps; /* in bytes */
203 /* We don't care about the 'IN token received' event */
204 USB_IEP_STS_MASK(i) = USB_EP_STAT_IN; /* OF: 0x840 */
205 USB_IEP_TXFSIZE (i) = mps/2; /* in dwords => mps*2 bytes */
206 USB_IEP_STS (i) = 0xffffffff; /* clear status */
207 USB_IEP_DESC_PTR(i) = 0;
209 if (i != 2) { /* Skip the OUT EP0 alias */
210 dma_desc_init(i, 1);
211 USB_OEP_CTRL (i) = USB_EP_CTRL_FLUSH|USB_EP_CTRL_SNAK;
212 USB_OEP_MPS (i) = (mps/2 << 16) | mps;
213 USB_OEP_STS_MASK(i) = USB_EP_STAT_BNA; /* OF: 0x1800 */
214 USB_OEP_RXFR (i) = 0; /* Always 0 in OF trace? */
215 USB_OEP_STS (i) = 0xffffffff; /* clear status */
216 USB_OEP_DESC_PTR(i) = 0;
220 setup_desc_init(setup_desc);
221 USB_OEP_SUP_PTR(0) = (int)setup_desc;
224 void usb_drv_init(void)
226 logf("usb_drv_init() !!!!\n");
228 usb_enable_pll();
230 /* we have external power, so boost cpu */
231 cpu_boost(1);
233 /* length regulator: normal operation */
234 ascodec_write(AS3514_CVDD_DCDC3, ascodec_read(AS3514_CVDD_DCDC3) | 1<<2);
236 /* AHB part */
237 CGU_PERI |= CGU_USB_CLOCK_ENABLE;
239 /* reset AHB */
240 CCU_SRC = CCU_SRC_USB_AHB_EN;
241 CCU_SRL = CCU_SRL_MAGIC_NUMBER;
242 mdelay(1);
243 CCU_SRC = CCU_SRL = 0;
245 USB_GPIO_CSR = USB_GPIO_TX_ENABLE_N
246 | USB_GPIO_TX_BIT_STUFF_EN
247 | USB_GPIO_XO_ON
248 | USB_GPIO_CLK_SEL10; /* 0x06180000; */
250 /* bug workaround according to linux patch */
251 USB_DEV_CFG = (USB_DEV_CFG & ~3) | 1; /* full speed */
253 /* enable soft disconnect */
254 USB_DEV_CTRL |= USB_DEV_CTRL_SOFT_DISCONN;
256 usb_phy_on();
257 usb_phy_suspend();
258 USB_DEV_CTRL |= USB_DEV_CTRL_SOFT_DISCONN;
260 /* We don't care about SVC or SOF events */
261 /* Right now we don't handle suspend, so mask those too */
262 USB_DEV_INTR_MASK = USB_DEV_INTR_SVC |
263 USB_DEV_INTR_SOF |
264 USB_DEV_INTR_USB_SUSPEND |
265 USB_DEV_INTR_EARLY_SUSPEND;
267 USB_DEV_CFG = USB_DEV_CFG_STAT_ACK |
268 USB_DEV_CFG_UNI_DIR |
269 USB_DEV_CFG_PI_16BIT |
270 USB_DEV_CFG_HS |
271 USB_DEV_CFG_SELF_POWERED |
272 USB_DEV_CFG_CSR_PRG |
273 USB_DEV_CFG_PHY_ERR_DETECT;
275 USB_DEV_CTRL = USB_DEV_CTRL_DESC_UPDATE |
276 USB_DEV_CTRL_THRES_ENABLE |
277 USB_DEV_CTRL_BURST_ENABLE |
278 USB_DEV_CTRL_BLEN_8DWORDS |
279 USB_DEV_CTRL_TLEN_8THMAXSIZE;
281 USB_DEV_EP_INTR_MASK &= ~((1<<0) | (1<<16)); /* ep 0 */
283 reset_endpoints(1);
285 /* clear pending interrupts */
286 USB_DEV_EP_INTR = 0xffffffff;
287 USB_DEV_INTR = 0xffffffff;
289 VIC_INT_ENABLE = INTERRUPT_USB;
291 usb_phy_resume();
292 USB_DEV_CTRL &= ~USB_DEV_CTRL_SOFT_DISCONN;
294 USB_GPIO_CSR = USB_GPIO_TX_ENABLE_N
295 | USB_GPIO_TX_BIT_STUFF_EN
296 | USB_GPIO_XO_ON
297 | USB_GPIO_HS_INTR
298 | USB_GPIO_CLK_SEL10; /* 0x06180000; */
300 tick_add_task(usb_tick);
303 void usb_drv_exit(void)
305 tick_remove_task(usb_tick);
306 USB_DEV_CTRL |= (1<<10); /* soft disconnect */
307 usb_phy_suspend();
309 * mask all interrupts _before_ writing to VIC_INT_EN_CLEAR,
310 * or else the core might latch the interrupt while
311 * the write ot VIC_INT_EN_CLEAR is in the pipeline and
312 * so cause a fake spurious interrupt.
314 USB_DEV_EP_INTR_MASK = 0xffffffff;
315 USB_DEV_INTR_MASK = 0xffffffff;
316 VIC_INT_EN_CLEAR = INTERRUPT_USB;
317 CGU_USB &= ~(1<<5);
318 CGU_PERI &= ~CGU_USB_CLOCK_ENABLE;
319 /* Disable UVDD generating LDO */
320 ascodec_write(AS3515_USB_UTIL, ascodec_read(AS3515_USB_UTIL) & ~(1<<4));
321 usb_disable_pll();
322 cpu_boost(0);
323 logf("usb_drv_exit() !!!!\n");
326 int usb_drv_port_speed(void)
328 return (USB_DEV_STS & USB_DEV_STS_MASK_SPD) ? 0 : 1;
331 int usb_drv_request_endpoint(int type, int dir)
333 int d = dir == USB_DIR_IN ? 0 : 1;
334 int i = 1; /* skip the control EP */
336 for(; i < USB_NUM_EPS; i++) {
337 if (endpoints[i][d].state & EP_STATE_ALLOCATED)
338 continue;
340 endpoints[i][d].state |= EP_STATE_ALLOCATED;
342 if (dir == USB_DIR_IN) {
343 USB_IEP_CTRL(i) = USB_EP_CTRL_FLUSH |
344 USB_EP_CTRL_SNAK |
345 USB_EP_CTRL_ACT |
346 (type << 4);
347 USB_DEV_EP_INTR_MASK &= ~(1<<i);
348 } else {
349 USB_OEP_CTRL(i) = USB_EP_CTRL_FLUSH |
350 USB_EP_CTRL_SNAK |
351 USB_EP_CTRL_ACT |
352 (type << 4);
353 USB_DEV_EP_INTR_MASK &= ~(1<<(16+i));
355 /* logf("usb_drv_request_endpoint(%d, %d): returning %02x\n", type, dir, i | dir); */
356 return i | dir;
359 logf("usb_drv_request_endpoint(%d, %d): no free endpoint found\n", type, dir);
360 return -1;
363 void usb_drv_release_endpoint(int ep)
365 int i = ep & 0x7f;
366 int d = ep & USB_DIR_IN ? 0 : 1;
368 if (i >= USB_NUM_EPS)
369 return;
371 * Check for control EP and ignore it.
372 * Unfortunately the usb core calls
373 * usb_drv_release_endpoint() for ep=0..(USB_NUM_ENDPOINTS-1),
374 * but doesn't request a new control EP after that...
376 if (i == 0 || /* Don't mask control EP */
377 (i == 2 && d == 1)) /* See reset_endpoints(), EP2_OUT == EP0_OUT */
378 return;
380 if (!(endpoints[i][d].state & EP_STATE_ALLOCATED))
381 return;
383 /* logf("usb_drv_release_endpoint(%d, %d)\n", i, d); */
384 endpoints[i][d].state = 0;
385 USB_DEV_EP_INTR_MASK |= (1<<(16*d+i));
386 USB_EP_CTRL(i, !d) = USB_EP_CTRL_FLUSH | USB_EP_CTRL_SNAK;
389 void usb_drv_cancel_all_transfers(void)
391 logf("usb_drv_cancel_all_transfers()\n");
392 return;
394 int flags = disable_irq_save();
395 reset_endpoints(0);
396 restore_irq(flags);
399 int usb_drv_recv(int ep, void *ptr, int len)
401 struct usb_dev_dma_desc *uc_desc = endpoints[ep][1].uc_desc;
403 ep &= 0x7f;
404 logf("usb_drv_recv(%d,%x,%d)\n", ep, (int)ptr, len);
406 if (len > USB_DMA_DESC_RXTX_BYTES)
407 panicf("usb_recv: len=%d > %d", len, USB_DMA_DESC_RXTX_BYTES);
409 if ((int)ptr & 31) {
410 logf("addr %08x not aligned!\n", (int)ptr);
413 endpoints[ep][1].state |= EP_STATE_BUSY;
414 endpoints[ep][1].len = len;
415 endpoints[ep][1].rc = -1;
416 endpoints[ep][1].buf = ptr;
418 /* remove data buffer from cache */
419 invalidate_dcache_range(ptr, len);
421 /* DMA setup */
422 uc_desc->status = USB_DMA_DESC_BS_HST_RDY |
423 USB_DMA_DESC_LAST |
424 len;
425 if (len == 0) {
426 uc_desc->status |= USB_DMA_DESC_ZERO_LEN;
427 uc_desc->data_ptr = 0;
428 } else {
429 uc_desc->data_ptr = ptr;
431 USB_OEP_DESC_PTR(ep) = (int)&dmadescs[ep][1];
432 USB_OEP_STS(ep) = USB_EP_STAT_OUT_RCVD; /* clear status */
434 /* Make sure receive DMA is on */
435 if (!(USB_DEV_CTRL & USB_DEV_CTRL_RDE)){
436 logf("enabling receive DMA\n");
437 USB_DEV_CTRL |= USB_DEV_CTRL_RDE;
438 if (!(USB_DEV_CTRL & USB_DEV_CTRL_RDE))
439 logf("failed to enable!\n");
442 USB_OEP_CTRL(ep) |= USB_EP_CTRL_CNAK; /* Go! */
444 if (USB_OEP_CTRL(ep) & USB_EP_CTRL_NAK) {
445 int i = 0;
446 while (USB_OEP_CTRL(ep) & USB_EP_CTRL_NAK) {
447 USB_OEP_CTRL(ep) |= USB_EP_CTRL_CNAK; /* Go! */
448 i++;
450 logf("ep%d CNAK needed %d retries CTRL=%x\n", ep, i, (int)USB_OEP_CTRL(ep));
453 return 0;
456 #if defined(LOGF_ENABLE)
457 static char hexbuf[1025];
458 static char hextab[16] = "0123456789abcdef";
460 char *make_hex(char *data, int len)
462 int i;
463 if (!((int)data & 0x40000000))
464 data = AS3525_UNCACHED_ADDR(data); /* don't pollute the cache */
466 if (len > 512)
467 len = 512;
469 for (i=0; i<len; i++) {
470 hexbuf[2*i ] = hextab[(unsigned char)data[i] >> 4 ];
471 hexbuf[2*i+1] = hextab[(unsigned char)data[i] & 0xf];
473 hexbuf[2*i] = 0;
475 return hexbuf;
477 #endif
479 void ep_send(int ep, void *ptr, int len)
481 struct usb_dev_dma_desc *uc_desc = endpoints[ep][0].uc_desc;
483 endpoints[ep][0].state |= EP_STATE_BUSY;
484 endpoints[ep][0].len = len;
485 endpoints[ep][0].rc = -1;
487 /* Make sure data is committed to memory */
488 clean_dcache_range(ptr, len);
490 logf("xx%s\n", make_hex(ptr, len));
492 uc_desc->status = USB_DMA_DESC_BS_HST_RDY |
493 USB_DMA_DESC_LAST |
494 len;
495 if (len == 0)
496 uc_desc->status |= USB_DMA_DESC_ZERO_LEN;
498 uc_desc->data_ptr = ptr;
500 USB_IEP_DESC_PTR(ep) = (int)&dmadescs[ep][0];
501 USB_IEP_STS(ep) = 0xffffffff; /* clear status */
502 /* start transfer */
503 USB_IEP_CTRL(ep) |= USB_EP_CTRL_CNAK | USB_EP_CTRL_PD;
504 /* HW automatically sets NAK bit later */
507 int usb_drv_send(int ep, void *ptr, int len)
509 logf("usb_drv_send(%d,%x,%d): ", ep, (int)ptr, len);
511 ep &= 0x7f;
513 if (ep == 0 && got_set_configuration) {
514 got_set_configuration = 0;
515 if (len != 0)
516 panicf("usb_drv_send: GSC, but len!=0");
517 /* Tell the HW we handled the request */
518 USB_DEV_CTRL |= USB_DEV_CTRL_APCSR_DONE;
519 return 0;
522 ep_send(ep, ptr, len);
523 while (endpoints[ep][0].state & EP_STATE_BUSY)
524 wakeup_wait(&endpoints[ep][0].complete, TIMEOUT_BLOCK);
526 return endpoints[ep][0].rc;
529 int usb_drv_send_nonblocking(int ep, void *ptr, int len)
531 logf("usb_drv_send_nonblocking(%d,%x,%d): ", ep, (int)ptr, len);
532 ep &= 0x7f;
533 endpoints[ep][0].state |= EP_STATE_ASYNC;
534 ep_send(ep, ptr, len);
535 return 0;
538 static void handle_in_ep(int ep)
540 int ep_sts = USB_IEP_STS(ep) & ~USB_IEP_STS_MASK(ep);
542 if (ep > 3)
543 panicf("in_ep > 3?!");
545 USB_IEP_STS(ep) = ep_sts; /* ack */
547 if (ep_sts & USB_EP_STAT_BNA) { /* Buffer was not set up */
548 int ctrl = USB_IEP_CTRL(ep);
549 logf("ep%d IN, status %x ctrl %x (BNA)\n", ep, ep_sts, ctrl);
550 panicf("ep%d IN 0x%x 0x%x (BNA)", ep, ep_sts, ctrl);
553 if (ep_sts & USB_EP_STAT_TDC) {
554 endpoints[ep][0].state &= ~EP_STATE_BUSY;
555 endpoints[ep][0].rc = 0;
556 logf("EP%d %x %stx done len %x stat %08x\n",
557 ep, ep_sts, endpoints[ep][0].state & EP_STATE_ASYNC ? "async " :"",
558 endpoints[ep][0].len,
559 endpoints[ep][0].uc_desc->status);
560 if (endpoints[ep][0].state & EP_STATE_ASYNC) {
561 endpoints[ep][0].state &= ~EP_STATE_ASYNC;
562 usb_core_transfer_complete(ep, USB_DIR_IN, 0, endpoints[ep][0].len);
563 } else {
564 wakeup_signal(&endpoints[ep][0].complete);
566 ep_sts &= ~USB_EP_STAT_TDC;
569 if (ep_sts) {
570 logf("ep%d IN, hwstat %lx, epstat %x\n", ep, USB_IEP_STS(ep), endpoints[ep][0].state);
571 panicf("ep%d IN 0x%x", ep, ep_sts);
575 static void handle_out_ep(int ep)
577 struct usb_ctrlrequest *req = (void*)AS3525_UNCACHED_ADDR(&setup_desc->data1);
578 int ep_sts = USB_OEP_STS(ep) & ~USB_OEP_STS_MASK(ep);
580 if (ep > 3)
581 panicf("out_ep > 3!?");
583 USB_OEP_STS(ep) = ep_sts; /* ACK */
585 if (ep_sts & USB_EP_STAT_BNA) { /* Buffer was not set up */
586 int ctrl = USB_OEP_CTRL(ep);
587 logf("ep%d OUT, status %x ctrl %x (BNA)\n", ep, ep_sts, ctrl);
588 panicf("ep%d OUT 0x%x 0x%x (BNA)", ep, ep_sts, ctrl);
589 ep_sts &= ~USB_EP_STAT_BNA;
592 if (ep_sts & USB_EP_STAT_OUT_RCVD) {
593 struct usb_dev_dma_desc *uc_desc = endpoints[ep][1].uc_desc;
594 int dma_sts = uc_desc->status;
595 int dma_len = dma_sts & 0xffff;
597 if (!(dma_sts & USB_DMA_DESC_ZERO_LEN)) {
598 logf("EP%d OUT token, st:%08x len:%d frm:%x data=%s epstate=%d\n",
599 ep, dma_sts & 0xf8000000, dma_len, (dma_sts >> 16) & 0x7ff,
600 make_hex(uc_desc->data_ptr, dma_len), endpoints[ep][1].state);
602 * If parts of the just dmaed range are in cache, dump them now.
604 dump_dcache_range(uc_desc->data_ptr, dma_len);
605 } else{
606 logf("EP%d OUT token, st:%08x frm:%x (no data)\n", ep,
607 dma_sts & 0xf8000000, (dma_sts >> 16) & 0x7ff);
610 if (endpoints[ep][1].state & EP_STATE_BUSY) {
611 endpoints[ep][1].state &= ~EP_STATE_BUSY;
612 endpoints[ep][1].rc = 0;
613 usb_core_transfer_complete(ep, USB_DIR_OUT, 0, dma_len);
614 } else {
615 logf("EP%d OUT, but no one was listening?\n", ep);
618 USB_OEP_CTRL(ep) |= USB_EP_CTRL_SNAK; /* make sure NAK is set */
619 ep_sts &= ~USB_EP_STAT_OUT_RCVD;
622 if (ep_sts & USB_EP_STAT_SETUP_RCVD) {
623 static struct usb_ctrlrequest req_copy;
625 req_copy = *req;
626 logf("t%ld:got SETUP packet: %s type=%d req=%d val=%d ind=%d len=%d\n",
627 current_tick,
628 make_hex((void*)req, 8),
629 req->bRequestType,
630 req->bRequest,
631 req->wValue,
632 req->wIndex,
633 req->wLength);
635 usb_core_control_request(&req_copy);
636 setup_desc_init(setup_desc);
638 ep_sts &= ~USB_EP_STAT_SETUP_RCVD;
641 if (ep_sts) {
642 logf("ep%d OUT, status %x\n", ep, ep_sts);
643 panicf("ep%d OUT 0x%x", ep, ep_sts);
646 #if 0
647 /* HW automatically disables RDE, re-enable it */
648 /* THEORY: Because we only set up one DMA buffer... */
649 USB_DEV_CTRL |= USB_DEV_CTRL_RDE;
650 #endif
652 if (!(USB_DEV_CTRL & USB_DEV_CTRL_RDE)){
653 logf("receive DMA is disabled!\n");
654 //USB_DEV_CTRL |= USB_DEV_CTRL_RDE;
659 * This is a simplified version of the timer based RDE enable from
660 * the Linux amd5536udc.c driver.
661 * We need this because of the following hw issue:
662 * The usb_storage buffer is 63KB, but Linux sends 120KB.
663 * We get the first part, but upon re-enabling receive dma we
664 * get a 'buffer not available' error from the hardware, since
665 * we haven't gotten the next usb_drv_recv() from the stack yet.
666 * It seems the NAK bit is ignored here and the HW tries to dma
667 * the incoming data anyway.
668 * In theory I think the BNA error should be recoverable, but
669 * I haven't figured out how to do that yet and this approach seems
670 * to work for now.
672 static void usb_tick(void)
674 static int rde_timer = 0;
675 static int rde_fails = 0;
677 if (USB_DEV_CTRL & USB_DEV_CTRL_RDE)
678 return;
680 if (!(USB_DEV_STS & USB_DEV_STS_RXF_EMPTY)) {
681 if (rde_timer == 0)
682 logf("usb_tick: fifo got filled\n");
683 rde_timer++;
686 if (rde_timer > 2) {
687 logf("usb_tick: re-enabling RDE\n");
688 USB_DEV_CTRL |= USB_DEV_CTRL_RDE;
689 rde_timer = 0;
690 if (USB_DEV_CTRL & USB_DEV_CTRL_RDE) {
691 rde_fails = 0;
692 } else {
693 rde_fails++;
694 if (rde_fails > 3)
695 panicf("usb_tick: failed to set RDE");
700 /* interrupt service routine */
701 void INT_USB(void)
703 int ep = USB_DEV_EP_INTR & ~USB_DEV_EP_INTR_MASK;
704 int intr = USB_DEV_INTR & ~USB_DEV_INTR_MASK;
706 /* ACK interrupt sources */
707 USB_DEV_EP_INTR = ep;
708 USB_DEV_INTR = intr;
710 /* Handle endpoint interrupts */
711 while (ep) {
712 int onebit = 31-__builtin_clz(ep);
714 if (onebit < 16) handle_in_ep(onebit);
715 else handle_out_ep(onebit-16);
717 ep &= ~(1 << onebit);
720 /* Handle general device interrupts */
721 if (intr) {
722 if (intr & USB_DEV_INTR_SET_INTERFACE) {/* SET_INTERFACE received */
723 logf("set interface\n");
724 panicf("set interface");
725 intr &= ~USB_DEV_INTR_SET_INTERFACE;
727 if (intr & USB_DEV_INTR_SET_CONFIG) {/* SET_CONFIGURATION received */
729 * This is handled in HW, we have to fake a request here
730 * for usb_core.
732 static struct usb_ctrlrequest set_config = {
733 bRequestType: USB_TYPE_STANDARD | USB_RECIP_DEVICE,
734 bRequest: USB_REQ_SET_CONFIGURATION,
735 wValue: 0,
736 wIndex: 0,
737 wLength: 0,
740 logf("set config\n");
741 got_set_configuration = 1;
743 set_config.wValue = USB_DEV_STS & USB_DEV_STS_MASK_CFG;
744 usb_core_control_request(&set_config);
745 intr &= ~USB_DEV_INTR_SET_CONFIG;
747 if (intr & USB_DEV_INTR_EARLY_SUSPEND) {/* idle >3ms detected */
748 logf("usb idle\n");
749 intr &= ~USB_DEV_INTR_EARLY_SUSPEND;
751 if (intr & USB_DEV_INTR_USB_RESET) {/* usb reset from host? */
752 logf("usb reset\n");
753 reset_endpoints(1);
754 usb_core_bus_reset();
755 intr &= ~USB_DEV_INTR_USB_RESET;
757 if (intr & USB_DEV_INTR_USB_SUSPEND) {/* suspend req from host? */
758 logf("usb suspend\n");
759 intr &= ~USB_DEV_INTR_USB_SUSPEND;
761 if (intr & USB_DEV_INTR_SOF) {/* sof received */
762 logf("sof\n");
763 intr &= ~USB_DEV_INTR_SOF;
765 if (intr & USB_DEV_INTR_SVC) {/* device status changed */
766 logf("svc: %08x otg: %08x\n", (int)USB_DEV_STS, (int)USB_OTG_CSR);
767 intr &= ~USB_DEV_INTR_SVC;
769 if (intr & USB_DEV_INTR_ENUM_DONE) {/* speed enumeration complete */
770 int spd = USB_DEV_STS & USB_DEV_STS_MASK_SPD; /* Enumerated Speed */
772 logf("speed enum complete: ");
773 if (spd == USB_DEV_STS_SPD_HS) logf("hs\n");
774 if (spd == USB_DEV_STS_SPD_FS) logf("fs\n");
775 if (spd == USB_DEV_STS_SPD_LS) logf("ls\n");
777 USB_PHY_EP0_INFO = 0x00200000 |
778 USB_CSR_DIR_OUT |
779 USB_CSR_TYPE_CTL;
780 USB_PHY_EP1_INFO = 0x00200000 |
781 USB_CSR_DIR_IN |
782 USB_CSR_TYPE_CTL;
783 USB_PHY_EP2_INFO = 0x00200001 |
784 USB_CSR_DIR_IN |
785 USB_CSR_TYPE_BULK;
786 USB_PHY_EP3_INFO = 0x00200001 |
787 USB_CSR_DIR_IN |
788 USB_CSR_TYPE_BULK;
789 USB_DEV_CTRL |= USB_DEV_CTRL_APCSR_DONE;
790 USB_IEP_CTRL(0) |= USB_EP_CTRL_ACT;
791 USB_OEP_CTRL(0) |= USB_EP_CTRL_ACT;
792 intr &= ~USB_DEV_INTR_ENUM_DONE;
794 if (intr & USB_DEV_INTR_MYSTERY) {
795 logf("got mystery dev intr\n");
796 USB_DEV_INTR_MASK |= USB_DEV_INTR_MYSTERY;
797 intr &= ~USB_DEV_INTR_MYSTERY;
799 if (intr) {
800 logf("usb devirq 0x%x", intr);
801 panicf("usb devirq 0x%x", intr);
806 /* (not essential? , not implemented in usb-tcc.c) */
807 void usb_drv_set_test_mode(int mode)
809 (void)mode;
812 /* handled internally by controller */
813 void usb_drv_set_address(int address)
815 (void)address;
818 void usb_drv_stall(int ep, bool stall, bool in)
820 if (stall) USB_EP_CTRL(ep, in) |= USB_EP_CTRL_STALL;
821 else USB_EP_CTRL(ep, in) &= ~USB_EP_CTRL_STALL;
824 bool usb_drv_stalled(int ep, bool in)
826 return USB_EP_CTRL(ep, in) & USB_EP_CTRL_STALL;
829 #else
831 void usb_attach(void)
835 void usb_drv_init(void)
839 void usb_drv_exit(void)
843 int usb_drv_port_speed(void)
845 return 0;
848 int usb_drv_request_endpoint(int type, int dir)
850 (void)type;
851 (void)dir;
853 return -1;
856 void usb_drv_release_endpoint(int ep)
858 (void)ep;
861 void usb_drv_cancel_all_transfers(void)
865 void usb_drv_set_test_mode(int mode)
867 (void)mode;
870 void usb_drv_set_address(int address)
872 (void)address;
875 int usb_drv_recv(int ep, void *ptr, int len)
877 (void)ep;
878 (void)ptr;
879 (void)len;
881 return -1;
884 int usb_drv_send(int ep, void *ptr, int len)
886 (void)ep;
887 (void)ptr;
888 (void)len;
890 return -1;
893 int usb_drv_send_nonblocking(int ep, void *ptr, int len)
895 (void)ep;
896 (void)ptr;
897 (void)len;
899 return -1;
902 void usb_drv_stall(int ep, bool stall, bool in)
904 (void)ep;
905 (void)stall;
906 (void)in;
909 bool usb_drv_stalled(int ep, bool in)
911 (void)ep;
912 (void)in;
914 return 0;
917 #endif