firmware/target/arm/imx31/gigabeat-s/system-target.h

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2007 by Greg White
  11  *
  12  * All files in this archive are subject to the GNU General Public License.
  13  * See the file COPYING in the source tree root for full license agreement.
  14  *
  15  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  16  * KIND, either express or implied.
  17  *
  18  ****************************************************************************/
  19 #ifndef SYSTEM_TARGET_H
  20 #define SYSTEM_TARGET_H
  21
  22 #include "system-arm.h"
  23 #include "mmu-arm.h"
  24
  25 #define CPUFREQ_NORMAL 532000000
  26
  27 static inline void udelay(unsigned int usecs)
  28 {
  29     volatile signed int stop = EPITCNT1 - usecs;
  30     while ((signed int)EPITCNT1 > stop);
  31 }
  32
  33 #define __dbg_hw_info(...) 0
  34 #define __dbg_ports(...) 0
  35
  36 void system_prepare_fw_start(void);
  37 void tick_stop(void);
  38 void kernel_device_init(void);
  39
  40 #define KDEV_INIT
  41
  42 #define HAVE_INVALIDATE_ICACHE
  43 static inline void invalidate_icache(void)
  44 {
  45     asm volatile(
  46         /* Clean and invalidate entire data cache */
  47         "mcr p15, 0, %0, c7, c14, 0 \n"
  48         /* Invalidate entire instruction cache */
  49         "mcr p15, 0, %0, c7, c5, 0  \n"
  50         : : "r"(0)
  51     );
  52 }
  53
  54 #define HAVE_FLUSH_ICACHE
  55 static inline void flush_icache(void)
  56 {
  57     asm volatile (
  58         /* Clean entire data cache */
  59         "mcr p15, 0, %0, c7, c10, 0 \n"
  60         : : "r"(0)
  61     );
  62 }
  63
  64 struct ARM_REGS {
  65         int r0;
  66         int r1;
  67         int r2;
  68         int r3;
  69         int r4;
  70         int r5;
  71         int r6;
  72         int r7;
  73         int r8;
  74         int r9;
  75         int r10;
  76         int r11;
  77         int r12;
  78         int sp;
  79         int lr;
  80         int pc;
  81         int cpsr;
  82 } regs;
  83
  84 inline void dumpregs(void);
  85
  86 #endif /* SYSTEM_TARGET_H */