Ingenic Jz4740: fix CPU boosting (was reversed)
[kugel-rb.git] / utils / jz4740_tools / jz4740.h
blob87b400e3b98c6bc6d77a02ab46d5f2baf30c6e50
1 /*
2 * Include file for Ingenic Semiconductor's JZ4740 CPU.
3 */
4 #ifndef __JZ4740_H__
5 #define __JZ4740_H__
7 #define REG8(addr) (addr)
8 #define REG16(addr) (addr)
9 #define REG32(addr) (addr)
11 //----------------------------------------------------------------------
12 // Boot ROM Specification
15 /* NOR Boot config */
16 #define JZ4740_NORBOOT_8BIT 0x00000000 /* 8-bit data bus flash */
17 #define JZ4740_NORBOOT_16BIT 0x10101010 /* 16-bit data bus flash */
18 #define JZ4740_NORBOOT_32BIT 0x20202020 /* 32-bit data bus flash */
20 /* NAND Boot config */
21 #define JZ4740_NANDBOOT_B8R3 0xffffffff /* 8-bit bus & 3 row cycles */
22 #define JZ4740_NANDBOOT_B8R2 0xf0f0f0f0 /* 8-bit bus & 2 row cycles */
23 #define JZ4740_NANDBOOT_B16R3 0x0f0f0f0f /* 16-bit bus & 3 row cycles */
24 #define JZ4740_NANDBOOT_B16R2 0x00000000 /* 16-bit bus & 2 row cycles */
27 //----------------------------------------------------------------------
28 // Register Definitions
30 #define CPM_BASE 0xB0000000
31 #define INTC_BASE 0xB0001000
32 #define TCU_BASE 0xB0002000
33 #define WDT_BASE 0xB0002000
34 #define RTC_BASE 0xB0003000
35 #define GPIO_BASE 0xB0010000
36 #define AIC_BASE 0xB0020000
37 #define ICDC_BASE 0xB0020000
38 #define MSC_BASE 0xB0021000
39 #define UART0_BASE 0xB0030000
40 #define I2C_BASE 0xB0042000
41 #define SSI_BASE 0xB0043000
42 #define SADC_BASE 0xB0070000
43 #define EMC_BASE 0xB3010000
44 #define DMAC_BASE 0xB3020000
45 #define UHC_BASE 0xB3030000
46 #define UDC_BASE 0xB3040000
47 #define LCD_BASE 0xB3050000
48 #define SLCD_BASE 0xB3050000
49 #define CIM_BASE 0xB3060000
50 #define ETH_BASE 0xB3100000
53 /*************************************************************************
54 * INTC (Interrupt Controller)
55 *************************************************************************/
56 #define INTC_ISR (INTC_BASE + 0x00)
57 #define INTC_IMR (INTC_BASE + 0x04)
58 #define INTC_IMSR (INTC_BASE + 0x08)
59 #define INTC_IMCR (INTC_BASE + 0x0c)
60 #define INTC_IPR (INTC_BASE + 0x10)
62 #define REG_INTC_ISR REG32(INTC_ISR)
63 #define REG_INTC_IMR REG32(INTC_IMR)
64 #define REG_INTC_IMSR REG32(INTC_IMSR)
65 #define REG_INTC_IMCR REG32(INTC_IMCR)
66 #define REG_INTC_IPR REG32(INTC_IPR)
68 // 1st-level interrupts
69 #define IRQ_I2C 1
70 #define IRQ_UHC 3
71 #define IRQ_UART0 9
72 #define IRQ_SADC 12
73 #define IRQ_MSC 14
74 #define IRQ_RTC 15
75 #define IRQ_SSI 16
76 #define IRQ_CIM 17
77 #define IRQ_AIC 18
78 #define IRQ_ETH 19
79 #define IRQ_DMAC 20
80 #define IRQ_TCU2 21
81 #define IRQ_TCU1 22
82 #define IRQ_TCU0 23
83 #define IRQ_UDC 24
84 #define IRQ_GPIO3 25
85 #define IRQ_GPIO2 26
86 #define IRQ_GPIO1 27
87 #define IRQ_GPIO0 28
88 #define IRQ_IPU 29
89 #define IRQ_LCD 30
91 // 2nd-level interrupts
92 #define IRQ_DMA_0 32 /* 32 to 37 for DMAC channel 0 to 5 */
93 #define IRQ_GPIO_0 48 /* 48 to 175 for GPIO pin 0 to 127 */
96 /*************************************************************************
97 * RTC
98 *************************************************************************/
99 #define RTC_RCR (RTC_BASE + 0x00) /* RTC Control Register */
100 #define RTC_RSR (RTC_BASE + 0x04) /* RTC Second Register */
101 #define RTC_RSAR (RTC_BASE + 0x08) /* RTC Second Alarm Register */
102 #define RTC_RGR (RTC_BASE + 0x0c) /* RTC Regulator Register */
104 #define RTC_HCR (RTC_BASE + 0x20) /* Hibernate Control Register */
105 #define RTC_HWFCR (RTC_BASE + 0x24) /* Hibernate Wakeup Filter Counter Reg */
106 #define RTC_HRCR (RTC_BASE + 0x28) /* Hibernate Reset Counter Register */
107 #define RTC_HWCR (RTC_BASE + 0x2c) /* Hibernate Wakeup Control Register */
108 #define RTC_HWSR (RTC_BASE + 0x30) /* Hibernate Wakeup Status Register */
110 #define REG_RTC_RCR REG32(RTC_RCR)
111 #define REG_RTC_RSR REG32(RTC_RSR)
112 #define REG_RTC_RSAR REG32(RTC_RSAR)
113 #define REG_RTC_RGR REG32(RTC_RGR)
114 #define REG_RTC_HCR REG32(RTC_HCR)
115 #define REG_RTC_HWFCR REG32(RTC_HWFCR)
116 #define REG_RTC_HRCR REG32(RTC_HRCR)
117 #define REG_RTC_HWCR REG32(RTC_HWCR)
118 #define REG_RTC_HWSR REG32(RTC_HWSR)
120 /* RTC Control Register */
121 #define RTC_RCR_WRDY (1 << 7) /* Write Ready Flag */
122 #define RTC_RCR_HZ (1 << 6) /* 1Hz Flag */
123 #define RTC_RCR_HZIE (1 << 5) /* 1Hz Interrupt Enable */
124 #define RTC_RCR_AF (1 << 4) /* Alarm Flag */
125 #define RTC_RCR_AIE (1 << 3) /* Alarm Interrupt Enable */
126 #define RTC_RCR_AE (1 << 2) /* Alarm Enable */
127 #define RTC_RCR_RTCE (1 << 0) /* RTC Enable */
129 /* RTC Regulator Register */
130 #define RTC_RGR_LOCK (1 << 31) /* Lock Bit */
131 #define RTC_RGR_ADJC_BIT 16
132 #define RTC_RGR_ADJC_MASK (0x3ff << RTC_RGR_ADJC_BIT)
133 #define RTC_RGR_NC1HZ_BIT 0
134 #define RTC_REG_NC1HZ_MASK (0xffff << RTC_RGR_NC1HZ_BIT)
136 /* Hibernate Control Register */
137 #define RTC_HCR_PD (1 << 0) /* Power Down */
139 /* Hibernate Wakeup Filter Counter Register */
140 #define RTC_HWFCR_BIT 5
141 #define RTC_HWFCR_MASK (0x7ff << RTC_HWFCR_BIT)
143 /* Hibernate Reset Counter Register */
144 #define RTC_HRCR_BIT 5
145 #define RTC_HRCR_MASK (0x7f << RTC_HRCR_BIT)
147 /* Hibernate Wakeup Control Register */
148 #define RTC_HWCR_WL (1 << 2) /* Wakeup pin level: 0-low 1-high */
149 #define RTC_HWCR_EPIN (1 << 1) /* Wakeup pin wakeup enable */
150 #define RTC_HWCR_EALM (1 << 0) /* RTC alarm wakeup enable */
152 /* Hibernate Wakeup Status Register */
153 #define RTC_HWSR_HR (1 << 5) /* Hibernate reset */
154 #define RTC_HWSR_POR (1 << 4) /* POR reset */
155 #define RTC_HWSR_PIN (1 << 1) /* Wakeup pin status bit */
156 #define RTC_HWSR_ALM (1 << 0) /* RTC alarm status bit */
159 /*************************************************************************
160 * CPM (Clock reset and Power control Management)
161 *************************************************************************/
162 #define CPM_CPCCR (CPM_BASE+0x00)
163 #define CPM_CPPCR (CPM_BASE+0x10)
164 #define CPM_I2SCDR (CPM_BASE+0x60)
165 #define CPM_LPCDR (CPM_BASE+0x64)
166 #define CPM_MSCCDR (CPM_BASE+0x68)
167 #define CPM_UHCCDR (CPM_BASE+0x6C)
169 #define CPM_LCR (CPM_BASE+0x04)
170 #define CPM_CLKGR (CPM_BASE+0x20)
171 #define CPM_SCR (CPM_BASE+0x24)
173 #define CPM_HCR (CPM_BASE+0x30)
174 #define CPM_HWFCR (CPM_BASE+0x34)
175 #define CPM_HRCR (CPM_BASE+0x38)
176 #define CPM_HWCR (CPM_BASE+0x3c)
177 #define CPM_HWSR (CPM_BASE+0x40)
178 #define CPM_HSPR (CPM_BASE+0x44)
180 #define CPM_RSR (CPM_BASE+0x08)
183 #define REG_CPM_CPCCR REG32(CPM_CPCCR)
184 #define REG_CPM_CPPCR REG32(CPM_CPPCR)
185 #define REG_CPM_I2SCDR REG32(CPM_I2SCDR)
186 #define REG_CPM_LPCDR REG32(CPM_LPCDR)
187 #define REG_CPM_MSCCDR REG32(CPM_MSCCDR)
188 #define REG_CPM_UHCCDR REG32(CPM_UHCCDR)
190 #define REG_CPM_LCR REG32(CPM_LCR)
191 #define REG_CPM_CLKGR REG32(CPM_CLKGR)
192 #define REG_CPM_SCR REG32(CPM_SCR)
193 #define REG_CPM_HCR REG32(CPM_HCR)
194 #define REG_CPM_HWFCR REG32(CPM_HWFCR)
195 #define REG_CPM_HRCR REG32(CPM_HRCR)
196 #define REG_CPM_HWCR REG32(CPM_HWCR)
197 #define REG_CPM_HWSR REG32(CPM_HWSR)
198 #define REG_CPM_HSPR REG32(CPM_HSPR)
200 #define REG_CPM_RSR REG32(CPM_RSR)
203 /* Clock Control Register */
204 #define CPM_CPCCR_I2CS (1 << 31)
205 #define CPM_CPCCR_CLKOEN (1 << 30)
206 #define CPM_CPCCR_UCS (1 << 29)
207 #define CPM_CPCCR_UDIV_BIT 23
208 #define CPM_CPCCR_UDIV_MASK (0x3f << CPM_CPCCR_UDIV_BIT)
209 #define CPM_CPCCR_CE (1 << 22)
210 #define CPM_CPCCR_PCS (1 << 21)
211 #define CPM_CPCCR_LDIV_BIT 16
212 #define CPM_CPCCR_LDIV_MASK (0x1f << CPM_CPCCR_LDIV_BIT)
213 #define CPM_CPCCR_MDIV_BIT 12
214 #define CPM_CPCCR_MDIV_MASK (0x0f << CPM_CPCCR_MDIV_BIT)
215 #define CPM_CPCCR_PDIV_BIT 8
216 #define CPM_CPCCR_PDIV_MASK (0x0f << CPM_CPCCR_PDIV_BIT)
217 #define CPM_CPCCR_HDIV_BIT 4
218 #define CPM_CPCCR_HDIV_MASK (0x0f << CPM_CPCCR_HDIV_BIT)
219 #define CPM_CPCCR_CDIV_BIT 0
220 #define CPM_CPCCR_CDIV_MASK (0x0f << CPM_CPCCR_CDIV_BIT)
222 /* I2S Clock Divider Register */
223 #define CPM_I2SCDR_I2SDIV_BIT 0
224 #define CPM_I2SCDR_I2SDIV_MASK (0x1ff << CPM_I2SCDR_I2SDIV_BIT)
226 /* LCD Pixel Clock Divider Register */
227 #define CPM_LPCDR_PIXDIV_BIT 0
228 #define CPM_LPCDR_PIXDIV_MASK (0x1ff << CPM_LPCDR_PIXDIV_BIT)
230 /* MSC Clock Divider Register */
231 #define CPM_MSCCDR_MSCDIV_BIT 0
232 #define CPM_MSCCDR_MSCDIV_MASK (0x1f << CPM_MSCCDR_MSCDIV_BIT)
234 /* PLL Control Register */
235 #define CPM_CPPCR_PLLM_BIT 23
236 #define CPM_CPPCR_PLLM_MASK (0x1ff << CPM_CPPCR_PLLM_BIT)
237 #define CPM_CPPCR_PLLN_BIT 18
238 #define CPM_CPPCR_PLLN_MASK (0x1f << CPM_CPPCR_PLLN_BIT)
239 #define CPM_CPPCR_PLLOD_BIT 16
240 #define CPM_CPPCR_PLLOD_MASK (0x03 << CPM_CPPCR_PLLOD_BIT)
241 #define CPM_CPPCR_PLLS (1 << 10)
242 #define CPM_CPPCR_PLLBP (1 << 9)
243 #define CPM_CPPCR_PLLEN (1 << 8)
244 #define CPM_CPPCR_PLLST_BIT 0
245 #define CPM_CPPCR_PLLST_MASK (0xff << CPM_CPPCR_PLLST_BIT)
247 /* Low Power Control Register */
248 #define CPM_LCR_DOZE_DUTY_BIT 3
249 #define CPM_LCR_DOZE_DUTY_MASK (0x1f << CPM_LCR_DOZE_DUTY_BIT)
250 #define CPM_LCR_DOZE_ON (1 << 2)
251 #define CPM_LCR_LPM_BIT 0
252 #define CPM_LCR_LPM_MASK (0x3 << CPM_LCR_LPM_BIT)
253 #define CPM_LCR_LPM_IDLE (0x0 << CPM_LCR_LPM_BIT)
254 #define CPM_LCR_LPM_SLEEP (0x1 << CPM_LCR_LPM_BIT)
256 /* Clock Gate Register */
257 #define CPM_CLKGR_UART1 (1 << 15)
258 #define CPM_CLKGR_UHC (1 << 14)
259 #define CPM_CLKGR_IPU (1 << 13)
260 #define CPM_CLKGR_DMAC (1 << 12)
261 #define CPM_CLKGR_UDC (1 << 11)
262 #define CPM_CLKGR_LCD (1 << 10)
263 #define CPM_CLKGR_CIM (1 << 9)
264 #define CPM_CLKGR_SADC (1 << 8)
265 #define CPM_CLKGR_MSC (1 << 7)
266 #define CPM_CLKGR_AIC1 (1 << 6)
267 #define CPM_CLKGR_AIC2 (1 << 5)
268 #define CPM_CLKGR_SSI (1 << 4)
269 #define CPM_CLKGR_I2C (1 << 3)
270 #define CPM_CLKGR_RTC (1 << 2)
271 #define CPM_CLKGR_TCU (1 << 1)
272 #define CPM_CLKGR_UART0 (1 << 0)
274 /* Sleep Control Register */
275 #define CPM_SCR_O1ST_BIT 8
276 #define CPM_SCR_O1ST_MASK (0xff << CPM_SCR_O1ST_BIT)
277 #define CPM_SCR_USBPHY_ENABLE (1 << 6)
278 #define CPM_SCR_OSC_ENABLE (1 << 4)
280 /* Hibernate Control Register */
281 #define CPM_HCR_PD (1 << 0)
283 /* Wakeup Filter Counter Register in Hibernate Mode */
284 #define CPM_HWFCR_TIME_BIT 0
285 #define CPM_HWFCR_TIME_MASK (0x3ff << CPM_HWFCR_TIME_BIT)
287 /* Reset Counter Register in Hibernate Mode */
288 #define CPM_HRCR_TIME_BIT 0
289 #define CPM_HRCR_TIME_MASK (0x7f << CPM_HRCR_TIME_BIT)
291 /* Wakeup Control Register in Hibernate Mode */
292 #define CPM_HWCR_WLE_LOW (0 << 2)
293 #define CPM_HWCR_WLE_HIGH (1 << 2)
294 #define CPM_HWCR_PIN_WAKEUP (1 << 1)
295 #define CPM_HWCR_RTC_WAKEUP (1 << 0)
297 /* Wakeup Status Register in Hibernate Mode */
298 #define CPM_HWSR_WSR_PIN (1 << 1)
299 #define CPM_HWSR_WSR_RTC (1 << 0)
301 /* Reset Status Register */
302 #define CPM_RSR_HR (1 << 2)
303 #define CPM_RSR_WR (1 << 1)
304 #define CPM_RSR_PR (1 << 0)
307 /*************************************************************************
308 * TCU (Timer Counter Unit)
309 *************************************************************************/
310 #define TCU_TSR (TCU_BASE + 0x1C) /* Timer Stop Register */
311 #define TCU_TSSR (TCU_BASE + 0x2C) /* Timer Stop Set Register */
312 #define TCU_TSCR (TCU_BASE + 0x3C) /* Timer Stop Clear Register */
313 #define TCU_TER (TCU_BASE + 0x10) /* Timer Counter Enable Register */
314 #define TCU_TESR (TCU_BASE + 0x14) /* Timer Counter Enable Set Register */
315 #define TCU_TECR (TCU_BASE + 0x18) /* Timer Counter Enable Clear Register */
316 #define TCU_TFR (TCU_BASE + 0x20) /* Timer Flag Register */
317 #define TCU_TFSR (TCU_BASE + 0x24) /* Timer Flag Set Register */
318 #define TCU_TFCR (TCU_BASE + 0x28) /* Timer Flag Clear Register */
319 #define TCU_TMR (TCU_BASE + 0x30) /* Timer Mask Register */
320 #define TCU_TMSR (TCU_BASE + 0x34) /* Timer Mask Set Register */
321 #define TCU_TMCR (TCU_BASE + 0x38) /* Timer Mask Clear Register */
322 #define TCU_TDFR0 (TCU_BASE + 0x40) /* Timer Data Full Register */
323 #define TCU_TDHR0 (TCU_BASE + 0x44) /* Timer Data Half Register */
324 #define TCU_TCNT0 (TCU_BASE + 0x48) /* Timer Counter Register */
325 #define TCU_TCSR0 (TCU_BASE + 0x4C) /* Timer Control Register */
326 #define TCU_TDFR1 (TCU_BASE + 0x50)
327 #define TCU_TDHR1 (TCU_BASE + 0x54)
328 #define TCU_TCNT1 (TCU_BASE + 0x58)
329 #define TCU_TCSR1 (TCU_BASE + 0x5C)
330 #define TCU_TDFR2 (TCU_BASE + 0x60)
331 #define TCU_TDHR2 (TCU_BASE + 0x64)
332 #define TCU_TCNT2 (TCU_BASE + 0x68)
333 #define TCU_TCSR2 (TCU_BASE + 0x6C)
334 #define TCU_TDFR3 (TCU_BASE + 0x70)
335 #define TCU_TDHR3 (TCU_BASE + 0x74)
336 #define TCU_TCNT3 (TCU_BASE + 0x78)
337 #define TCU_TCSR3 (TCU_BASE + 0x7C)
338 #define TCU_TDFR4 (TCU_BASE + 0x80)
339 #define TCU_TDHR4 (TCU_BASE + 0x84)
340 #define TCU_TCNT4 (TCU_BASE + 0x88)
341 #define TCU_TCSR4 (TCU_BASE + 0x8C)
342 #define TCU_TDFR5 (TCU_BASE + 0x90)
343 #define TCU_TDHR5 (TCU_BASE + 0x94)
344 #define TCU_TCNT5 (TCU_BASE + 0x98)
345 #define TCU_TCSR5 (TCU_BASE + 0x9C)
347 #define REG_TCU_TSR REG32(TCU_TSR)
348 #define REG_TCU_TSSR REG32(TCU_TSSR)
349 #define REG_TCU_TSCR REG32(TCU_TSCR)
350 #define REG_TCU_TER REG8(TCU_TER)
351 #define REG_TCU_TESR REG8(TCU_TESR)
352 #define REG_TCU_TECR REG8(TCU_TECR)
353 #define REG_TCU_TFR REG32(TCU_TFR)
354 #define REG_TCU_TFSR REG32(TCU_TFSR)
355 #define REG_TCU_TFCR REG32(TCU_TFCR)
356 #define REG_TCU_TMR REG32(TCU_TMR)
357 #define REG_TCU_TMSR REG32(TCU_TMSR)
358 #define REG_TCU_TMCR REG32(TCU_TMCR)
359 #define REG_TCU_TDFR0 REG16(TCU_TDFR0)
360 #define REG_TCU_TDHR0 REG16(TCU_TDHR0)
361 #define REG_TCU_TCNT0 REG16(TCU_TCNT0)
362 #define REG_TCU_TCSR0 REG16(TCU_TCSR0)
363 #define REG_TCU_TDFR1 REG16(TCU_TDFR1)
364 #define REG_TCU_TDHR1 REG16(TCU_TDHR1)
365 #define REG_TCU_TCNT1 REG16(TCU_TCNT1)
366 #define REG_TCU_TCSR1 REG16(TCU_TCSR1)
367 #define REG_TCU_TDFR2 REG16(TCU_TDFR2)
368 #define REG_TCU_TDHR2 REG16(TCU_TDHR2)
369 #define REG_TCU_TCNT2 REG16(TCU_TCNT2)
370 #define REG_TCU_TCSR2 REG16(TCU_TCSR2)
371 #define REG_TCU_TDFR3 REG16(TCU_TDFR3)
372 #define REG_TCU_TDHR3 REG16(TCU_TDHR3)
373 #define REG_TCU_TCNT3 REG16(TCU_TCNT3)
374 #define REG_TCU_TCSR3 REG16(TCU_TCSR3)
375 #define REG_TCU_TDFR4 REG16(TCU_TDFR4)
376 #define REG_TCU_TDHR4 REG16(TCU_TDHR4)
377 #define REG_TCU_TCNT4 REG16(TCU_TCNT4)
378 #define REG_TCU_TCSR4 REG16(TCU_TCSR4)
380 // n = 0,1,2,3,4,5
381 #define TCU_TDFR(n) (TCU_BASE + (0x40 + (n)*0x10)) /* Timer Data Full Reg */
382 #define TCU_TDHR(n) (TCU_BASE + (0x44 + (n)*0x10)) /* Timer Data Half Reg */
383 #define TCU_TCNT(n) (TCU_BASE + (0x48 + (n)*0x10)) /* Timer Counter Reg */
384 #define TCU_TCSR(n) (TCU_BASE + (0x4C + (n)*0x10)) /* Timer Control Reg */
386 #define REG_TCU_TDFR(n) REG16(TCU_TDFR((n)))
387 #define REG_TCU_TDHR(n) REG16(TCU_TDHR((n)))
388 #define REG_TCU_TCNT(n) REG16(TCU_TCNT((n)))
389 #define REG_TCU_TCSR(n) REG16(TCU_TCSR((n)))
391 // Register definitions
392 #define TCU_TCSR_PWM_SD (1 << 9)
393 #define TCU_TCSR_PWM_INITL_HIGH (1 << 8)
394 #define TCU_TCSR_PWM_EN (1 << 7)
395 #define TCU_TCSR_PRESCALE_BIT 3
396 #define TCU_TCSR_PRESCALE_MASK (0x7 << TCU_TCSR_PRESCALE_BIT)
397 #define TCU_TCSR_PRESCALE1 (0x0 << TCU_TCSR_PRESCALE_BIT)
398 #define TCU_TCSR_PRESCALE4 (0x1 << TCU_TCSR_PRESCALE_BIT)
399 #define TCU_TCSR_PRESCALE16 (0x2 << TCU_TCSR_PRESCALE_BIT)
400 #define TCU_TCSR_PRESCALE64 (0x3 << TCU_TCSR_PRESCALE_BIT)
401 #define TCU_TCSR_PRESCALE256 (0x4 << TCU_TCSR_PRESCALE_BIT)
402 #define TCU_TCSR_PRESCALE1024 (0x5 << TCU_TCSR_PRESCALE_BIT)
403 #define TCU_TCSR_EXT_EN (1 << 2)
404 #define TCU_TCSR_RTC_EN (1 << 1)
405 #define TCU_TCSR_PCK_EN (1 << 0)
407 #define TCU_TER_TCEN5 (1 << 5)
408 #define TCU_TER_TCEN4 (1 << 4)
409 #define TCU_TER_TCEN3 (1 << 3)
410 #define TCU_TER_TCEN2 (1 << 2)
411 #define TCU_TER_TCEN1 (1 << 1)
412 #define TCU_TER_TCEN0 (1 << 0)
414 #define TCU_TESR_TCST5 (1 << 5)
415 #define TCU_TESR_TCST4 (1 << 4)
416 #define TCU_TESR_TCST3 (1 << 3)
417 #define TCU_TESR_TCST2 (1 << 2)
418 #define TCU_TESR_TCST1 (1 << 1)
419 #define TCU_TESR_TCST0 (1 << 0)
421 #define TCU_TECR_TCCL5 (1 << 5)
422 #define TCU_TECR_TCCL4 (1 << 4)
423 #define TCU_TECR_TCCL3 (1 << 3)
424 #define TCU_TECR_TCCL2 (1 << 2)
425 #define TCU_TECR_TCCL1 (1 << 1)
426 #define TCU_TECR_TCCL0 (1 << 0)
428 #define TCU_TFR_HFLAG5 (1 << 21)
429 #define TCU_TFR_HFLAG4 (1 << 20)
430 #define TCU_TFR_HFLAG3 (1 << 19)
431 #define TCU_TFR_HFLAG2 (1 << 18)
432 #define TCU_TFR_HFLAG1 (1 << 17)
433 #define TCU_TFR_HFLAG0 (1 << 16)
434 #define TCU_TFR_FFLAG5 (1 << 5)
435 #define TCU_TFR_FFLAG4 (1 << 4)
436 #define TCU_TFR_FFLAG3 (1 << 3)
437 #define TCU_TFR_FFLAG2 (1 << 2)
438 #define TCU_TFR_FFLAG1 (1 << 1)
439 #define TCU_TFR_FFLAG0 (1 << 0)
441 #define TCU_TFSR_HFLAG5 (1 << 21)
442 #define TCU_TFSR_HFLAG4 (1 << 20)
443 #define TCU_TFSR_HFLAG3 (1 << 19)
444 #define TCU_TFSR_HFLAG2 (1 << 18)
445 #define TCU_TFSR_HFLAG1 (1 << 17)
446 #define TCU_TFSR_HFLAG0 (1 << 16)
447 #define TCU_TFSR_FFLAG5 (1 << 5)
448 #define TCU_TFSR_FFLAG4 (1 << 4)
449 #define TCU_TFSR_FFLAG3 (1 << 3)
450 #define TCU_TFSR_FFLAG2 (1 << 2)
451 #define TCU_TFSR_FFLAG1 (1 << 1)
452 #define TCU_TFSR_FFLAG0 (1 << 0)
454 #define TCU_TFCR_HFLAG5 (1 << 21)
455 #define TCU_TFCR_HFLAG4 (1 << 20)
456 #define TCU_TFCR_HFLAG3 (1 << 19)
457 #define TCU_TFCR_HFLAG2 (1 << 18)
458 #define TCU_TFCR_HFLAG1 (1 << 17)
459 #define TCU_TFCR_HFLAG0 (1 << 16)
460 #define TCU_TFCR_FFLAG5 (1 << 5)
461 #define TCU_TFCR_FFLAG4 (1 << 4)
462 #define TCU_TFCR_FFLAG3 (1 << 3)
463 #define TCU_TFCR_FFLAG2 (1 << 2)
464 #define TCU_TFCR_FFLAG1 (1 << 1)
465 #define TCU_TFCR_FFLAG0 (1 << 0)
467 #define TCU_TMR_HMASK5 (1 << 21)
468 #define TCU_TMR_HMASK4 (1 << 20)
469 #define TCU_TMR_HMASK3 (1 << 19)
470 #define TCU_TMR_HMASK2 (1 << 18)
471 #define TCU_TMR_HMASK1 (1 << 17)
472 #define TCU_TMR_HMASK0 (1 << 16)
473 #define TCU_TMR_FMASK5 (1 << 5)
474 #define TCU_TMR_FMASK4 (1 << 4)
475 #define TCU_TMR_FMASK3 (1 << 3)
476 #define TCU_TMR_FMASK2 (1 << 2)
477 #define TCU_TMR_FMASK1 (1 << 1)
478 #define TCU_TMR_FMASK0 (1 << 0)
480 #define TCU_TMSR_HMST5 (1 << 21)
481 #define TCU_TMSR_HMST4 (1 << 20)
482 #define TCU_TMSR_HMST3 (1 << 19)
483 #define TCU_TMSR_HMST2 (1 << 18)
484 #define TCU_TMSR_HMST1 (1 << 17)
485 #define TCU_TMSR_HMST0 (1 << 16)
486 #define TCU_TMSR_FMST5 (1 << 5)
487 #define TCU_TMSR_FMST4 (1 << 4)
488 #define TCU_TMSR_FMST3 (1 << 3)
489 #define TCU_TMSR_FMST2 (1 << 2)
490 #define TCU_TMSR_FMST1 (1 << 1)
491 #define TCU_TMSR_FMST0 (1 << 0)
493 #define TCU_TMCR_HMCL5 (1 << 21)
494 #define TCU_TMCR_HMCL4 (1 << 20)
495 #define TCU_TMCR_HMCL3 (1 << 19)
496 #define TCU_TMCR_HMCL2 (1 << 18)
497 #define TCU_TMCR_HMCL1 (1 << 17)
498 #define TCU_TMCR_HMCL0 (1 << 16)
499 #define TCU_TMCR_FMCL5 (1 << 5)
500 #define TCU_TMCR_FMCL4 (1 << 4)
501 #define TCU_TMCR_FMCL3 (1 << 3)
502 #define TCU_TMCR_FMCL2 (1 << 2)
503 #define TCU_TMCR_FMCL1 (1 << 1)
504 #define TCU_TMCR_FMCL0 (1 << 0)
506 #define TCU_TSR_WDTS (1 << 16)
507 #define TCU_TSR_STOP5 (1 << 5)
508 #define TCU_TSR_STOP4 (1 << 4)
509 #define TCU_TSR_STOP3 (1 << 3)
510 #define TCU_TSR_STOP2 (1 << 2)
511 #define TCU_TSR_STOP1 (1 << 1)
512 #define TCU_TSR_STOP0 (1 << 0)
514 #define TCU_TSSR_WDTSS (1 << 16)
515 #define TCU_TSSR_STPS5 (1 << 5)
516 #define TCU_TSSR_STPS4 (1 << 4)
517 #define TCU_TSSR_STPS3 (1 << 3)
518 #define TCU_TSSR_STPS2 (1 << 2)
519 #define TCU_TSSR_STPS1 (1 << 1)
520 #define TCU_TSSR_STPS0 (1 << 0)
522 #define TCU_TSSR_WDTSC (1 << 16)
523 #define TCU_TSSR_STPC5 (1 << 5)
524 #define TCU_TSSR_STPC4 (1 << 4)
525 #define TCU_TSSR_STPC3 (1 << 3)
526 #define TCU_TSSR_STPC2 (1 << 2)
527 #define TCU_TSSR_STPC1 (1 << 1)
528 #define TCU_TSSR_STPC0 (1 << 0)
531 /*************************************************************************
532 * WDT (WatchDog Timer)
533 *************************************************************************/
534 #define WDT_TDR (WDT_BASE + 0x00)
535 #define WDT_TCER (WDT_BASE + 0x04)
536 #define WDT_TCNT (WDT_BASE + 0x08)
537 #define WDT_TCSR (WDT_BASE + 0x0C)
539 #define REG_WDT_TDR REG16(WDT_TDR)
540 #define REG_WDT_TCER REG8(WDT_TCER)
541 #define REG_WDT_TCNT REG16(WDT_TCNT)
542 #define REG_WDT_TCSR REG16(WDT_TCSR)
544 // Register definition
545 #define WDT_TCSR_PRESCALE_BIT 3
546 #define WDT_TCSR_PRESCALE_MASK (0x7 << WDT_TCSR_PRESCALE_BIT)
547 #define WDT_TCSR_PRESCALE1 (0x0 << WDT_TCSR_PRESCALE_BIT)
548 #define WDT_TCSR_PRESCALE4 (0x1 << WDT_TCSR_PRESCALE_BIT)
549 #define WDT_TCSR_PRESCALE16 (0x2 << WDT_TCSR_PRESCALE_BIT)
550 #define WDT_TCSR_PRESCALE64 (0x3 << WDT_TCSR_PRESCALE_BIT)
551 #define WDT_TCSR_PRESCALE256 (0x4 << WDT_TCSR_PRESCALE_BIT)
552 #define WDT_TCSR_PRESCALE1024 (0x5 << WDT_TCSR_PRESCALE_BIT)
553 #define WDT_TCSR_EXT_EN (1 << 2)
554 #define WDT_TCSR_RTC_EN (1 << 1)
555 #define WDT_TCSR_PCK_EN (1 << 0)
557 #define WDT_TCER_TCEN (1 << 0)
560 /*************************************************************************
561 * DMAC (DMA Controller)
562 *************************************************************************/
564 #define MAX_DMA_NUM 6 /* max 6 channels */
566 #define DMAC_DSAR(n) (DMAC_BASE + (0x00 + (n) * 0x20)) /* DMA source address */
567 #define DMAC_DTAR(n) (DMAC_BASE + (0x04 + (n) * 0x20)) /* DMA target address */
568 #define DMAC_DTCR(n) (DMAC_BASE + (0x08 + (n) * 0x20)) /* DMA transfer count */
569 #define DMAC_DRSR(n) (DMAC_BASE + (0x0c + (n) * 0x20)) /* DMA request source */
570 #define DMAC_DCCSR(n) (DMAC_BASE + (0x10 + (n) * 0x20)) /* DMA control/status */
571 #define DMAC_DCMD(n) (DMAC_BASE + (0x14 + (n) * 0x20)) /* DMA command */
572 #define DMAC_DDA(n) (DMAC_BASE + (0x18 + (n) * 0x20)) /* DMA descriptor address */
573 #define DMAC_DMACR (DMAC_BASE + 0x0300) /* DMA control register */
574 #define DMAC_DMAIPR (DMAC_BASE + 0x0304) /* DMA interrupt pending */
575 #define DMAC_DMADBR (DMAC_BASE + 0x0308) /* DMA doorbell */
576 #define DMAC_DMADBSR (DMAC_BASE + 0x030C) /* DMA doorbell set */
578 // channel 0
579 #define DMAC_DSAR0 DMAC_DSAR(0)
580 #define DMAC_DTAR0 DMAC_DTAR(0)
581 #define DMAC_DTCR0 DMAC_DTCR(0)
582 #define DMAC_DRSR0 DMAC_DRSR(0)
583 #define DMAC_DCCSR0 DMAC_DCCSR(0)
584 #define DMAC_DCMD0 DMAC_DCMD(0)
585 #define DMAC_DDA0 DMAC_DDA(0)
587 // channel 1
588 #define DMAC_DSAR1 DMAC_DSAR(1)
589 #define DMAC_DTAR1 DMAC_DTAR(1)
590 #define DMAC_DTCR1 DMAC_DTCR(1)
591 #define DMAC_DRSR1 DMAC_DRSR(1)
592 #define DMAC_DCCSR1 DMAC_DCCSR(1)
593 #define DMAC_DCMD1 DMAC_DCMD(1)
594 #define DMAC_DDA1 DMAC_DDA(1)
596 // channel 2
597 #define DMAC_DSAR2 DMAC_DSAR(2)
598 #define DMAC_DTAR2 DMAC_DTAR(2)
599 #define DMAC_DTCR2 DMAC_DTCR(2)
600 #define DMAC_DRSR2 DMAC_DRSR(2)
601 #define DMAC_DCCSR2 DMAC_DCCSR(2)
602 #define DMAC_DCMD2 DMAC_DCMD(2)
603 #define DMAC_DDA2 DMAC_DDA(2)
605 // channel 3
606 #define DMAC_DSAR3 DMAC_DSAR(3)
607 #define DMAC_DTAR3 DMAC_DTAR(3)
608 #define DMAC_DTCR3 DMAC_DTCR(3)
609 #define DMAC_DRSR3 DMAC_DRSR(3)
610 #define DMAC_DCCSR3 DMAC_DCCSR(3)
611 #define DMAC_DCMD3 DMAC_DCMD(3)
612 #define DMAC_DDA3 DMAC_DDA(3)
614 // channel 4
615 #define DMAC_DSAR4 DMAC_DSAR(4)
616 #define DMAC_DTAR4 DMAC_DTAR(4)
617 #define DMAC_DTCR4 DMAC_DTCR(4)
618 #define DMAC_DRSR4 DMAC_DRSR(4)
619 #define DMAC_DCCSR4 DMAC_DCCSR(4)
620 #define DMAC_DCMD4 DMAC_DCMD(4)
621 #define DMAC_DDA4 DMAC_DDA(4)
623 // channel 5
624 #define DMAC_DSAR5 DMAC_DSAR(5)
625 #define DMAC_DTAR5 DMAC_DTAR(5)
626 #define DMAC_DTCR5 DMAC_DTCR(5)
627 #define DMAC_DRSR5 DMAC_DRSR(5)
628 #define DMAC_DCCSR5 DMAC_DCCSR(5)
629 #define DMAC_DCMD5 DMAC_DCMD(5)
630 #define DMAC_DDA5 DMAC_DDA(5)
632 #define REG_DMAC_DSAR(n) REG32(DMAC_DSAR((n)))
633 #define REG_DMAC_DTAR(n) REG32(DMAC_DTAR((n)))
634 #define REG_DMAC_DTCR(n) REG32(DMAC_DTCR((n)))
635 #define REG_DMAC_DRSR(n) REG32(DMAC_DRSR((n)))
636 #define REG_DMAC_DCCSR(n) REG32(DMAC_DCCSR((n)))
637 #define REG_DMAC_DCMD(n) REG32(DMAC_DCMD((n)))
638 #define REG_DMAC_DDA(n) REG32(DMAC_DDA((n)))
639 #define REG_DMAC_DMACR REG32(DMAC_DMACR)
640 #define REG_DMAC_DMAIPR REG32(DMAC_DMAIPR)
641 #define REG_DMAC_DMADBR REG32(DMAC_DMADBR)
642 #define REG_DMAC_DMADBSR REG32(DMAC_DMADBSR)
644 // DMA request source register
645 #define DMAC_DRSR_RS_BIT 0
646 #define DMAC_DRSR_RS_MASK (0x1f << DMAC_DRSR_RS_BIT)
647 #define DMAC_DRSR_RS_AUTO (8 << DMAC_DRSR_RS_BIT)
648 #define DMAC_DRSR_RS_UART0OUT (20 << DMAC_DRSR_RS_BIT)
649 #define DMAC_DRSR_RS_UART0IN (21 << DMAC_DRSR_RS_BIT)
650 #define DMAC_DRSR_RS_SSIOUT (22 << DMAC_DRSR_RS_BIT)
651 #define DMAC_DRSR_RS_SSIIN (23 << DMAC_DRSR_RS_BIT)
652 #define DMAC_DRSR_RS_AICOUT (24 << DMAC_DRSR_RS_BIT)
653 #define DMAC_DRSR_RS_AICIN (25 << DMAC_DRSR_RS_BIT)
654 #define DMAC_DRSR_RS_MSCOUT (26 << DMAC_DRSR_RS_BIT)
655 #define DMAC_DRSR_RS_MSCIN (27 << DMAC_DRSR_RS_BIT)
656 #define DMAC_DRSR_RS_TCU (28 << DMAC_DRSR_RS_BIT)
657 #define DMAC_DRSR_RS_SADC (29 << DMAC_DRSR_RS_BIT)
658 #define DMAC_DRSR_RS_SLCD (30 << DMAC_DRSR_RS_BIT)
660 // DMA channel control/status register
661 #define DMAC_DCCSR_NDES (1 << 31) /* descriptor (0) or not (1) ? */
662 #define DMAC_DCCSR_CDOA_BIT 16 /* copy of DMA offset address */
663 #define DMAC_DCCSR_CDOA_MASK (0xff << DMAC_DCCSR_CDOA_BIT)
664 #define DMAC_DCCSR_INV (1 << 6) /* descriptor invalid */
665 #define DMAC_DCCSR_AR (1 << 4) /* address error */
666 #define DMAC_DCCSR_TT (1 << 3) /* transfer terminated */
667 #define DMAC_DCCSR_HLT (1 << 2) /* DMA halted */
668 #define DMAC_DCCSR_CT (1 << 1) /* count terminated */
669 #define DMAC_DCCSR_EN (1 << 0) /* channel enable bit */
671 // DMA channel command register
672 #define DMAC_DCMD_SAI (1 << 23) /* source address increment */
673 #define DMAC_DCMD_DAI (1 << 22) /* dest address increment */
674 #define DMAC_DCMD_RDIL_BIT 16 /* request detection interval length */
675 #define DMAC_DCMD_RDIL_MASK (0x0f << DMAC_DCMD_RDIL_BIT)
676 #define DMAC_DCMD_RDIL_IGN (0 << DMAC_DCMD_RDIL_BIT)
677 #define DMAC_DCMD_RDIL_2 (1 << DMAC_DCMD_RDIL_BIT)
678 #define DMAC_DCMD_RDIL_4 (2 << DMAC_DCMD_RDIL_BIT)
679 #define DMAC_DCMD_RDIL_8 (3 << DMAC_DCMD_RDIL_BIT)
680 #define DMAC_DCMD_RDIL_12 (4 << DMAC_DCMD_RDIL_BIT)
681 #define DMAC_DCMD_RDIL_16 (5 << DMAC_DCMD_RDIL_BIT)
682 #define DMAC_DCMD_RDIL_20 (6 << DMAC_DCMD_RDIL_BIT)
683 #define DMAC_DCMD_RDIL_24 (7 << DMAC_DCMD_RDIL_BIT)
684 #define DMAC_DCMD_RDIL_28 (8 << DMAC_DCMD_RDIL_BIT)
685 #define DMAC_DCMD_RDIL_32 (9 << DMAC_DCMD_RDIL_BIT)
686 #define DMAC_DCMD_RDIL_48 (10 << DMAC_DCMD_RDIL_BIT)
687 #define DMAC_DCMD_RDIL_60 (11 << DMAC_DCMD_RDIL_BIT)
688 #define DMAC_DCMD_RDIL_64 (12 << DMAC_DCMD_RDIL_BIT)
689 #define DMAC_DCMD_RDIL_124 (13 << DMAC_DCMD_RDIL_BIT)
690 #define DMAC_DCMD_RDIL_128 (14 << DMAC_DCMD_RDIL_BIT)
691 #define DMAC_DCMD_RDIL_200 (15 << DMAC_DCMD_RDIL_BIT)
692 #define DMAC_DCMD_SWDH_BIT 14 /* source port width */
693 #define DMAC_DCMD_SWDH_MASK (0x03 << DMAC_DCMD_SWDH_BIT)
694 #define DMAC_DCMD_SWDH_32 (0 << DMAC_DCMD_SWDH_BIT)
695 #define DMAC_DCMD_SWDH_8 (1 << DMAC_DCMD_SWDH_BIT)
696 #define DMAC_DCMD_SWDH_16 (2 << DMAC_DCMD_SWDH_BIT)
697 #define DMAC_DCMD_DWDH_BIT 12 /* dest port width */
698 #define DMAC_DCMD_DWDH_MASK (0x03 << DMAC_DCMD_DWDH_BIT)
699 #define DMAC_DCMD_DWDH_32 (0 << DMAC_DCMD_DWDH_BIT)
700 #define DMAC_DCMD_DWDH_8 (1 << DMAC_DCMD_DWDH_BIT)
701 #define DMAC_DCMD_DWDH_16 (2 << DMAC_DCMD_DWDH_BIT)
702 #define DMAC_DCMD_DS_BIT 8 /* transfer data size of a data unit */
703 #define DMAC_DCMD_DS_MASK (0x07 << DMAC_DCMD_DS_BIT)
704 #define DMAC_DCMD_DS_32BIT (0 << DMAC_DCMD_DS_BIT)
705 #define DMAC_DCMD_DS_8BIT (1 << DMAC_DCMD_DS_BIT)
706 #define DMAC_DCMD_DS_16BIT (2 << DMAC_DCMD_DS_BIT)
707 #define DMAC_DCMD_DS_16BYTE (3 << DMAC_DCMD_DS_BIT)
708 #define DMAC_DCMD_DS_32BYTE (4 << DMAC_DCMD_DS_BIT)
709 #define DMAC_DCMD_TM (1 << 7) /* transfer mode: 0-single 1-block */
710 #define DMAC_DCMD_DES_V (1 << 4) /* descriptor valid flag */
711 #define DMAC_DCMD_DES_VM (1 << 3) /* descriptor valid mask: 1:support V-bit */
712 #define DMAC_DCMD_DES_VIE (1 << 2) /* DMA valid error interrupt enable */
713 #define DMAC_DCMD_TIE (1 << 1) /* DMA transfer interrupt enable */
714 #define DMAC_DCMD_LINK (1 << 0) /* descriptor link enable */
716 // DMA descriptor address register
717 #define DMAC_DDA_BASE_BIT 12 /* descriptor base address */
718 #define DMAC_DDA_BASE_MASK (0x0fffff << DMAC_DDA_BASE_BIT)
719 #define DMAC_DDA_OFFSET_BIT 4 /* descriptor offset address */
720 #define DMAC_DDA_OFFSET_MASK (0x0ff << DMAC_DDA_OFFSET_BIT)
722 // DMA control register
723 #define DMAC_DMACR_PR_BIT 8 /* channel priority mode */
724 #define DMAC_DMACR_PR_MASK (0x03 << DMAC_DMACR_PR_BIT)
725 #define DMAC_DMACR_PR_012345 (0 << DMAC_DMACR_PR_BIT)
726 #define DMAC_DMACR_PR_023145 (1 << DMAC_DMACR_PR_BIT)
727 #define DMAC_DMACR_PR_201345 (2 << DMAC_DMACR_PR_BIT)
728 #define DMAC_DMACR_PR_RR (3 << DMAC_DMACR_PR_BIT) /* round robin */
729 #define DMAC_DMACR_HLT (1 << 3) /* DMA halt flag */
730 #define DMAC_DMACR_AR (1 << 2) /* address error flag */
731 #define DMAC_DMACR_DMAE (1 << 0) /* DMA enable bit */
733 // DMA doorbell register
734 #define DMAC_DMADBR_DB5 (1 << 5) /* doorbell for channel 5 */
735 #define DMAC_DMADBR_DB4 (1 << 5) /* doorbell for channel 4 */
736 #define DMAC_DMADBR_DB3 (1 << 5) /* doorbell for channel 3 */
737 #define DMAC_DMADBR_DB2 (1 << 5) /* doorbell for channel 2 */
738 #define DMAC_DMADBR_DB1 (1 << 5) /* doorbell for channel 1 */
739 #define DMAC_DMADBR_DB0 (1 << 5) /* doorbell for channel 0 */
741 // DMA doorbell set register
742 #define DMAC_DMADBSR_DBS5 (1 << 5) /* enable doorbell for channel 5 */
743 #define DMAC_DMADBSR_DBS4 (1 << 5) /* enable doorbell for channel 4 */
744 #define DMAC_DMADBSR_DBS3 (1 << 5) /* enable doorbell for channel 3 */
745 #define DMAC_DMADBSR_DBS2 (1 << 5) /* enable doorbell for channel 2 */
746 #define DMAC_DMADBSR_DBS1 (1 << 5) /* enable doorbell for channel 1 */
747 #define DMAC_DMADBSR_DBS0 (1 << 5) /* enable doorbell for channel 0 */
749 // DMA interrupt pending register
750 #define DMAC_DMAIPR_CIRQ5 (1 << 5) /* irq pending status for channel 5 */
751 #define DMAC_DMAIPR_CIRQ4 (1 << 4) /* irq pending status for channel 4 */
752 #define DMAC_DMAIPR_CIRQ3 (1 << 3) /* irq pending status for channel 3 */
753 #define DMAC_DMAIPR_CIRQ2 (1 << 2) /* irq pending status for channel 2 */
754 #define DMAC_DMAIPR_CIRQ1 (1 << 1) /* irq pending status for channel 1 */
755 #define DMAC_DMAIPR_CIRQ0 (1 << 0) /* irq pending status for channel 0 */
758 /*************************************************************************
759 * GPIO (General-Purpose I/O Ports)
760 *************************************************************************/
761 #define MAX_GPIO_NUM 128
763 //n = 0,1,2,3
764 #define GPIO_PXPIN(n) (GPIO_BASE + (0x00 + (n)*0x100)) /* PIN Level Register */
765 #define GPIO_PXDAT(n) (GPIO_BASE + (0x10 + (n)*0x100)) /* Port Data Register */
766 #define GPIO_PXDATS(n) (GPIO_BASE + (0x14 + (n)*0x100)) /* Port Data Set Register */
767 #define GPIO_PXDATC(n) (GPIO_BASE + (0x18 + (n)*0x100)) /* Port Data Clear Register */
768 #define GPIO_PXIM(n) (GPIO_BASE + (0x20 + (n)*0x100)) /* Interrupt Mask Register */
769 #define GPIO_PXIMS(n) (GPIO_BASE + (0x24 + (n)*0x100)) /* Interrupt Mask Set Reg */
770 #define GPIO_PXIMC(n) (GPIO_BASE + (0x28 + (n)*0x100)) /* Interrupt Mask Clear Reg */
771 #define GPIO_PXPE(n) (GPIO_BASE + (0x30 + (n)*0x100)) /* Pull Enable Register */
772 #define GPIO_PXPES(n) (GPIO_BASE + (0x34 + (n)*0x100)) /* Pull Enable Set Reg. */
773 #define GPIO_PXPEC(n) (GPIO_BASE + (0x38 + (n)*0x100)) /* Pull Enable Clear Reg. */
774 #define GPIO_PXFUN(n) (GPIO_BASE + (0x40 + (n)*0x100)) /* Function Register */
775 #define GPIO_PXFUNS(n) (GPIO_BASE + (0x44 + (n)*0x100)) /* Function Set Register */
776 #define GPIO_PXFUNC(n) (GPIO_BASE + (0x48 + (n)*0x100)) /* Function Clear Register */
777 #define GPIO_PXSEL(n) (GPIO_BASE + (0x50 + (n)*0x100)) /* Select Register */
778 #define GPIO_PXSELS(n) (GPIO_BASE + (0x54 + (n)*0x100)) /* Select Set Register */
779 #define GPIO_PXSELC(n) (GPIO_BASE + (0x58 + (n)*0x100)) /* Select Clear Register */
780 #define GPIO_PXDIR(n) (GPIO_BASE + (0x60 + (n)*0x100)) /* Direction Register */
781 #define GPIO_PXDIRS(n) (GPIO_BASE + (0x64 + (n)*0x100)) /* Direction Set Register */
782 #define GPIO_PXDIRC(n) (GPIO_BASE + (0x68 + (n)*0x100)) /* Direction Clear Register */
783 #define GPIO_PXTRG(n) (GPIO_BASE + (0x70 + (n)*0x100)) /* Trigger Register */
784 #define GPIO_PXTRGS(n) (GPIO_BASE + (0x74 + (n)*0x100)) /* Trigger Set Register */
785 #define GPIO_PXTRGC(n) (GPIO_BASE + (0x78 + (n)*0x100)) /* Trigger Set Register */
786 #define GPIO_PXFLG(n) (GPIO_BASE + (0x80 + (n)*0x100)) /* Port Flag Register */
788 #define REG_GPIO_PXPIN(n) REG32(GPIO_PXPIN((n))) /* PIN level */
789 #define REG_GPIO_PXDAT(n) REG32(GPIO_PXDAT((n))) /* 1: interrupt pending */
790 #define REG_GPIO_PXDATS(n) REG32(GPIO_PXDATS((n)))
791 #define REG_GPIO_PXDATC(n) REG32(GPIO_PXDATC((n)))
792 #define REG_GPIO_PXIM(n) REG32(GPIO_PXIM((n))) /* 1: mask pin interrupt */
793 #define REG_GPIO_PXIMS(n) REG32(GPIO_PXIMS((n)))
794 #define REG_GPIO_PXIMC(n) REG32(GPIO_PXIMC((n)))
795 #define REG_GPIO_PXPE(n) REG32(GPIO_PXPE((n))) /* 1: disable pull up/down */
796 #define REG_GPIO_PXPES(n) REG32(GPIO_PXPES((n)))
797 #define REG_GPIO_PXPEC(n) REG32(GPIO_PXPEC((n)))
798 #define REG_GPIO_PXFUN(n) REG32(GPIO_PXFUN((n))) /* 0:GPIO or intr, 1:FUNC */
799 #define REG_GPIO_PXFUNS(n) REG32(GPIO_PXFUNS((n)))
800 #define REG_GPIO_PXFUNC(n) REG32(GPIO_PXFUNC((n)))
801 #define REG_GPIO_PXSEL(n) REG32(GPIO_PXSEL((n))) /* 0:GPIO/Fun0,1:intr/fun1*/
802 #define REG_GPIO_PXSELS(n) REG32(GPIO_PXSELS((n)))
803 #define REG_GPIO_PXSELC(n) REG32(GPIO_PXSELC((n)))
804 #define REG_GPIO_PXDIR(n) REG32(GPIO_PXDIR((n))) /* 0:input/low-level-trig/falling-edge-trig, 1:output/high-level-trig/rising-edge-trig */
805 #define REG_GPIO_PXDIRS(n) REG32(GPIO_PXDIRS((n)))
806 #define REG_GPIO_PXDIRC(n) REG32(GPIO_PXDIRC((n)))
807 #define REG_GPIO_PXTRG(n) REG32(GPIO_PXTRG((n))) /* 0:level-trigger, 1:edge-trigger */
808 #define REG_GPIO_PXTRGS(n) REG32(GPIO_PXTRGS((n)))
809 #define REG_GPIO_PXTRGC(n) REG32(GPIO_PXTRGC((n)))
810 #define REG_GPIO_PXFLG(n) REG32(GPIO_PXFLG((n))) /* interrupt flag */
813 /*************************************************************************
814 * UART
815 *************************************************************************/
817 #define IRDA_BASE UART0_BASE
818 #define UART_BASE UART0_BASE
819 #define UART_OFF 0x1000
821 /* Register Offset */
822 #define OFF_RDR (0x00) /* R 8b H'xx */
823 #define OFF_TDR (0x00) /* W 8b H'xx */
824 #define OFF_DLLR (0x00) /* RW 8b H'00 */
825 #define OFF_DLHR (0x04) /* RW 8b H'00 */
826 #define OFF_IER (0x04) /* RW 8b H'00 */
827 #define OFF_ISR (0x08) /* R 8b H'01 */
828 #define OFF_FCR (0x08) /* W 8b H'00 */
829 #define OFF_LCR (0x0C) /* RW 8b H'00 */
830 #define OFF_MCR (0x10) /* RW 8b H'00 */
831 #define OFF_LSR (0x14) /* R 8b H'00 */
832 #define OFF_MSR (0x18) /* R 8b H'00 */
833 #define OFF_SPR (0x1C) /* RW 8b H'00 */
834 #define OFF_SIRCR (0x20) /* RW 8b H'00, UART0 */
835 #define OFF_UMR (0x24) /* RW 8b H'00, UART M Register */
836 #define OFF_UACR (0x28) /* RW 8b H'00, UART Add Cycle Register */
838 /* Register Address */
839 #define UART0_RDR (UART0_BASE + OFF_RDR)
840 #define UART0_TDR (UART0_BASE + OFF_TDR)
841 #define UART0_DLLR (UART0_BASE + OFF_DLLR)
842 #define UART0_DLHR (UART0_BASE + OFF_DLHR)
843 #define UART0_IER (UART0_BASE + OFF_IER)
844 #define UART0_ISR (UART0_BASE + OFF_ISR)
845 #define UART0_FCR (UART0_BASE + OFF_FCR)
846 #define UART0_LCR (UART0_BASE + OFF_LCR)
847 #define UART0_MCR (UART0_BASE + OFF_MCR)
848 #define UART0_LSR (UART0_BASE + OFF_LSR)
849 #define UART0_MSR (UART0_BASE + OFF_MSR)
850 #define UART0_SPR (UART0_BASE + OFF_SPR)
851 #define UART0_SIRCR (UART0_BASE + OFF_SIRCR)
852 #define UART0_UMR (UART0_BASE + OFF_UMR)
853 #define UART0_UACR (UART0_BASE + OFF_UACR)
856 * Define macros for UART_IER
857 * UART Interrupt Enable Register
859 #define UART_IER_RIE (1 << 0) /* 0: receive fifo "full" interrupt disable */
860 #define UART_IER_TIE (1 << 1) /* 0: transmit fifo "empty" interrupt disable */
861 #define UART_IER_RLIE (1 << 2) /* 0: receive line status interrupt disable */
862 #define UART_IER_MIE (1 << 3) /* 0: modem status interrupt disable */
863 #define UART_IER_RTIE (1 << 4) /* 0: receive timeout interrupt disable */
866 * Define macros for UART_ISR
867 * UART Interrupt Status Register
869 #define UART_ISR_IP (1 << 0) /* 0: interrupt is pending 1: no interrupt */
870 #define UART_ISR_IID (7 << 1) /* Source of Interrupt */
871 #define UART_ISR_IID_MSI (0 << 1) /* Modem status interrupt */
872 #define UART_ISR_IID_THRI (1 << 1) /* Transmitter holding register empty */
873 #define UART_ISR_IID_RDI (2 << 1) /* Receiver data interrupt */
874 #define UART_ISR_IID_RLSI (3 << 1) /* Receiver line status interrupt */
875 #define UART_ISR_FFMS (3 << 6) /* FIFO mode select, set when UART_FCR.FE is set to 1 */
876 #define UART_ISR_FFMS_NO_FIFO (0 << 6)
877 #define UART_ISR_FFMS_FIFO_MODE (3 << 6)
880 * Define macros for UART_FCR
881 * UART FIFO Control Register
883 #define UART_FCR_FE (1 << 0) /* 0: non-FIFO mode 1: FIFO mode */
884 #define UART_FCR_RFLS (1 << 1) /* write 1 to flush receive FIFO */
885 #define UART_FCR_TFLS (1 << 2) /* write 1 to flush transmit FIFO */
886 #define UART_FCR_DMS (1 << 3) /* 0: disable DMA mode */
887 #define UART_FCR_UUE (1 << 4) /* 0: disable UART */
888 #define UART_FCR_RTRG (3 << 6) /* Receive FIFO Data Trigger */
889 #define UART_FCR_RTRG_1 (0 << 6)
890 #define UART_FCR_RTRG_4 (1 << 6)
891 #define UART_FCR_RTRG_8 (2 << 6)
892 #define UART_FCR_RTRG_15 (3 << 6)
895 * Define macros for UART_LCR
896 * UART Line Control Register
898 #define UART_LCR_WLEN (3 << 0) /* word length */
899 #define UART_LCR_WLEN_5 (0 << 0)
900 #define UART_LCR_WLEN_6 (1 << 0)
901 #define UART_LCR_WLEN_7 (2 << 0)
902 #define UART_LCR_WLEN_8 (3 << 0)
903 #define UART_LCR_STOP (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8
904 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
905 #define UART_LCR_STOP_1 (0 << 2) /* 0: 1 stop bit when word length is 5,6,7,8
906 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
907 #define UART_LCR_STOP_2 (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8
908 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
910 #define UART_LCR_PE (1 << 3) /* 0: parity disable */
911 #define UART_LCR_PROE (1 << 4) /* 0: even parity 1: odd parity */
912 #define UART_LCR_SPAR (1 << 5) /* 0: sticky parity disable */
913 #define UART_LCR_SBRK (1 << 6) /* write 0 normal, write 1 send break */
914 #define UART_LCR_DLAB (1 << 7) /* 0: access UART_RDR/TDR/IER 1: access UART_DLLR/DLHR */
917 * Define macros for UART_LSR
918 * UART Line Status Register
920 #define UART_LSR_DR (1 << 0) /* 0: receive FIFO is empty 1: receive data is ready */
921 #define UART_LSR_ORER (1 << 1) /* 0: no overrun error */
922 #define UART_LSR_PER (1 << 2) /* 0: no parity error */
923 #define UART_LSR_FER (1 << 3) /* 0; no framing error */
924 #define UART_LSR_BRK (1 << 4) /* 0: no break detected 1: receive a break signal */
925 #define UART_LSR_TDRQ (1 << 5) /* 1: transmit FIFO half "empty" */
926 #define UART_LSR_TEMT (1 << 6) /* 1: transmit FIFO and shift registers empty */
927 #define UART_LSR_RFER (1 << 7) /* 0: no receive error 1: receive error in FIFO mode */
930 * Define macros for UART_MCR
931 * UART Modem Control Register
933 #define UART_MCR_DTR (1 << 0) /* 0: DTR_ ouput high */
934 #define UART_MCR_RTS (1 << 1) /* 0: RTS_ output high */
935 #define UART_MCR_OUT1 (1 << 2) /* 0: UART_MSR.RI is set to 0 and RI_ input high */
936 #define UART_MCR_OUT2 (1 << 3) /* 0: UART_MSR.DCD is set to 0 and DCD_ input high */
937 #define UART_MCR_LOOP (1 << 4) /* 0: normal 1: loopback mode */
938 #define UART_MCR_MCE (1 << 7) /* 0: modem function is disable */
941 * Define macros for UART_MSR
942 * UART Modem Status Register
944 #define UART_MSR_DCTS (1 << 0) /* 0: no change on CTS_ pin since last read of UART_MSR */
945 #define UART_MSR_DDSR (1 << 1) /* 0: no change on DSR_ pin since last read of UART_MSR */
946 #define UART_MSR_DRI (1 << 2) /* 0: no change on RI_ pin since last read of UART_MSR */
947 #define UART_MSR_DDCD (1 << 3) /* 0: no change on DCD_ pin since last read of UART_MSR */
948 #define UART_MSR_CTS (1 << 4) /* 0: CTS_ pin is high */
949 #define UART_MSR_DSR (1 << 5) /* 0: DSR_ pin is high */
950 #define UART_MSR_RI (1 << 6) /* 0: RI_ pin is high */
951 #define UART_MSR_DCD (1 << 7) /* 0: DCD_ pin is high */
954 * Define macros for SIRCR
955 * Slow IrDA Control Register
957 #define SIRCR_TSIRE (1 << 0) /* 0: transmitter is in UART mode 1: IrDA mode */
958 #define SIRCR_RSIRE (1 << 1) /* 0: receiver is in UART mode 1: IrDA mode */
959 #define SIRCR_TPWS (1 << 2) /* 0: transmit 0 pulse width is 3/16 of bit length
960 1: 0 pulse width is 1.6us for 115.2Kbps */
961 #define SIRCR_TXPL (1 << 3) /* 0: encoder generates a positive pulse for 0 */
962 #define SIRCR_RXPL (1 << 4) /* 0: decoder interprets positive pulse as 0 */
965 /*************************************************************************
966 * AIC (AC97/I2S Controller)
967 *************************************************************************/
968 #define AIC_FR (AIC_BASE + 0x000)
969 #define AIC_CR (AIC_BASE + 0x004)
970 #define AIC_ACCR1 (AIC_BASE + 0x008)
971 #define AIC_ACCR2 (AIC_BASE + 0x00C)
972 #define AIC_I2SCR (AIC_BASE + 0x010)
973 #define AIC_SR (AIC_BASE + 0x014)
974 #define AIC_ACSR (AIC_BASE + 0x018)
975 #define AIC_I2SSR (AIC_BASE + 0x01C)
976 #define AIC_ACCAR (AIC_BASE + 0x020)
977 #define AIC_ACCDR (AIC_BASE + 0x024)
978 #define AIC_ACSAR (AIC_BASE + 0x028)
979 #define AIC_ACSDR (AIC_BASE + 0x02C)
980 #define AIC_I2SDIV (AIC_BASE + 0x030)
981 #define AIC_DR (AIC_BASE + 0x034)
983 #define REG_AIC_FR REG32(AIC_FR)
984 #define REG_AIC_CR REG32(AIC_CR)
985 #define REG_AIC_ACCR1 REG32(AIC_ACCR1)
986 #define REG_AIC_ACCR2 REG32(AIC_ACCR2)
987 #define REG_AIC_I2SCR REG32(AIC_I2SCR)
988 #define REG_AIC_SR REG32(AIC_SR)
989 #define REG_AIC_ACSR REG32(AIC_ACSR)
990 #define REG_AIC_I2SSR REG32(AIC_I2SSR)
991 #define REG_AIC_ACCAR REG32(AIC_ACCAR)
992 #define REG_AIC_ACCDR REG32(AIC_ACCDR)
993 #define REG_AIC_ACSAR REG32(AIC_ACSAR)
994 #define REG_AIC_ACSDR REG32(AIC_ACSDR)
995 #define REG_AIC_I2SDIV REG32(AIC_I2SDIV)
996 #define REG_AIC_DR REG32(AIC_DR)
998 /* AIC Controller Configuration Register (AIC_FR) */
1000 #define AIC_FR_RFTH_BIT 12 /* Receive FIFO Threshold */
1001 #define AIC_FR_RFTH_MASK (0xf << AIC_FR_RFTH_BIT)
1002 #define AIC_FR_TFTH_BIT 8 /* Transmit FIFO Threshold */
1003 #define AIC_FR_TFTH_MASK (0xf << AIC_FR_TFTH_BIT)
1004 #define AIC_FR_ICDC (1 << 5) /* External(0) or Internal CODEC(1) */
1005 #define AIC_FR_AUSEL (1 << 4) /* AC97(0) or I2S/MSB-justified(1) */
1006 #define AIC_FR_RST (1 << 3) /* AIC registers reset */
1007 #define AIC_FR_BCKD (1 << 2) /* I2S BIT_CLK direction, 0:input,1:output */
1008 #define AIC_FR_SYNCD (1 << 1) /* I2S SYNC direction, 0:input,1:output */
1009 #define AIC_FR_ENB (1 << 0) /* AIC enable bit */
1011 /* AIC Controller Common Control Register (AIC_CR) */
1013 #define AIC_CR_OSS_BIT 19 /* Output Sample Size from memory (AIC V2 only) */
1014 #define AIC_CR_OSS_MASK (0x7 << AIC_CR_OSS_BIT)
1015 #define AIC_CR_OSS_8BIT (0x0 << AIC_CR_OSS_BIT)
1016 #define AIC_CR_OSS_16BIT (0x1 << AIC_CR_OSS_BIT)
1017 #define AIC_CR_OSS_18BIT (0x2 << AIC_CR_OSS_BIT)
1018 #define AIC_CR_OSS_20BIT (0x3 << AIC_CR_OSS_BIT)
1019 #define AIC_CR_OSS_24BIT (0x4 << AIC_CR_OSS_BIT)
1020 #define AIC_CR_ISS_BIT 16 /* Input Sample Size from memory (AIC V2 only) */
1021 #define AIC_CR_ISS_MASK (0x7 << AIC_CR_ISS_BIT)
1022 #define AIC_CR_ISS_8BIT (0x0 << AIC_CR_ISS_BIT)
1023 #define AIC_CR_ISS_16BIT (0x1 << AIC_CR_ISS_BIT)
1024 #define AIC_CR_ISS_18BIT (0x2 << AIC_CR_ISS_BIT)
1025 #define AIC_CR_ISS_20BIT (0x3 << AIC_CR_ISS_BIT)
1026 #define AIC_CR_ISS_24BIT (0x4 << AIC_CR_ISS_BIT)
1027 #define AIC_CR_RDMS (1 << 15) /* Receive DMA enable */
1028 #define AIC_CR_TDMS (1 << 14) /* Transmit DMA enable */
1029 #define AIC_CR_M2S (1 << 11) /* Mono to Stereo enable */
1030 #define AIC_CR_ENDSW (1 << 10) /* Endian switch enable */
1031 #define AIC_CR_AVSTSU (1 << 9) /* Signed <-> Unsigned toggle enable */
1032 #define AIC_CR_FLUSH (1 << 8) /* Flush FIFO */
1033 #define AIC_CR_EROR (1 << 6) /* Enable ROR interrupt */
1034 #define AIC_CR_ETUR (1 << 5) /* Enable TUR interrupt */
1035 #define AIC_CR_ERFS (1 << 4) /* Enable RFS interrupt */
1036 #define AIC_CR_ETFS (1 << 3) /* Enable TFS interrupt */
1037 #define AIC_CR_ENLBF (1 << 2) /* Enable Loopback Function */
1038 #define AIC_CR_ERPL (1 << 1) /* Enable Playback Function */
1039 #define AIC_CR_EREC (1 << 0) /* Enable Record Function */
1041 /* AIC Controller AC-link Control Register 1 (AIC_ACCR1) */
1043 #define AIC_ACCR1_RS_BIT 16 /* Receive Valid Slots */
1044 #define AIC_ACCR1_RS_MASK (0x3ff << AIC_ACCR1_RS_BIT)
1045 #define AIC_ACCR1_RS_SLOT12 (1 << 25) /* Slot 12 valid bit */
1046 #define AIC_ACCR1_RS_SLOT11 (1 << 24) /* Slot 11 valid bit */
1047 #define AIC_ACCR1_RS_SLOT10 (1 << 23) /* Slot 10 valid bit */
1048 #define AIC_ACCR1_RS_SLOT9 (1 << 22) /* Slot 9 valid bit, LFE */
1049 #define AIC_ACCR1_RS_SLOT8 (1 << 21) /* Slot 8 valid bit, Surround Right */
1050 #define AIC_ACCR1_RS_SLOT7 (1 << 20) /* Slot 7 valid bit, Surround Left */
1051 #define AIC_ACCR1_RS_SLOT6 (1 << 19) /* Slot 6 valid bit, PCM Center */
1052 #define AIC_ACCR1_RS_SLOT5 (1 << 18) /* Slot 5 valid bit */
1053 #define AIC_ACCR1_RS_SLOT4 (1 << 17) /* Slot 4 valid bit, PCM Right */
1054 #define AIC_ACCR1_RS_SLOT3 (1 << 16) /* Slot 3 valid bit, PCM Left */
1055 #define AIC_ACCR1_XS_BIT 0 /* Transmit Valid Slots */
1056 #define AIC_ACCR1_XS_MASK (0x3ff << AIC_ACCR1_XS_BIT)
1057 #define AIC_ACCR1_XS_SLOT12 (1 << 9) /* Slot 12 valid bit */
1058 #define AIC_ACCR1_XS_SLOT11 (1 << 8) /* Slot 11 valid bit */
1059 #define AIC_ACCR1_XS_SLOT10 (1 << 7) /* Slot 10 valid bit */
1060 #define AIC_ACCR1_XS_SLOT9 (1 << 6) /* Slot 9 valid bit, LFE */
1061 #define AIC_ACCR1_XS_SLOT8 (1 << 5) /* Slot 8 valid bit, Surround Right */
1062 #define AIC_ACCR1_XS_SLOT7 (1 << 4) /* Slot 7 valid bit, Surround Left */
1063 #define AIC_ACCR1_XS_SLOT6 (1 << 3) /* Slot 6 valid bit, PCM Center */
1064 #define AIC_ACCR1_XS_SLOT5 (1 << 2) /* Slot 5 valid bit */
1065 #define AIC_ACCR1_XS_SLOT4 (1 << 1) /* Slot 4 valid bit, PCM Right */
1066 #define AIC_ACCR1_XS_SLOT3 (1 << 0) /* Slot 3 valid bit, PCM Left */
1068 /* AIC Controller AC-link Control Register 2 (AIC_ACCR2) */
1070 #define AIC_ACCR2_ERSTO (1 << 18) /* Enable RSTO interrupt */
1071 #define AIC_ACCR2_ESADR (1 << 17) /* Enable SADR interrupt */
1072 #define AIC_ACCR2_ECADT (1 << 16) /* Enable CADT interrupt */
1073 #define AIC_ACCR2_OASS_BIT 8 /* Output Sample Size for AC-link */
1074 #define AIC_ACCR2_OASS_MASK (0x3 << AIC_ACCR2_OASS_BIT)
1075 #define AIC_ACCR2_OASS_20BIT (0 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 20-bit */
1076 #define AIC_ACCR2_OASS_18BIT (1 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 18-bit */
1077 #define AIC_ACCR2_OASS_16BIT (2 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 16-bit */
1078 #define AIC_ACCR2_OASS_8BIT (3 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 8-bit */
1079 #define AIC_ACCR2_IASS_BIT 6 /* Output Sample Size for AC-link */
1080 #define AIC_ACCR2_IASS_MASK (0x3 << AIC_ACCR2_IASS_BIT)
1081 #define AIC_ACCR2_IASS_20BIT (0 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 20-bit */
1082 #define AIC_ACCR2_IASS_18BIT (1 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 18-bit */
1083 #define AIC_ACCR2_IASS_16BIT (2 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 16-bit */
1084 #define AIC_ACCR2_IASS_8BIT (3 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 8-bit */
1085 #define AIC_ACCR2_SO (1 << 3) /* SDATA_OUT output value */
1086 #define AIC_ACCR2_SR (1 << 2) /* RESET# pin level */
1087 #define AIC_ACCR2_SS (1 << 1) /* SYNC pin level */
1088 #define AIC_ACCR2_SA (1 << 0) /* SYNC and SDATA_OUT alternation */
1090 /* AIC Controller I2S/MSB-justified Control Register (AIC_I2SCR) */
1092 #define AIC_I2SCR_STPBK (1 << 12) /* Stop BIT_CLK for I2S/MSB-justified */
1093 #define AIC_I2SCR_WL_BIT 1 /* Input/Output Sample Size for I2S/MSB-justified */
1094 #define AIC_I2SCR_WL_MASK (0x7 << AIC_I2SCR_WL_BIT)
1095 #define AIC_I2SCR_WL_24BIT (0 << AIC_I2SCR_WL_BIT) /* Word Length is 24 bit */
1096 #define AIC_I2SCR_WL_20BIT (1 << AIC_I2SCR_WL_BIT) /* Word Length is 20 bit */
1097 #define AIC_I2SCR_WL_18BIT (2 << AIC_I2SCR_WL_BIT) /* Word Length is 18 bit */
1098 #define AIC_I2SCR_WL_16BIT (3 << AIC_I2SCR_WL_BIT) /* Word Length is 16 bit */
1099 #define AIC_I2SCR_WL_8BIT (4 << AIC_I2SCR_WL_BIT) /* Word Length is 8 bit */
1100 #define AIC_I2SCR_AMSL (1 << 0) /* 0:I2S, 1:MSB-justified */
1102 /* AIC Controller FIFO Status Register (AIC_SR) */
1104 #define AIC_SR_RFL_BIT 24 /* Receive FIFO Level */
1105 #define AIC_SR_RFL_MASK (0x3f << AIC_SR_RFL_BIT)
1106 #define AIC_SR_TFL_BIT 8 /* Transmit FIFO level */
1107 #define AIC_SR_TFL_MASK (0x3f << AIC_SR_TFL_BIT)
1108 #define AIC_SR_ROR (1 << 6) /* Receive FIFO Overrun */
1109 #define AIC_SR_TUR (1 << 5) /* Transmit FIFO Underrun */
1110 #define AIC_SR_RFS (1 << 4) /* Receive FIFO Service Request */
1111 #define AIC_SR_TFS (1 << 3) /* Transmit FIFO Service Request */
1113 /* AIC Controller AC-link Status Register (AIC_ACSR) */
1115 #define AIC_ACSR_SLTERR (1 << 21) /* Slot Error Flag */
1116 #define AIC_ACSR_CRDY (1 << 20) /* External CODEC Ready Flag */
1117 #define AIC_ACSR_CLPM (1 << 19) /* External CODEC low power mode flag */
1118 #define AIC_ACSR_RSTO (1 << 18) /* External CODEC regs read status timeout */
1119 #define AIC_ACSR_SADR (1 << 17) /* External CODEC regs status addr and data received */
1120 #define AIC_ACSR_CADT (1 << 16) /* Command Address and Data Transmitted */
1122 /* AIC Controller I2S/MSB-justified Status Register (AIC_I2SSR) */
1124 #define AIC_I2SSR_BSY (1 << 2) /* AIC Busy in I2S/MSB-justified format */
1126 /* AIC Controller AC97 codec Command Address Register (AIC_ACCAR) */
1128 #define AIC_ACCAR_CAR_BIT 0
1129 #define AIC_ACCAR_CAR_MASK (0xfffff << AIC_ACCAR_CAR_BIT)
1131 /* AIC Controller AC97 codec Command Data Register (AIC_ACCDR) */
1133 #define AIC_ACCDR_CDR_BIT 0
1134 #define AIC_ACCDR_CDR_MASK (0xfffff << AIC_ACCDR_CDR_BIT)
1136 /* AIC Controller AC97 codec Status Address Register (AIC_ACSAR) */
1138 #define AIC_ACSAR_SAR_BIT 0
1139 #define AIC_ACSAR_SAR_MASK (0xfffff << AIC_ACSAR_SAR_BIT)
1141 /* AIC Controller AC97 codec Status Data Register (AIC_ACSDR) */
1143 #define AIC_ACSDR_SDR_BIT 0
1144 #define AIC_ACSDR_SDR_MASK (0xfffff << AIC_ACSDR_SDR_BIT)
1146 /* AIC Controller I2S/MSB-justified Clock Divider Register (AIC_I2SDIV) */
1148 #define AIC_I2SDIV_DIV_BIT 0
1149 #define AIC_I2SDIV_DIV_MASK (0x7f << AIC_I2SDIV_DIV_BIT)
1150 #define AIC_I2SDIV_BITCLK_3072KHZ (0x0C << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 3.072MHz */
1151 #define AIC_I2SDIV_BITCLK_2836KHZ (0x0D << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 2.836MHz */
1152 #define AIC_I2SDIV_BITCLK_1418KHZ (0x1A << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.418MHz */
1153 #define AIC_I2SDIV_BITCLK_1024KHZ (0x24 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.024MHz */
1154 #define AIC_I2SDIV_BITCLK_7089KHZ (0x34 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 708.92KHz */
1155 #define AIC_I2SDIV_BITCLK_512KHZ (0x48 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 512.00KHz */
1158 /*************************************************************************
1159 * ICDC (Internal CODEC)
1160 *************************************************************************/
1161 #define ICDC_CR (ICDC_BASE + 0x0400) /* ICDC Control Register */
1162 #define ICDC_APWAIT (ICDC_BASE + 0x0404) /* Anti-Pop WAIT Stage Timing Control Register */
1163 #define ICDC_APPRE (ICDC_BASE + 0x0408) /* Anti-Pop HPEN-PRE Stage Timing Control Register */
1164 #define ICDC_APHPEN (ICDC_BASE + 0x040C) /* Anti-Pop HPEN Stage Timing Control Register */
1165 #define ICDC_APSR (ICDC_BASE + 0x0410) /* Anti-Pop Status Register */
1166 #define ICDC_CDCCR1 (ICDC_BASE + 0x0080)
1167 #define ICDC_CDCCR2 (ICDC_BASE + 0x0084)
1169 #define REG_ICDC_CR REG32(ICDC_CR)
1170 #define REG_ICDC_APWAIT REG32(ICDC_APWAIT)
1171 #define REG_ICDC_APPRE REG32(ICDC_APPRE)
1172 #define REG_ICDC_APHPEN REG32(ICDC_APHPEN)
1173 #define REG_ICDC_APSR REG32(ICDC_APSR)
1174 #define REG_ICDC_CDCCR1 REG32(ICDC_CDCCR1)
1175 #define REG_ICDC_CDCCR2 REG32(ICDC_CDCCR2)
1177 /* ICDC Control Register */
1178 #define ICDC_CR_LINVOL_BIT 24 /* LINE Input Volume Gain: GAIN=LINVOL*1.5-34.5 */
1179 #define ICDC_CR_LINVOL_MASK (0x1f << ICDC_CR_LINVOL_BIT)
1180 #define ICDC_CR_ASRATE_BIT 20 /* Audio Sample Rate */
1181 #define ICDC_CR_ASRATE_MASK (0x0f << ICDC_CR_ASRATE_BIT)
1182 #define ICDC_CR_ASRATE_8000 (0x0 << ICDC_CR_ASRATE_BIT)
1183 #define ICDC_CR_ASRATE_11025 (0x1 << ICDC_CR_ASRATE_BIT)
1184 #define ICDC_CR_ASRATE_12000 (0x2 << ICDC_CR_ASRATE_BIT)
1185 #define ICDC_CR_ASRATE_16000 (0x3 << ICDC_CR_ASRATE_BIT)
1186 #define ICDC_CR_ASRATE_22050 (0x4 << ICDC_CR_ASRATE_BIT)
1187 #define ICDC_CR_ASRATE_24000 (0x5 << ICDC_CR_ASRATE_BIT)
1188 #define ICDC_CR_ASRATE_32000 (0x6 << ICDC_CR_ASRATE_BIT)
1189 #define ICDC_CR_ASRATE_44100 (0x7 << ICDC_CR_ASRATE_BIT)
1190 #define ICDC_CR_ASRATE_48000 (0x8 << ICDC_CR_ASRATE_BIT)
1191 #define ICDC_CR_MICBG_BIT 18 /* MIC Boost Gain */
1192 #define ICDC_CR_MICBG_MASK (0x3 << ICDC_CR_MICBG_BIT)
1193 #define ICDC_CR_MICBG_0DB (0x0 << ICDC_CR_MICBG_BIT)
1194 #define ICDC_CR_MICBG_6DB (0x1 << ICDC_CR_MICBG_BIT)
1195 #define ICDC_CR_MICBG_12DB (0x2 << ICDC_CR_MICBG_BIT)
1196 #define ICDC_CR_MICBG_20DB (0x3 << ICDC_CR_MICBG_BIT)
1197 #define ICDC_CR_HPVOL_BIT 16 /* Headphone Volume Gain */
1198 #define ICDC_CR_HPVOL_MASK (0x3 << ICDC_CR_HPVOL_BIT)
1199 #define ICDC_CR_HPVOL_0DB (0x0 << ICDC_CR_HPVOL_BIT)
1200 #define ICDC_CR_HPVOL_2DB (0x1 << ICDC_CR_HPVOL_BIT)
1201 #define ICDC_CR_HPVOL_4DB (0x2 << ICDC_CR_HPVOL_BIT)
1202 #define ICDC_CR_HPVOL_6DB (0x3 << ICDC_CR_HPVOL_BIT)
1203 #define ICDC_CR_ELINEIN (1 << 13) /* Enable LINE Input */
1204 #define ICDC_CR_EMIC (1 << 12) /* Enable MIC Input */
1205 #define ICDC_CR_SW1ON (1 << 11) /* Switch 1 in CODEC is on */
1206 #define ICDC_CR_EADC (1 << 10) /* Enable ADC */
1207 #define ICDC_CR_SW2ON (1 << 9) /* Switch 2 in CODEC is on */
1208 #define ICDC_CR_EDAC (1 << 8) /* Enable DAC */
1209 #define ICDC_CR_HPMUTE (1 << 5) /* Headphone Mute */
1210 #define ICDC_CR_HPTON (1 << 4) /* Headphone Amplifier Trun On */
1211 #define ICDC_CR_HPTOFF (1 << 3) /* Headphone Amplifier Trun Off */
1212 #define ICDC_CR_TAAP (1 << 2) /* Turn Around of the Anti-Pop Procedure */
1213 #define ICDC_CR_EAP (1 << 1) /* Enable Anti-Pop Procedure */
1214 #define ICDC_CR_SUSPD (1 << 0) /* CODEC Suspend */
1216 /* Anti-Pop WAIT Stage Timing Control Register */
1217 #define ICDC_APWAIT_WAITSN_BIT 0
1218 #define ICDC_APWAIT_WAITSN_MASK (0x7ff << ICDC_APWAIT_WAITSN_BIT)
1220 /* Anti-Pop HPEN-PRE Stage Timing Control Register */
1221 #define ICDC_APPRE_PRESN_BIT 0
1222 #define ICDC_APPRE_PRESN_MASK (0x1ff << ICDC_APPRE_PRESN_BIT)
1224 /* Anti-Pop HPEN Stage Timing Control Register */
1225 #define ICDC_APHPEN_HPENSN_BIT 0
1226 #define ICDC_APHPEN_HPENSN_MASK (0x3fff << ICDC_APHPEN_HPENSN_BIT)
1228 /* Anti-Pop Status Register */
1229 #define ICDC_SR_HPST_BIT 14 /* Headphone Amplifier State */
1230 #define ICDC_SR_HPST_MASK (0x7 << ICDC_SR_HPST_BIT)
1231 #define ICDC_SR_HPST_HP_OFF (0x0 << ICDC_SR_HPST_BIT) /* HP amplifier is off */
1232 #define ICDC_SR_HPST_TON_WAIT (0x1 << ICDC_SR_HPST_BIT) /* wait state in turn-on */
1233 #define ICDC_SR_HPST_TON_PRE (0x2 << ICDC_SR_HPST_BIT) /* pre-enable state in turn-on */
1234 #define ICDC_SR_HPST_TON_HPEN (0x3 << ICDC_SR_HPST_BIT) /* HP enable state in turn-on */
1235 #define ICDC_SR_HPST_TOFF_HPEN (0x4 << ICDC_SR_HPST_BIT) /* HP enable state in turn-off */
1236 #define ICDC_SR_HPST_TOFF_PRE (0x5 << ICDC_SR_HPST_BIT) /* pre-enable state in turn-off */
1237 #define ICDC_SR_HPST_TOFF_WAIT (0x6 << ICDC_SR_HPST_BIT) /* wait state in turn-off */
1238 #define ICDC_SR_HPST_HP_ON (0x7 << ICDC_SR_HPST_BIT) /* HP amplifier is on */
1239 #define ICDC_SR_SNCNT_BIT 0 /* Sample Number Counter */
1240 #define ICDC_SR_SNCNT_MASK (0x3fff << ICDC_SR_SNCNT_BIT)
1243 /*************************************************************************
1244 * I2C
1245 *************************************************************************/
1246 #define I2C_DR (I2C_BASE + 0x000)
1247 #define I2C_CR (I2C_BASE + 0x004)
1248 #define I2C_SR (I2C_BASE + 0x008)
1249 #define I2C_GR (I2C_BASE + 0x00C)
1251 #define REG_I2C_DR REG8(I2C_DR)
1252 #define REG_I2C_CR REG8(I2C_CR)
1253 #define REG_I2C_SR REG8(I2C_SR)
1254 #define REG_I2C_GR REG16(I2C_GR)
1256 /* I2C Control Register (I2C_CR) */
1258 #define I2C_CR_IEN (1 << 4)
1259 #define I2C_CR_STA (1 << 3)
1260 #define I2C_CR_STO (1 << 2)
1261 #define I2C_CR_AC (1 << 1)
1262 #define I2C_CR_I2CE (1 << 0)
1264 /* I2C Status Register (I2C_SR) */
1266 #define I2C_SR_STX (1 << 4)
1267 #define I2C_SR_BUSY (1 << 3)
1268 #define I2C_SR_TEND (1 << 2)
1269 #define I2C_SR_DRF (1 << 1)
1270 #define I2C_SR_ACKF (1 << 0)
1273 /*************************************************************************
1274 * SSI
1275 *************************************************************************/
1276 #define SSI_DR (SSI_BASE + 0x000)
1277 #define SSI_CR0 (SSI_BASE + 0x004)
1278 #define SSI_CR1 (SSI_BASE + 0x008)
1279 #define SSI_SR (SSI_BASE + 0x00C)
1280 #define SSI_ITR (SSI_BASE + 0x010)
1281 #define SSI_ICR (SSI_BASE + 0x014)
1282 #define SSI_GR (SSI_BASE + 0x018)
1284 #define REG_SSI_DR REG32(SSI_DR)
1285 #define REG_SSI_CR0 REG16(SSI_CR0)
1286 #define REG_SSI_CR1 REG32(SSI_CR1)
1287 #define REG_SSI_SR REG32(SSI_SR)
1288 #define REG_SSI_ITR REG16(SSI_ITR)
1289 #define REG_SSI_ICR REG8(SSI_ICR)
1290 #define REG_SSI_GR REG16(SSI_GR)
1292 /* SSI Data Register (SSI_DR) */
1294 #define SSI_DR_GPC_BIT 0
1295 #define SSI_DR_GPC_MASK (0x1ff << SSI_DR_GPC_BIT)
1297 /* SSI Control Register 0 (SSI_CR0) */
1299 #define SSI_CR0_SSIE (1 << 15)
1300 #define SSI_CR0_TIE (1 << 14)
1301 #define SSI_CR0_RIE (1 << 13)
1302 #define SSI_CR0_TEIE (1 << 12)
1303 #define SSI_CR0_REIE (1 << 11)
1304 #define SSI_CR0_LOOP (1 << 10)
1305 #define SSI_CR0_RFINE (1 << 9)
1306 #define SSI_CR0_RFINC (1 << 8)
1307 #define SSI_CR0_FSEL (1 << 6)
1308 #define SSI_CR0_TFLUSH (1 << 2)
1309 #define SSI_CR0_RFLUSH (1 << 1)
1310 #define SSI_CR0_DISREV (1 << 0)
1312 /* SSI Control Register 1 (SSI_CR1) */
1314 #define SSI_CR1_FRMHL_BIT 30
1315 #define SSI_CR1_FRMHL_MASK (0x3 << SSI_CR1_FRMHL_BIT)
1316 #define SSI_CR1_FRMHL_CELOW_CE2LOW (0 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is low valid */
1317 #define SSI_CR1_FRMHL_CEHIGH_CE2LOW (1 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is low valid */
1318 #define SSI_CR1_FRMHL_CELOW_CE2HIGH (2 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is high valid */
1319 #define SSI_CR1_FRMHL_CEHIGH_CE2HIGH (3 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is high valid */
1320 #define SSI_CR1_TFVCK_BIT 28
1321 #define SSI_CR1_TFVCK_MASK (0x3 << SSI_CR1_TFVCK_BIT)
1322 #define SSI_CR1_TFVCK_0 (0 << SSI_CR1_TFVCK_BIT)
1323 #define SSI_CR1_TFVCK_1 (1 << SSI_CR1_TFVCK_BIT)
1324 #define SSI_CR1_TFVCK_2 (2 << SSI_CR1_TFVCK_BIT)
1325 #define SSI_CR1_TFVCK_3 (3 << SSI_CR1_TFVCK_BIT)
1326 #define SSI_CR1_TCKFI_BIT 26
1327 #define SSI_CR1_TCKFI_MASK (0x3 << SSI_CR1_TCKFI_BIT)
1328 #define SSI_CR1_TCKFI_0 (0 << SSI_CR1_TCKFI_BIT)
1329 #define SSI_CR1_TCKFI_1 (1 << SSI_CR1_TCKFI_BIT)
1330 #define SSI_CR1_TCKFI_2 (2 << SSI_CR1_TCKFI_BIT)
1331 #define SSI_CR1_TCKFI_3 (3 << SSI_CR1_TCKFI_BIT)
1332 #define SSI_CR1_LFST (1 << 25)
1333 #define SSI_CR1_ITFRM (1 << 24)
1334 #define SSI_CR1_UNFIN (1 << 23)
1335 #define SSI_CR1_MULTS (1 << 22)
1336 #define SSI_CR1_FMAT_BIT 20
1337 #define SSI_CR1_FMAT_MASK (0x3 << SSI_CR1_FMAT_BIT)
1338 #define SSI_CR1_FMAT_SPI (0 << SSI_CR1_FMAT_BIT) /* Motorola¡¯s SPI format */
1339 #define SSI_CR1_FMAT_SSP (1 << SSI_CR1_FMAT_BIT) /* TI's SSP format */
1340 #define SSI_CR1_FMAT_MW1 (2 << SSI_CR1_FMAT_BIT) /* National Microwire 1 format */
1341 #define SSI_CR1_FMAT_MW2 (3 << SSI_CR1_FMAT_BIT) /* National Microwire 2 format */
1342 #define SSI_CR1_MCOM_BIT 12
1343 #define SSI_CR1_MCOM_MASK (0xf << SSI_CR1_MCOM_BIT)
1344 #define SSI_CR1_MCOM_1BIT (0x0 << SSI_CR1_MCOM_BIT) /* 1-bit command selected */
1345 #define SSI_CR1_MCOM_2BIT (0x1 << SSI_CR1_MCOM_BIT) /* 2-bit command selected */
1346 #define SSI_CR1_MCOM_3BIT (0x2 << SSI_CR1_MCOM_BIT) /* 3-bit command selected */
1347 #define SSI_CR1_MCOM_4BIT (0x3 << SSI_CR1_MCOM_BIT) /* 4-bit command selected */
1348 #define SSI_CR1_MCOM_5BIT (0x4 << SSI_CR1_MCOM_BIT) /* 5-bit command selected */
1349 #define SSI_CR1_MCOM_6BIT (0x5 << SSI_CR1_MCOM_BIT) /* 6-bit command selected */
1350 #define SSI_CR1_MCOM_7BIT (0x6 << SSI_CR1_MCOM_BIT) /* 7-bit command selected */
1351 #define SSI_CR1_MCOM_8BIT (0x7 << SSI_CR1_MCOM_BIT) /* 8-bit command selected */
1352 #define SSI_CR1_MCOM_9BIT (0x8 << SSI_CR1_MCOM_BIT) /* 9-bit command selected */
1353 #define SSI_CR1_MCOM_10BIT (0x9 << SSI_CR1_MCOM_BIT) /* 10-bit command selected */
1354 #define SSI_CR1_MCOM_11BIT (0xA << SSI_CR1_MCOM_BIT) /* 11-bit command selected */
1355 #define SSI_CR1_MCOM_12BIT (0xB << SSI_CR1_MCOM_BIT) /* 12-bit command selected */
1356 #define SSI_CR1_MCOM_13BIT (0xC << SSI_CR1_MCOM_BIT) /* 13-bit command selected */
1357 #define SSI_CR1_MCOM_14BIT (0xD << SSI_CR1_MCOM_BIT) /* 14-bit command selected */
1358 #define SSI_CR1_MCOM_15BIT (0xE << SSI_CR1_MCOM_BIT) /* 15-bit command selected */
1359 #define SSI_CR1_MCOM_16BIT (0xF << SSI_CR1_MCOM_BIT) /* 16-bit command selected */
1360 #define SSI_CR1_TTRG_BIT 10
1361 #define SSI_CR1_TTRG_MASK (0x3 << SSI_CR1_TTRG_BIT)
1362 #define SSI_CR1_TTRG_1 (0 << SSI_CR1_TTRG_BIT)/* Less than or equal to 1 */
1363 #define SSI_CR1_TTRG_4 (1 << SSI_CR1_TTRG_BIT) /* Less than or equal to 4 */
1364 #define SSI_CR1_TTRG_8 (2 << SSI_CR1_TTRG_BIT) /* Less than or equal to 8 */
1365 #define SSI_CR1_TTRG_14 (3 << SSI_CR1_TTRG_BIT) /* Less than or equal to 14 */
1366 #define SSI_CR1_RTRG_BIT 8
1367 #define SSI_CR1_RTRG_MASK (0x3 << SSI_CR1_RTRG_BIT)
1368 #define SSI_CR1_RTRG_1 (0 << SSI_CR1_RTRG_BIT) /* More than or equal to 1 */
1369 #define SSI_CR1_RTRG_4 (1 << SSI_CR1_RTRG_BIT) /* More than or equal to 4 */
1370 #define SSI_CR1_RTRG_8 (2 << SSI_CR1_RTRG_BIT) /* More than or equal to 8 */
1371 #define SSI_CR1_RTRG_14 (3 << SSI_CR1_RTRG_BIT) /* More than or equal to 14 */
1372 #define SSI_CR1_FLEN_BIT 4
1373 #define SSI_CR1_FLEN_MASK (0xf << SSI_CR1_FLEN_BIT)
1374 #define SSI_CR1_FLEN_2BIT (0x0 << SSI_CR1_FLEN_BIT)
1375 #define SSI_CR1_FLEN_3BIT (0x1 << SSI_CR1_FLEN_BIT)
1376 #define SSI_CR1_FLEN_4BIT (0x2 << SSI_CR1_FLEN_BIT)
1377 #define SSI_CR1_FLEN_5BIT (0x3 << SSI_CR1_FLEN_BIT)
1378 #define SSI_CR1_FLEN_6BIT (0x4 << SSI_CR1_FLEN_BIT)
1379 #define SSI_CR1_FLEN_7BIT (0x5 << SSI_CR1_FLEN_BIT)
1380 #define SSI_CR1_FLEN_8BIT (0x6 << SSI_CR1_FLEN_BIT)
1381 #define SSI_CR1_FLEN_9BIT (0x7 << SSI_CR1_FLEN_BIT)
1382 #define SSI_CR1_FLEN_10BIT (0x8 << SSI_CR1_FLEN_BIT)
1383 #define SSI_CR1_FLEN_11BIT (0x9 << SSI_CR1_FLEN_BIT)
1384 #define SSI_CR1_FLEN_12BIT (0xA << SSI_CR1_FLEN_BIT)
1385 #define SSI_CR1_FLEN_13BIT (0xB << SSI_CR1_FLEN_BIT)
1386 #define SSI_CR1_FLEN_14BIT (0xC << SSI_CR1_FLEN_BIT)
1387 #define SSI_CR1_FLEN_15BIT (0xD << SSI_CR1_FLEN_BIT)
1388 #define SSI_CR1_FLEN_16BIT (0xE << SSI_CR1_FLEN_BIT)
1389 #define SSI_CR1_FLEN_17BIT (0xF << SSI_CR1_FLEN_BIT)
1390 #define SSI_CR1_PHA (1 << 1)
1391 #define SSI_CR1_POL (1 << 0)
1393 /* SSI Status Register (SSI_SR) */
1395 #define SSI_SR_TFIFONUM_BIT 13
1396 #define SSI_SR_TFIFONUM_MASK (0x1f << SSI_SR_TFIFONUM_BIT)
1397 #define SSI_SR_RFIFONUM_BIT 8
1398 #define SSI_SR_RFIFONUM_MASK (0x1f << SSI_SR_RFIFONUM_BIT)
1399 #define SSI_SR_END (1 << 7)
1400 #define SSI_SR_BUSY (1 << 6)
1401 #define SSI_SR_TFF (1 << 5)
1402 #define SSI_SR_RFE (1 << 4)
1403 #define SSI_SR_TFHE (1 << 3)
1404 #define SSI_SR_RFHF (1 << 2)
1405 #define SSI_SR_UNDR (1 << 1)
1406 #define SSI_SR_OVER (1 << 0)
1408 /* SSI Interval Time Control Register (SSI_ITR) */
1410 #define SSI_ITR_CNTCLK (1 << 15)
1411 #define SSI_ITR_IVLTM_BIT 0
1412 #define SSI_ITR_IVLTM_MASK (0x7fff << SSI_ITR_IVLTM_BIT)
1415 /*************************************************************************
1416 * MSC
1417 *************************************************************************/
1418 #define MSC_STRPCL (MSC_BASE + 0x000)
1419 #define MSC_STAT (MSC_BASE + 0x004)
1420 #define MSC_CLKRT (MSC_BASE + 0x008)
1421 #define MSC_CMDAT (MSC_BASE + 0x00C)
1422 #define MSC_RESTO (MSC_BASE + 0x010)
1423 #define MSC_RDTO (MSC_BASE + 0x014)
1424 #define MSC_BLKLEN (MSC_BASE + 0x018)
1425 #define MSC_NOB (MSC_BASE + 0x01C)
1426 #define MSC_SNOB (MSC_BASE + 0x020)
1427 #define MSC_IMASK (MSC_BASE + 0x024)
1428 #define MSC_IREG (MSC_BASE + 0x028)
1429 #define MSC_CMD (MSC_BASE + 0x02C)
1430 #define MSC_ARG (MSC_BASE + 0x030)
1431 #define MSC_RES (MSC_BASE + 0x034)
1432 #define MSC_RXFIFO (MSC_BASE + 0x038)
1433 #define MSC_TXFIFO (MSC_BASE + 0x03C)
1435 #define REG_MSC_STRPCL REG16(MSC_STRPCL)
1436 #define REG_MSC_STAT REG32(MSC_STAT)
1437 #define REG_MSC_CLKRT REG16(MSC_CLKRT)
1438 #define REG_MSC_CMDAT REG32(MSC_CMDAT)
1439 #define REG_MSC_RESTO REG16(MSC_RESTO)
1440 #define REG_MSC_RDTO REG16(MSC_RDTO)
1441 #define REG_MSC_BLKLEN REG16(MSC_BLKLEN)
1442 #define REG_MSC_NOB REG16(MSC_NOB)
1443 #define REG_MSC_SNOB REG16(MSC_SNOB)
1444 #define REG_MSC_IMASK REG16(MSC_IMASK)
1445 #define REG_MSC_IREG REG16(MSC_IREG)
1446 #define REG_MSC_CMD REG8(MSC_CMD)
1447 #define REG_MSC_ARG REG32(MSC_ARG)
1448 #define REG_MSC_RES REG16(MSC_RES)
1449 #define REG_MSC_RXFIFO REG32(MSC_RXFIFO)
1450 #define REG_MSC_TXFIFO REG32(MSC_TXFIFO)
1452 /* MSC Clock and Control Register (MSC_STRPCL) */
1454 #define MSC_STRPCL_EXIT_MULTIPLE (1 << 7)
1455 #define MSC_STRPCL_EXIT_TRANSFER (1 << 6)
1456 #define MSC_STRPCL_START_READWAIT (1 << 5)
1457 #define MSC_STRPCL_STOP_READWAIT (1 << 4)
1458 #define MSC_STRPCL_RESET (1 << 3)
1459 #define MSC_STRPCL_START_OP (1 << 2)
1460 #define MSC_STRPCL_CLOCK_CONTROL_BIT 0
1461 #define MSC_STRPCL_CLOCK_CONTROL_MASK (0x3 << MSC_STRPCL_CLOCK_CONTROL_BIT)
1462 #define MSC_STRPCL_CLOCK_CONTROL_STOP (0x1 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Stop MMC/SD clock */
1463 #define MSC_STRPCL_CLOCK_CONTROL_START (0x2 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Start MMC/SD clock */
1465 /* MSC Status Register (MSC_STAT) */
1467 #define MSC_STAT_IS_RESETTING (1 << 15)
1468 #define MSC_STAT_SDIO_INT_ACTIVE (1 << 14)
1469 #define MSC_STAT_PRG_DONE (1 << 13)
1470 #define MSC_STAT_DATA_TRAN_DONE (1 << 12)
1471 #define MSC_STAT_END_CMD_RES (1 << 11)
1472 #define MSC_STAT_DATA_FIFO_AFULL (1 << 10)
1473 #define MSC_STAT_IS_READWAIT (1 << 9)
1474 #define MSC_STAT_CLK_EN (1 << 8)
1475 #define MSC_STAT_DATA_FIFO_FULL (1 << 7)
1476 #define MSC_STAT_DATA_FIFO_EMPTY (1 << 6)
1477 #define MSC_STAT_CRC_RES_ERR (1 << 5)
1478 #define MSC_STAT_CRC_READ_ERROR (1 << 4)
1479 #define MSC_STAT_CRC_WRITE_ERROR_BIT 2
1480 #define MSC_STAT_CRC_WRITE_ERROR_MASK (0x3 << MSC_STAT_CRC_WRITE_ERROR_BIT)
1481 #define MSC_STAT_CRC_WRITE_ERROR_NO (0 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No error on transmission of data */
1482 #define MSC_STAT_CRC_WRITE_ERROR (1 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* Card observed erroneous transmission of data */
1483 #define MSC_STAT_CRC_WRITE_ERROR_NOSTS (2 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No CRC status is sent back */
1484 #define MSC_STAT_TIME_OUT_RES (1 << 1)
1485 #define MSC_STAT_TIME_OUT_READ (1 << 0)
1487 /* MSC Bus Clock Control Register (MSC_CLKRT) */
1489 #define MSC_CLKRT_CLK_RATE_BIT 0
1490 #define MSC_CLKRT_CLK_RATE_MASK (0x7 << MSC_CLKRT_CLK_RATE_BIT)
1491 #define MSC_CLKRT_CLK_RATE_DIV_1 (0x0 << MSC_CLKRT_CLK_RATE_BIT) /* CLK_SRC */
1492 #define MSC_CLKRT_CLK_RATE_DIV_2 (0x1 << MSC_CLKRT_CLK_RATE_BIT) /* 1/2 of CLK_SRC */
1493 #define MSC_CLKRT_CLK_RATE_DIV_4 (0x2 << MSC_CLKRT_CLK_RATE_BIT) /* 1/4 of CLK_SRC */
1494 #define MSC_CLKRT_CLK_RATE_DIV_8 (0x3 << MSC_CLKRT_CLK_RATE_BIT) /* 1/8 of CLK_SRC */
1495 #define MSC_CLKRT_CLK_RATE_DIV_16 (0x4 << MSC_CLKRT_CLK_RATE_BIT) /* 1/16 of CLK_SRC */
1496 #define MSC_CLKRT_CLK_RATE_DIV_32 (0x5 << MSC_CLKRT_CLK_RATE_BIT) /* 1/32 of CLK_SRC */
1497 #define MSC_CLKRT_CLK_RATE_DIV_64 (0x6 << MSC_CLKRT_CLK_RATE_BIT) /* 1/64 of CLK_SRC */
1498 #define MSC_CLKRT_CLK_RATE_DIV_128 (0x7 << MSC_CLKRT_CLK_RATE_BIT) /* 1/128 of CLK_SRC */
1500 /* MSC Command Sequence Control Register (MSC_CMDAT) */
1502 #define MSC_CMDAT_IO_ABORT (1 << 11)
1503 #define MSC_CMDAT_BUS_WIDTH_BIT 9
1504 #define MSC_CMDAT_BUS_WIDTH_MASK (0x3 << MSC_CMDAT_BUS_WIDTH_BIT)
1505 #define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) /* 1-bit data bus */
1506 #define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) /* 4-bit data bus */
1507 #define CMDAT_BUS_WIDTH1 (0x0 << MSC_CMDAT_BUS_WIDTH_BIT)
1508 #define CMDAT_BUS_WIDTH4 (0x2 << MSC_CMDAT_BUS_WIDTH_BIT)
1509 #define MSC_CMDAT_DMA_EN (1 << 8)
1510 #define MSC_CMDAT_INIT (1 << 7)
1511 #define MSC_CMDAT_BUSY (1 << 6)
1512 #define MSC_CMDAT_STREAM_BLOCK (1 << 5)
1513 #define MSC_CMDAT_WRITE (1 << 4)
1514 #define MSC_CMDAT_READ (0 << 4)
1515 #define MSC_CMDAT_DATA_EN (1 << 3)
1516 #define MSC_CMDAT_RESPONSE_BIT 0
1517 #define MSC_CMDAT_RESPONSE_MASK (0x7 << MSC_CMDAT_RESPONSE_BIT)
1518 #define MSC_CMDAT_RESPONSE_NONE (0x0 << MSC_CMDAT_RESPONSE_BIT) /* No response */
1519 #define MSC_CMDAT_RESPONSE_R1 (0x1 << MSC_CMDAT_RESPONSE_BIT) /* Format R1 and R1b */
1520 #define MSC_CMDAT_RESPONSE_R2 (0x2 << MSC_CMDAT_RESPONSE_BIT) /* Format R2 */
1521 #define MSC_CMDAT_RESPONSE_R3 (0x3 << MSC_CMDAT_RESPONSE_BIT) /* Format R3 */
1522 #define MSC_CMDAT_RESPONSE_R4 (0x4 << MSC_CMDAT_RESPONSE_BIT) /* Format R4 */
1523 #define MSC_CMDAT_RESPONSE_R5 (0x5 << MSC_CMDAT_RESPONSE_BIT) /* Format R5 */
1524 #define MSC_CMDAT_RESPONSE_R6 (0x6 << MSC_CMDAT_RESPONSE_BIT) /* Format R6 */
1526 #define CMDAT_DMA_EN (1 << 8)
1527 #define CMDAT_INIT (1 << 7)
1528 #define CMDAT_BUSY (1 << 6)
1529 #define CMDAT_STREAM (1 << 5)
1530 #define CMDAT_WRITE (1 << 4)
1531 #define CMDAT_DATA_EN (1 << 3)
1533 /* MSC Interrupts Mask Register (MSC_IMASK) */
1535 #define MSC_IMASK_SDIO (1 << 7)
1536 #define MSC_IMASK_TXFIFO_WR_REQ (1 << 6)
1537 #define MSC_IMASK_RXFIFO_RD_REQ (1 << 5)
1538 #define MSC_IMASK_END_CMD_RES (1 << 2)
1539 #define MSC_IMASK_PRG_DONE (1 << 1)
1540 #define MSC_IMASK_DATA_TRAN_DONE (1 << 0)
1543 /* MSC Interrupts Status Register (MSC_IREG) */
1545 #define MSC_IREG_SDIO (1 << 7)
1546 #define MSC_IREG_TXFIFO_WR_REQ (1 << 6)
1547 #define MSC_IREG_RXFIFO_RD_REQ (1 << 5)
1548 #define MSC_IREG_END_CMD_RES (1 << 2)
1549 #define MSC_IREG_PRG_DONE (1 << 1)
1550 #define MSC_IREG_DATA_TRAN_DONE (1 << 0)
1553 /*************************************************************************
1554 * EMC (External Memory Controller)
1555 *************************************************************************/
1556 #define EMC_BCR (EMC_BASE + 0x10) /* BCR */
1558 #define EMC_SMCR0 (EMC_BASE + 0x10) /* Static Memory Control Register 0 */
1559 #define EMC_SMCR1 (EMC_BASE + 0x14) /* Static Memory Control Register 1 */
1560 #define EMC_SMCR2 (EMC_BASE + 0x18) /* Static Memory Control Register 2 */
1561 #define EMC_SMCR3 (EMC_BASE + 0x1c) /* Static Memory Control Register 3 */
1562 #define EMC_SMCR4 (EMC_BASE + 0x20) /* Static Memory Control Register 4 */
1563 #define EMC_SACR0 (EMC_BASE + 0x30) /* Static Memory Bank 0 Addr Config Reg */
1564 #define EMC_SACR1 (EMC_BASE + 0x34) /* Static Memory Bank 1 Addr Config Reg */
1565 #define EMC_SACR2 (EMC_BASE + 0x38) /* Static Memory Bank 2 Addr Config Reg */
1566 #define EMC_SACR3 (EMC_BASE + 0x3c) /* Static Memory Bank 3 Addr Config Reg */
1567 #define EMC_SACR4 (EMC_BASE + 0x40) /* Static Memory Bank 4 Addr Config Reg */
1569 #define EMC_NFCSR (EMC_BASE + 0x050) /* NAND Flash Control/Status Register */
1570 #define EMC_NFECR (EMC_BASE + 0x100) /* NAND Flash ECC Control Register */
1571 #define EMC_NFECC (EMC_BASE + 0x104) /* NAND Flash ECC Data Register */
1572 #define EMC_NFPAR0 (EMC_BASE + 0x108) /* NAND Flash RS Parity 0 Register */
1573 #define EMC_NFPAR1 (EMC_BASE + 0x10c) /* NAND Flash RS Parity 1 Register */
1574 #define EMC_NFPAR2 (EMC_BASE + 0x110) /* NAND Flash RS Parity 2 Register */
1575 #define EMC_NFINTS (EMC_BASE + 0x114) /* NAND Flash Interrupt Status Register */
1576 #define EMC_NFINTE (EMC_BASE + 0x118) /* NAND Flash Interrupt Enable Register */
1577 #define EMC_NFERR0 (EMC_BASE + 0x11c) /* NAND Flash RS Error Report 0 Register */
1578 #define EMC_NFERR1 (EMC_BASE + 0x120) /* NAND Flash RS Error Report 1 Register */
1579 #define EMC_NFERR2 (EMC_BASE + 0x124) /* NAND Flash RS Error Report 2 Register */
1580 #define EMC_NFERR3 (EMC_BASE + 0x128) /* NAND Flash RS Error Report 3 Register */
1582 #define EMC_DMCR (EMC_BASE + 0x80) /* DRAM Control Register */
1583 #define EMC_RTCSR (EMC_BASE + 0x84) /* Refresh Time Control/Status Register */
1584 #define EMC_RTCNT (EMC_BASE + 0x88) /* Refresh Timer Counter */
1585 #define EMC_RTCOR (EMC_BASE + 0x8c) /* Refresh Time Constant Register */
1586 #define EMC_DMAR0 (EMC_BASE + 0x90) /* SDRAM Bank 0 Addr Config Register */
1587 #define EMC_SDMR0 (EMC_BASE + 0xa000) /* Mode Register of SDRAM bank 0 */
1589 #define REG_EMC_BCR REG32(EMC_BCR)
1591 #define REG_EMC_SMCR0 REG32(EMC_SMCR0)
1592 #define REG_EMC_SMCR1 REG32(EMC_SMCR1)
1593 #define REG_EMC_SMCR2 REG32(EMC_SMCR2)
1594 #define REG_EMC_SMCR3 REG32(EMC_SMCR3)
1595 #define REG_EMC_SMCR4 REG32(EMC_SMCR4)
1596 #define REG_EMC_SACR0 REG32(EMC_SACR0)
1597 #define REG_EMC_SACR1 REG32(EMC_SACR1)
1598 #define REG_EMC_SACR2 REG32(EMC_SACR2)
1599 #define REG_EMC_SACR3 REG32(EMC_SACR3)
1600 #define REG_EMC_SACR4 REG32(EMC_SACR4)
1602 #define REG_EMC_NFCSR REG32(EMC_NFCSR)
1603 #define REG_EMC_NFECR REG32(EMC_NFECR)
1604 #define REG_EMC_NFECC REG32(EMC_NFECC)
1605 #define REG_EMC_NFPAR0 REG32(EMC_NFPAR0)
1606 #define REG_EMC_NFPAR1 REG32(EMC_NFPAR1)
1607 #define REG_EMC_NFPAR2 REG32(EMC_NFPAR2)
1608 #define REG_EMC_NFINTS REG32(EMC_NFINTS)
1609 #define REG_EMC_NFINTE REG32(EMC_NFINTE)
1610 #define REG_EMC_NFERR0 REG32(EMC_NFERR0)
1611 #define REG_EMC_NFERR1 REG32(EMC_NFERR1)
1612 #define REG_EMC_NFERR2 REG32(EMC_NFERR2)
1613 #define REG_EMC_NFERR3 REG32(EMC_NFERR3)
1615 #define REG_EMC_DMCR REG32(EMC_DMCR)
1616 #define REG_EMC_RTCSR REG16(EMC_RTCSR)
1617 #define REG_EMC_RTCNT REG16(EMC_RTCNT)
1618 #define REG_EMC_RTCOR REG16(EMC_RTCOR)
1619 #define REG_EMC_DMAR0 REG32(EMC_DMAR0)
1621 /* Static Memory Control Register */
1622 #define EMC_SMCR_STRV_BIT 24
1623 #define EMC_SMCR_STRV_MASK (0x0f << EMC_SMCR_STRV_BIT)
1624 #define EMC_SMCR_TAW_BIT 20
1625 #define EMC_SMCR_TAW_MASK (0x0f << EMC_SMCR_TAW_BIT)
1626 #define EMC_SMCR_TBP_BIT 16
1627 #define EMC_SMCR_TBP_MASK (0x0f << EMC_SMCR_TBP_BIT)
1628 #define EMC_SMCR_TAH_BIT 12
1629 #define EMC_SMCR_TAH_MASK (0x07 << EMC_SMCR_TAH_BIT)
1630 #define EMC_SMCR_TAS_BIT 8
1631 #define EMC_SMCR_TAS_MASK (0x07 << EMC_SMCR_TAS_BIT)
1632 #define EMC_SMCR_BW_BIT 6
1633 #define EMC_SMCR_BW_MASK (0x03 << EMC_SMCR_BW_BIT)
1634 #define EMC_SMCR_BW_8BIT (0 << EMC_SMCR_BW_BIT)
1635 #define EMC_SMCR_BW_16BIT (1 << EMC_SMCR_BW_BIT)
1636 #define EMC_SMCR_BW_32BIT (2 << EMC_SMCR_BW_BIT)
1637 #define EMC_SMCR_BCM (1 << 3)
1638 #define EMC_SMCR_BL_BIT 1
1639 #define EMC_SMCR_BL_MASK (0x03 << EMC_SMCR_BL_BIT)
1640 #define EMC_SMCR_BL_4 (0 << EMC_SMCR_BL_BIT)
1641 #define EMC_SMCR_BL_8 (1 << EMC_SMCR_BL_BIT)
1642 #define EMC_SMCR_BL_16 (2 << EMC_SMCR_BL_BIT)
1643 #define EMC_SMCR_BL_32 (3 << EMC_SMCR_BL_BIT)
1644 #define EMC_SMCR_SMT (1 << 0)
1646 /* Static Memory Bank Addr Config Reg */
1647 #define EMC_SACR_BASE_BIT 8
1648 #define EMC_SACR_BASE_MASK (0xff << EMC_SACR_BASE_BIT)
1649 #define EMC_SACR_MASK_BIT 0
1650 #define EMC_SACR_MASK_MASK (0xff << EMC_SACR_MASK_BIT)
1652 /* NAND Flash Control/Status Register */
1653 #define EMC_NFCSR_NFCE4 (1 << 7) /* NAND Flash Enable */
1654 #define EMC_NFCSR_NFE4 (1 << 6) /* NAND Flash FCE# Assertion Enable */
1655 #define EMC_NFCSR_NFCE3 (1 << 5)
1656 #define EMC_NFCSR_NFE3 (1 << 4)
1657 #define EMC_NFCSR_NFCE2 (1 << 3)
1658 #define EMC_NFCSR_NFE2 (1 << 2)
1659 #define EMC_NFCSR_NFCE1 (1 << 1)
1660 #define EMC_NFCSR_NFE1 (1 << 0)
1662 /* NAND Flash ECC Control Register */
1663 #define EMC_NFECR_PRDY (1 << 4) /* Parity Ready */
1664 #define EMC_NFECR_RS_DECODING (0 << 3) /* RS is in decoding phase */
1665 #define EMC_NFECR_RS_ENCODING (1 << 3) /* RS is in encoding phase */
1666 #define EMC_NFECR_HAMMING (0 << 2) /* Select HAMMING Correction Algorithm */
1667 #define EMC_NFECR_RS (1 << 2) /* Select RS Correction Algorithm */
1668 #define EMC_NFECR_ERST (1 << 1) /* ECC Reset */
1669 #define EMC_NFECR_ECCE (1 << 0) /* ECC Enable */
1671 /* NAND Flash ECC Data Register */
1672 #define EMC_NFECC_ECC2_BIT 16
1673 #define EMC_NFECC_ECC2_MASK (0xff << EMC_NFECC_ECC2_BIT)
1674 #define EMC_NFECC_ECC1_BIT 8
1675 #define EMC_NFECC_ECC1_MASK (0xff << EMC_NFECC_ECC1_BIT)
1676 #define EMC_NFECC_ECC0_BIT 0
1677 #define EMC_NFECC_ECC0_MASK (0xff << EMC_NFECC_ECC0_BIT)
1679 /* NAND Flash Interrupt Status Register */
1680 #define EMC_NFINTS_ERRCNT_BIT 29 /* Error Count */
1681 #define EMC_NFINTS_ERRCNT_MASK (0x7 << EMC_NFINTS_ERRCNT_BIT)
1682 #define EMC_NFINTS_PADF (1 << 4) /* Padding Finished */
1683 #define EMC_NFINTS_DECF (1 << 3) /* Decoding Finished */
1684 #define EMC_NFINTS_ENCF (1 << 2) /* Encoding Finished */
1685 #define EMC_NFINTS_UNCOR (1 << 1) /* Uncorrectable Error Occurred */
1686 #define EMC_NFINTS_ERR (1 << 0) /* Error Occurred */
1688 /* NAND Flash Interrupt Enable Register */
1689 #define EMC_NFINTE_PADFE (1 << 4) /* Padding Finished Interrupt Enable */
1690 #define EMC_NFINTE_DECFE (1 << 3) /* Decoding Finished Interrupt Enable */
1691 #define EMC_NFINTE_ENCFE (1 << 2) /* Encoding Finished Interrupt Enable */
1692 #define EMC_NFINTE_UNCORE (1 << 1) /* Uncorrectable Error Occurred Intr Enable */
1693 #define EMC_NFINTE_ERRE (1 << 0) /* Error Occurred Interrupt */
1695 /* NAND Flash RS Error Report Register */
1696 #define EMC_NFERR_INDEX_BIT 16 /* Error Symbol Index */
1697 #define EMC_NFERR_INDEX_MASK (0x1ff << EMC_NFERR_INDEX_BIT)
1698 #define EMC_NFERR_MASK_BIT 0 /* Error Symbol Value */
1699 #define EMC_NFERR_MASK_MASK (0x1ff << EMC_NFERR_MASK_BIT)
1702 /* DRAM Control Register */
1703 #define EMC_DMCR_BW_BIT 31
1704 #define EMC_DMCR_BW (1 << EMC_DMCR_BW_BIT)
1705 #define EMC_DMCR_CA_BIT 26
1706 #define EMC_DMCR_CA_MASK (0x07 << EMC_DMCR_CA_BIT)
1707 #define EMC_DMCR_CA_8 (0 << EMC_DMCR_CA_BIT)
1708 #define EMC_DMCR_CA_9 (1 << EMC_DMCR_CA_BIT)
1709 #define EMC_DMCR_CA_10 (2 << EMC_DMCR_CA_BIT)
1710 #define EMC_DMCR_CA_11 (3 << EMC_DMCR_CA_BIT)
1711 #define EMC_DMCR_CA_12 (4 << EMC_DMCR_CA_BIT)
1712 #define EMC_DMCR_RMODE (1 << 25)
1713 #define EMC_DMCR_RFSH (1 << 24)
1714 #define EMC_DMCR_MRSET (1 << 23)
1715 #define EMC_DMCR_RA_BIT 20
1716 #define EMC_DMCR_RA_MASK (0x03 << EMC_DMCR_RA_BIT)
1717 #define EMC_DMCR_RA_11 (0 << EMC_DMCR_RA_BIT)
1718 #define EMC_DMCR_RA_12 (1 << EMC_DMCR_RA_BIT)
1719 #define EMC_DMCR_RA_13 (2 << EMC_DMCR_RA_BIT)
1720 #define EMC_DMCR_BA_BIT 19
1721 #define EMC_DMCR_BA (1 << EMC_DMCR_BA_BIT)
1722 #define EMC_DMCR_PDM (1 << 18)
1723 #define EMC_DMCR_EPIN (1 << 17)
1724 #define EMC_DMCR_TRAS_BIT 13
1725 #define EMC_DMCR_TRAS_MASK (0x07 << EMC_DMCR_TRAS_BIT)
1726 #define EMC_DMCR_RCD_BIT 11
1727 #define EMC_DMCR_RCD_MASK (0x03 << EMC_DMCR_RCD_BIT)
1728 #define EMC_DMCR_TPC_BIT 8
1729 #define EMC_DMCR_TPC_MASK (0x07 << EMC_DMCR_TPC_BIT)
1730 #define EMC_DMCR_TRWL_BIT 5
1731 #define EMC_DMCR_TRWL_MASK (0x03 << EMC_DMCR_TRWL_BIT)
1732 #define EMC_DMCR_TRC_BIT 2
1733 #define EMC_DMCR_TRC_MASK (0x07 << EMC_DMCR_TRC_BIT)
1734 #define EMC_DMCR_TCL_BIT 0
1735 #define EMC_DMCR_TCL_MASK (0x03 << EMC_DMCR_TCL_BIT)
1737 /* Refresh Time Control/Status Register */
1738 #define EMC_RTCSR_CMF (1 << 7)
1739 #define EMC_RTCSR_CKS_BIT 0
1740 #define EMC_RTCSR_CKS_MASK (0x07 << EMC_RTCSR_CKS_BIT)
1741 #define EMC_RTCSR_CKS_DISABLE (0 << EMC_RTCSR_CKS_BIT)
1742 #define EMC_RTCSR_CKS_4 (1 << EMC_RTCSR_CKS_BIT)
1743 #define EMC_RTCSR_CKS_16 (2 << EMC_RTCSR_CKS_BIT)
1744 #define EMC_RTCSR_CKS_64 (3 << EMC_RTCSR_CKS_BIT)
1745 #define EMC_RTCSR_CKS_256 (4 << EMC_RTCSR_CKS_BIT)
1746 #define EMC_RTCSR_CKS_1024 (5 << EMC_RTCSR_CKS_BIT)
1747 #define EMC_RTCSR_CKS_2048 (6 << EMC_RTCSR_CKS_BIT)
1748 #define EMC_RTCSR_CKS_4096 (7 << EMC_RTCSR_CKS_BIT)
1750 /* SDRAM Bank Address Configuration Register */
1751 #define EMC_DMAR_BASE_BIT 8
1752 #define EMC_DMAR_BASE_MASK (0xff << EMC_DMAR_BASE_BIT)
1753 #define EMC_DMAR_MASK_BIT 0
1754 #define EMC_DMAR_MASK_MASK (0xff << EMC_DMAR_MASK_BIT)
1756 /* Mode Register of SDRAM bank 0 */
1757 #define EMC_SDMR_BM (1 << 9) /* Write Burst Mode */
1758 #define EMC_SDMR_OM_BIT 7 /* Operating Mode */
1759 #define EMC_SDMR_OM_MASK (3 << EMC_SDMR_OM_BIT)
1760 #define EMC_SDMR_OM_NORMAL (0 << EMC_SDMR_OM_BIT)
1761 #define EMC_SDMR_CAS_BIT 4 /* CAS Latency */
1762 #define EMC_SDMR_CAS_MASK (7 << EMC_SDMR_CAS_BIT)
1763 #define EMC_SDMR_CAS_1 (1 << EMC_SDMR_CAS_BIT)
1764 #define EMC_SDMR_CAS_2 (2 << EMC_SDMR_CAS_BIT)
1765 #define EMC_SDMR_CAS_3 (3 << EMC_SDMR_CAS_BIT)
1766 #define EMC_SDMR_BT_BIT 3 /* Burst Type */
1767 #define EMC_SDMR_BT_MASK (1 << EMC_SDMR_BT_BIT)
1768 #define EMC_SDMR_BT_SEQ (0 << EMC_SDMR_BT_BIT) /* Sequential */
1769 #define EMC_SDMR_BT_INT (1 << EMC_SDMR_BT_BIT) /* Interleave */
1770 #define EMC_SDMR_BL_BIT 0 /* Burst Length */
1771 #define EMC_SDMR_BL_MASK (7 << EMC_SDMR_BL_BIT)
1772 #define EMC_SDMR_BL_1 (0 << EMC_SDMR_BL_BIT)
1773 #define EMC_SDMR_BL_2 (1 << EMC_SDMR_BL_BIT)
1774 #define EMC_SDMR_BL_4 (2 << EMC_SDMR_BL_BIT)
1775 #define EMC_SDMR_BL_8 (3 << EMC_SDMR_BL_BIT)
1777 #define EMC_SDMR_CAS2_16BIT \
1778 (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
1779 #define EMC_SDMR_CAS2_32BIT \
1780 (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
1781 #define EMC_SDMR_CAS3_16BIT \
1782 (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
1783 #define EMC_SDMR_CAS3_32BIT \
1784 (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
1787 /*************************************************************************
1788 * CIM
1789 *************************************************************************/
1790 #define CIM_CFG (CIM_BASE + 0x0000)
1791 #define CIM_CTRL (CIM_BASE + 0x0004)
1792 #define CIM_STATE (CIM_BASE + 0x0008)
1793 #define CIM_IID (CIM_BASE + 0x000C)
1794 #define CIM_RXFIFO (CIM_BASE + 0x0010)
1795 #define CIM_DA (CIM_BASE + 0x0020)
1796 #define CIM_FA (CIM_BASE + 0x0024)
1797 #define CIM_FID (CIM_BASE + 0x0028)
1798 #define CIM_CMD (CIM_BASE + 0x002C)
1800 #define REG_CIM_CFG REG32(CIM_CFG)
1801 #define REG_CIM_CTRL REG32(CIM_CTRL)
1802 #define REG_CIM_STATE REG32(CIM_STATE)
1803 #define REG_CIM_IID REG32(CIM_IID)
1804 #define REG_CIM_RXFIFO REG32(CIM_RXFIFO)
1805 #define REG_CIM_DA REG32(CIM_DA)
1806 #define REG_CIM_FA REG32(CIM_FA)
1807 #define REG_CIM_FID REG32(CIM_FID)
1808 #define REG_CIM_CMD REG32(CIM_CMD)
1810 /* CIM Configuration Register (CIM_CFG) */
1812 #define CIM_CFG_INV_DAT (1 << 15)
1813 #define CIM_CFG_VSP (1 << 14)
1814 #define CIM_CFG_HSP (1 << 13)
1815 #define CIM_CFG_PCP (1 << 12)
1816 #define CIM_CFG_DUMMY_ZERO (1 << 9)
1817 #define CIM_CFG_EXT_VSYNC (1 << 8)
1818 #define CIM_CFG_PACK_BIT 4
1819 #define CIM_CFG_PACK_MASK (0x7 << CIM_CFG_PACK_BIT)
1820 #define CIM_CFG_PACK_0 (0 << CIM_CFG_PACK_BIT)
1821 #define CIM_CFG_PACK_1 (1 << CIM_CFG_PACK_BIT)
1822 #define CIM_CFG_PACK_2 (2 << CIM_CFG_PACK_BIT)
1823 #define CIM_CFG_PACK_3 (3 << CIM_CFG_PACK_BIT)
1824 #define CIM_CFG_PACK_4 (4 << CIM_CFG_PACK_BIT)
1825 #define CIM_CFG_PACK_5 (5 << CIM_CFG_PACK_BIT)
1826 #define CIM_CFG_PACK_6 (6 << CIM_CFG_PACK_BIT)
1827 #define CIM_CFG_PACK_7 (7 << CIM_CFG_PACK_BIT)
1828 #define CIM_CFG_DSM_BIT 0
1829 #define CIM_CFG_DSM_MASK (0x3 << CIM_CFG_DSM_BIT)
1830 #define CIM_CFG_DSM_CPM (0 << CIM_CFG_DSM_BIT) /* CCIR656 Progressive Mode */
1831 #define CIM_CFG_DSM_CIM (1 << CIM_CFG_DSM_BIT) /* CCIR656 Interlace Mode */
1832 #define CIM_CFG_DSM_GCM (2 << CIM_CFG_DSM_BIT) /* Gated Clock Mode */
1833 #define CIM_CFG_DSM_NGCM (3 << CIM_CFG_DSM_BIT) /* Non-Gated Clock Mode */
1835 /* CIM Control Register (CIM_CTRL) */
1837 #define CIM_CTRL_MCLKDIV_BIT 24
1838 #define CIM_CTRL_MCLKDIV_MASK (0xff << CIM_CTRL_MCLKDIV_BIT)
1839 #define CIM_CTRL_FRC_BIT 16
1840 #define CIM_CTRL_FRC_MASK (0xf << CIM_CTRL_FRC_BIT)
1841 #define CIM_CTRL_FRC_1 (0x0 << CIM_CTRL_FRC_BIT) /* Sample every frame */
1842 #define CIM_CTRL_FRC_2 (0x1 << CIM_CTRL_FRC_BIT) /* Sample 1/2 frame */
1843 #define CIM_CTRL_FRC_3 (0x2 << CIM_CTRL_FRC_BIT) /* Sample 1/3 frame */
1844 #define CIM_CTRL_FRC_4 (0x3 << CIM_CTRL_FRC_BIT) /* Sample 1/4 frame */
1845 #define CIM_CTRL_FRC_5 (0x4 << CIM_CTRL_FRC_BIT) /* Sample 1/5 frame */
1846 #define CIM_CTRL_FRC_6 (0x5 << CIM_CTRL_FRC_BIT) /* Sample 1/6 frame */
1847 #define CIM_CTRL_FRC_7 (0x6 << CIM_CTRL_FRC_BIT) /* Sample 1/7 frame */
1848 #define CIM_CTRL_FRC_8 (0x7 << CIM_CTRL_FRC_BIT) /* Sample 1/8 frame */
1849 #define CIM_CTRL_FRC_9 (0x8 << CIM_CTRL_FRC_BIT) /* Sample 1/9 frame */
1850 #define CIM_CTRL_FRC_10 (0x9 << CIM_CTRL_FRC_BIT) /* Sample 1/10 frame */
1851 #define CIM_CTRL_FRC_11 (0xA << CIM_CTRL_FRC_BIT) /* Sample 1/11 frame */
1852 #define CIM_CTRL_FRC_12 (0xB << CIM_CTRL_FRC_BIT) /* Sample 1/12 frame */
1853 #define CIM_CTRL_FRC_13 (0xC << CIM_CTRL_FRC_BIT) /* Sample 1/13 frame */
1854 #define CIM_CTRL_FRC_14 (0xD << CIM_CTRL_FRC_BIT) /* Sample 1/14 frame */
1855 #define CIM_CTRL_FRC_15 (0xE << CIM_CTRL_FRC_BIT) /* Sample 1/15 frame */
1856 #define CIM_CTRL_FRC_16 (0xF << CIM_CTRL_FRC_BIT) /* Sample 1/16 frame */
1857 #define CIM_CTRL_VDDM (1 << 13)
1858 #define CIM_CTRL_DMA_SOFM (1 << 12)
1859 #define CIM_CTRL_DMA_EOFM (1 << 11)
1860 #define CIM_CTRL_DMA_STOPM (1 << 10)
1861 #define CIM_CTRL_RXF_TRIGM (1 << 9)
1862 #define CIM_CTRL_RXF_OFM (1 << 8)
1863 #define CIM_CTRL_RXF_TRIG_BIT 4
1864 #define CIM_CTRL_RXF_TRIG_MASK (0x7 << CIM_CTRL_RXF_TRIG_BIT)
1865 #define CIM_CTRL_RXF_TRIG_4 (0 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 4 */
1866 #define CIM_CTRL_RXF_TRIG_8 (1 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 8 */
1867 #define CIM_CTRL_RXF_TRIG_12 (2 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 12 */
1868 #define CIM_CTRL_RXF_TRIG_16 (3 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 16 */
1869 #define CIM_CTRL_RXF_TRIG_20 (4 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 20 */
1870 #define CIM_CTRL_RXF_TRIG_24 (5 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 24 */
1871 #define CIM_CTRL_RXF_TRIG_28 (6 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 28 */
1872 #define CIM_CTRL_RXF_TRIG_32 (7 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 32 */
1873 #define CIM_CTRL_DMA_EN (1 << 2)
1874 #define CIM_CTRL_RXF_RST (1 << 1)
1875 #define CIM_CTRL_ENA (1 << 0)
1877 /* CIM State Register (CIM_STATE) */
1879 #define CIM_STATE_DMA_SOF (1 << 6)
1880 #define CIM_STATE_DMA_EOF (1 << 5)
1881 #define CIM_STATE_DMA_STOP (1 << 4)
1882 #define CIM_STATE_RXF_OF (1 << 3)
1883 #define CIM_STATE_RXF_TRIG (1 << 2)
1884 #define CIM_STATE_RXF_EMPTY (1 << 1)
1885 #define CIM_STATE_VDD (1 << 0)
1887 /* CIM DMA Command Register (CIM_CMD) */
1889 #define CIM_CMD_SOFINT (1 << 31)
1890 #define CIM_CMD_EOFINT (1 << 30)
1891 #define CIM_CMD_STOP (1 << 28)
1892 #define CIM_CMD_LEN_BIT 0
1893 #define CIM_CMD_LEN_MASK (0xffffff << CIM_CMD_LEN_BIT)
1896 /*************************************************************************
1897 * SADC (Smart A/D Controller)
1898 *************************************************************************/
1900 #define SADC_ENA (SADC_BASE + 0x00) /* ADC Enable Register */
1901 #define SADC_CFG (SADC_BASE + 0x04) /* ADC Configure Register */
1902 #define SADC_CTRL (SADC_BASE + 0x08) /* ADC Control Register */
1903 #define SADC_STATE (SADC_BASE + 0x0C) /* ADC Status Register*/
1904 #define SADC_SAMETIME (SADC_BASE + 0x10) /* ADC Same Point Time Register */
1905 #define SADC_WAITTIME (SADC_BASE + 0x14) /* ADC Wait Time Register */
1906 #define SADC_TSDAT (SADC_BASE + 0x18) /* ADC Touch Screen Data Register */
1907 #define SADC_BATDAT (SADC_BASE + 0x1C) /* ADC PBAT Data Register */
1908 #define SADC_SADDAT (SADC_BASE + 0x20) /* ADC SADCIN Data Register */
1910 #define REG_SADC_ENA REG8(SADC_ENA)
1911 #define REG_SADC_CFG REG32(SADC_CFG)
1912 #define REG_SADC_CTRL REG8(SADC_CTRL)
1913 #define REG_SADC_STATE REG8(SADC_STATE)
1914 #define REG_SADC_SAMETIME REG16(SADC_SAMETIME)
1915 #define REG_SADC_WAITTIME REG16(SADC_WAITTIME)
1916 #define REG_SADC_TSDAT REG32(SADC_TSDAT)
1917 #define REG_SADC_BATDAT REG16(SADC_BATDAT)
1918 #define REG_SADC_SADDAT REG16(SADC_SADDAT)
1920 /* ADC Enable Register */
1921 #define SADC_ENA_ADEN (1 << 7) /* Touch Screen Enable */
1922 #define SADC_ENA_TSEN (1 << 2) /* Touch Screen Enable */
1923 #define SADC_ENA_PBATEN (1 << 1) /* PBAT Enable */
1924 #define SADC_ENA_SADCINEN (1 << 0) /* SADCIN Enable */
1926 /* ADC Configure Register */
1927 #define SADC_CFG_CLKOUT_NUM_BIT 16
1928 #define SADC_CFG_CLKOUT_NUM_MASK (0x7 << SADC_CFG_CLKOUT_NUM_BIT)
1929 #define SADC_CFG_TS_DMA (1 << 15) /* Touch Screen DMA Enable */
1930 #define SADC_CFG_XYZ_BIT 13 /* XYZ selection */
1931 #define SADC_CFG_XYZ_MASK (0x3 << SADC_CFG_XYZ_BIT)
1932 #define SADC_CFG_XY (0 << SADC_CFG_XYZ_BIT)
1933 #define SADC_CFG_XYZ (1 << SADC_CFG_XYZ_BIT)
1934 #define SADC_CFG_XYZ1Z2 (2 << SADC_CFG_XYZ_BIT)
1935 #define SADC_CFG_SNUM_BIT 10 /* Sample Number */
1936 #define SADC_CFG_SNUM_MASK (0x7 << SADC_CFG_SNUM_BIT)
1937 #define SADC_CFG_SNUM_1 (0x0 << SADC_CFG_SNUM_BIT)
1938 #define SADC_CFG_SNUM_2 (0x1 << SADC_CFG_SNUM_BIT)
1939 #define SADC_CFG_SNUM_3 (0x2 << SADC_CFG_SNUM_BIT)
1940 #define SADC_CFG_SNUM_4 (0x3 << SADC_CFG_SNUM_BIT)
1941 #define SADC_CFG_SNUM_5 (0x4 << SADC_CFG_SNUM_BIT)
1942 #define SADC_CFG_SNUM_6 (0x5 << SADC_CFG_SNUM_BIT)
1943 #define SADC_CFG_SNUM_8 (0x6 << SADC_CFG_SNUM_BIT)
1944 #define SADC_CFG_SNUM_9 (0x7 << SADC_CFG_SNUM_BIT)
1945 #define SADC_CFG_CLKDIV_BIT 5 /* AD Converter frequency clock divider */
1946 #define SADC_CFG_CLKDIV_MASK (0x1f << SADC_CFG_CLKDIV_BIT)
1947 #define SADC_CFG_PBAT_HIGH (0 << 4) /* PBAT >= 2.5V */
1948 #define SADC_CFG_PBAT_LOW (1 << 4) /* PBAT < 2.5V */
1949 #define SADC_CFG_CMD_BIT 0 /* ADC Command */
1950 #define SADC_CFG_CMD_MASK (0xf << SADC_CFG_CMD_BIT)
1951 #define SADC_CFG_CMD_X_SE (0x0 << SADC_CFG_CMD_BIT) /* X Single-End */
1952 #define SADC_CFG_CMD_Y_SE (0x1 << SADC_CFG_CMD_BIT) /* Y Single-End */
1953 #define SADC_CFG_CMD_X_DIFF (0x2 << SADC_CFG_CMD_BIT) /* X Differential */
1954 #define SADC_CFG_CMD_Y_DIFF (0x3 << SADC_CFG_CMD_BIT) /* Y Differential */
1955 #define SADC_CFG_CMD_Z1_DIFF (0x4 << SADC_CFG_CMD_BIT) /* Z1 Differential */
1956 #define SADC_CFG_CMD_Z2_DIFF (0x5 << SADC_CFG_CMD_BIT) /* Z2 Differential */
1957 #define SADC_CFG_CMD_Z3_DIFF (0x6 << SADC_CFG_CMD_BIT) /* Z3 Differential */
1958 #define SADC_CFG_CMD_Z4_DIFF (0x7 << SADC_CFG_CMD_BIT) /* Z4 Differential */
1959 #define SADC_CFG_CMD_TP_SE (0x8 << SADC_CFG_CMD_BIT) /* Touch Pressure */
1960 #define SADC_CFG_CMD_PBATH_SE (0x9 << SADC_CFG_CMD_BIT) /* PBAT >= 2.5V */
1961 #define SADC_CFG_CMD_PBATL_SE (0xa << SADC_CFG_CMD_BIT) /* PBAT < 2.5V */
1962 #define SADC_CFG_CMD_SADCIN_SE (0xb << SADC_CFG_CMD_BIT) /* Measure SADCIN */
1963 #define SADC_CFG_CMD_INT_PEN (0xc << SADC_CFG_CMD_BIT) /* INT_PEN Enable */
1965 /* ADC Control Register */
1966 #define SADC_CTRL_PENDM (1 << 4) /* Pen Down Interrupt Mask */
1967 #define SADC_CTRL_PENUM (1 << 3) /* Pen Up Interrupt Mask */
1968 #define SADC_CTRL_TSRDYM (1 << 2) /* Touch Screen Data Ready Interrupt Mask */
1969 #define SADC_CTRL_PBATRDYM (1 << 1) /* PBAT Data Ready Interrupt Mask */
1970 #define SADC_CTRL_SRDYM (1 << 0) /* SADCIN Data Ready Interrupt Mask */
1972 /* ADC Status Register */
1973 #define SADC_STATE_TSBUSY (1 << 7) /* TS A/D is working */
1974 #define SADC_STATE_PBATBUSY (1 << 6) /* PBAT A/D is working */
1975 #define SADC_STATE_SBUSY (1 << 5) /* SADCIN A/D is working */
1976 #define SADC_STATE_PEND (1 << 4) /* Pen Down Interrupt Flag */
1977 #define SADC_STATE_PENU (1 << 3) /* Pen Up Interrupt Flag */
1978 #define SADC_STATE_TSRDY (1 << 2) /* Touch Screen Data Ready Interrupt Flag */
1979 #define SADC_STATE_PBATRDY (1 << 1) /* PBAT Data Ready Interrupt Flag */
1980 #define SADC_STATE_SRDY (1 << 0) /* SADCIN Data Ready Interrupt Flag */
1982 /* ADC Touch Screen Data Register */
1983 #define SADC_TSDAT_DATA0_BIT 0
1984 #define SADC_TSDAT_DATA0_MASK (0xfff << SADC_TSDAT_DATA0_BIT)
1985 #define SADC_TSDAT_TYPE0 (1 << 15)
1986 #define SADC_TSDAT_DATA1_BIT 16
1987 #define SADC_TSDAT_DATA1_MASK (0xfff << SADC_TSDAT_DATA1_BIT)
1988 #define SADC_TSDAT_TYPE1 (1 << 31)
1991 /*************************************************************************
1992 * SLCD (Smart LCD Controller)
1993 *************************************************************************/
1995 #define SLCD_CFG (SLCD_BASE + 0xA0) /* SLCD Configure Register */
1996 #define SLCD_CTRL (SLCD_BASE + 0xA4) /* SLCD Control Register */
1997 #define SLCD_STATE (SLCD_BASE + 0xA8) /* SLCD Status Register */
1998 #define SLCD_DATA (SLCD_BASE + 0xAC) /* SLCD Data Register */
1999 #define SLCD_FIFO (SLCD_BASE + 0xB0) /* SLCD FIFO Register */
2001 #define REG_SLCD_CFG REG32(SLCD_CFG)
2002 #define REG_SLCD_CTRL REG8(SLCD_CTRL)
2003 #define REG_SLCD_STATE REG8(SLCD_STATE)
2004 #define REG_SLCD_DATA REG32(SLCD_DATA)
2005 #define REG_SLCD_FIFO REG32(SLCD_FIFO)
2007 /* SLCD Configure Register */
2008 #define SLCD_CFG_BURST_BIT 14
2009 #define SLCD_CFG_BURST_MASK (0x3 << SLCD_CFG_BURST_BIT)
2010 #define SLCD_CFG_BURST_4_WORD (0 << SLCD_CFG_BURST_BIT)
2011 #define SLCD_CFG_BURST_8_WORD (1 << SLCD_CFG_BURST_BIT)
2012 #define SLCD_CFG_DWIDTH_BIT 10
2013 #define SLCD_CFG_DWIDTH_MASK (0x7 << SLCD_CFG_DWIDTH_BIT)
2014 #define SLCD_CFG_DWIDTH_18 (0 << SLCD_CFG_DWIDTH_BIT)
2015 #define SLCD_CFG_DWIDTH_16 (1 << SLCD_CFG_DWIDTH_BIT)
2016 #define SLCD_CFG_DWIDTH_8_x3 (2 << SLCD_CFG_DWIDTH_BIT)
2017 #define SLCD_CFG_DWIDTH_8_x2 (3 << SLCD_CFG_DWIDTH_BIT)
2018 #define SLCD_CFG_DWIDTH_9_x2 (4 << SLCD_CFG_DWIDTH_BIT)
2019 #define SLCD_CFG_CWIDTH_16BIT (0 << 8)
2020 #define SLCD_CFG_CWIDTH_8BIT (1 << 8)
2021 #define SLCD_CFG_CS_ACTIVE_LOW (0 << 4)
2022 #define SLCD_CFG_CS_ACTIVE_HIGH (1 << 4)
2023 #define SLCD_CFG_RS_CMD_LOW (0 << 3)
2024 #define SLCD_CFG_RS_CMD_HIGH (1 << 3)
2025 #define SLCD_CFG_CLK_ACTIVE_FALLING (0 << 1)
2026 #define SLCD_CFG_CLK_ACTIVE_RISING (1 << 1)
2027 #define SLCD_CFG_TYPE_PARALLEL (0 << 0)
2028 #define SLCD_CFG_TYPE_SERIAL (1 << 0)
2030 /* SLCD Control Register */
2031 #define SLCD_CTRL_DMA_EN (1 << 0)
2033 /* SLCD Status Register */
2034 #define SLCD_STATE_BUSY (1 << 0)
2036 /* SLCD Data Register */
2037 #define SLCD_DATA_RS_DATA (0 << 31)
2038 #define SLCD_DATA_RS_COMMAND (1 << 31)
2040 /* SLCD FIFO Register */
2041 #define SLCD_FIFO_RS_DATA (0 << 31)
2042 #define SLCD_FIFO_RS_COMMAND (1 << 31)
2045 /*************************************************************************
2046 * LCD (LCD Controller)
2047 *************************************************************************/
2048 #define LCD_CFG (LCD_BASE + 0x00) /* LCD Configure Register */
2049 #define LCD_VSYNC (LCD_BASE + 0x04) /* Vertical Synchronize Register */
2050 #define LCD_HSYNC (LCD_BASE + 0x08) /* Horizontal Synchronize Register */
2051 #define LCD_VAT (LCD_BASE + 0x0c) /* Virtual Area Setting Register */
2052 #define LCD_DAH (LCD_BASE + 0x10) /* Display Area Horizontal Start/End Point */
2053 #define LCD_DAV (LCD_BASE + 0x14) /* Display Area Vertical Start/End Point */
2054 #define LCD_PS (LCD_BASE + 0x18) /* PS Signal Setting */
2055 #define LCD_CLS (LCD_BASE + 0x1c) /* CLS Signal Setting */
2056 #define LCD_SPL (LCD_BASE + 0x20) /* SPL Signal Setting */
2057 #define LCD_REV (LCD_BASE + 0x24) /* REV Signal Setting */
2058 #define LCD_CTRL (LCD_BASE + 0x30) /* LCD Control Register */
2059 #define LCD_STATE (LCD_BASE + 0x34) /* LCD Status Register */
2060 #define LCD_IID (LCD_BASE + 0x38) /* Interrupt ID Register */
2061 #define LCD_DA0 (LCD_BASE + 0x40) /* Descriptor Address Register 0 */
2062 #define LCD_SA0 (LCD_BASE + 0x44) /* Source Address Register 0 */
2063 #define LCD_FID0 (LCD_BASE + 0x48) /* Frame ID Register 0 */
2064 #define LCD_CMD0 (LCD_BASE + 0x4c) /* DMA Command Register 0 */
2065 #define LCD_DA1 (LCD_BASE + 0x50) /* Descriptor Address Register 1 */
2066 #define LCD_SA1 (LCD_BASE + 0x54) /* Source Address Register 1 */
2067 #define LCD_FID1 (LCD_BASE + 0x58) /* Frame ID Register 1 */
2068 #define LCD_CMD1 (LCD_BASE + 0x5c) /* DMA Command Register 1 */
2070 #define REG_LCD_CFG REG32(LCD_CFG)
2071 #define REG_LCD_VSYNC REG32(LCD_VSYNC)
2072 #define REG_LCD_HSYNC REG32(LCD_HSYNC)
2073 #define REG_LCD_VAT REG32(LCD_VAT)
2074 #define REG_LCD_DAH REG32(LCD_DAH)
2075 #define REG_LCD_DAV REG32(LCD_DAV)
2076 #define REG_LCD_PS REG32(LCD_PS)
2077 #define REG_LCD_CLS REG32(LCD_CLS)
2078 #define REG_LCD_SPL REG32(LCD_SPL)
2079 #define REG_LCD_REV REG32(LCD_REV)
2080 #define REG_LCD_CTRL REG32(LCD_CTRL)
2081 #define REG_LCD_STATE REG32(LCD_STATE)
2082 #define REG_LCD_IID REG32(LCD_IID)
2083 #define REG_LCD_DA0 REG32(LCD_DA0)
2084 #define REG_LCD_SA0 REG32(LCD_SA0)
2085 #define REG_LCD_FID0 REG32(LCD_FID0)
2086 #define REG_LCD_CMD0 REG32(LCD_CMD0)
2087 #define REG_LCD_DA1 REG32(LCD_DA1)
2088 #define REG_LCD_SA1 REG32(LCD_SA1)
2089 #define REG_LCD_FID1 REG32(LCD_FID1)
2090 #define REG_LCD_CMD1 REG32(LCD_CMD1)
2092 /* LCD Configure Register */
2093 #define LCD_CFG_LCDPIN_BIT 31 /* LCD pins selection */
2094 #define LCD_CFG_LCDPIN_MASK (0x1 << LCD_CFG_LCDPIN_BIT)
2095 #define LCD_CFG_LCDPIN_LCD (0x0 << LCD_CFG_LCDPIN_BIT)
2096 #define LCD_CFG_LCDPIN_SLCD (0x1 << LCD_CFG_LCDPIN_BIT)
2097 #define LCD_CFG_PSM (1 << 23) /* PS signal mode */
2098 #define LCD_CFG_CLSM (1 << 22) /* CLS signal mode */
2099 #define LCD_CFG_SPLM (1 << 21) /* SPL signal mode */
2100 #define LCD_CFG_REVM (1 << 20) /* REV signal mode */
2101 #define LCD_CFG_HSYNM (1 << 19) /* HSYNC signal mode */
2102 #define LCD_CFG_PCLKM (1 << 18) /* PCLK signal mode */
2103 #define LCD_CFG_INVDAT (1 << 17) /* Inverse output data */
2104 #define LCD_CFG_SYNDIR_IN (1 << 16) /* VSYNC&HSYNC direction */
2105 #define LCD_CFG_PSP (1 << 15) /* PS pin reset state */
2106 #define LCD_CFG_CLSP (1 << 14) /* CLS pin reset state */
2107 #define LCD_CFG_SPLP (1 << 13) /* SPL pin reset state */
2108 #define LCD_CFG_REVP (1 << 12) /* REV pin reset state */
2109 #define LCD_CFG_HSP (1 << 11) /* HSYNC pority:0-active high,1-active low */
2110 #define LCD_CFG_PCP (1 << 10) /* PCLK pority:0-rising,1-falling */
2111 #define LCD_CFG_DEP (1 << 9) /* DE pority:0-active high,1-active low */
2112 #define LCD_CFG_VSP (1 << 8) /* VSYNC pority:0-rising,1-falling */
2113 #define LCD_CFG_PDW_BIT 4 /* STN pins utilization */
2114 #define LCD_CFG_PDW_MASK (0x3 << LCD_DEV_PDW_BIT)
2115 #define LCD_CFG_PDW_1 (0 << LCD_CFG_PDW_BIT) /* LCD_D[0] */
2116 #define LCD_CFG_PDW_2 (1 << LCD_CFG_PDW_BIT) /* LCD_D[0:1] */
2117 #define LCD_CFG_PDW_4 (2 << LCD_CFG_PDW_BIT) /* LCD_D[0:3]/LCD_D[8:11] */
2118 #define LCD_CFG_PDW_8 (3 << LCD_CFG_PDW_BIT) /* LCD_D[0:7]/LCD_D[8:15] */
2119 #define LCD_CFG_MODE_BIT 0 /* Display Device Mode Select */
2120 #define LCD_CFG_MODE_MASK (0x0f << LCD_CFG_MODE_BIT)
2121 #define LCD_CFG_MODE_GENERIC_TFT (0 << LCD_CFG_MODE_BIT) /* 16,18 bit TFT */
2122 #define LCD_CFG_MODE_SPECIAL_TFT_1 (1 << LCD_CFG_MODE_BIT)
2123 #define LCD_CFG_MODE_SPECIAL_TFT_2 (2 << LCD_CFG_MODE_BIT)
2124 #define LCD_CFG_MODE_SPECIAL_TFT_3 (3 << LCD_CFG_MODE_BIT)
2125 #define LCD_CFG_MODE_NONINTER_CCIR656 (4 << LCD_CFG_MODE_BIT)
2126 #define LCD_CFG_MODE_INTER_CCIR656 (5 << LCD_CFG_MODE_BIT)
2127 #define LCD_CFG_MODE_SINGLE_CSTN (8 << LCD_CFG_MODE_BIT)
2128 #define LCD_CFG_MODE_SINGLE_MSTN (9 << LCD_CFG_MODE_BIT)
2129 #define LCD_CFG_MODE_DUAL_CSTN (10 << LCD_CFG_MODE_BIT)
2130 #define LCD_CFG_MODE_DUAL_MSTN (11 << LCD_CFG_MODE_BIT)
2131 #define LCD_CFG_MODE_SERIAL_TFT (12 << LCD_CFG_MODE_BIT)
2132 #define LCD_CFG_MODE_GENERIC_18BIT_TFT (13 << LCD_CFG_MODE_BIT)
2133 /* JZ47XX defines */
2134 #define LCD_CFG_MODE_SHARP_HR (1 << LCD_CFG_MODE_BIT)
2135 #define LCD_CFG_MODE_CASIO_TFT (2 << LCD_CFG_MODE_BIT)
2136 #define LCD_CFG_MODE_SAMSUNG_ALPHA (3 << LCD_CFG_MODE_BIT)
2140 /* Vertical Synchronize Register */
2141 #define LCD_VSYNC_VPS_BIT 16 /* VSYNC pulse start in line clock, fixed to 0 */
2142 #define LCD_VSYNC_VPS_MASK (0xffff << LCD_VSYNC_VPS_BIT)
2143 #define LCD_VSYNC_VPE_BIT 0 /* VSYNC pulse end in line clock */
2144 #define LCD_VSYNC_VPE_MASK (0xffff << LCD_VSYNC_VPS_BIT)
2146 /* Horizontal Synchronize Register */
2147 #define LCD_HSYNC_HPS_BIT 16 /* HSYNC pulse start position in dot clock */
2148 #define LCD_HSYNC_HPS_MASK (0xffff << LCD_HSYNC_HPS_BIT)
2149 #define LCD_HSYNC_HPE_BIT 0 /* HSYNC pulse end position in dot clock */
2150 #define LCD_HSYNC_HPE_MASK (0xffff << LCD_HSYNC_HPE_BIT)
2152 /* Virtual Area Setting Register */
2153 #define LCD_VAT_HT_BIT 16 /* Horizontal Total size in dot clock */
2154 #define LCD_VAT_HT_MASK (0xffff << LCD_VAT_HT_BIT)
2155 #define LCD_VAT_VT_BIT 0 /* Vertical Total size in dot clock */
2156 #define LCD_VAT_VT_MASK (0xffff << LCD_VAT_VT_BIT)
2158 /* Display Area Horizontal Start/End Point Register */
2159 #define LCD_DAH_HDS_BIT 16 /* Horizontal display area start in dot clock */
2160 #define LCD_DAH_HDS_MASK (0xffff << LCD_DAH_HDS_BIT)
2161 #define LCD_DAH_HDE_BIT 0 /* Horizontal display area end in dot clock */
2162 #define LCD_DAH_HDE_MASK (0xffff << LCD_DAH_HDE_BIT)
2164 /* Display Area Vertical Start/End Point Register */
2165 #define LCD_DAV_VDS_BIT 16 /* Vertical display area start in line clock */
2166 #define LCD_DAV_VDS_MASK (0xffff << LCD_DAV_VDS_BIT)
2167 #define LCD_DAV_VDE_BIT 0 /* Vertical display area end in line clock */
2168 #define LCD_DAV_VDE_MASK (0xffff << LCD_DAV_VDE_BIT)
2170 /* PS Signal Setting */
2171 #define LCD_PS_PSS_BIT 16 /* PS signal start position in dot clock */
2172 #define LCD_PS_PSS_MASK (0xffff << LCD_PS_PSS_BIT)
2173 #define LCD_PS_PSE_BIT 0 /* PS signal end position in dot clock */
2174 #define LCD_PS_PSE_MASK (0xffff << LCD_PS_PSE_BIT)
2176 /* CLS Signal Setting */
2177 #define LCD_CLS_CLSS_BIT 16 /* CLS signal start position in dot clock */
2178 #define LCD_CLS_CLSS_MASK (0xffff << LCD_CLS_CLSS_BIT)
2179 #define LCD_CLS_CLSE_BIT 0 /* CLS signal end position in dot clock */
2180 #define LCD_CLS_CLSE_MASK (0xffff << LCD_CLS_CLSE_BIT)
2182 /* SPL Signal Setting */
2183 #define LCD_SPL_SPLS_BIT 16 /* SPL signal start position in dot clock */
2184 #define LCD_SPL_SPLS_MASK (0xffff << LCD_SPL_SPLS_BIT)
2185 #define LCD_SPL_SPLE_BIT 0 /* SPL signal end position in dot clock */
2186 #define LCD_SPL_SPLE_MASK (0xffff << LCD_SPL_SPLE_BIT)
2188 /* REV Signal Setting */
2189 #define LCD_REV_REVS_BIT 16 /* REV signal start position in dot clock */
2190 #define LCD_REV_REVS_MASK (0xffff << LCD_REV_REVS_BIT)
2192 /* LCD Control Register */
2193 #define LCD_CTRL_BST_BIT 28 /* Burst Length Selection */
2194 #define LCD_CTRL_BST_MASK (0x03 << LCD_CTRL_BST_BIT)
2195 #define LCD_CTRL_BST_4 (0 << LCD_CTRL_BST_BIT) /* 4-word */
2196 #define LCD_CTRL_BST_8 (1 << LCD_CTRL_BST_BIT) /* 8-word */
2197 #define LCD_CTRL_BST_16 (2 << LCD_CTRL_BST_BIT) /* 16-word */
2198 #define LCD_CTRL_RGB565 (0 << 27) /* RGB565 mode */
2199 #define LCD_CTRL_RGB555 (1 << 27) /* RGB555 mode */
2200 #define LCD_CTRL_OFUP (1 << 26) /* Output FIFO underrun protection enable */
2201 #define LCD_CTRL_FRC_BIT 24 /* STN FRC Algorithm Selection */
2202 #define LCD_CTRL_FRC_MASK (0x03 << LCD_CTRL_FRC_BIT)
2203 #define LCD_CTRL_FRC_16 (0 << LCD_CTRL_FRC_BIT) /* 16 grayscale */
2204 #define LCD_CTRL_FRC_4 (1 << LCD_CTRL_FRC_BIT) /* 4 grayscale */
2205 #define LCD_CTRL_FRC_2 (2 << LCD_CTRL_FRC_BIT) /* 2 grayscale */
2206 #define LCD_CTRL_PDD_BIT 16 /* Load Palette Delay Counter */
2207 #define LCD_CTRL_PDD_MASK (0xff << LCD_CTRL_PDD_BIT)
2208 #define LCD_CTRL_EOFM (1 << 13) /* EOF interrupt mask */
2209 #define LCD_CTRL_SOFM (1 << 12) /* SOF interrupt mask */
2210 #define LCD_CTRL_OFUM (1 << 11) /* Output FIFO underrun interrupt mask */
2211 #define LCD_CTRL_IFUM0 (1 << 10) /* Input FIFO 0 underrun interrupt mask */
2212 #define LCD_CTRL_IFUM1 (1 << 9) /* Input FIFO 1 underrun interrupt mask */
2213 #define LCD_CTRL_LDDM (1 << 8) /* LCD disable done interrupt mask */
2214 #define LCD_CTRL_QDM (1 << 7) /* LCD quick disable done interrupt mask */
2215 #define LCD_CTRL_BEDN (1 << 6) /* Endian selection */
2216 #define LCD_CTRL_PEDN (1 << 5) /* Endian in byte:0-msb first, 1-lsb first */
2217 #define LCD_CTRL_DIS (1 << 4) /* Disable indicate bit */
2218 #define LCD_CTRL_ENA (1 << 3) /* LCD enable bit */
2219 #define LCD_CTRL_BPP_BIT 0 /* Bits Per Pixel */
2220 #define LCD_CTRL_BPP_MASK (0x07 << LCD_CTRL_BPP_BIT)
2221 #define LCD_CTRL_BPP_1 (0 << LCD_CTRL_BPP_BIT) /* 1 bpp */
2222 #define LCD_CTRL_BPP_2 (1 << LCD_CTRL_BPP_BIT) /* 2 bpp */
2223 #define LCD_CTRL_BPP_4 (2 << LCD_CTRL_BPP_BIT) /* 4 bpp */
2224 #define LCD_CTRL_BPP_8 (3 << LCD_CTRL_BPP_BIT) /* 8 bpp */
2225 #define LCD_CTRL_BPP_16 (4 << LCD_CTRL_BPP_BIT) /* 15/16 bpp */
2226 #define LCD_CTRL_BPP_18_24 (5 << LCD_CTRL_BPP_BIT) /* 18/24/32 bpp */
2228 /* LCD Status Register */
2229 #define LCD_STATE_QD (1 << 7) /* Quick Disable Done */
2230 #define LCD_STATE_EOF (1 << 5) /* EOF Flag */
2231 #define LCD_STATE_SOF (1 << 4) /* SOF Flag */
2232 #define LCD_STATE_OFU (1 << 3) /* Output FIFO Underrun */
2233 #define LCD_STATE_IFU0 (1 << 2) /* Input FIFO 0 Underrun */
2234 #define LCD_STATE_IFU1 (1 << 1) /* Input FIFO 1 Underrun */
2235 #define LCD_STATE_LDD (1 << 0) /* LCD Disabled */
2237 /* DMA Command Register */
2238 #define LCD_CMD_SOFINT (1 << 31)
2239 #define LCD_CMD_EOFINT (1 << 30)
2240 #define LCD_CMD_PAL (1 << 28)
2241 #define LCD_CMD_LEN_BIT 0
2242 #define LCD_CMD_LEN_MASK (0xffffff << LCD_CMD_LEN_BIT)
2245 /*************************************************************************
2246 * USB Device
2247 *************************************************************************/
2248 #define USB_BASE UDC_BASE
2250 #define USB_REG_FADDR (USB_BASE + 0x00) /* Function Address 8-bit */
2251 #define USB_REG_POWER (USB_BASE + 0x01) /* Power Managemetn 8-bit */
2252 #define USB_REG_INTRIN (USB_BASE + 0x02) /* Interrupt IN 16-bit */
2253 #define USB_REG_INTROUT (USB_BASE + 0x04) /* Interrupt OUT 16-bit */
2254 #define USB_REG_INTRINE (USB_BASE + 0x06) /* Intr IN enable 16-bit */
2255 #define USB_REG_INTROUTE (USB_BASE + 0x08) /* Intr OUT enable 16-bit */
2256 #define USB_REG_INTRUSB (USB_BASE + 0x0a) /* Interrupt USB 8-bit */
2257 #define USB_REG_INTRUSBE (USB_BASE + 0x0b) /* Interrupt USB Enable 8-bit */
2258 #define USB_REG_FRAME (USB_BASE + 0x0c) /* Frame number 16-bit */
2259 #define USB_REG_INDEX (USB_BASE + 0x0e) /* Index register 8-bit */
2260 #define USB_REG_TESTMODE (USB_BASE + 0x0f) /* USB test mode 8-bit */
2262 #define USB_REG_CSR0 (USB_BASE + 0x12) /* EP0 CSR 8-bit */
2263 #define USB_REG_INMAXP (USB_BASE + 0x10) /* EP1-2 IN Max Pkt Size 16-bit */
2264 #define USB_REG_INCSR (USB_BASE + 0x12) /* EP1-2 IN CSR LSB 8/16bit */
2265 #define USB_REG_INCSRH (USB_BASE + 0x13) /* EP1-2 IN CSR MSB 8-bit */
2266 #define USB_REG_OUTMAXP (USB_BASE + 0x14) /* EP1 OUT Max Pkt Size 16-bit */
2267 #define USB_REG_OUTCSR (USB_BASE + 0x16) /* EP1 OUT CSR LSB 8/16bit */
2268 #define USB_REG_OUTCSRH (USB_BASE + 0x17) /* EP1 OUT CSR MSB 8-bit */
2269 #define USB_REG_OUTCOUNT (USB_BASE + 0x18) /* bytes in EP0/1 OUT FIFO 16-bit */
2271 #define USB_FIFO_EP0 (USB_BASE + 0x20)
2272 #define USB_FIFO_EP1 (USB_BASE + 0x24)
2273 #define USB_FIFO_EP2 (USB_BASE + 0x28)
2275 #define USB_REG_EPINFO (USB_BASE + 0x78) /* Endpoint information */
2276 #define USB_REG_RAMINFO (USB_BASE + 0x79) /* RAM information */
2278 #define USB_REG_INTR (USB_BASE + 0x200) /* DMA pending interrupts */
2279 #define USB_REG_CNTL1 (USB_BASE + 0x204) /* DMA channel 1 control */
2280 #define USB_REG_ADDR1 (USB_BASE + 0x208) /* DMA channel 1 AHB memory addr */
2281 #define USB_REG_COUNT1 (USB_BASE + 0x20c) /* DMA channel 1 byte count */
2282 #define USB_REG_CNTL2 (USB_BASE + 0x214) /* DMA channel 2 control */
2283 #define USB_REG_ADDR2 (USB_BASE + 0x218) /* DMA channel 2 AHB memory addr */
2284 #define USB_REG_COUNT2 (USB_BASE + 0x21c) /* DMA channel 2 byte count */
2287 /* Power register bit masks */
2288 #define USB_POWER_SUSPENDM 0x01
2289 #define USB_POWER_RESUME 0x04
2290 #define USB_POWER_HSMODE 0x10
2291 #define USB_POWER_HSENAB 0x20
2292 #define USB_POWER_SOFTCONN 0x40
2294 /* Interrupt register bit masks */
2295 #define USB_INTR_SUSPEND 0x01
2296 #define USB_INTR_RESUME 0x02
2297 #define USB_INTR_RESET 0x04
2299 #define USB_INTR_EP0 0x0001
2300 #define USB_INTR_INEP1 0x0002
2301 #define USB_INTR_INEP2 0x0004
2302 #define USB_INTR_OUTEP1 0x0002
2304 /* CSR0 bit masks */
2305 #define USB_CSR0_OUTPKTRDY 0x01
2306 #define USB_CSR0_INPKTRDY 0x02
2307 #define USB_CSR0_SENTSTALL 0x04
2308 #define USB_CSR0_DATAEND 0x08
2309 #define USB_CSR0_SETUPEND 0x10
2310 #define USB_CSR0_SENDSTALL 0x20
2311 #define USB_CSR0_SVDOUTPKTRDY 0x40
2312 #define USB_CSR0_SVDSETUPEND 0x80
2314 /* Endpoint CSR register bits */
2315 #define USB_INCSRH_AUTOSET 0x80
2316 #define USB_INCSRH_ISO 0x40
2317 #define USB_INCSRH_MODE 0x20
2318 #define USB_INCSRH_DMAREQENAB 0x10
2319 #define USB_INCSRH_DMAREQMODE 0x04
2320 #define USB_INCSR_CDT 0x40
2321 #define USB_INCSR_SENTSTALL 0x20
2322 #define USB_INCSR_SENDSTALL 0x10
2323 #define USB_INCSR_FF 0x08
2324 #define USB_INCSR_UNDERRUN 0x04
2325 #define USB_INCSR_FFNOTEMPT 0x02
2326 #define USB_INCSR_INPKTRDY 0x01
2327 #define USB_OUTCSRH_AUTOCLR 0x80
2328 #define USB_OUTCSRH_ISO 0x40
2329 #define USB_OUTCSRH_DMAREQENAB 0x20
2330 #define USB_OUTCSRH_DNYT 0x10
2331 #define USB_OUTCSRH_DMAREQMODE 0x08
2332 #define USB_OUTCSR_CDT 0x80
2333 #define USB_OUTCSR_SENTSTALL 0x40
2334 #define USB_OUTCSR_SENDSTALL 0x20
2335 #define USB_OUTCSR_FF 0x10
2336 #define USB_OUTCSR_DATAERR 0x08
2337 #define USB_OUTCSR_OVERRUN 0x04
2338 #define USB_OUTCSR_FFFULL 0x02
2339 #define USB_OUTCSR_OUTPKTRDY 0x01
2341 /* Testmode register bits */
2342 #define USB_TEST_SE0NAK 0x01
2343 #define USB_TEST_J 0x02
2344 #define USB_TEST_K 0x04
2345 #define USB_TEST_PACKET 0x08
2347 /* DMA control bits */
2348 #define USB_CNTL_ENA 0x01
2349 #define USB_CNTL_DIR_IN 0x02
2350 #define USB_CNTL_MODE_1 0x04
2351 #define USB_CNTL_INTR_EN 0x08
2352 #define USB_CNTL_EP(n) ((n) << 4)
2353 #define USB_CNTL_BURST_0 (0 << 9)
2354 #define USB_CNTL_BURST_4 (1 << 9)
2355 #define USB_CNTL_BURST_8 (2 << 9)
2356 #define USB_CNTL_BURST_16 (3 << 9)
2358 #endif /* __JZ4740_H__ */