firmware/target/arm/as3525/sd-as3525.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2006 Daniel Ankers
  11  * Copyright © 2008-2009 Rafaël Carré
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License
  15  * as published by the Free Software Foundation; either version 2
  16  * of the License, or (at your option) any later version.
  17  *
  18  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  19  * KIND, either express or implied.
  20  *
  21  ****************************************************************************/
  22
  23 /* Driver for the ARM PL180 SD/MMC controller inside AS3525 SoC */
  24
  25 /* TODO: Find the real capacity of >2GB models (will be useful for USB) */
  26
  27 #include "config.h" /* for HAVE_MULTIDRIVE & AMS_OF_SIZE */
  28 #include "fat.h"
  29 #include "thread.h"
  30 #include "led.h"
  31 #include "hotswap.h"
  32 #include "system.h"
  33 #include "cpu.h"
  34 #include <stdio.h>
  35 #include <stdlib.h>
  36 #include <string.h>
  37 #include "as3525.h"
  38 #include "pl180.h"  /* SD controller */
  39 #include "pl081.h"  /* DMA controller */
  40 #include "dma-target.h" /* DMA request lines */
  41 #include "clock-target.h"
  42 #include "panic.h"
  43 #ifdef HAVE_BUTTON_LIGHT
  44 #include "backlight-target.h"
  45 #endif
  46 #include "stdbool.h"
  47 #include "ata_idle_notify.h"
  48 #include "sd.h"
  49 #include "usb.h"
  50
  51 #ifdef HAVE_HOTSWAP
  52 #include "disk.h"
  53 #endif
  54
  55 /* command flags */
  56 #define MCI_NO_FLAGS    (0<<0)
  57 #define MCI_RESP        (1<<0)
  58 #define MCI_LONG_RESP   (1<<1)
  59 #define MCI_ARG         (1<<2)
  60
  61 /* ARM PL180 registers */
  62 #define MCI_POWER(i)       (*(volatile unsigned char *) (pl180_base[i]+0x00))
  63 #define MCI_CLOCK(i)       (*(volatile unsigned long *) (pl180_base[i]+0x04))
  64 #define MCI_ARGUMENT(i)    (*(volatile unsigned long *) (pl180_base[i]+0x08))
  65 #define MCI_COMMAND(i)     (*(volatile unsigned long *) (pl180_base[i]+0x0C))
  66 #define MCI_RESPCMD(i)     (*(volatile unsigned long *) (pl180_base[i]+0x10))
  67 #define MCI_RESP0(i)       (*(volatile unsigned long *) (pl180_base[i]+0x14))
  68 #define MCI_RESP1(i)       (*(volatile unsigned long *) (pl180_base[i]+0x18))
  69 #define MCI_RESP2(i)       (*(volatile unsigned long *) (pl180_base[i]+0x1C))
  70 #define MCI_RESP3(i)       (*(volatile unsigned long *) (pl180_base[i]+0x20))
  71 #define MCI_DATA_TIMER(i)  (*(volatile unsigned long *) (pl180_base[i]+0x24))
  72 #define MCI_DATA_LENGTH(i) (*(volatile unsigned short*) (pl180_base[i]+0x28))
  73 #define MCI_DATA_CTRL(i)   (*(volatile unsigned char *) (pl180_base[i]+0x2C))
  74 #define MCI_DATA_CNT(i)    (*(volatile unsigned short*) (pl180_base[i]+0x30))
  75 #define MCI_STATUS(i)      (*(volatile unsigned long *) (pl180_base[i]+0x34))
  76 #define MCI_CLEAR(i)       (*(volatile unsigned long *) (pl180_base[i]+0x38))
  77 #define MCI_MASK0(i)       (*(volatile unsigned long *) (pl180_base[i]+0x3C))
  78 #define MCI_MASK1(i)       (*(volatile unsigned long *) (pl180_base[i]+0x40))
  79 #define MCI_SELECT(i)      (*(volatile unsigned long *) (pl180_base[i]+0x44))
  80 #define MCI_FIFO_CNT(i)    (*(volatile unsigned long *) (pl180_base[i]+0x48))
  81
  82 #define MCI_DATA_ERROR    \
  83     ( MCI_DATA_CRC_FAIL   \
  84     | MCI_DATA_TIMEOUT    \
  85     | MCI_TX_UNDERRUN     \
  86     | MCI_RX_OVERRUN      \
  87     | MCI_START_BIT_ERR)
  88
  89 #define MCI_RESPONSE_ERROR    \
  90     ( MCI_CMD_TIMEOUT         \
  91     | MCI_CMD_CRC_FAIL)
  92
  93 #define MCI_FIFO(i)        ((unsigned long *) (pl180_base[i]+0x80))
  94 /* volumes */
  95 #define     INTERNAL_AS3525 0   /* embedded SD card */
  96 #define     SD_SLOT_AS3525   1   /* SD slot if present */
  97
  98 static const int pl180_base[NUM_DRIVES] = {
  99             NAND_FLASH_BASE
 100 #ifdef HAVE_MULTIDRIVE
 101             , SD_MCI_BASE
 102 #endif
 103 };
 104
 105 static int sd_wait_for_state(const int drive, unsigned int state);
 106 static int sd_select_bank(signed char bank);
 107 static int sd_init_card(const int drive);
 108 static void init_pl180_controller(const int drive);
 109
 110 #define BLOCKS_PER_BANK 0x7a7800
 111
 112 static tCardInfo card_info[NUM_DRIVES];
 113
 114 /* maximum timeouts recommanded in the SD Specification v2.00 */
 115 #define SD_MAX_READ_TIMEOUT     ((AS3525_PCLK_FREQ) / 1000 * 100) /* 100 ms */
 116 #define SD_MAX_WRITE_TIMEOUT    ((AS3525_PCLK_FREQ) / 1000 * 250) /* 250 ms */
 117
 118 /* for compatibility */
 119 static long last_disk_activity = -1;
 120
 121 #define MIN_YIELD_PERIOD 5  /* ticks */
 122 static long next_yield = 0;
 123
 124 static long sd_stack [(DEFAULT_STACK_SIZE*2 + 0x200)/sizeof(long)];
 125 static const char         sd_thread_name[] = "ata/sd";
 126 static struct mutex       sd_mtx;
 127 static struct event_queue sd_queue;
 128 #ifndef BOOTLOADER
 129 bool sd_enabled = false;
 130 #endif
 131
 132 #if defined(HAVE_MULTIDRIVE)
 133 static bool hs_card = false;
 134 #define EXT_SD_BITS (1<<2)
 135 #endif
 136
 137 static struct wakeup transfer_completion_signal;
 138 static volatile unsigned int transfer_error[NUM_VOLUMES];
 139 #define PL180_MAX_TRANSFER_ERRORS 10
 140
 141 #define UNALIGNED_NUM_SECTORS 10
 142 static unsigned char aligned_buffer[UNALIGNED_NUM_SECTORS* SD_BLOCK_SIZE] __attribute__((aligned(32)));   /* align on cache line size */
 143 static unsigned char *uncached_buffer = UNCACHED_ADDR(&aligned_buffer[0]);
 144
 145
 146 static inline void mci_delay(void) { udelay(1000) ; }
 147
 148
 149 static inline bool card_detect_target(void)
 150 {
 151 #if defined(HAVE_MULTIDRIVE)
 152     return !(GPIOA_PIN(2));
 153 #else
 154     return false;
 155 #endif
 156 }
 157
 158
 159 #ifdef HAVE_HOTSWAP
 160 static int sd1_oneshot_callback(struct timeout *tmo)
 161 {
 162     (void)tmo;
 163
 164     /* This is called only if the state was stable for 300ms - check state
 165      * and post appropriate event. */
 166     if (card_detect_target())
 167     {
 168         queue_broadcast(SYS_HOTSWAP_INSERTED, 0);
 169     }
 170     else
 171         queue_broadcast(SYS_HOTSWAP_EXTRACTED, 0);
 172
 173     return 0;
 174 }
 175
 176 void sd_gpioa_isr(void)
 177 {
 178     static struct timeout sd1_oneshot;
 179     if (GPIOA_MIS & EXT_SD_BITS)
 180         timeout_register(&sd1_oneshot, sd1_oneshot_callback, (3*HZ/10), 0);
 181     /* acknowledge interrupt */
 182     GPIOA_IC = EXT_SD_BITS;
 183 }
 184 #endif  /* HAVE_HOTSWAP */
 185
 186 void INT_NAND(void)
 187 {
 188     const int status = MCI_STATUS(INTERNAL_AS3525);
 189
 190     transfer_error[INTERNAL_AS3525] = status & MCI_DATA_ERROR;
 191
 192     wakeup_signal(&transfer_completion_signal);
 193     MCI_CLEAR(INTERNAL_AS3525) = status;
 194 }
 195
 196 #ifdef HAVE_MULTIDRIVE
 197 void INT_MCI0(void)
 198 {
 199     const int status = MCI_STATUS(SD_SLOT_AS3525);
 200
 201     transfer_error[SD_SLOT_AS3525] = status & MCI_DATA_ERROR;
 202
 203     wakeup_signal(&transfer_completion_signal);
 204     MCI_CLEAR(SD_SLOT_AS3525) = status;
 205 }
 206 #endif
 207
 208 static bool send_cmd(const int drive, const int cmd, const int arg,
 209                      const int flags, long *response)
 210 {
 211     int status;
 212
 213     /* Clear old status flags */
 214     MCI_CLEAR(drive) = 0x7ff;
 215
 216     /* Load command argument or clear if none */
 217     MCI_ARGUMENT(drive) = (flags & MCI_ARG) ? arg : 0;
 218
 219     /* Construct MCI_COMMAND & enable CPSM */
 220     MCI_COMMAND(drive) =
 221        /*b0:5*/  cmd
 222        /* b6 */| ((flags & (MCI_RESP|MCI_LONG_RESP)) ? MCI_COMMAND_RESPONSE : 0)
 223        /* b7 */| ((flags & MCI_LONG_RESP) ? MCI_COMMAND_LONG_RESPONSE : 0)
 224        /* b8   | MCI_COMMAND_INTERRUPT */
 225        /* b9   | MCI_COMMAND_PENDING */  /*Only used with stream data transfer*/
 226        /* b10*/| MCI_COMMAND_ENABLE;     /* Enables CPSM */
 227
 228     /* Wait while cmd completes then disable CPSM */
 229     while(MCI_STATUS(drive) & MCI_CMD_ACTIVE);
 230     MCI_COMMAND(drive) = 0;
 231
 232     status = MCI_STATUS(drive);
 233
 234     /*  Handle command responses */
 235     if(flags & MCI_RESP)                   /*  CMD expects response  */
 236     {
 237         response[0] = MCI_RESP0(drive);    /*  Always prepare short response  */
 238
 239         if(status & MCI_RESPONSE_ERROR)    /* timeout or crc failure */
 240             return false;
 241
 242         if(status & MCI_CMD_RESP_END)      /* Response passed CRC check */
 243         {
 244             if(flags & MCI_LONG_RESP)
 245             {   /* response[0] has already been read */
 246                 response[1] = MCI_RESP1(drive);
 247                 response[2] = MCI_RESP2(drive);
 248                 response[3] = MCI_RESP3(drive);
 249             }
 250             return true;
 251         }
 252     }
 253     else if(status & MCI_CMD_SENT)          /* CMD sent, no response required */
 254         return true;
 255
 256     return false;
 257 }
 258
 259 #define MCI_FULLSPEED     (MCI_CLOCK_ENABLE | MCI_CLOCK_BYPASS)     /* MCLK   */
 260 #define MCI_HALFSPEED     (MCI_CLOCK_ENABLE)                        /* MCLK/2 */
 261 #define MCI_QUARTERSPEED  (MCI_CLOCK_ENABLE | 1)                    /* MCLK/4 */
 262 #define MCI_IDENTSPEED    (MCI_CLOCK_ENABLE | AS3525_SD_IDENT_DIV)  /* IDENT  */
 263
 264 static int sd_init_card(const int drive)
 265 {
 266     unsigned long response;
 267     long init_timeout;
 268     bool sd_v2 = false;
 269
 270     /* MCLCK on and set to 400kHz ident frequency  */
 271     MCI_CLOCK(drive) = MCI_IDENTSPEED;
 272
 273     /* 100 - 400kHz clock required for Identification Mode  */
 274     /*  Start of Card Identification Mode ************************************/
 275
 276     /* CMD0 Go Idle  */
 277     if(!send_cmd(drive, SD_GO_IDLE_STATE, 0, MCI_NO_FLAGS, NULL))
 278         return -1;
 279     mci_delay();
 280
 281     /* CMD8 Check for v2 sd card.  Must be sent before using ACMD41
 282       Non v2 cards will not respond to this command*/
 283     if(send_cmd(drive, SD_SEND_IF_COND, 0x1AA, MCI_RESP|MCI_ARG, &response))
 284         if((response & 0xFFF) == 0x1AA)
 285             sd_v2 = true;
 286
 287     /* timeout for initialization is 1sec, from SD Specification 2.00 */
 288     init_timeout = current_tick + HZ;
 289
 290     do {
 291         /* this timeout is the only valid error for this loop*/
 292         if(TIME_AFTER(current_tick, init_timeout))
 293             return -2;
 294
 295         /* app_cmd */
 296         send_cmd(drive, SD_APP_CMD, 0, MCI_RESP|MCI_ARG, &response);
 297
 298         /* ACMD41 For v2 cards set HCS bit[30] & send host voltage range to all */
 299         send_cmd(drive, SD_APP_OP_COND, (0x00FF8000 | (sd_v2 ? 1<<30 : 0)),
 300                         MCI_RESP|MCI_ARG, &card_info[drive].ocr);
 301
 302     } while(!(card_info[drive].ocr & (1<<31)));
 303
 304     /* CMD2 send CID */
 305     if(!send_cmd(drive, SD_ALL_SEND_CID, 0, MCI_RESP|MCI_LONG_RESP|MCI_ARG,
 306                             card_info[drive].cid))
 307         return -3;
 308
 309     /* CMD3 send RCA */
 310     if(!send_cmd(drive, SD_SEND_RELATIVE_ADDR, 0, MCI_RESP|MCI_ARG,
 311                 &card_info[drive].rca))
 312         return -4;
 313
 314     /*  End of Card Identification Mode   ************************************/
 315
 316 #ifdef HAVE_MULTIDRIVE        /*  The internal SDs are v1 */
 317
 318     /* Try to switch V2 cards to HS timings, non HS seem to ignore this */
 319     if(sd_v2)
 320     {
 321         /*  CMD7 w/rca: Select card to put it in TRAN state */
 322         if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_ARG, NULL))
 323             return -5;
 324         mci_delay();
 325
 326         if(sd_wait_for_state(drive, SD_TRAN))
 327             return -6;
 328         /* CMD6 */
 329         if(!send_cmd(drive, SD_SWITCH_FUNC, 0x80fffff1, MCI_ARG, NULL))
 330             return -7;
 331         mci_delay();
 332
 333         /*  go back to STBY state so we can read csd */
 334         /*  CMD7 w/rca=0:  Deselect card to put it in STBY state */
 335         if(!send_cmd(drive, SD_DESELECT_CARD, 0, MCI_ARG, NULL))
 336             return -8;
 337         mci_delay();
 338     }
 339 #endif /*  HAVE_MULTIDRIVE  */
 340
 341     /* CMD9 send CSD */
 342     if(!send_cmd(drive, SD_SEND_CSD, card_info[drive].rca,
 343                  MCI_RESP|MCI_LONG_RESP|MCI_ARG, card_info[drive].csd))
 344         return -9;
 345
 346     sd_parse_csd(&card_info[drive]);
 347
 348 #if defined(HAVE_MULTIDRIVE)
 349     hs_card = (card_info[drive].speed == 50000000);
 350 #endif
 351
 352     /* Boost MCICLK to operating speed */
 353     if(drive == INTERNAL_AS3525)
 354         MCI_CLOCK(drive) = MCI_HALFSPEED;  /* MCICLK = IDE_CLK/2 = 25 MHz  */
 355 #if defined(HAVE_MULTIDRIVE)
 356     else
 357         /* MCICLK = PCLK/2 = 31MHz(HS) or PCLK/4 = 15.5 Mhz (STD)*/
 358         MCI_CLOCK(drive) = (hs_card ? MCI_HALFSPEED : MCI_QUARTERSPEED);
 359 #endif
 360
 361     /*  CMD7 w/rca: Select card to put it in TRAN state */
 362     if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_ARG, NULL))
 363         return -10;
 364     mci_delay();
 365
 366     /*
 367      * enable bank switching
 368      * without issuing this command, we only have access to 1/4 of the blocks
 369      * of the first bank (0x1E9E00 blocks, which is the size reported in the
 370      * CSD register)
 371      */
 372     if(drive == INTERNAL_AS3525)
 373     {
 374         const int ret = sd_select_bank(-1);
 375         if(ret < 0)
 376             return ret -16;
 377     }
 378
 379     card_info[drive].initialized = 1;
 380
 381     return 0;
 382 }
 383
 384 static void sd_thread(void) __attribute__((noreturn));
 385 static void sd_thread(void)
 386 {
 387     struct queue_event ev;
 388     bool idle_notified = false;
 389
 390     while (1)
 391     {
 392         queue_wait_w_tmo(&sd_queue, &ev, HZ);
 393
 394         switch ( ev.id )
 395         {
 396 #ifdef HAVE_HOTSWAP
 397         case SYS_HOTSWAP_INSERTED:
 398         case SYS_HOTSWAP_EXTRACTED:
 399         {
 400             int microsd_init = 1;
 401             fat_lock();          /* lock-out FAT activity first -
 402                                     prevent deadlocking via disk_mount that
 403                                     would cause a reverse-order attempt with
 404                                     another thread */
 405             mutex_lock(&sd_mtx); /* lock-out card activity - direct calls
 406                                     into driver that bypass the fat cache */
 407
 408             /* We now have exclusive control of fat cache and ata */
 409
 410             disk_unmount(SD_SLOT_AS3525);     /* release "by force", ensure file
 411                                     descriptors aren't leaked and any busy
 412                                     ones are invalid if mounting */
 413
 414             /* Force card init for new card, re-init for re-inserted one or
 415              * clear if the last attempt to init failed with an error. */
 416             card_info[SD_SLOT_AS3525].initialized = 0;
 417
 418             if (ev.id == SYS_HOTSWAP_INSERTED)
 419             {
 420                 sd_enable(true);
 421                 init_pl180_controller(SD_SLOT_AS3525);
 422                 microsd_init = sd_init_card(SD_SLOT_AS3525);
 423                 if (microsd_init < 0) /* initialisation failed */
 424                     panicf("microSD init failed : %d", microsd_init);
 425
 426                 microsd_init = disk_mount(SD_SLOT_AS3525); /* 0 if fail */
 427             }
 428
 429             /*
 430              * Mount succeeded, or this was an EXTRACTED event,
 431              * in both cases notify the system about the changed filesystems
 432              */
 433             if (microsd_init)
 434                 queue_broadcast(SYS_FS_CHANGED, 0);
 435
 436             /* Access is now safe */
 437             mutex_unlock(&sd_mtx);
 438             fat_unlock();
 439             sd_enable(false);
 440         }
 441             break;
 442 #endif
 443         case SYS_TIMEOUT:
 444             if (TIME_BEFORE(current_tick, last_disk_activity+(3*HZ)))
 445             {
 446                 idle_notified = false;
 447             }
 448             else
 449             {
 450                 /* never let a timer wrap confuse us */
 451                 next_yield = current_tick;
 452
 453                 if (!idle_notified)
 454                 {
 455                     call_storage_idle_notifys(false);
 456                     idle_notified = true;
 457                 }
 458             }
 459             break;
 460
 461         case SYS_USB_CONNECTED:
 462             usb_acknowledge(SYS_USB_CONNECTED_ACK);
 463             /* Wait until the USB cable is extracted again */
 464             usb_wait_for_disconnect(&sd_queue);
 465
 466             break;
 467         case SYS_USB_DISCONNECTED:
 468             usb_acknowledge(SYS_USB_DISCONNECTED_ACK);
 469             break;
 470         }
 471     }
 472 }
 473
 474 static void init_pl180_controller(const int drive)
 475 {
 476     MCI_COMMAND(drive) = MCI_DATA_CTRL(drive) = 0;
 477     MCI_CLEAR(drive) = 0x7ff;
 478
 479     MCI_MASK0(drive) = MCI_DATA_ERROR | MCI_DATA_END;
 480     MCI_MASK1(drive) = 0;
 481 #ifdef HAVE_MULTIDRIVE
 482     VIC_INT_ENABLE =
 483         (drive == INTERNAL_AS3525) ? INTERRUPT_NAND : INTERRUPT_MCI0;
 484     /* clear previous irq */
 485     GPIOA_IC = EXT_SD_BITS;
 486     /* enable edge detecting */
 487     GPIOA_IS &= ~EXT_SD_BITS;
 488     /* detect both raising and falling edges */
 489     GPIOA_IBE |= EXT_SD_BITS;
 490
 491 #else
 492     VIC_INT_ENABLE = INTERRUPT_NAND;
 493 #endif
 494
 495     MCI_POWER(drive) = MCI_POWER_UP | (MCI_VDD_3_0);  /*  OF Setting  */
 496     mci_delay();
 497
 498     MCI_POWER(drive) |= MCI_POWER_ON;
 499     mci_delay();
 500
 501     MCI_SELECT(drive) = 0;
 502
 503     /* Pl180 clocks get turned on at start of card init */
 504 }
 505
 506 int sd_init(void)
 507 {
 508     int ret;
 509     CGU_IDE =   (1<<6)                  /*  enable non AHB interface*/
 510             |   (AS3525_IDE_DIV << 2)
 511             |    AS3525_CLK_PLLA;       /* clock source = PLLA */
 512
 513     CGU_PERI |= CGU_NAF_CLOCK_ENABLE;
 514 #ifdef HAVE_MULTIDRIVE
 515     CGU_PERI |= CGU_MCI_CLOCK_ENABLE;
 516     CCU_IO &= ~(1<<3);           /* bits 3:2 = 01, xpd is SD interface */
 517     CCU_IO |= (1<<2);
 518 #endif
 519
 520     wakeup_init(&transfer_completion_signal);
 521
 522     init_pl180_controller(INTERNAL_AS3525);
 523     ret = sd_init_card(INTERNAL_AS3525);
 524     if(ret < 0)
 525         return ret;
 526 #ifdef HAVE_MULTIDRIVE
 527     init_pl180_controller(SD_SLOT_AS3525);
 528 #endif
 529
 530     /* init mutex */
 531     mutex_init(&sd_mtx);
 532
 533     queue_init(&sd_queue, true);
 534     create_thread(sd_thread, sd_stack, sizeof(sd_stack), 0,
 535             sd_thread_name IF_PRIO(, PRIORITY_USER_INTERFACE) IF_COP(, CPU));
 536
 537 #ifndef BOOTLOADER
 538     sd_enabled = true;
 539     sd_enable(false);
 540 #endif
 541     return 0;
 542 }
 543
 544 #ifdef HAVE_HOTSWAP
 545 bool sd_removable(IF_MD_NONVOID(int drive))
 546 {
 547     return (drive==1);
 548 }
 549
 550 bool sd_present(IF_MD_NONVOID(int drive))
 551 {
 552     return (drive == 0) ? true : card_detect_target();
 553 }
 554 #endif /* HAVE_HOTSWAP */
 555
 556 static int sd_wait_for_state(const int drive, unsigned int state)
 557 {
 558     unsigned long response = 0;
 559     unsigned int timeout = current_tick + 100; /* 100 ticks timeout */
 560
 561     while (1)
 562     {
 563         if(!send_cmd(drive, SD_SEND_STATUS, card_info[drive].rca,
 564                     MCI_RESP|MCI_ARG, &response))
 565             return -1;
 566
 567         if (((response >> 9) & 0xf) == state)
 568             return 0;
 569
 570         if(TIME_AFTER(current_tick, timeout))
 571             return -2;
 572
 573         if (TIME_AFTER(current_tick, next_yield))
 574         {
 575             yield();
 576             next_yield = current_tick + MIN_YIELD_PERIOD;
 577         }
 578     }
 579 }
 580
 581 static int sd_select_bank(signed char bank)
 582 {
 583     int ret;
 584     unsigned loops = 0;
 585
 586     do {
 587         if(loops++ > PL180_MAX_TRANSFER_ERRORS)
 588             panicf("SD bank %d error : 0x%x", bank,
 589                     transfer_error[INTERNAL_AS3525]);
 590
 591         ret = sd_wait_for_state(INTERNAL_AS3525, SD_TRAN);
 592         if (ret < 0)
 593             return ret - 2;
 594
 595         if(!send_cmd(INTERNAL_AS3525, SD_SWITCH_FUNC, 0x80ffffef, MCI_ARG, NULL))
 596             return -1;
 597
 598         mci_delay();
 599
 600         if(!send_cmd(INTERNAL_AS3525, 35, 0, MCI_NO_FLAGS, NULL))
 601             return -2;
 602
 603         mci_delay();
 604
 605         memset(uncached_buffer, 0, 512);
 606         if(bank == -1)
 607         {   /* enable bank switching */
 608             uncached_buffer[0] = 16;
 609             uncached_buffer[1] = 1;
 610             uncached_buffer[2] = 10;
 611         }
 612         else
 613             uncached_buffer[0] = bank;
 614
 615         dma_retain();
 616         /* we don't use the uncached buffer here, because we need the
 617          * physical memory address for DMA transfers */
 618         dma_enable_channel(0, aligned_buffer, MCI_FIFO(INTERNAL_AS3525),
 619             DMA_PERI_SD, DMAC_FLOWCTRL_PERI_MEM_TO_PERI, true, false, 0, DMA_S8,
 620             NULL);
 621
 622         MCI_DATA_TIMER(INTERNAL_AS3525) = SD_MAX_WRITE_TIMEOUT;
 623         MCI_DATA_LENGTH(INTERNAL_AS3525) = 512;
 624         MCI_DATA_CTRL(INTERNAL_AS3525) =  (1<<0) /* enable */   |
 625                                 (0<<1) /* transfer direction */ |
 626                                 (1<<3) /* DMA */                |
 627                                 (9<<4) /* 2^9 = 512 */ ;
 628
 629         /* Wakeup signal from NAND/MCIO isr on MCI_DATA_ERROR | MCI_DATA_END */
 630         wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK);
 631
 632         /*  Wait for FIFO to empty, card may still be in PRG state  */
 633         while(MCI_STATUS(INTERNAL_AS3525) & MCI_TX_ACTIVE );
 634
 635         dma_release();
 636
 637     } while(transfer_error[INTERNAL_AS3525]);
 638
 639     card_info[INTERNAL_AS3525].current_bank = (bank == -1) ? 0 : bank;
 640
 641     return 0;
 642 }
 643
 644 static int sd_transfer_sectors(IF_MD2(int drive,) unsigned long start,
 645                                int count, void* buf, const bool write)
 646 {
 647 #ifndef HAVE_MULTIDRIVE
 648     const int drive = 0;
 649 #endif
 650     int ret = 0;
 651     unsigned loops = 0;
 652
 653     /* skip SanDisk OF */
 654     if (drive == INTERNAL_AS3525)
 655         start += AMS_OF_SIZE;
 656
 657     mutex_lock(&sd_mtx);
 658 #ifndef BOOTLOADER
 659     sd_enable(true);
 660     led(true);
 661 #endif
 662
 663     if (card_info[drive].initialized <= 0)
 664     {
 665         ret = sd_init_card(drive);
 666         if (!(card_info[drive].initialized))
 667             goto sd_transfer_error;
 668     }
 669
 670     last_disk_activity = current_tick;
 671
 672     dma_retain();
 673
 674     while(count)
 675     {
 676         /* 128 * 512 = 2^16, and doesn't fit in the 16 bits of DATA_LENGTH
 677          * register, so we have to transfer maximum 127 sectors at a time. */
 678         unsigned int transfer = (count >= 128) ? 127 : count; /* sectors */
 679         void *dma_buf;
 680         const int cmd =
 681             write ? SD_WRITE_MULTIPLE_BLOCK : SD_READ_MULTIPLE_BLOCK;
 682         unsigned long bank_start = start;
 683
 684         /* Only switch banks for internal storage */
 685         if(drive == INTERNAL_AS3525)
 686         {
 687             unsigned int bank = start / BLOCKS_PER_BANK; /* Current bank */
 688
 689             /* Switch bank if needed */
 690             if(card_info[INTERNAL_AS3525].current_bank != bank)
 691             {
 692                 ret = sd_select_bank(bank);
 693                 if (ret < 0)
 694                 {
 695                     ret -= 20;
 696                     goto sd_transfer_error;
 697                 }
 698             }
 699
 700             /* Adjust start block in current bank */
 701             bank_start -= bank * BLOCKS_PER_BANK;
 702
 703             /* Do not cross a bank boundary in a single transfer loop */
 704             if((transfer + bank_start) > BLOCKS_PER_BANK)
 705                 transfer = BLOCKS_PER_BANK - bank_start;
 706         }
 707
 708         /* Set bank_start to the correct unit (blocks or bytes) */
 709         if(!(card_info[drive].ocr & (1<<30)))   /* not SDHC */
 710             bank_start *= SD_BLOCK_SIZE;
 711
 712         dma_buf = aligned_buffer;
 713         if(transfer > UNALIGNED_NUM_SECTORS)
 714             transfer = UNALIGNED_NUM_SECTORS;
 715
 716         if(write)
 717             memcpy(uncached_buffer, buf, transfer * SD_BLOCK_SIZE);
 718
 719         ret = sd_wait_for_state(drive, SD_TRAN);
 720         if (ret < 0)
 721         {
 722             ret -= 2*20;
 723             goto sd_transfer_error;
 724         }
 725
 726         if(!send_cmd(drive, cmd, bank_start, MCI_ARG, NULL))
 727         {
 728             ret -= 3*20;
 729             goto sd_transfer_error;
 730         }
 731
 732         if(write)
 733         {
 734             dma_enable_channel(0, dma_buf, MCI_FIFO(drive),
 735                 (drive == INTERNAL_AS3525) ? DMA_PERI_SD : DMA_PERI_SD_SLOT,
 736                 DMAC_FLOWCTRL_PERI_MEM_TO_PERI, true, false, 0, DMA_S8, NULL);
 737
 738             /*Small delay for writes prevents data crc failures at lower freqs*/
 739 #ifdef HAVE_MULTIDRIVE
 740             if((drive == SD_SLOT_AS3525) && !hs_card)
 741             {
 742                 int write_delay = 125;
 743                 while(write_delay--);
 744             }
 745 #endif
 746         }
 747         else
 748             dma_enable_channel(0, MCI_FIFO(drive), dma_buf,
 749                 (drive == INTERNAL_AS3525) ? DMA_PERI_SD : DMA_PERI_SD_SLOT,
 750                 DMAC_FLOWCTRL_PERI_PERI_TO_MEM, false, true, 0, DMA_S8, NULL);
 751
 752         MCI_DATA_TIMER(drive) = write ?
 753                 SD_MAX_WRITE_TIMEOUT : SD_MAX_READ_TIMEOUT;
 754         MCI_DATA_LENGTH(drive) = transfer * SD_BLOCK_SIZE;
 755         MCI_DATA_CTRL(drive) =  (1<<0) /* enable */                     |
 756                                 (!write<<1) /* transfer direction */    |
 757                                 (1<<3) /* DMA */                        |
 758                                 (9<<4) /* 2^9 = 512 */ ;
 759
 760         /* Wakeup signal from NAND/MCIO isr on MCI_DATA_ERROR | MCI_DATA_END */
 761         wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK);
 762
 763         /*  Wait for FIFO to empty, card may still be in PRG state for writes */
 764         while(MCI_STATUS(drive) & MCI_TX_ACTIVE);
 765
 766         last_disk_activity = current_tick;
 767
 768         if(!send_cmd(drive, SD_STOP_TRANSMISSION, 0, MCI_NO_FLAGS, NULL))
 769         {
 770             ret = -4*20;
 771             goto sd_transfer_error;
 772         }
 773
 774         if(!transfer_error[drive])
 775         {
 776             if(!write)
 777                 memcpy(buf, uncached_buffer, transfer * SD_BLOCK_SIZE);
 778             buf += transfer * SD_BLOCK_SIZE;
 779             start += transfer;
 780             count -= transfer;
 781             loops = 0;  /* reset errors counter */
 782         }
 783         else if(loops++ > PL180_MAX_TRANSFER_ERRORS)
 784                 panicf("SD Xfer %s err:0x%x Disk%d", (write? "write": "read"),
 785                                                   transfer_error[drive], drive);
 786     }
 787
 788     ret = 0;    /* success */
 789
 790 sd_transfer_error:
 791
 792     dma_release();
 793
 794 #ifndef BOOTLOADER
 795     led(false);
 796     sd_enable(false);
 797 #endif
 798
 799     if (ret)    /* error */
 800         card_info[drive].initialized = 0;
 801
 802     mutex_unlock(&sd_mtx);
 803     return ret;
 804 }
 805
 806 int sd_read_sectors(IF_MD2(int drive,) unsigned long start, int count,
 807                      void* buf)
 808 {
 809     return sd_transfer_sectors(IF_MD2(drive,) start, count, buf, false);
 810 }
 811
 812 int sd_write_sectors(IF_MD2(int drive,) unsigned long start, int count,
 813                      const void* buf)
 814 {
 815
 816 #ifdef BOOTLOADER /* we don't need write support in bootloader */
 817 #ifdef HAVE_MULTIDRIVE
 818     (void) drive;
 819 #endif
 820     (void) start;
 821     (void) count;
 822     (void) buf;
 823     return -1;
 824 #else
 825     return sd_transfer_sectors(IF_MD2(drive,) start, count, (void*)buf, true);
 826 #endif
 827 }
 828
 829 #ifndef BOOTLOADER
 830 long sd_last_disk_activity(void)
 831 {
 832     return last_disk_activity;
 833 }
 834
 835 void sd_enable(bool on)
 836 {
 837 #if defined(HAVE_BUTTON_LIGHT) && defined(HAVE_MULTIDRIVE)
 838     extern int buttonlight_is_on;
 839 #endif
 840
 841 #if defined(HAVE_HOTSWAP) && defined (HAVE_ADJUSTABLE_CPU_VOLTAGE)
 842     static bool cpu_boosted = false;
 843 #endif
 844
 845     if (sd_enabled == on)
 846         return; /* nothing to do */
 847     if(on)
 848     {
 849         /*  Enable both NAF_CLOCK & IDE clk for internal SD */
 850         CGU_PERI |= CGU_NAF_CLOCK_ENABLE;
 851         CGU_IDE  |= (1<<6);     /* enable non AHB interface*/
 852 #ifdef HAVE_MULTIDRIVE
 853         /* Enable MCI clk for uSD */
 854         CGU_PERI |= CGU_MCI_CLOCK_ENABLE;
 855 #ifdef HAVE_BUTTON_LIGHT
 856         /* buttonlight AMSes need a bit of special handling for the buttonlight
 857          * here due to the dual mapping of GPIOD and XPD */
 858         CCU_IO |= (1<<2);              /* XPD is SD-MCI interface (b3:2 = 01) */
 859         if (buttonlight_is_on)
 860             GPIOD_DIR &= ~(1<<7);
 861         else
 862             _buttonlight_off();
 863 #endif /* HAVE_BUTTON_LIGHT */
 864 #endif /* HAVE_MULTIDRIVE */
 865         sd_enabled = true;
 866
 867 #if defined(HAVE_HOTSWAP) && defined (HAVE_ADJUSTABLE_CPU_VOLTAGE)
 868         if(card_detect_target())  /* If SD card present Boost cpu for voltage */
 869         {
 870             cpu_boosted = true;
 871             cpu_boost(true);
 872         }
 873 #endif  /* defined(HAVE_HOTSWAP) && defined (HAVE_ADJUSTABLE_CPU_VOLTAGE) */
 874     }
 875     else
 876     {
 877 #if defined(HAVE_HOTSWAP) && defined (HAVE_ADJUSTABLE_CPU_VOLTAGE)
 878         if(cpu_boosted)
 879         {
 880             cpu_boost(false);
 881             cpu_boosted = false;
 882         }
 883 #endif  /* defined(HAVE_HOTSWAP) && defined (HAVE_ADJUSTABLE_CPU_VOLTAGE) */
 884
 885         sd_enabled = false;
 886
 887 #ifdef HAVE_MULTIDRIVE
 888 #ifdef HAVE_BUTTON_LIGHT
 889         CCU_IO &= ~(1<<2);           /* XPD is general purpose IO (b3:2 = 00) */
 890         if (buttonlight_is_on)
 891             _buttonlight_on();
 892 #endif /* HAVE_BUTTON_LIGHT */
 893         /* Disable MCI clk for uSD */
 894         CGU_PERI &= ~CGU_MCI_CLOCK_ENABLE;
 895 #endif /* HAVE_MULTIDRIVE */
 896
 897         /*  Disable both NAF_CLOCK & IDE clk for internal SD */
 898         CGU_PERI &= ~CGU_NAF_CLOCK_ENABLE;
 899         CGU_IDE &= ~(1<<6);       /* disable non AHB interface*/
 900     }
 901 }
 902
 903 tCardInfo *card_get_info_target(int card_no)
 904 {
 905     return &card_info[card_no];
 906 }
 907
 908 #ifdef HAVE_HOTSWAP
 909 void card_enable_monitoring_target(bool on)
 910 {
 911     if (on) /* enable interrupt */
 912         GPIOA_IE |= EXT_SD_BITS;
 913     else    /* disable interrupt */
 914         GPIOA_IE &= ~EXT_SD_BITS;
 915 }
 916 #endif /* HAVE_HOTSWAP */
 917
 918 #endif /* !BOOTLOADER */
 919
 920 #ifdef CONFIG_STORAGE_MULTI
 921 int sd_num_drives(int first_drive)
 922 {
 923     /* We don't care which logical drive number(s) we have been assigned */
 924     (void)first_drive;
 925
 926     return NUM_DRIVES;
 927 }
 928 #endif /* CONFIG_STORAGE_MULTI */