firmware/target/arm/imx31/gigabeat-s/kernel-gigabeat-s.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2007 by Michael Sevakis
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21 #include "config.h"
  22 #include "system.h"
  23 #include "avic-imx31.h"
  24 #include "spi-imx31.h"
  25 #include "mc13783.h"
  26 #include "ccm-imx31.h"
  27 #include "sdma-imx31.h"
  28 #include "dvfs_dptc-imx31.h"
  29 #include "kernel.h"
  30 #include "thread.h"
  31
  32 static __attribute__((interrupt("IRQ"))) void EPIT1_HANDLER(void)
  33 {
  34     EPITSR1 = EPITSR_OCIF; /* Clear the pending status */
  35
  36     /* Run through the list of tick tasks */
  37     call_tick_tasks();
  38 }
  39
  40 void INIT_ATTR tick_start(unsigned int interval_in_ms)
  41 {
  42     ccm_module_clock_gating(CG_EPIT1, CGM_ON_RUN_WAIT); /* EPIT1 module
  43                                                clock ON - before writing
  44                                                regs! */
  45     EPITCR1 &= ~(EPITCR_OCIEN | EPITCR_EN); /* Disable the counter */
  46     CCM_WIMR0 &= ~CCM_WIMR0_IPI_INT_EPIT1;  /* Clear wakeup mask */
  47
  48     /* mcu_main_clk = 528MHz = 27MHz * 2 * ((9 + 7/9) / 1)
  49      * CLKSRC = ipg_clk = 528MHz / 4 / 2 = 66MHz,
  50      * EPIT Output Disconnected,
  51      * Enabled in wait mode
  52      * Prescale 1/2640 for 25KHz
  53      * Reload from modulus register,
  54      * Compare interrupt enabled,
  55      * Count from load value */
  56     EPITCR1 = EPITCR_CLKSRC_IPG_CLK | EPITCR_WAITEN | EPITCR_IOVW |
  57               ((2640-1) << EPITCR_PRESCALER_POS) | EPITCR_RLD |
  58               EPITCR_OCIEN | EPITCR_ENMOD;
  59
  60     EPITLR1 = interval_in_ms*25; /* Count down from interval */
  61     EPITCMPR1 = 0;               /* Event when counter reaches 0 */
  62     EPITSR1 = EPITSR_OCIF;       /* Clear any pending interrupt */
  63     avic_enable_int(INT_EPIT1, INT_TYPE_IRQ, INT_PRIO_DEFAULT,
  64                     EPIT1_HANDLER);
  65     EPITCR1 |= EPITCR_EN;        /* Enable the counter */
  66 }
  67
  68 void INIT_ATTR kernel_device_init(void)
  69 {
  70     sdma_init();
  71     spi_init();
  72     mc13783_init();
  73     dvfs_dptc_init();
  74     dvfs_wfi_monitor(true); /* Monitor the WFI signal */
  75 #ifndef BOOTLOADER
  76     dvfs_dptc_start(); /* Should be ok to start even so early */
  77 #endif
  78 }
  79
  80 void tick_stop(void)
  81 {
  82     avic_disable_int(INT_EPIT1);            /* Disable insterrupt */
  83     EPITCR1 &= ~(EPITCR_OCIEN | EPITCR_EN); /* Disable counter */
  84     EPITSR1 = EPITSR_OCIF;                  /* Clear pending */
  85     ccm_module_clock_gating(CG_EPIT1, CGM_OFF); /* Turn off module clock */
  86 }
  87