firmware/target/arm/as3525/sd-as3525.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2006 Daniel Ankers
  11  * Copyright © 2008-2009 Rafaël Carré
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License
  15  * as published by the Free Software Foundation; either version 2
  16  * of the License, or (at your option) any later version.
  17  *
  18  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  19  * KIND, either express or implied.
  20  *
  21  ****************************************************************************/
  22
  23 /* Driver for the ARM PL180 SD/MMC controller inside AS3525 SoC */
  24
  25 #include "config.h" /* for HAVE_MULTIDRIVE & AMS_OF_SIZE */
  26 #include "fat.h"
  27 #include "thread.h"
  28 #include "led.h"
  29 #include "sdmmc.h"
  30 #include "system.h"
  31 #include "cpu.h"
  32 #include <stdio.h>
  33 #include <stdlib.h>
  34 #include <string.h>
  35 #include "as3525.h"
  36 #include "pl180.h"  /* SD controller */
  37 #include "pl081.h"  /* DMA controller */
  38 #include "dma-target.h" /* DMA request lines */
  39 #include "clock-target.h"
  40 #include "panic.h"
  41 #ifdef HAVE_BUTTON_LIGHT
  42 #include "backlight-target.h"
  43 #endif
  44 #include "stdbool.h"
  45 #include "ata_idle_notify.h"
  46 #include "sd.h"
  47 #include "usb.h"
  48 /*#define LOGF_ENABLE*/
  49 #include "logf.h"
  50
  51 #ifdef HAVE_HOTSWAP
  52 #include "disk.h"
  53 #endif
  54
  55 #define VERIFY_WRITE 1
  56
  57 /* command flags */
  58 #define MCI_NO_RESP     (0<<0)
  59 #define MCI_RESP        (1<<0)
  60 #define MCI_LONG_RESP   (1<<1)
  61 #define MCI_ACMD        (1<<2)
  62 #define MCI_NOCRC       (1<<3)
  63
  64 /* ARM PL180 registers */
  65 #define MCI_POWER(i)       (*(volatile unsigned char *) (pl180_base[i]+0x00))
  66 #define MCI_CLOCK(i)       (*(volatile unsigned long *) (pl180_base[i]+0x04))
  67 #define MCI_ARGUMENT(i)    (*(volatile unsigned long *) (pl180_base[i]+0x08))
  68 #define MCI_COMMAND(i)     (*(volatile unsigned long *) (pl180_base[i]+0x0C))
  69 #define MCI_RESPCMD(i)     (*(volatile unsigned long *) (pl180_base[i]+0x10))
  70 #define MCI_RESP0(i)       (*(volatile unsigned long *) (pl180_base[i]+0x14))
  71 #define MCI_RESP1(i)       (*(volatile unsigned long *) (pl180_base[i]+0x18))
  72 #define MCI_RESP2(i)       (*(volatile unsigned long *) (pl180_base[i]+0x1C))
  73 #define MCI_RESP3(i)       (*(volatile unsigned long *) (pl180_base[i]+0x20))
  74 #define MCI_DATA_TIMER(i)  (*(volatile unsigned long *) (pl180_base[i]+0x24))
  75 #define MCI_DATA_LENGTH(i) (*(volatile unsigned short*) (pl180_base[i]+0x28))
  76 #define MCI_DATA_CTRL(i)   (*(volatile unsigned char *) (pl180_base[i]+0x2C))
  77 #define MCI_DATA_CNT(i)    (*(volatile unsigned short*) (pl180_base[i]+0x30))
  78 #define MCI_STATUS(i)      (*(volatile unsigned long *) (pl180_base[i]+0x34))
  79 #define MCI_CLEAR(i)       (*(volatile unsigned long *) (pl180_base[i]+0x38))
  80 #define MCI_MASK0(i)       (*(volatile unsigned long *) (pl180_base[i]+0x3C))
  81 #define MCI_MASK1(i)       (*(volatile unsigned long *) (pl180_base[i]+0x40))
  82 #define MCI_SELECT(i)      (*(volatile unsigned long *) (pl180_base[i]+0x44))
  83 #define MCI_FIFO_CNT(i)    (*(volatile unsigned long *) (pl180_base[i]+0x48))
  84
  85 #define MCI_DATA_ERROR    \
  86     ( MCI_DATA_CRC_FAIL   \
  87     | MCI_DATA_TIMEOUT    \
  88     | MCI_TX_UNDERRUN     \
  89     | MCI_RX_OVERRUN      \
  90     | MCI_START_BIT_ERR)
  91
  92 #define MCI_RESPONSE_ERROR    \
  93     ( MCI_CMD_TIMEOUT         \
  94     | MCI_CMD_CRC_FAIL)
  95
  96 #define MCI_FIFO(i)        ((unsigned long *) (pl180_base[i]+0x80))
  97 /* volumes */
  98 #define     INTERNAL_AS3525 0   /* embedded SD card */
  99 #define     SD_SLOT_AS3525   1   /* SD slot if present */
 100
 101 static const int pl180_base[NUM_DRIVES] = {
 102             NAND_FLASH_BASE
 103 #ifdef HAVE_MULTIDRIVE
 104             , SD_MCI_BASE
 105 #endif
 106 };
 107
 108 static int sd_wait_for_tran_state(const int drive);
 109 static int sd_select_bank(signed char bank);
 110 static int sd_init_card(const int drive);
 111 static void init_pl180_controller(const int drive);
 112
 113 #define BLOCKS_PER_BANK 0x7a7800u
 114
 115 static tCardInfo card_info[NUM_DRIVES];
 116
 117 /* maximum timeouts recommanded in the SD Specification v2.00 */
 118 #define SD_MAX_READ_TIMEOUT     ((AS3525_PCLK_FREQ) / 1000 * 100) /* 100 ms */
 119 #define SD_MAX_WRITE_TIMEOUT    ((AS3525_PCLK_FREQ) / 1000 * 250) /* 250 ms */
 120
 121 /* for compatibility */
 122 static long last_disk_activity = -1;
 123
 124 #define MIN_YIELD_PERIOD 5  /* ticks */
 125 static long next_yield = 0;
 126
 127 static long sd_stack [(DEFAULT_STACK_SIZE*2 + 0x200)/sizeof(long)];
 128 static const char         sd_thread_name[] = "ata/sd";
 129 static struct mutex       sd_mtx;
 130 static struct event_queue sd_queue;
 131 bool sd_enabled = false;
 132
 133 #if defined(HAVE_MULTIDRIVE)
 134 static bool hs_card = false;
 135 #define EXT_SD_BITS (1<<2)
 136 #endif
 137
 138 static struct wakeup transfer_completion_signal;
 139 static volatile unsigned int transfer_error[NUM_VOLUMES];
 140 #define PL180_MAX_TRANSFER_ERRORS 10
 141
 142 #define UNALIGNED_NUM_SECTORS 10
 143 static unsigned char aligned_buffer[UNALIGNED_NUM_SECTORS* SD_BLOCK_SIZE] __attribute__((aligned(32)));   /* align on cache line size */
 144 static unsigned char *uncached_buffer = AS3525_UNCACHED_ADDR(&aligned_buffer[0]);
 145
 146
 147 static inline void mci_delay(void) { udelay(1000) ; }
 148
 149
 150 static inline bool card_detect_target(void)
 151 {
 152 #if defined(HAVE_MULTIDRIVE)
 153     return !(GPIOA_PIN(2));
 154 #else
 155     return false;
 156 #endif
 157 }
 158
 159
 160 #ifdef HAVE_HOTSWAP
 161 static int sd1_oneshot_callback(struct timeout *tmo)
 162 {
 163     (void)tmo;
 164
 165     /* This is called only if the state was stable for 300ms - check state
 166      * and post appropriate event. */
 167     if (card_detect_target())
 168     {
 169         queue_broadcast(SYS_HOTSWAP_INSERTED, 0);
 170     }
 171     else
 172         queue_broadcast(SYS_HOTSWAP_EXTRACTED, 0);
 173
 174     return 0;
 175 }
 176
 177 void sd_gpioa_isr(void)
 178 {
 179     static struct timeout sd1_oneshot;
 180     if (GPIOA_MIS & EXT_SD_BITS)
 181         timeout_register(&sd1_oneshot, sd1_oneshot_callback, (3*HZ/10), 0);
 182     /* acknowledge interrupt */
 183     GPIOA_IC = EXT_SD_BITS;
 184 }
 185 #endif  /* HAVE_HOTSWAP */
 186
 187 void INT_NAND(void)
 188 {
 189     const int status = MCI_STATUS(INTERNAL_AS3525);
 190
 191     transfer_error[INTERNAL_AS3525] = status & MCI_DATA_ERROR;
 192
 193     wakeup_signal(&transfer_completion_signal);
 194     MCI_CLEAR(INTERNAL_AS3525) = status;
 195 }
 196
 197 #ifdef HAVE_MULTIDRIVE
 198 void INT_MCI0(void)
 199 {
 200     const int status = MCI_STATUS(SD_SLOT_AS3525);
 201
 202     transfer_error[SD_SLOT_AS3525] = status & MCI_DATA_ERROR;
 203
 204     wakeup_signal(&transfer_completion_signal);
 205     MCI_CLEAR(SD_SLOT_AS3525) = status;
 206 }
 207 #endif
 208
 209 static bool send_cmd(const int drive, const int cmd, const int arg,
 210                      const int flags, long *response)
 211 {
 212     int status;
 213
 214     unsigned cmd_retries = 6;
 215     while(cmd_retries--)
 216     {
 217         if ((flags & MCI_ACMD) && /* send SD_APP_CMD before each try */
 218             !send_cmd(drive, SD_APP_CMD, card_info[drive].rca, MCI_RESP, response))
 219             return false;
 220
 221         /* Clear old status flags */
 222         MCI_CLEAR(drive) = 0x7ff;
 223
 224         /* Load command argument or clear if none */
 225         MCI_ARGUMENT(drive) = arg;
 226
 227         /* Construct MCI_COMMAND & enable CPSM */
 228         MCI_COMMAND(drive) =
 229            /*b0:5*/  cmd
 230            /* b6 */| ((flags & (MCI_RESP|MCI_LONG_RESP)) ? MCI_COMMAND_RESPONSE : 0)
 231            /* b7 */| ((flags & MCI_LONG_RESP) ? MCI_COMMAND_LONG_RESPONSE : 0)
 232            /* b8   | MCI_COMMAND_INTERRUPT */
 233            /* b9   | MCI_COMMAND_PENDING */  /*Only used with stream data transfer*/
 234            /* b10*/| MCI_COMMAND_ENABLE;     /* Enables CPSM */
 235
 236         /* Wait while cmd completes then disable CPSM */
 237         while(MCI_STATUS(drive) & MCI_CMD_ACTIVE);
 238         MCI_COMMAND(drive) = 0;
 239
 240         status = MCI_STATUS(drive);
 241
 242         /*  Handle command responses */
 243         if(flags & MCI_RESP)                /* CMD expects response */
 244         {
 245             response[0] = MCI_RESP0(drive); /* Always prepare short response */
 246
 247             if(status & MCI_RESPONSE_ERROR) {/* timeout or crc failure */
 248                 if ((status & MCI_CMD_CRC_FAIL) &&
 249                     (flags & MCI_NOCRC))
 250                     break;
 251                 logf("sd cmd error: drive %d cmd %d arg %08x sd_status %08x resp0 %08lx",
 252                      drive, cmd, arg, status, response[0]);
 253                 continue;
 254             }
 255
 256             if((flags & MCI_RESP) &&
 257                !(flags & MCI_LONG_RESP) &&
 258                (response[0] & SD_R1_CARD_ERROR)) {
 259                 logf("sd card error: drive %d cmd %d arg %08x r1 %08lx",
 260                      drive, cmd, arg, response[0]);
 261             }
 262
 263             if(status & MCI_CMD_RESP_END)   /* Response passed CRC check */
 264             {
 265                 if(flags & MCI_LONG_RESP)
 266                 {   /* response[0] has already been read */
 267                     response[1] = MCI_RESP1(drive);
 268                     response[2] = MCI_RESP2(drive);
 269                     response[3] = MCI_RESP3(drive);
 270                 }
 271                 return true;
 272             }
 273         }
 274         else if(status & MCI_CMD_SENT)  /* CMD sent, no response required */
 275             return true;
 276     }
 277
 278     return false;
 279 }
 280
 281 #define MCI_FULLSPEED     (MCI_CLOCK_ENABLE | MCI_CLOCK_BYPASS)     /* MCLK   */
 282 #define MCI_HALFSPEED     (MCI_CLOCK_ENABLE)                        /* MCLK/2 */
 283 #define MCI_QUARTERSPEED  (MCI_CLOCK_ENABLE | 1)                    /* MCLK/4 */
 284 #define MCI_IDENTSPEED    (MCI_CLOCK_ENABLE | AS3525_SD_IDENT_DIV)  /* IDENT  */
 285
 286 static int sd_init_card(const int drive)
 287 {
 288     unsigned long response;
 289     long init_timeout;
 290     bool sd_v2 = false;
 291
 292     card_info[drive].rca = 0;
 293
 294     /* MCLCK on and set to 400kHz ident frequency  */
 295     MCI_CLOCK(drive) = MCI_IDENTSPEED;
 296
 297     /* 100 - 400kHz clock required for Identification Mode  */
 298     /*  Start of Card Identification Mode ************************************/
 299
 300     /* CMD0 Go Idle  */
 301     if(!send_cmd(drive, SD_GO_IDLE_STATE, 0, MCI_NO_RESP, NULL))
 302         return -1;
 303     mci_delay();
 304
 305     /* CMD8 Check for v2 sd card.  Must be sent before using ACMD41
 306       Non v2 cards will not respond to this command*/
 307     if(send_cmd(drive, SD_SEND_IF_COND, 0x1AA, MCI_RESP, &response))
 308         if((response & 0xFFF) == 0x1AA)
 309             sd_v2 = true;
 310
 311     /* timeout for initialization is 1sec, from SD Specification 2.00 */
 312     init_timeout = current_tick + HZ;
 313
 314     do {
 315         /* this timeout is the only valid error for this loop*/
 316         if(TIME_AFTER(current_tick, init_timeout))
 317             return -2;
 318
 319         /* ACMD41 For v2 cards set HCS bit[30] & send host voltage range to all */
 320         send_cmd(drive, SD_APP_OP_COND, (0x00FF8000 | (sd_v2 ? 1<<30 : 0)),
 321                         MCI_ACMD|MCI_NOCRC|MCI_RESP, &card_info[drive].ocr);
 322
 323     } while(!(card_info[drive].ocr & (1<<31)));
 324
 325     /* CMD2 send CID */
 326     if(!send_cmd(drive, SD_ALL_SEND_CID, 0, MCI_RESP|MCI_LONG_RESP,
 327                             card_info[drive].cid))
 328         return -3;
 329
 330     /* CMD3 send RCA */
 331     if(!send_cmd(drive, SD_SEND_RELATIVE_ADDR, 0, MCI_RESP,
 332                 &card_info[drive].rca))
 333         return -4;
 334
 335     /*  End of Card Identification Mode   ************************************/
 336
 337 #ifdef HAVE_MULTIDRIVE        /*  The internal SDs are v1 */
 338
 339     /* Try to switch V2 cards to HS timings, non HS seem to ignore this */
 340     if(sd_v2)
 341     {
 342         /*  CMD7 w/rca: Select card to put it in TRAN state */
 343         if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_RESP, &response))
 344             return -5;
 345
 346         if(sd_wait_for_tran_state(drive))
 347             return -6;
 348         /* CMD6 */
 349         if(!send_cmd(drive, SD_SWITCH_FUNC, 0x80fffff1, MCI_NO_RESP, NULL))
 350             return -7;
 351         mci_delay();
 352
 353         /*  go back to STBY state so we can read csd */
 354         /*  CMD7 w/rca=0:  Deselect card to put it in STBY state */
 355         if(!send_cmd(drive, SD_DESELECT_CARD, 0, MCI_NO_RESP, NULL))
 356             return -8;
 357         mci_delay();
 358     }
 359 #endif /*  HAVE_MULTIDRIVE  */
 360
 361     /* CMD9 send CSD */
 362     if(!send_cmd(drive, SD_SEND_CSD, card_info[drive].rca,
 363                  MCI_RESP|MCI_LONG_RESP, card_info[drive].csd))
 364         return -9;
 365
 366     sd_parse_csd(&card_info[drive]);
 367
 368 #if defined(HAVE_MULTIDRIVE)
 369     hs_card = (card_info[drive].speed == 50000000);
 370 #endif
 371
 372     /* Boost MCICLK to operating speed */
 373     if(drive == INTERNAL_AS3525)
 374         MCI_CLOCK(drive) = MCI_HALFSPEED;  /* MCICLK = IDE_CLK/2 = 25 MHz  */
 375 #if defined(HAVE_MULTIDRIVE)
 376     else
 377         /* MCICLK = PCLK/2 = 31MHz(HS) or PCLK/4 = 15.5 Mhz (STD)*/
 378         MCI_CLOCK(drive) = (hs_card ? MCI_HALFSPEED : MCI_QUARTERSPEED);
 379 #endif
 380
 381     /*  CMD7 w/rca: Select card to put it in TRAN state */
 382     if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_RESP, &response))
 383         return -10;
 384
 385     /*  Switch to to 4 bit widebus mode  */
 386     if(sd_wait_for_tran_state(drive) < 0)
 387         return -11;
 388     /* ACMD42  */
 389     if(!send_cmd(drive, SD_SET_CLR_CARD_DETECT, 0, MCI_ACMD|MCI_RESP, &response))
 390         return -15;
 391     /* ACMD6  */
 392     if(!send_cmd(drive, SD_SET_BUS_WIDTH, 2, MCI_ACMD|MCI_RESP, &response))
 393         return -13;
 394     /* Now that card is widebus make controller aware */
 395     MCI_CLOCK(drive) |= MCI_CLOCK_WIDEBUS;
 396
 397     /*
 398      * enable bank switching
 399      * without issuing this command, we only have access to 1/4 of the blocks
 400      * of the first bank (0x1E9E00 blocks, which is the size reported in the
 401      * CSD register)
 402      */
 403     if(drive == INTERNAL_AS3525)
 404     {
 405         const int ret = sd_select_bank(-1);
 406         if(ret < 0)
 407             return ret -16;
 408
 409         /*  CMD7 w/rca = 0: Unselect card to put it in STBY state */
 410         if(!send_cmd(drive, SD_SELECT_CARD, 0, MCI_NO_RESP, NULL))
 411             return -17;
 412         mci_delay();
 413
 414         /* CMD9 send CSD again, so we got the correct number of blocks */
 415         if(!send_cmd(drive, SD_SEND_CSD, card_info[drive].rca,
 416                      MCI_RESP|MCI_LONG_RESP, card_info[drive].csd))
 417             return -18;
 418
 419         sd_parse_csd(&card_info[drive]);
 420         /* The OF is stored in the first blocks */
 421         card_info[INTERNAL_AS3525].numblocks -= AMS_OF_SIZE;
 422
 423         /*  CMD7 w/rca: Select card to put it in TRAN state */
 424         if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_RESP, &response))
 425             return -19;
 426     }
 427
 428     card_info[drive].initialized = 1;
 429
 430     return 0;
 431 }
 432
 433 static void sd_thread(void) __attribute__((noreturn));
 434 static void sd_thread(void)
 435 {
 436     struct queue_event ev;
 437     bool idle_notified = false;
 438
 439     while (1)
 440     {
 441         queue_wait_w_tmo(&sd_queue, &ev, HZ);
 442
 443         switch ( ev.id )
 444         {
 445 #ifdef HAVE_HOTSWAP
 446         case SYS_HOTSWAP_INSERTED:
 447         case SYS_HOTSWAP_EXTRACTED:
 448         {
 449             int microsd_init = 1;
 450             fat_lock();          /* lock-out FAT activity first -
 451                                     prevent deadlocking via disk_mount that
 452                                     would cause a reverse-order attempt with
 453                                     another thread */
 454             mutex_lock(&sd_mtx); /* lock-out card activity - direct calls
 455                                     into driver that bypass the fat cache */
 456
 457             /* We now have exclusive control of fat cache and ata */
 458
 459             disk_unmount(SD_SLOT_AS3525);     /* release "by force", ensure file
 460                                     descriptors aren't leaked and any busy
 461                                     ones are invalid if mounting */
 462
 463             /* Force card init for new card, re-init for re-inserted one or
 464              * clear if the last attempt to init failed with an error. */
 465             card_info[SD_SLOT_AS3525].initialized = 0;
 466
 467             if (ev.id == SYS_HOTSWAP_INSERTED)
 468             {
 469                 sd_enable(true);
 470                 init_pl180_controller(SD_SLOT_AS3525);
 471                 microsd_init = sd_init_card(SD_SLOT_AS3525);
 472                 if (microsd_init < 0) /* initialisation failed */
 473                     panicf("microSD init failed : %d", microsd_init);
 474
 475                 microsd_init = disk_mount(SD_SLOT_AS3525); /* 0 if fail */
 476             }
 477
 478             /*
 479              * Mount succeeded, or this was an EXTRACTED event,
 480              * in both cases notify the system about the changed filesystems
 481              */
 482             if (microsd_init)
 483                 queue_broadcast(SYS_FS_CHANGED, 0);
 484
 485             /* Access is now safe */
 486             mutex_unlock(&sd_mtx);
 487             fat_unlock();
 488             sd_enable(false);
 489         }
 490             break;
 491 #endif
 492         case SYS_TIMEOUT:
 493             if (TIME_BEFORE(current_tick, last_disk_activity+(3*HZ)))
 494             {
 495                 idle_notified = false;
 496             }
 497             else
 498             {
 499                 /* never let a timer wrap confuse us */
 500                 next_yield = current_tick;
 501
 502                 if (!idle_notified)
 503                 {
 504                     call_storage_idle_notifys(false);
 505                     idle_notified = true;
 506                 }
 507             }
 508             break;
 509
 510         case SYS_USB_CONNECTED:
 511             usb_acknowledge(SYS_USB_CONNECTED_ACK);
 512             /* Wait until the USB cable is extracted again */
 513             usb_wait_for_disconnect(&sd_queue);
 514
 515             break;
 516         case SYS_USB_DISCONNECTED:
 517             usb_acknowledge(SYS_USB_DISCONNECTED_ACK);
 518             break;
 519         }
 520     }
 521 }
 522
 523 static void init_pl180_controller(const int drive)
 524 {
 525     MCI_COMMAND(drive) = MCI_DATA_CTRL(drive) = 0;
 526     MCI_CLEAR(drive) = 0x7ff;
 527
 528     MCI_MASK0(drive) = MCI_DATA_ERROR | MCI_DATA_END;
 529     MCI_MASK1(drive) = 0;
 530 #ifdef HAVE_MULTIDRIVE
 531     VIC_INT_ENABLE =
 532         (drive == INTERNAL_AS3525) ? INTERRUPT_NAND : INTERRUPT_MCI0;
 533     /* clear previous irq */
 534     GPIOA_IC = EXT_SD_BITS;
 535     /* enable edge detecting */
 536     GPIOA_IS &= ~EXT_SD_BITS;
 537     /* detect both raising and falling edges */
 538     GPIOA_IBE |= EXT_SD_BITS;
 539     /* enable the card detect interrupt */
 540     GPIOA_IE |= EXT_SD_BITS;
 541
 542 #else
 543     VIC_INT_ENABLE = INTERRUPT_NAND;
 544 #endif
 545
 546     MCI_POWER(drive) = MCI_POWER_UP | (MCI_VDD_3_0);  /*  OF Setting  */
 547     mci_delay();
 548
 549     MCI_POWER(drive) |= MCI_POWER_ON;
 550     mci_delay();
 551
 552     MCI_SELECT(drive) = 0;
 553
 554     /* Pl180 clocks get turned on at start of card init */
 555 }
 556
 557 int sd_init(void)
 558 {
 559     int ret;
 560     CGU_IDE =   (1<<6)                  /*  enable non AHB interface*/
 561             |   (AS3525_IDE_DIV << 2)
 562             |    AS3525_CLK_PLLA;       /* clock source = PLLA */
 563
 564     bitset32(&CGU_PERI, CGU_NAF_CLOCK_ENABLE);
 565 #ifdef HAVE_MULTIDRIVE
 566     bitset32(&CGU_PERI, CGU_MCI_CLOCK_ENABLE);
 567     CCU_IO &= ~(1<<3);           /* bits 3:2 = 01, xpd is SD interface */
 568     CCU_IO |= (1<<2);
 569 #endif
 570
 571     wakeup_init(&transfer_completion_signal);
 572
 573     init_pl180_controller(INTERNAL_AS3525);
 574     ret = sd_init_card(INTERNAL_AS3525);
 575     if(ret < 0)
 576         return ret;
 577 #ifdef HAVE_MULTIDRIVE
 578     init_pl180_controller(SD_SLOT_AS3525);
 579 #endif
 580
 581     /* init mutex */
 582     mutex_init(&sd_mtx);
 583
 584     queue_init(&sd_queue, true);
 585     create_thread(sd_thread, sd_stack, sizeof(sd_stack), 0,
 586             sd_thread_name IF_PRIO(, PRIORITY_USER_INTERFACE) IF_COP(, CPU));
 587
 588     sd_enabled = true;
 589     sd_enable(false);
 590
 591     return 0;
 592 }
 593
 594 #ifdef HAVE_HOTSWAP
 595 bool sd_removable(IF_MD_NONVOID(int drive))
 596 {
 597     return (drive==1);
 598 }
 599
 600 bool sd_present(IF_MD_NONVOID(int drive))
 601 {
 602     return (drive == 0) ? true : card_detect_target();
 603 }
 604 #endif /* HAVE_HOTSWAP */
 605
 606 static int sd_wait_for_tran_state(const int drive)
 607 {
 608     unsigned long response = 0;
 609     unsigned int timeout = current_tick + 5 * HZ;
 610
 611     while (1)
 612     {
 613         if(!send_cmd(drive, SD_SEND_STATUS, card_info[drive].rca, MCI_RESP,
 614                     &response))
 615             return -1;
 616
 617         if (((response >> 9) & 0xf) == SD_TRAN)
 618             return 0;
 619
 620         if(TIME_AFTER(current_tick, timeout))
 621             return -2;
 622
 623         if (TIME_AFTER(current_tick, next_yield))
 624         {
 625             yield();
 626             next_yield = current_tick + MIN_YIELD_PERIOD;
 627         }
 628     }
 629 }
 630
 631 static int sd_select_bank(signed char bank)
 632 {
 633     int ret;
 634     unsigned loops = 0;
 635
 636     memset(uncached_buffer, 0, 512);
 637     if(bank == -1)
 638     {   /* enable bank switching */
 639         uncached_buffer[0] = 16;
 640         uncached_buffer[1] = 1;
 641         uncached_buffer[2] = 10;
 642     }
 643     else
 644         uncached_buffer[0] = bank;
 645
 646     do {
 647         if(loops++ > PL180_MAX_TRANSFER_ERRORS)
 648             panicf("SD bank %d error : 0x%x", bank,
 649                     transfer_error[INTERNAL_AS3525]);
 650
 651         ret = sd_wait_for_tran_state(INTERNAL_AS3525);
 652         if (ret < 0)
 653             return ret - 2;
 654
 655         if(!send_cmd(INTERNAL_AS3525, SD_SWITCH_FUNC, 0x80ffffef, MCI_NO_RESP,
 656                      NULL))
 657             return -1;
 658
 659         mci_delay();
 660
 661         if(!send_cmd(INTERNAL_AS3525, 35, 0, MCI_NO_RESP, NULL))
 662             return -2;
 663
 664         mci_delay();
 665
 666         dma_retain();
 667         /* we don't use the uncached buffer here, because we need the
 668          * physical memory address for DMA transfers */
 669         dma_enable_channel(0, aligned_buffer, MCI_FIFO(INTERNAL_AS3525),
 670             DMA_PERI_SD, DMAC_FLOWCTRL_PERI_MEM_TO_PERI, true, false, 0, DMA_S8,
 671             NULL);
 672
 673         MCI_DATA_TIMER(INTERNAL_AS3525) = SD_MAX_WRITE_TIMEOUT;
 674         MCI_DATA_LENGTH(INTERNAL_AS3525) = 512;
 675         MCI_DATA_CTRL(INTERNAL_AS3525) =  (1<<0) /* enable */   |
 676                                 (0<<1) /* transfer direction */ |
 677                                 (1<<3) /* DMA */                |
 678                                 (9<<4) /* 2^9 = 512 */ ;
 679
 680         /* Wakeup signal from NAND/MCIO isr on MCI_DATA_ERROR | MCI_DATA_END */
 681         wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK);
 682
 683         /*  Wait for FIFO to empty, card may still be in PRG state  */
 684         while(MCI_STATUS(INTERNAL_AS3525) & MCI_TX_ACTIVE );
 685
 686         dma_release();
 687
 688     } while(transfer_error[INTERNAL_AS3525]);
 689
 690     card_info[INTERNAL_AS3525].current_bank = (bank == -1) ? 0 : bank;
 691
 692     return 0;
 693 }
 694
 695 static int sd_transfer_sectors(IF_MD2(int drive,) unsigned long start,
 696                                int count, void* buf, const bool write)
 697 {
 698 #ifndef HAVE_MULTIDRIVE
 699     const int drive = 0;
 700 #endif
 701     int ret = 0;
 702     unsigned loops = 0;
 703     unsigned long response;
 704     bool aligned = !((uintptr_t)buf & (CACHEALIGN_SIZE - 1));
 705
 706     sd_enable(true);
 707     led(true);
 708
 709     if (card_info[drive].initialized <= 0)
 710     {
 711         ret = sd_init_card(drive);
 712         if (!(card_info[drive].initialized))
 713             goto sd_transfer_error_nodma;
 714     }
 715
 716     if(count < 0) /* XXX: why is it signed ? */
 717     {
 718         ret = -20;
 719         goto sd_transfer_error_nodma;
 720     }
 721     if((start+count) > card_info[drive].numblocks)
 722     {
 723         ret = -21;
 724         goto sd_transfer_error_nodma;
 725     }
 726
 727     /* skip SanDisk OF */
 728     if (drive == INTERNAL_AS3525)
 729         start += AMS_OF_SIZE;
 730
 731     last_disk_activity = current_tick;
 732
 733     dma_retain();
 734
 735     if(aligned)
 736     {
 737         if(write)
 738             clean_dcache_range(buf, count * SECTOR_SIZE);
 739         else
 740             dump_dcache_range(buf, count * SECTOR_SIZE);
 741     }
 742
 743     while(count)
 744     {
 745         /* 128 * 512 = 2^16, and doesn't fit in the 16 bits of DATA_LENGTH
 746          * register, so we have to transfer maximum 127 sectors at a time. */
 747         unsigned int transfer = (count >= 128) ? 127 : count; /* sectors */
 748         void *dma_buf;
 749         const int cmd =
 750             write ? SD_WRITE_MULTIPLE_BLOCK : SD_READ_MULTIPLE_BLOCK;
 751         unsigned long bank_start = start;
 752         unsigned long status;
 753
 754         /* Only switch banks for internal storage */
 755         if(drive == INTERNAL_AS3525)
 756         {
 757             unsigned int bank = 0;
 758             while(bank_start >= BLOCKS_PER_BANK)
 759             {
 760                 bank_start -= BLOCKS_PER_BANK;
 761                 bank++;
 762             }
 763
 764             /* Switch bank if needed */
 765             if(card_info[INTERNAL_AS3525].current_bank != bank)
 766             {
 767                 ret = sd_select_bank(bank);
 768                 if (ret < 0)
 769                 {
 770                     ret -= 20;
 771                     goto sd_transfer_error;
 772                 }
 773             }
 774
 775             /* Do not cross a bank boundary in a single transfer loop */
 776             if((transfer + bank_start) > BLOCKS_PER_BANK)
 777                 transfer = BLOCKS_PER_BANK - bank_start;
 778         }
 779
 780         /* Set bank_start to the correct unit (blocks or bytes) */
 781         if(!(card_info[drive].ocr & (1<<30)))   /* not SDHC */
 782             bank_start *= SD_BLOCK_SIZE;
 783
 784         if(aligned)
 785         {
 786             dma_buf = AS3525_PHYSICAL_ADDR(buf);
 787         }
 788         else
 789         {
 790             dma_buf = aligned_buffer;
 791             if(transfer > UNALIGNED_NUM_SECTORS)
 792                 transfer = UNALIGNED_NUM_SECTORS;
 793
 794             if(write)
 795                 memcpy(uncached_buffer, buf, transfer * SD_BLOCK_SIZE);
 796         }
 797
 798         ret = sd_wait_for_tran_state(drive);
 799         if (ret < 0)
 800         {
 801             ret -= 2*20;
 802             goto sd_transfer_error;
 803         }
 804
 805         if(!send_cmd(drive, cmd, bank_start, MCI_RESP, &response))
 806         {
 807             ret -= 3*20;
 808             goto sd_transfer_error;
 809         }
 810
 811         if(write)
 812         {
 813             dma_enable_channel(0, dma_buf, MCI_FIFO(drive),
 814                 (drive == INTERNAL_AS3525) ? DMA_PERI_SD : DMA_PERI_SD_SLOT,
 815                 DMAC_FLOWCTRL_PERI_MEM_TO_PERI, true, false, 0, DMA_S8, NULL);
 816
 817             /*Small delay for writes prevents data crc failures at lower freqs*/
 818 #ifdef HAVE_MULTIDRIVE
 819             if((drive == SD_SLOT_AS3525) && !hs_card)
 820             {
 821                 int write_delay = 125;
 822                 while(write_delay--);
 823             }
 824 #endif
 825         }
 826         else
 827             dma_enable_channel(0, MCI_FIFO(drive), dma_buf,
 828                 (drive == INTERNAL_AS3525) ? DMA_PERI_SD : DMA_PERI_SD_SLOT,
 829                 DMAC_FLOWCTRL_PERI_PERI_TO_MEM, false, true, 0, DMA_S8, NULL);
 830
 831         MCI_DATA_TIMER(drive) = write ?
 832                 SD_MAX_WRITE_TIMEOUT : SD_MAX_READ_TIMEOUT;
 833         MCI_DATA_LENGTH(drive) = transfer * SD_BLOCK_SIZE;
 834         MCI_DATA_CTRL(drive) =  (1<<0) /* enable */                     |
 835                                 (!write<<1) /* transfer direction */    |
 836                                 (1<<3) /* DMA */                        |
 837                                 (9<<4) /* 2^9 = 512 */ ;
 838
 839         /* Wakeup signal from NAND/MCIO isr on MCI_DATA_ERROR | MCI_DATA_END */
 840         wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK);
 841
 842         /*  Wait for FIFO to empty, card may still be in PRG state for writes */
 843         while(MCI_STATUS(drive) & MCI_TX_ACTIVE);
 844
 845         /*
 846          * If the write aborted early due to a tx underrun, disable the
 847          * dma channel here, otherwise there are still 4 words in the fifo
 848          * and the retried write will get corrupted.
 849          */
 850         dma_disable_channel(0);
 851
 852         last_disk_activity = current_tick;
 853
 854         if(!send_cmd(drive, SD_STOP_TRANSMISSION, 0, MCI_RESP, &status))
 855         {
 856             ret = -4*20;
 857             goto sd_transfer_error;
 858         }
 859
 860         if(!transfer_error[drive])
 861         {
 862             if(!write && !aligned)
 863                 memcpy(buf, uncached_buffer, transfer * SD_BLOCK_SIZE);
 864             buf += transfer * SD_BLOCK_SIZE;
 865             start += transfer;
 866             count -= transfer;
 867             loops = 0;  /* reset errors counter */
 868         }
 869         else if(loops++ > PL180_MAX_TRANSFER_ERRORS)
 870                 panicf("SD Xfer %s err:0x%x Disk%d", (write? "write": "read"),
 871                                                   transfer_error[drive], drive);
 872     }
 873
 874 sd_transfer_error:
 875
 876     dma_release();
 877
 878 sd_transfer_error_nodma:
 879
 880     led(false);
 881     sd_enable(false);
 882
 883     if (ret)    /* error */
 884         card_info[drive].initialized = 0;
 885
 886     return ret;
 887 }
 888
 889 int sd_read_sectors(IF_MD2(int drive,) unsigned long start, int count,
 890                      void* buf)
 891 {
 892     int ret;
 893
 894     mutex_lock(&sd_mtx);
 895     ret = sd_transfer_sectors(IF_MD2(drive,) start, count, buf, false);
 896     mutex_unlock(&sd_mtx);
 897
 898     return ret;
 899 }
 900
 901 int sd_write_sectors(IF_MD2(int drive,) unsigned long start, int count,
 902                      const void* buf)
 903 {
 904 #ifdef VERIFY_WRITE
 905     unsigned long saved_start = start;
 906     int saved_count = count;
 907     void *saved_buf = (void*)buf;
 908 #endif
 909     int ret;
 910
 911     mutex_lock(&sd_mtx);
 912
 913     ret = sd_transfer_sectors(IF_MD2(drive,) start, count, (void*)buf, true);
 914
 915 #ifdef VERIFY_WRITE
 916     if (ret) /* write failed, no point in verifying */
 917         goto write_error;
 918
 919     count = saved_count;
 920     buf = saved_buf;
 921     start = saved_start;
 922     while (count) {
 923         int transfer = count;
 924         if(transfer > UNALIGNED_NUM_SECTORS)
 925             transfer = UNALIGNED_NUM_SECTORS;
 926
 927         sd_transfer_sectors(IF_MD2(drive,) start, transfer, aligned_buffer, false);
 928         if (memcmp(buf, aligned_buffer, transfer * 512) != 0) {
 929             /* try the write again in the hope to repair the damage */
 930             sd_transfer_sectors(IF_MD2(drive,) saved_start, saved_count, saved_buf, true);
 931             panicf("sd: verify failed: sec=%ld n=%d!", start, transfer);
 932         }
 933
 934         buf   += transfer * 512;
 935         count -= transfer;
 936         start += transfer;
 937     }
 938 #endif
 939
 940 write_error:
 941     mutex_unlock(&sd_mtx);
 942
 943     return ret;
 944 }
 945
 946 long sd_last_disk_activity(void)
 947 {
 948     return last_disk_activity;
 949 }
 950
 951 void sd_enable(bool on)
 952 {
 953 #if defined(HAVE_BUTTON_LIGHT) && defined(HAVE_MULTIDRIVE)
 954     extern int buttonlight_is_on;
 955 #endif
 956
 957 #if defined(HAVE_HOTSWAP) && defined (HAVE_ADJUSTABLE_CPU_VOLTAGE)
 958     static bool cpu_boosted = false;
 959 #endif
 960
 961     if (sd_enabled == on)
 962         return; /* nothing to do */
 963
 964     sd_enabled = on;
 965
 966     if(on)
 967     {
 968 #if defined(HAVE_BUTTON_LIGHT) && defined(HAVE_MULTIDRIVE)
 969         /* buttonlight AMSes need a bit of special handling for the buttonlight
 970          * here due to the dual mapping of GPIOD and XPD */
 971         CCU_IO |= (1<<2);              /* XPD is SD-MCI interface (b3:2 = 01) */
 972         if (buttonlight_is_on)
 973             GPIOD_DIR &= ~(1<<7);
 974         else
 975             _buttonlight_off();
 976 #endif
 977
 978 #if defined(HAVE_HOTSWAP) && defined (HAVE_ADJUSTABLE_CPU_VOLTAGE)
 979         if(card_detect_target())  /* If SD card present Boost cpu for voltage */
 980         {
 981             cpu_boosted = true;
 982             cpu_boost(true);
 983         }
 984 #endif  /* defined(HAVE_HOTSWAP) && defined (HAVE_ADJUSTABLE_CPU_VOLTAGE) */
 985     }
 986     else
 987     {
 988 #if defined(HAVE_HOTSWAP) && defined (HAVE_ADJUSTABLE_CPU_VOLTAGE)
 989         if(cpu_boosted)
 990         {
 991             cpu_boost(false);
 992             cpu_boosted = false;
 993         }
 994 #endif  /* defined(HAVE_HOTSWAP) && defined (HAVE_ADJUSTABLE_CPU_VOLTAGE) */
 995
 996 #if defined(HAVE_BUTTON_LIGHT) && defined(HAVE_MULTIDRIVE)
 997         CCU_IO &= ~(1<<2);           /* XPD is general purpose IO (b3:2 = 00) */
 998         if (buttonlight_is_on)
 999             _buttonlight_on();
1000 #endif
1001     }
1002 }
1003
1004 tCardInfo *card_get_info_target(int card_no)
1005 {
1006     return &card_info[card_no];
1007 }
1008
1009 #ifdef CONFIG_STORAGE_MULTI
1010 int sd_num_drives(int first_drive)
1011 {
1012     /* We don't care which logical drive number(s) we have been assigned */
1013     (void)first_drive;
1014
1015     return NUM_DRIVES;
1016 }
1017 #endif /* CONFIG_STORAGE_MULTI */