1 /***************************************************************************
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
10 * Copyright (C) 2008 by Maurus Cuelenaere
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
20 ****************************************************************************/
25 * Initialization code for JzRISC.
28 * e-mail: seeger.chin@gmail.com
30 * Copyright (C) 2006 Ingenic Semiconductor Inc.
32 * This program is free software; you can redistribute it and/or modify
33 * it under the terms of the GNU General Public License version 2 as
34 * published by the Free Software Foundation.
53 /* These will get filled in by scramble */
55 .word 0 /* Filesize */
57 /* Relocate bootloader */
58 la t0, (_loadaddress-0xE00000)
65 bne t1, t2, _relocate_loop
72 ----------------------------------------------------
74 ----------------------------------------------------
79 li t0, (M_StatusBEV | M_StatusIM7 | M_StatusIM6 \
80 | M_StatusIM5 | M_StatusIM4 | M_StatusIM3 \
81 | M_StatusIM2 | M_StatusERL)
83 BEV = Enable Boot Exception Vectors
85 ERL = Denotes error level
93 ----------------------------------------------------
94 Init caches, assumes a 4way*128set*32byte I/D cache
95 ----------------------------------------------------
97 li t0, 3 # enable cache for kseg0 accesses
98 mtc0 t0, C0_CONFIG # CONFIG reg
99 la t0, 0x80000000 # an idx op should use an unmappable address
100 ori t1, t0, 0x4000 # 16kB cache
101 mtc0 zero, C0_TAGLO # TAGLO reg
102 mtc0 zero, C0_TAGHI # TAGHI reg
105 cache 0x8, 0(t0) # index store icache tag
106 cache 0x9, 0(t0) # index store dcache tag
107 bne t0, t1, _cache_loop
108 addiu t0, t0, 0x20 # 32 bytes per cache line
112 ----------------------------------------------------
114 ----------------------------------------------------
123 ----------------------------------------------------
125 * copy IRAM first before BSS gets cleared, as both
126 have the same address
127 ----------------------------------------------------
136 bne t1, t2, _iram_loop
140 ----------------------------------------------------
142 ----------------------------------------------------
148 bne t0, t1, _bss_loop
152 ----------------------------------------------------
154 ----------------------------------------------------
162 bne t0, sp, _stack_loop
166 ----------------------------------------------------
168 ----------------------------------------------------
170 jal system_main /* Init clocks etc first */
177 * 0x0 - Simple TLB refill handler
178 * 0x100 - Cache error handler
179 * 0x180 - Exception/Interrupt handler
180 * 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE)
183 .section .vectors.1, "ax", %progbits
187 .section .vectors.2, "ax", %progbits
188 j real_exception_handler
191 .section .vectors.3, "ax", %progbits
192 j real_exception_handler
195 .section .vectors.4, "ax", %progbits
196 j real_exception_handler
199 .section .vectors, "ax", %progbits
200 real_exception_handler:
249 li k1, M_CauseExcCode
274 jal exception_handler