FS#8961 - Anti-Aliased Fonts.
[kugel-rb.git] / firmware / export / r61509.h
blob5d45c4ebcdd6e29a75ea3a7a2c7fb6386bba42c8
1 /***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
10 * Copyright (C) 2008 by Maurus Cuelenaere
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
20 ****************************************************************************/
23 * Register definitions for the Renesas R61509 TFT Panel
25 #ifndef __R61509_H
26 #define __R61509_H
28 /* Register list */
29 #define REG_DEVICE_CODE 0x000
30 #define REG_DRIVER_OUTPUT 0x001
31 #define REG_LCD_DR_WAVE_CTRL 0x002
32 #define REG_ENTRY_MODE 0x003
33 #define REG_OUTL_SHARP_CTRL 0x006
34 #define REG_DISP_CTRL1 0x007
35 #define REG_DISP_CTRL2 0x008
36 #define REG_DISP_CTRL3 0x009
37 #define REG_LPCTRL 0x00B
38 #define REG_EXT_DISP_CTRL1 0x00C
39 #define REG_EXT_DISP_CTRL2 0x00F
40 #define REG_PAN_INTF_CTRL1 0x010
41 #define REG_PAN_INTF_CTRL2 0x011
42 #define REG_PAN_INTF_CTRL3 0x012
43 #define REG_PAN_INTF_CTRL4 0x020
44 #define REG_PAN_INTF_CTRL5 0x021
45 #define REG_PAN_INTF_CTRL6 0x022
46 #define REG_FRM_MRKR_CTRL 0x090
48 #define REG_PWR_CTRL1 0x100
49 #define REG_PWR_CTRL2 0x101
50 #define REG_PWR_CTRL3 0x102
51 #define REG_PWR_CTRL4 0x103
52 #define REG_PWR_CTRL5 0x107
53 #define REG_PWR_CTRL6 0x110
54 #define REG_PWR_CTRL7 0x112
56 #define REG_RAM_HADDR_SET 0x200
57 #define REG_RAM_VADDR_SET 0x201
58 #define REG_RW_GRAM 0x202
59 #define REG_RAM_HADDR_START 0x210
60 #define REG_RAM_HADDR_END 0x211
61 #define REG_RAM_VADDR_START 0x212
62 #define REG_RAM_VADDR_END 0x213
63 #define REG_RW_NVM 0x280
64 #define REG_VCOM_HVOLTAGE1 0x281
65 #define REG_VCOM_HVOLTAGE2 0x282
67 #define REG_GAMMA_CTRL1 0x300
68 #define REG_GAMMA_CTRL2 0x301
69 #define REG_GAMMA_CTRL3 0x302
70 #define REG_GAMMA_CTRL4 0x303
71 #define REG_GAMMA_CTRL5 0x304
72 #define REG_GAMMA_CTRL6 0x305
73 #define REG_GAMMA_CTRL7 0x306
74 #define REG_GAMMA_CTRL8 0x307
75 #define REG_GAMMA_CTRL9 0x308
76 #define REG_GAMMA_CTRL10 0x309
77 #define REG_GAMMA_CTRL11 0x30A
78 #define REG_GAMMA_CTRL12 0x30B
79 #define REG_GAMMA_CTRL13 0x30C
80 #define REG_GAMMA_CTRL14 0x30D
82 #define REG_BIMG_NR_LINE 0x400
83 #define REG_BIMG_DISP_CTRL 0x401
84 #define REG_BIMG_VSCROLL_CTRL 0x404
86 #define REG_PARTIMG1_POS 0x500
87 #define REG_PARTIMG1_RAM_START 0x501
88 #define REG_PARTIMG1_RAM_END 0x502
89 #define REG_PARTIMG2_POS 0x503
90 #define REG_PARTIMG2_RAM_START 0x504
91 #define REG_PARTIMG2_RAM_END 0x505
93 #define REG_SOFT_RESET 0x600
94 #define REG_ENDIAN_CTRL 0x606
95 #define REG_NVM_ACCESS_CTRL 0x6F0
97 /* Bits */
98 #define DRIVER_OUTPUT_SS_BIT (1 << 8)
99 #define DRIVER_OUTPUT_SM_BIT (1 << 10)
101 #define ENTRY_MODE_TRI (1 << 15)
102 #define ENTRY_MODE_DFM (1 << 14)
103 #define ENTRY_MODE_BGR (1 << 12)
104 #define ENTRY_MODE_HWM (1 << 9)
105 #define ENTRY_MODE_ORG (1 << 7)
106 #define ENTRY_MODE_VID (1 << 5)
107 #define ENTRY_MODE_HID (1 << 4)
108 #define ENTRY_MODE_AM (1 << 3)
109 #define ENTRY_MODE_EPF(n) (n & 3)
111 #define OUTL_SHARP_CTRL_EGMODE (1 << 15)
112 #define OUTL_SHARP_CTRL_AVST(n) ((n & 7) << 7)
113 #define OUTL_SHARP_CTRL_ADST(n) ((n & 7) << 4)
114 #define OUTL_SHARP_CTRL_DTHU(n) ((n & 3) << 2)
115 #define OUTL_SHARP_CTRL_DTHL(n) (n & 3)
117 #define DISP_CTRL1_PTDE(n) ((n & 4) << 12)
118 #define DISP_CTRL1_BASEE (1 << 8)
119 #define DISP_CTRL1_VON (1 << 6)
120 #define DISP_CTRL1_GON (1 << 5)
121 #define DISP_CTRL1_DTE (1 << 4)
122 #define DISP_CTRL1_D(n) (n & 3)
124 #define EXT_DISP_CTRL1_ENC(n) ((n & 7) << 12)
125 #define EXT_DISP_CTRL1_RM(n) ((n & 1) << 8)
126 #define EXT_DISP_CTRL1_DM(n) ((n & 3) << 4)
127 #define EXT_DISP_CTRL1_RIM(n) (n & 3)
129 #define PWR_CTRL1_SAP(n) ((n & 3) << 13)
130 #define PWR_CTRL1_SAPE (1 << 12)
131 #define PWR_CTRL1_BT(n) ((n & 7) << 8)
132 #define PWR_CTRL1_APE (1 << 7)
133 #define PWR_CTRL1_AP(n) ((n & 7) << 4)
134 #define PWR_CTRL1_DSTB (1 << 2)
135 #define PWR_CTRL1_SLP (1 << 1)
137 #define SOFT_RESET(n) (n << 0)
139 #endif /* __R61509_H */