firmware/export/pl081.h

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright © 2008 Rafaël Carré
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21
  22 /* Note: since the base address is not specified, you need to define DMAC_BASE
  23  * before including this file */
  24
  25 /* ARM PrimeCell PL081 Single Master DMA controller */
  26
  27 #define DMAC_INT_STATUS           (*(volatile unsigned long*)(DMAC_BASE+0x000))
  28 #define DMAC_INT_TC_STATUS        (*(volatile unsigned long*)(DMAC_BASE+0x004))
  29 #define DMAC_INT_TC_CLEAR         (*(volatile unsigned long*)(DMAC_BASE+0x008))
  30 #define DMAC_INT_ERROR_STATUS     (*(volatile unsigned long*)(DMAC_BASE+0x00C))
  31 #define DMAC_INT_ERR_CLEAR        (*(volatile unsigned long*)(DMAC_BASE+0x010))
  32 #define DMAC_RAW_INT_TC_STATUS    (*(volatile unsigned long*)(DMAC_BASE+0x014))
  33 #define DMAC_RAW_INT_ERROR_STATUS (*(volatile unsigned long*)(DMAC_BASE+0x018))
  34 #define DMAC_ENBLD_CHANS          (*(volatile unsigned long*)(DMAC_BASE+0x01C))
  35 #define DMAC_SOFT_B_REQ           (*(volatile unsigned long*)(DMAC_BASE+0x020))
  36 #define DMAC_SOFT_S_REQ           (*(volatile unsigned long*)(DMAC_BASE+0x024))
  37 #define DMAC_SOFT_LB_REQ          (*(volatile unsigned long*)(DMAC_BASE+0x028))
  38 #define DMAC_SOFT_LS_REQ          (*(volatile unsigned long*)(DMAC_BASE+0x02C))
  39 #define DMAC_CONFIGURATION        (*(volatile unsigned long*)(DMAC_BASE+0x030))
  40 #define DMAC_SYNC                 (*(volatile unsigned long*)(DMAC_BASE+0x034))
  41
  42 /* Channel registers (0 & 1) */
  43 #define DMAC_CH_SRC_ADDR(c)       (*(volatile unsigned long*)(DMAC_BASE+0x100+(0x20*c)))
  44 #define DMAC_CH_DST_ADDR(c)       (*(volatile unsigned long*)(DMAC_BASE+0x104+(0x20*c)))
  45 #define DMAC_CH_LLI(c)            (*(volatile unsigned long*)(DMAC_BASE+0x108+(0x20*c)))
  46 #define DMAC_CH_CONTROL(c)        (*(volatile unsigned long*)(DMAC_BASE+0x10C+(0x20*c)))
  47 #define DMAC_CH_CONFIGURATION(c)  (*(volatile unsigned long*)(DMAC_BASE+0x110+(0x20*c)))
  48
  49 /* Test registers */
  50 #define DMAC_ITCR                 (*(volatile unsigned long*)(DMAC_BASE+0x500))
  51 #define DMAC_ITOP1                (*(volatile unsigned long*)(DMAC_BASE+0x504))
  52 #define DMAC_ITOP2                (*(volatile unsigned long*)(DMAC_BASE+0x508))
  53 #define DMAC_ITOP3                (*(volatile unsigned long*)(DMAC_BASE+0x50C))
  54
  55 /* Flow controllers */
  56
  57 /* Controller is DMAC */
  58 #define DMAC_FLOWCTRL_DMAC_MEM_TO_MEM       0
  59 #define DMAC_FLOWCTRL_DMAC_MEM_TO_PERI      1
  60 #define DMAC_FLOWCTRL_DMAC_PERI_TO_MEM      2
  61 #define DMAC_FLOWCTRL_DMAC_PERI_TO_PERI     3
  62
  63 /* Controller is peripheral */
  64 #define DMAC_FLOWCTRL_SRC_PERI_PERI_TO_PERI 4
  65 #define DMAC_FLOWCTRL_PERI_MEM_TO_PERI      5
  66 #define DMAC_FLOWCTRL_PERI_PERI_TO_MEM      6
  67 #define DMAC_FLOWCTRL_DST_PERI_PERI_TO_PERI 7
  68
  69 /* Transfer request sizes */
  70 #define DMA_S1      0
  71 #define DMA_S4      1
  72 #define DMA_S8      2
  73 #define DMA_S16     3
  74 #define DMA_S32     4
  75 #define DMA_S64     5
  76 #define DMA_S128    6
  77 #define DMA_S256    7