FS#8961 - Anti-Aliased Fonts.
[kugel-rb.git] / firmware / export / jz4740.h
blob820b43f880df4d2861e017e76a468e010ded1e0b
1 /***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
10 * Copyright (C) 2008 by Maurus Cuelenaere
11 * Copyright (C) 2006-2007 by Ingenic Semiconductor Inc.
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version 2
16 * of the License, or (at your option) any later version.
18 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
19 * KIND, either express or implied.
21 ****************************************************************************/
24 * linux/include/asm-mips/mach-jz4740/jz4740.h
26 * JZ4740 common definition.
28 * Copyright (C) 2006 - 2007 Ingenic Semiconductor Inc.
30 * Author: <lhhuang@ingenic.cn>
32 * This program is free software; you can redistribute it and/or modify
33 * it under the terms of the GNU General Public License version 2 as
34 * published by the Free Software Foundation.
38 * Include file for Ingenic Semiconductor's JZ4740 CPU.
40 #ifndef __JZ4740_H__
41 #define __JZ4740_H__
43 #ifndef __ASSEMBLY__
45 #define REG8(addr) (*(volatile unsigned char *)(addr))
46 #define REG16(addr) (*(volatile unsigned short *)(addr))
47 #define REG32(addr) (*(volatile unsigned int *)(addr))
49 #endif /* !ASSEMBLY */
51 /*************************************************************************
52 * Boot ROM Specification
55 /* NOR Boot config */
56 #define JZ4740_NORBOOT_8BIT 0x00000000 /* 8-bit data bus flash */
57 #define JZ4740_NORBOOT_16BIT 0x10101010 /* 16-bit data bus flash */
58 #define JZ4740_NORBOOT_32BIT 0x20202020 /* 32-bit data bus flash */
60 /* NAND Boot config */
61 #define JZ4740_NANDBOOT_B8R3 0xffffffff /* 8-bit bus & 3 row cycles */
62 #define JZ4740_NANDBOOT_B8R2 0xf0f0f0f0 /* 8-bit bus & 2 row cycles */
63 #define JZ4740_NANDBOOT_B16R3 0x0f0f0f0f /* 16-bit bus & 3 row cycles */
64 #define JZ4740_NANDBOOT_B16R2 0x00000000 /* 16-bit bus & 2 row cycles */
67 /*************************************************************************
68 * Register Definitions
70 #define CPM_BASE 0xB0000000
71 #define INTC_BASE 0xB0001000
72 #define TCU_BASE 0xB0002000
73 #define WDT_BASE 0xB0002000
74 #define RTC_BASE 0xB0003000
75 #define GPIO_BASE 0xB0010000
76 #define AIC_BASE 0xB0020000
77 #define ICDC_BASE 0xB0020000
78 #define MSC_BASE 0xB0021000
79 #define UART0_BASE 0xB0030000
80 #define I2C_BASE 0xB0042000
81 #define SSI_BASE 0xB0043000
82 #define SADC_BASE 0xB0070000
83 #define EMC_BASE 0xB3010000
84 #define DMAC_BASE 0xB3020000
85 #define UHC_BASE 0xB3030000
86 #define UDC_BASE 0xB3040000
87 #define LCD_BASE 0xB3050000
88 #define SLCD_BASE 0xB3050000
89 #define CIM_BASE 0xB3060000
90 #define ETH_BASE 0xB3100000
93 /*************************************************************************
94 * INTC (Interrupt Controller)
95 *************************************************************************/
96 #define INTC_ISR (INTC_BASE + 0x00)
97 #define INTC_IMR (INTC_BASE + 0x04)
98 #define INTC_IMSR (INTC_BASE + 0x08)
99 #define INTC_IMCR (INTC_BASE + 0x0c)
100 #define INTC_IPR (INTC_BASE + 0x10)
102 #define REG_INTC_ISR REG32(INTC_ISR)
103 #define REG_INTC_IMR REG32(INTC_IMR)
104 #define REG_INTC_IMSR REG32(INTC_IMSR)
105 #define REG_INTC_IMCR REG32(INTC_IMCR)
106 #define REG_INTC_IPR REG32(INTC_IPR)
108 // 1st-level interrupts
109 #define IRQ_I2C 1
110 #define IRQ_EMC 2
111 #define IRQ_UHC 3
112 #define IRQ_UART0 9
113 #define IRQ_SADC 12
114 #define IRQ_MSC 14
115 #define IRQ_RTC 15
116 #define IRQ_SSI 16
117 #define IRQ_CIM 17
118 #define IRQ_AIC 18
119 #define IRQ_ETH 19
120 #define IRQ_DMAC 20
121 #define IRQ_TCU2 21
122 #define IRQ_TCU1 22
123 #define IRQ_TCU0 23
124 #define IRQ_UDC 24
125 #define IRQ_GPIO3 25
126 #define IRQ_GPIO2 26
127 #define IRQ_GPIO1 27
128 #define IRQ_GPIO0 28
129 #define IRQ_IPU 29
130 #define IRQ_LCD 30
132 // 2nd-level interrupts
133 #define IRQ_DMA_0 32 /* 32 to 37 for DMAC channel 0 to 5 */
134 #define IRQ_GPIO_0 48 /* 48 to 175 for GPIO pin 0 to 127 */
137 /*************************************************************************
138 * RTC
139 *************************************************************************/
140 #define RTC_RCR (RTC_BASE + 0x00) /* RTC Control Register */
141 #define RTC_RSR (RTC_BASE + 0x04) /* RTC Second Register */
142 #define RTC_RSAR (RTC_BASE + 0x08) /* RTC Second Alarm Register */
143 #define RTC_RGR (RTC_BASE + 0x0c) /* RTC Regulator Register */
145 #define RTC_HCR (RTC_BASE + 0x20) /* Hibernate Control Register */
146 #define RTC_HWFCR (RTC_BASE + 0x24) /* Hibernate Wakeup Filter Counter Reg */
147 #define RTC_HRCR (RTC_BASE + 0x28) /* Hibernate Reset Counter Register */
148 #define RTC_HWCR (RTC_BASE + 0x2c) /* Hibernate Wakeup Control Register */
149 #define RTC_HWRSR (RTC_BASE + 0x30) /* Hibernate Wakeup Status Register */
150 #define RTC_HSPR (RTC_BASE + 0x34) /* Hibernate Scratch Pattern Register */
152 #define REG_RTC_RCR REG32(RTC_RCR)
153 #define REG_RTC_RSR REG32(RTC_RSR)
154 #define REG_RTC_RSAR REG32(RTC_RSAR)
155 #define REG_RTC_RGR REG32(RTC_RGR)
156 #define REG_RTC_HCR REG32(RTC_HCR)
157 #define REG_RTC_HWFCR REG32(RTC_HWFCR)
158 #define REG_RTC_HRCR REG32(RTC_HRCR)
159 #define REG_RTC_HWCR REG32(RTC_HWCR)
160 #define REG_RTC_HWRSR REG32(RTC_HWRSR)
161 #define REG_RTC_HSPR REG32(RTC_HSPR)
163 /* RTC Control Register */
164 #define RTC_RCR_WRDY (1 << 7) /* Write Ready Flag */
165 #define RTC_RCR_HZ (1 << 6) /* 1Hz Flag */
166 #define RTC_RCR_HZIE (1 << 5) /* 1Hz Interrupt Enable */
167 #define RTC_RCR_AF (1 << 4) /* Alarm Flag */
168 #define RTC_RCR_AF_BIT 4 /* Alarm Flag */
169 #define RTC_RCR_AIE (1 << 3) /* Alarm Interrupt Enable */
170 #define RTC_RCR_AE (1 << 2) /* Alarm Enable */
171 #define RTC_RCR_RTCE (1 << 0) /* RTC Enable */
173 /* RTC Regulator Register */
174 #define RTC_RGR_LOCK (1 << 31) /* Lock Bit */
175 #define RTC_RGR_ADJC_BIT 16
176 #define RTC_RGR_ADJC_MASK (0x3ff << RTC_RGR_ADJC_BIT)
177 #define RTC_RGR_NC1HZ_BIT 0
178 #define RTC_RGR_NC1HZ_MASK (0xffff << RTC_RGR_NC1HZ_BIT)
180 /* Hibernate Control Register */
181 #define RTC_HCR_PD (1 << 0) /* Power Down */
183 /* Hibernate Wakeup Filter Counter Register */
184 #define RTC_HWFCR_BIT 5
185 #define RTC_HWFCR_MASK (0x7ff << RTC_HWFCR_BIT)
187 /* Hibernate Reset Counter Register */
188 #define RTC_HRCR_BIT 5
189 #define RTC_HRCR_MASK (0x7f << RTC_HRCR_BIT)
191 /* Hibernate Wakeup Control Register */
192 #define RTC_HWCR_EALM (1 << 0) /* RTC alarm wakeup enable */
194 /* Hibernate Wakeup Status Register */
195 #define RTC_HWRSR_HR (1 << 5) /* Hibernate reset */
196 #define RTC_HWRSR_PPR (1 << 4) /* PPR reset */
197 #define RTC_HWRSR_PIN (1 << 1) /* Wakeup pin status bit */
198 #define RTC_HWRSR_ALM (1 << 0) /* RTC alarm status bit */
201 /*************************************************************************
202 * CPM (Clock reset and Power control Management)
203 *************************************************************************/
204 #define CPM_CPCCR (CPM_BASE+0x00)
205 #define CPM_CPPCR (CPM_BASE+0x10)
206 #define CPM_I2SCDR (CPM_BASE+0x60)
207 #define CPM_LPCDR (CPM_BASE+0x64)
208 #define CPM_MSCCDR (CPM_BASE+0x68)
209 #define CPM_UHCCDR (CPM_BASE+0x6C)
211 #define CPM_LCR (CPM_BASE+0x04)
212 #define CPM_CLKGR (CPM_BASE+0x20)
213 #define CPM_SCR (CPM_BASE+0x24)
215 #define CPM_HCR (CPM_BASE+0x30)
216 #define CPM_HWFCR (CPM_BASE+0x34)
217 #define CPM_HRCR (CPM_BASE+0x38)
218 #define CPM_HWCR (CPM_BASE+0x3c)
219 #define CPM_HWSR (CPM_BASE+0x40)
220 #define CPM_HSPR (CPM_BASE+0x44)
222 #define CPM_RSR (CPM_BASE+0x08)
225 #define REG_CPM_CPCCR REG32(CPM_CPCCR)
226 #define REG_CPM_CPPCR REG32(CPM_CPPCR)
227 #define REG_CPM_I2SCDR REG32(CPM_I2SCDR)
228 #define REG_CPM_LPCDR REG32(CPM_LPCDR)
229 #define REG_CPM_MSCCDR REG32(CPM_MSCCDR)
230 #define REG_CPM_UHCCDR REG32(CPM_UHCCDR)
232 #define REG_CPM_LCR REG32(CPM_LCR)
233 #define REG_CPM_CLKGR REG32(CPM_CLKGR)
234 #define REG_CPM_SCR REG32(CPM_SCR)
235 #define REG_CPM_HCR REG32(CPM_HCR)
236 #define REG_CPM_HWFCR REG32(CPM_HWFCR)
237 #define REG_CPM_HRCR REG32(CPM_HRCR)
238 #define REG_CPM_HWCR REG32(CPM_HWCR)
239 #define REG_CPM_HWSR REG32(CPM_HWSR)
240 #define REG_CPM_HSPR REG32(CPM_HSPR)
242 #define REG_CPM_RSR REG32(CPM_RSR)
245 /* Clock Control Register */
246 #define CPM_CPCCR_I2CS (1 << 31)
247 #define CPM_CPCCR_CLKOEN (1 << 30)
248 #define CPM_CPCCR_UCS (1 << 29)
249 #define CPM_CPCCR_UDIV_BIT 23
250 #define CPM_CPCCR_UDIV_MASK (0x3f << CPM_CPCCR_UDIV_BIT)
251 #define CPM_CPCCR_CE (1 << 22)
252 #define CPM_CPCCR_PCS (1 << 21)
253 #define CPM_CPCCR_LDIV_BIT 16
254 #define CPM_CPCCR_LDIV_MASK (0x1f << CPM_CPCCR_LDIV_BIT)
255 #define CPM_CPCCR_MDIV_BIT 12
256 #define CPM_CPCCR_MDIV_MASK (0x0f << CPM_CPCCR_MDIV_BIT)
257 #define CPM_CPCCR_PDIV_BIT 8
258 #define CPM_CPCCR_PDIV_MASK (0x0f << CPM_CPCCR_PDIV_BIT)
259 #define CPM_CPCCR_HDIV_BIT 4
260 #define CPM_CPCCR_HDIV_MASK (0x0f << CPM_CPCCR_HDIV_BIT)
261 #define CPM_CPCCR_CDIV_BIT 0
262 #define CPM_CPCCR_CDIV_MASK (0x0f << CPM_CPCCR_CDIV_BIT)
264 /* I2S Clock Divider Register */
265 #define CPM_I2SCDR_I2SDIV_BIT 0
266 #define CPM_I2SCDR_I2SDIV_MASK (0x1ff << CPM_I2SCDR_I2SDIV_BIT)
268 /* LCD Pixel Clock Divider Register */
269 #define CPM_LPCDR_PIXDIV_BIT 0
270 #define CPM_LPCDR_PIXDIV_MASK (0x1ff << CPM_LPCDR_PIXDIV_BIT)
272 /* MSC Clock Divider Register */
273 #define CPM_MSCCDR_MSCDIV_BIT 0
274 #define CPM_MSCCDR_MSCDIV_MASK (0x1f << CPM_MSCCDR_MSCDIV_BIT)
276 /* PLL Control Register */
277 #define CPM_CPPCR_PLLM_BIT 23
278 #define CPM_CPPCR_PLLM_MASK (0x1ff << CPM_CPPCR_PLLM_BIT)
279 #define CPM_CPPCR_PLLN_BIT 18
280 #define CPM_CPPCR_PLLN_MASK (0x1f << CPM_CPPCR_PLLN_BIT)
281 #define CPM_CPPCR_PLLOD_BIT 16
282 #define CPM_CPPCR_PLLOD_MASK (0x03 << CPM_CPPCR_PLLOD_BIT)
283 #define CPM_CPPCR_PLLS (1 << 10)
284 #define CPM_CPPCR_PLLBP (1 << 9)
285 #define CPM_CPPCR_PLLEN (1 << 8)
286 #define CPM_CPPCR_PLLST_BIT 0
287 #define CPM_CPPCR_PLLST_MASK (0xff << CPM_CPPCR_PLLST_BIT)
289 /* Low Power Control Register */
290 #define CPM_LCR_DOZE_DUTY_BIT 3
291 #define CPM_LCR_DOZE_DUTY_MASK (0x1f << CPM_LCR_DOZE_DUTY_BIT)
292 #define CPM_LCR_DOZE_ON (1 << 2)
293 #define CPM_LCR_LPM_BIT 0
294 #define CPM_LCR_LPM_MASK (0x3 << CPM_LCR_LPM_BIT)
295 #define CPM_LCR_LPM_IDLE (0x0 << CPM_LCR_LPM_BIT)
296 #define CPM_LCR_LPM_SLEEP (0x1 << CPM_LCR_LPM_BIT)
298 /* Clock Gate Register */
299 #define CPM_CLKGR_UART1 (1 << 15)
300 #define CPM_CLKGR_UHC (1 << 14)
301 #define CPM_CLKGR_IPU (1 << 13)
302 #define CPM_CLKGR_DMAC (1 << 12)
303 #define CPM_CLKGR_UDC (1 << 11)
304 #define CPM_CLKGR_LCD (1 << 10)
305 #define CPM_CLKGR_CIM (1 << 9)
306 #define CPM_CLKGR_SADC (1 << 8)
307 #define CPM_CLKGR_MSC (1 << 7)
308 #define CPM_CLKGR_AIC1 (1 << 6)
309 #define CPM_CLKGR_AIC2 (1 << 5)
310 #define CPM_CLKGR_SSI (1 << 4)
311 #define CPM_CLKGR_I2C (1 << 3)
312 #define CPM_CLKGR_RTC (1 << 2)
313 #define CPM_CLKGR_TCU (1 << 1)
314 #define CPM_CLKGR_UART0 (1 << 0)
316 /* Sleep Control Register */
317 #define CPM_SCR_O1ST_BIT 8
318 #define CPM_SCR_O1ST_MASK (0xff << CPM_SCR_O1ST_BIT)
319 #define CPM_SCR_USBHOST_SUSPEND (1 << 7)
320 #define CPM_SCR_USBPHY_ENABLE (1 << 6)
321 #define CPM_SCR_OSC_ENABLE (1 << 4)
323 /* Hibernate Control Register */
324 #define CPM_HCR_PD (1 << 0)
326 /* Wakeup Filter Counter Register in Hibernate Mode */
327 #define CPM_HWFCR_TIME_BIT 0
328 #define CPM_HWFCR_TIME_MASK (0x3ff << CPM_HWFCR_TIME_BIT)
330 /* Reset Counter Register in Hibernate Mode */
331 #define CPM_HRCR_TIME_BIT 0
332 #define CPM_HRCR_TIME_MASK (0x7f << CPM_HRCR_TIME_BIT)
334 /* Wakeup Control Register in Hibernate Mode */
335 #define CPM_HWCR_WLE_LOW (0 << 2)
336 #define CPM_HWCR_WLE_HIGH (1 << 2)
337 #define CPM_HWCR_PIN_WAKEUP (1 << 1)
338 #define CPM_HWCR_RTC_WAKEUP (1 << 0)
340 /* Wakeup Status Register in Hibernate Mode */
341 #define CPM_HWSR_WSR_PIN (1 << 1)
342 #define CPM_HWSR_WSR_RTC (1 << 0)
344 /* Reset Status Register */
345 #define CPM_RSR_HR (1 << 2)
346 #define CPM_RSR_WR (1 << 1)
347 #define CPM_RSR_PR (1 << 0)
350 /*************************************************************************
351 * TCU (Timer Counter Unit)
352 *************************************************************************/
353 #define TCU_TSR (TCU_BASE + 0x1C) /* Timer Stop Register */
354 #define TCU_TSSR (TCU_BASE + 0x2C) /* Timer Stop Set Register */
355 #define TCU_TSCR (TCU_BASE + 0x3C) /* Timer Stop Clear Register */
356 #define TCU_TER (TCU_BASE + 0x10) /* Timer Counter Enable Register */
357 #define TCU_TESR (TCU_BASE + 0x14) /* Timer Counter Enable Set Register */
358 #define TCU_TECR (TCU_BASE + 0x18) /* Timer Counter Enable Clear Register */
359 #define TCU_TFR (TCU_BASE + 0x20) /* Timer Flag Register */
360 #define TCU_TFSR (TCU_BASE + 0x24) /* Timer Flag Set Register */
361 #define TCU_TFCR (TCU_BASE + 0x28) /* Timer Flag Clear Register */
362 #define TCU_TMR (TCU_BASE + 0x30) /* Timer Mask Register */
363 #define TCU_TMSR (TCU_BASE + 0x34) /* Timer Mask Set Register */
364 #define TCU_TMCR (TCU_BASE + 0x38) /* Timer Mask Clear Register */
365 #define TCU_TDFR0 (TCU_BASE + 0x40) /* Timer Data Full Register */
366 #define TCU_TDHR0 (TCU_BASE + 0x44) /* Timer Data Half Register */
367 #define TCU_TCNT0 (TCU_BASE + 0x48) /* Timer Counter Register */
368 #define TCU_TCSR0 (TCU_BASE + 0x4C) /* Timer Control Register */
369 #define TCU_TDFR1 (TCU_BASE + 0x50)
370 #define TCU_TDHR1 (TCU_BASE + 0x54)
371 #define TCU_TCNT1 (TCU_BASE + 0x58)
372 #define TCU_TCSR1 (TCU_BASE + 0x5C)
373 #define TCU_TDFR2 (TCU_BASE + 0x60)
374 #define TCU_TDHR2 (TCU_BASE + 0x64)
375 #define TCU_TCNT2 (TCU_BASE + 0x68)
376 #define TCU_TCSR2 (TCU_BASE + 0x6C)
377 #define TCU_TDFR3 (TCU_BASE + 0x70)
378 #define TCU_TDHR3 (TCU_BASE + 0x74)
379 #define TCU_TCNT3 (TCU_BASE + 0x78)
380 #define TCU_TCSR3 (TCU_BASE + 0x7C)
381 #define TCU_TDFR4 (TCU_BASE + 0x80)
382 #define TCU_TDHR4 (TCU_BASE + 0x84)
383 #define TCU_TCNT4 (TCU_BASE + 0x88)
384 #define TCU_TCSR4 (TCU_BASE + 0x8C)
385 #define TCU_TDFR5 (TCU_BASE + 0x90)
386 #define TCU_TDHR5 (TCU_BASE + 0x94)
387 #define TCU_TCNT5 (TCU_BASE + 0x98)
388 #define TCU_TCSR5 (TCU_BASE + 0x9C)
390 #define REG_TCU_TSR REG32(TCU_TSR)
391 #define REG_TCU_TSSR REG32(TCU_TSSR)
392 #define REG_TCU_TSCR REG32(TCU_TSCR)
393 #define REG_TCU_TER REG8(TCU_TER)
394 #define REG_TCU_TESR REG8(TCU_TESR)
395 #define REG_TCU_TECR REG8(TCU_TECR)
396 #define REG_TCU_TFR REG32(TCU_TFR)
397 #define REG_TCU_TFSR REG32(TCU_TFSR)
398 #define REG_TCU_TFCR REG32(TCU_TFCR)
399 #define REG_TCU_TMR REG32(TCU_TMR)
400 #define REG_TCU_TMSR REG32(TCU_TMSR)
401 #define REG_TCU_TMCR REG32(TCU_TMCR)
402 #define REG_TCU_TDFR0 REG16(TCU_TDFR0)
403 #define REG_TCU_TDHR0 REG16(TCU_TDHR0)
404 #define REG_TCU_TCNT0 REG16(TCU_TCNT0)
405 #define REG_TCU_TCSR0 REG16(TCU_TCSR0)
406 #define REG_TCU_TDFR1 REG16(TCU_TDFR1)
407 #define REG_TCU_TDHR1 REG16(TCU_TDHR1)
408 #define REG_TCU_TCNT1 REG16(TCU_TCNT1)
409 #define REG_TCU_TCSR1 REG16(TCU_TCSR1)
410 #define REG_TCU_TDFR2 REG16(TCU_TDFR2)
411 #define REG_TCU_TDHR2 REG16(TCU_TDHR2)
412 #define REG_TCU_TCNT2 REG16(TCU_TCNT2)
413 #define REG_TCU_TCSR2 REG16(TCU_TCSR2)
414 #define REG_TCU_TDFR3 REG16(TCU_TDFR3)
415 #define REG_TCU_TDHR3 REG16(TCU_TDHR3)
416 #define REG_TCU_TCNT3 REG16(TCU_TCNT3)
417 #define REG_TCU_TCSR3 REG16(TCU_TCSR3)
418 #define REG_TCU_TDFR4 REG16(TCU_TDFR4)
419 #define REG_TCU_TDHR4 REG16(TCU_TDHR4)
420 #define REG_TCU_TCNT4 REG16(TCU_TCNT4)
421 #define REG_TCU_TCSR4 REG16(TCU_TCSR4)
423 // n = 0,1,2,3,4,5,6,7
424 #define TCU_TDFR(n) (TCU_BASE + (0x40 + (n)*0x10)) /* Timer Data Full Reg */
425 #define TCU_TDHR(n) (TCU_BASE + (0x44 + (n)*0x10)) /* Timer Data Half Reg */
426 #define TCU_TCNT(n) (TCU_BASE + (0x48 + (n)*0x10)) /* Timer Counter Reg */
427 #define TCU_TCSR(n) (TCU_BASE + (0x4C + (n)*0x10)) /* Timer Control Reg */
429 #define REG_TCU_TDFR(n) REG16(TCU_TDFR((n)))
430 #define REG_TCU_TDHR(n) REG16(TCU_TDHR((n)))
431 #define REG_TCU_TCNT(n) REG16(TCU_TCNT((n)))
432 #define REG_TCU_TCSR(n) REG16(TCU_TCSR((n)))
434 // Register definitions
435 #define TCU_TCSR_PWM_SD (1 << 9)
436 #define TCU_TCSR_PWM_INITL_HIGH (1 << 8)
437 #define TCU_TCSR_PWM_EN (1 << 7)
438 #define TCU_TCSR_PRESCALE_BIT 3
439 #define TCU_TCSR_PRESCALE_MASK (0x7 << TCU_TCSR_PRESCALE_BIT)
440 #define TCU_TCSR_PRESCALE1 (0x0 << TCU_TCSR_PRESCALE_BIT)
441 #define TCU_TCSR_PRESCALE4 (0x1 << TCU_TCSR_PRESCALE_BIT)
442 #define TCU_TCSR_PRESCALE16 (0x2 << TCU_TCSR_PRESCALE_BIT)
443 #define TCU_TCSR_PRESCALE64 (0x3 << TCU_TCSR_PRESCALE_BIT)
444 #define TCU_TCSR_PRESCALE256 (0x4 << TCU_TCSR_PRESCALE_BIT)
445 #define TCU_TCSR_PRESCALE1024 (0x5 << TCU_TCSR_PRESCALE_BIT)
446 #define TCU_TCSR_EXT_EN (1 << 2)
447 #define TCU_TCSR_RTC_EN (1 << 1)
448 #define TCU_TCSR_PCK_EN (1 << 0)
450 #define TCU_TER_TCEN5 (1 << 5)
451 #define TCU_TER_TCEN4 (1 << 4)
452 #define TCU_TER_TCEN3 (1 << 3)
453 #define TCU_TER_TCEN2 (1 << 2)
454 #define TCU_TER_TCEN1 (1 << 1)
455 #define TCU_TER_TCEN0 (1 << 0)
457 #define TCU_TESR_TCST5 (1 << 5)
458 #define TCU_TESR_TCST4 (1 << 4)
459 #define TCU_TESR_TCST3 (1 << 3)
460 #define TCU_TESR_TCST2 (1 << 2)
461 #define TCU_TESR_TCST1 (1 << 1)
462 #define TCU_TESR_TCST0 (1 << 0)
464 #define TCU_TECR_TCCL5 (1 << 5)
465 #define TCU_TECR_TCCL4 (1 << 4)
466 #define TCU_TECR_TCCL3 (1 << 3)
467 #define TCU_TECR_TCCL2 (1 << 2)
468 #define TCU_TECR_TCCL1 (1 << 1)
469 #define TCU_TECR_TCCL0 (1 << 0)
471 #define TCU_TFR_HFLAG5 (1 << 21)
472 #define TCU_TFR_HFLAG4 (1 << 20)
473 #define TCU_TFR_HFLAG3 (1 << 19)
474 #define TCU_TFR_HFLAG2 (1 << 18)
475 #define TCU_TFR_HFLAG1 (1 << 17)
476 #define TCU_TFR_HFLAG0 (1 << 16)
477 #define TCU_TFR_FFLAG5 (1 << 5)
478 #define TCU_TFR_FFLAG4 (1 << 4)
479 #define TCU_TFR_FFLAG3 (1 << 3)
480 #define TCU_TFR_FFLAG2 (1 << 2)
481 #define TCU_TFR_FFLAG1 (1 << 1)
482 #define TCU_TFR_FFLAG0 (1 << 0)
484 #define TCU_TFSR_HFLAG5 (1 << 21)
485 #define TCU_TFSR_HFLAG4 (1 << 20)
486 #define TCU_TFSR_HFLAG3 (1 << 19)
487 #define TCU_TFSR_HFLAG2 (1 << 18)
488 #define TCU_TFSR_HFLAG1 (1 << 17)
489 #define TCU_TFSR_HFLAG0 (1 << 16)
490 #define TCU_TFSR_FFLAG5 (1 << 5)
491 #define TCU_TFSR_FFLAG4 (1 << 4)
492 #define TCU_TFSR_FFLAG3 (1 << 3)
493 #define TCU_TFSR_FFLAG2 (1 << 2)
494 #define TCU_TFSR_FFLAG1 (1 << 1)
495 #define TCU_TFSR_FFLAG0 (1 << 0)
497 #define TCU_TFCR_HFLAG5 (1 << 21)
498 #define TCU_TFCR_HFLAG4 (1 << 20)
499 #define TCU_TFCR_HFLAG3 (1 << 19)
500 #define TCU_TFCR_HFLAG2 (1 << 18)
501 #define TCU_TFCR_HFLAG1 (1 << 17)
502 #define TCU_TFCR_HFLAG0 (1 << 16)
503 #define TCU_TFCR_FFLAG5 (1 << 5)
504 #define TCU_TFCR_FFLAG4 (1 << 4)
505 #define TCU_TFCR_FFLAG3 (1 << 3)
506 #define TCU_TFCR_FFLAG2 (1 << 2)
507 #define TCU_TFCR_FFLAG1 (1 << 1)
508 #define TCU_TFCR_FFLAG0 (1 << 0)
510 #define TCU_TMR_HMASK5 (1 << 21)
511 #define TCU_TMR_HMASK4 (1 << 20)
512 #define TCU_TMR_HMASK3 (1 << 19)
513 #define TCU_TMR_HMASK2 (1 << 18)
514 #define TCU_TMR_HMASK1 (1 << 17)
515 #define TCU_TMR_HMASK0 (1 << 16)
516 #define TCU_TMR_FMASK5 (1 << 5)
517 #define TCU_TMR_FMASK4 (1 << 4)
518 #define TCU_TMR_FMASK3 (1 << 3)
519 #define TCU_TMR_FMASK2 (1 << 2)
520 #define TCU_TMR_FMASK1 (1 << 1)
521 #define TCU_TMR_FMASK0 (1 << 0)
523 #define TCU_TMSR_HMST5 (1 << 21)
524 #define TCU_TMSR_HMST4 (1 << 20)
525 #define TCU_TMSR_HMST3 (1 << 19)
526 #define TCU_TMSR_HMST2 (1 << 18)
527 #define TCU_TMSR_HMST1 (1 << 17)
528 #define TCU_TMSR_HMST0 (1 << 16)
529 #define TCU_TMSR_FMST5 (1 << 5)
530 #define TCU_TMSR_FMST4 (1 << 4)
531 #define TCU_TMSR_FMST3 (1 << 3)
532 #define TCU_TMSR_FMST2 (1 << 2)
533 #define TCU_TMSR_FMST1 (1 << 1)
534 #define TCU_TMSR_FMST0 (1 << 0)
536 #define TCU_TMCR_HMCL5 (1 << 21)
537 #define TCU_TMCR_HMCL4 (1 << 20)
538 #define TCU_TMCR_HMCL3 (1 << 19)
539 #define TCU_TMCR_HMCL2 (1 << 18)
540 #define TCU_TMCR_HMCL1 (1 << 17)
541 #define TCU_TMCR_HMCL0 (1 << 16)
542 #define TCU_TMCR_FMCL5 (1 << 5)
543 #define TCU_TMCR_FMCL4 (1 << 4)
544 #define TCU_TMCR_FMCL3 (1 << 3)
545 #define TCU_TMCR_FMCL2 (1 << 2)
546 #define TCU_TMCR_FMCL1 (1 << 1)
547 #define TCU_TMCR_FMCL0 (1 << 0)
549 #define TCU_TSR_WDTS (1 << 16)
550 #define TCU_TSR_STOP5 (1 << 5)
551 #define TCU_TSR_STOP4 (1 << 4)
552 #define TCU_TSR_STOP3 (1 << 3)
553 #define TCU_TSR_STOP2 (1 << 2)
554 #define TCU_TSR_STOP1 (1 << 1)
555 #define TCU_TSR_STOP0 (1 << 0)
557 #define TCU_TSSR_WDTSS (1 << 16)
558 #define TCU_TSSR_STPS5 (1 << 5)
559 #define TCU_TSSR_STPS4 (1 << 4)
560 #define TCU_TSSR_STPS3 (1 << 3)
561 #define TCU_TSSR_STPS2 (1 << 2)
562 #define TCU_TSSR_STPS1 (1 << 1)
563 #define TCU_TSSR_STPS0 (1 << 0)
565 #define TCU_TSSR_WDTSC (1 << 16)
566 #define TCU_TSSR_STPC5 (1 << 5)
567 #define TCU_TSSR_STPC4 (1 << 4)
568 #define TCU_TSSR_STPC3 (1 << 3)
569 #define TCU_TSSR_STPC2 (1 << 2)
570 #define TCU_TSSR_STPC1 (1 << 1)
571 #define TCU_TSSR_STPC0 (1 << 0)
574 /*************************************************************************
575 * WDT (WatchDog Timer)
576 *************************************************************************/
577 #define WDT_TDR (WDT_BASE + 0x00)
578 #define WDT_TCER (WDT_BASE + 0x04)
579 #define WDT_TCNT (WDT_BASE + 0x08)
580 #define WDT_TCSR (WDT_BASE + 0x0C)
582 #define REG_WDT_TDR REG16(WDT_TDR)
583 #define REG_WDT_TCER REG8(WDT_TCER)
584 #define REG_WDT_TCNT REG16(WDT_TCNT)
585 #define REG_WDT_TCSR REG16(WDT_TCSR)
587 // Register definition
588 #define WDT_TCSR_PRESCALE_BIT 3
589 #define WDT_TCSR_PRESCALE_MASK (0x7 << WDT_TCSR_PRESCALE_BIT)
590 #define WDT_TCSR_PRESCALE1 (0x0 << WDT_TCSR_PRESCALE_BIT)
591 #define WDT_TCSR_PRESCALE4 (0x1 << WDT_TCSR_PRESCALE_BIT)
592 #define WDT_TCSR_PRESCALE16 (0x2 << WDT_TCSR_PRESCALE_BIT)
593 #define WDT_TCSR_PRESCALE64 (0x3 << WDT_TCSR_PRESCALE_BIT)
594 #define WDT_TCSR_PRESCALE256 (0x4 << WDT_TCSR_PRESCALE_BIT)
595 #define WDT_TCSR_PRESCALE1024 (0x5 << WDT_TCSR_PRESCALE_BIT)
596 #define WDT_TCSR_EXT_EN (1 << 2)
597 #define WDT_TCSR_RTC_EN (1 << 1)
598 #define WDT_TCSR_PCK_EN (1 << 0)
600 #define WDT_TCER_TCEN (1 << 0)
603 /*************************************************************************
604 * DMAC (DMA Controller)
605 *************************************************************************/
607 #define MAX_DMA_NUM 6 /* max 6 channels */
609 #define DMAC_DSAR(n) (DMAC_BASE + (0x00 + (n) * 0x20)) /* DMA source address */
610 #define DMAC_DTAR(n) (DMAC_BASE + (0x04 + (n) * 0x20)) /* DMA target address */
611 #define DMAC_DTCR(n) (DMAC_BASE + (0x08 + (n) * 0x20)) /* DMA transfer count */
612 #define DMAC_DRSR(n) (DMAC_BASE + (0x0c + (n) * 0x20)) /* DMA request source */
613 #define DMAC_DCCSR(n) (DMAC_BASE + (0x10 + (n) * 0x20)) /* DMA control/status */
614 #define DMAC_DCMD(n) (DMAC_BASE + (0x14 + (n) * 0x20)) /* DMA command */
615 #define DMAC_DDA(n) (DMAC_BASE + (0x18 + (n) * 0x20)) /* DMA descriptor address */
616 #define DMAC_DMACR (DMAC_BASE + 0x0300) /* DMA control register */
617 #define DMAC_DMAIPR (DMAC_BASE + 0x0304) /* DMA interrupt pending */
618 #define DMAC_DMADBR (DMAC_BASE + 0x0308) /* DMA doorbell */
619 #define DMAC_DMADBSR (DMAC_BASE + 0x030C) /* DMA doorbell set */
621 // channel 0
622 #define DMAC_DSAR0 DMAC_DSAR(0)
623 #define DMAC_DTAR0 DMAC_DTAR(0)
624 #define DMAC_DTCR0 DMAC_DTCR(0)
625 #define DMAC_DRSR0 DMAC_DRSR(0)
626 #define DMAC_DCCSR0 DMAC_DCCSR(0)
627 #define DMAC_DCMD0 DMAC_DCMD(0)
628 #define DMAC_DDA0 DMAC_DDA(0)
630 // channel 1
631 #define DMAC_DSAR1 DMAC_DSAR(1)
632 #define DMAC_DTAR1 DMAC_DTAR(1)
633 #define DMAC_DTCR1 DMAC_DTCR(1)
634 #define DMAC_DRSR1 DMAC_DRSR(1)
635 #define DMAC_DCCSR1 DMAC_DCCSR(1)
636 #define DMAC_DCMD1 DMAC_DCMD(1)
637 #define DMAC_DDA1 DMAC_DDA(1)
639 // channel 2
640 #define DMAC_DSAR2 DMAC_DSAR(2)
641 #define DMAC_DTAR2 DMAC_DTAR(2)
642 #define DMAC_DTCR2 DMAC_DTCR(2)
643 #define DMAC_DRSR2 DMAC_DRSR(2)
644 #define DMAC_DCCSR2 DMAC_DCCSR(2)
645 #define DMAC_DCMD2 DMAC_DCMD(2)
646 #define DMAC_DDA2 DMAC_DDA(2)
648 // channel 3
649 #define DMAC_DSAR3 DMAC_DSAR(3)
650 #define DMAC_DTAR3 DMAC_DTAR(3)
651 #define DMAC_DTCR3 DMAC_DTCR(3)
652 #define DMAC_DRSR3 DMAC_DRSR(3)
653 #define DMAC_DCCSR3 DMAC_DCCSR(3)
654 #define DMAC_DCMD3 DMAC_DCMD(3)
655 #define DMAC_DDA3 DMAC_DDA(3)
657 // channel 4
658 #define DMAC_DSAR4 DMAC_DSAR(4)
659 #define DMAC_DTAR4 DMAC_DTAR(4)
660 #define DMAC_DTCR4 DMAC_DTCR(4)
661 #define DMAC_DRSR4 DMAC_DRSR(4)
662 #define DMAC_DCCSR4 DMAC_DCCSR(4)
663 #define DMAC_DCMD4 DMAC_DCMD(4)
664 #define DMAC_DDA4 DMAC_DDA(4)
666 // channel 5
667 #define DMAC_DSAR5 DMAC_DSAR(5)
668 #define DMAC_DTAR5 DMAC_DTAR(5)
669 #define DMAC_DTCR5 DMAC_DTCR(5)
670 #define DMAC_DRSR5 DMAC_DRSR(5)
671 #define DMAC_DCCSR5 DMAC_DCCSR(5)
672 #define DMAC_DCMD5 DMAC_DCMD(5)
673 #define DMAC_DDA5 DMAC_DDA(5)
675 #define REG_DMAC_DSAR(n) REG32(DMAC_DSAR((n)))
676 #define REG_DMAC_DTAR(n) REG32(DMAC_DTAR((n)))
677 #define REG_DMAC_DTCR(n) REG32(DMAC_DTCR((n)))
678 #define REG_DMAC_DRSR(n) REG32(DMAC_DRSR((n)))
679 #define REG_DMAC_DCCSR(n) REG32(DMAC_DCCSR((n)))
680 #define REG_DMAC_DCMD(n) REG32(DMAC_DCMD((n)))
681 #define REG_DMAC_DDA(n) REG32(DMAC_DDA((n)))
682 #define REG_DMAC_DMACR REG32(DMAC_DMACR)
683 #define REG_DMAC_DMAIPR REG32(DMAC_DMAIPR)
684 #define REG_DMAC_DMADBR REG32(DMAC_DMADBR)
685 #define REG_DMAC_DMADBSR REG32(DMAC_DMADBSR)
687 // DMA request source register
688 #define DMAC_DRSR_RS_BIT 0
689 #define DMAC_DRSR_RS_MASK (0x1f << DMAC_DRSR_RS_BIT)
690 #define DMAC_DRSR_RS_AUTO (8 << DMAC_DRSR_RS_BIT)
691 #define DMAC_DRSR_RS_UART0OUT (20 << DMAC_DRSR_RS_BIT)
692 #define DMAC_DRSR_RS_UART0IN (21 << DMAC_DRSR_RS_BIT)
693 #define DMAC_DRSR_RS_SSIOUT (22 << DMAC_DRSR_RS_BIT)
694 #define DMAC_DRSR_RS_SSIIN (23 << DMAC_DRSR_RS_BIT)
695 #define DMAC_DRSR_RS_AICOUT (24 << DMAC_DRSR_RS_BIT)
696 #define DMAC_DRSR_RS_AICIN (25 << DMAC_DRSR_RS_BIT)
697 #define DMAC_DRSR_RS_MSCOUT (26 << DMAC_DRSR_RS_BIT)
698 #define DMAC_DRSR_RS_MSCIN (27 << DMAC_DRSR_RS_BIT)
699 #define DMAC_DRSR_RS_TCU (28 << DMAC_DRSR_RS_BIT)
700 #define DMAC_DRSR_RS_SADC (29 << DMAC_DRSR_RS_BIT)
701 #define DMAC_DRSR_RS_SLCD (30 << DMAC_DRSR_RS_BIT)
703 // DMA channel control/status register
704 #define DMAC_DCCSR_NDES (1 << 31) /* descriptor (0) or not (1) ? */
705 #define DMAC_DCCSR_CDOA_BIT 16 /* copy of DMA offset address */
706 #define DMAC_DCCSR_CDOA_MASK (0xff << DMAC_DCCSR_CDOA_BIT)
707 #define DMAC_DCCSR_INV (1 << 6) /* descriptor invalid */
708 #define DMAC_DCCSR_AR (1 << 4) /* address error */
709 #define DMAC_DCCSR_TT (1 << 3) /* transfer terminated */
710 #define DMAC_DCCSR_HLT (1 << 2) /* DMA halted */
711 #define DMAC_DCCSR_CT (1 << 1) /* count terminated */
712 #define DMAC_DCCSR_EN (1 << 0) /* channel enable bit */
714 // DMA channel command register
715 #define DMAC_DCMD_SAI (1 << 23) /* source address increment */
716 #define DMAC_DCMD_DAI (1 << 22) /* dest address increment */
717 #define DMAC_DCMD_RDIL_BIT 16 /* request detection interval length */
718 #define DMAC_DCMD_RDIL_MASK (0x0f << DMAC_DCMD_RDIL_BIT)
719 #define DMAC_DCMD_RDIL_IGN (0 << DMAC_DCMD_RDIL_BIT)
720 #define DMAC_DCMD_RDIL_2 (1 << DMAC_DCMD_RDIL_BIT)
721 #define DMAC_DCMD_RDIL_4 (2 << DMAC_DCMD_RDIL_BIT)
722 #define DMAC_DCMD_RDIL_8 (3 << DMAC_DCMD_RDIL_BIT)
723 #define DMAC_DCMD_RDIL_12 (4 << DMAC_DCMD_RDIL_BIT)
724 #define DMAC_DCMD_RDIL_16 (5 << DMAC_DCMD_RDIL_BIT)
725 #define DMAC_DCMD_RDIL_20 (6 << DMAC_DCMD_RDIL_BIT)
726 #define DMAC_DCMD_RDIL_24 (7 << DMAC_DCMD_RDIL_BIT)
727 #define DMAC_DCMD_RDIL_28 (8 << DMAC_DCMD_RDIL_BIT)
728 #define DMAC_DCMD_RDIL_32 (9 << DMAC_DCMD_RDIL_BIT)
729 #define DMAC_DCMD_RDIL_48 (10 << DMAC_DCMD_RDIL_BIT)
730 #define DMAC_DCMD_RDIL_60 (11 << DMAC_DCMD_RDIL_BIT)
731 #define DMAC_DCMD_RDIL_64 (12 << DMAC_DCMD_RDIL_BIT)
732 #define DMAC_DCMD_RDIL_124 (13 << DMAC_DCMD_RDIL_BIT)
733 #define DMAC_DCMD_RDIL_128 (14 << DMAC_DCMD_RDIL_BIT)
734 #define DMAC_DCMD_RDIL_200 (15 << DMAC_DCMD_RDIL_BIT)
735 #define DMAC_DCMD_SWDH_BIT 14 /* source port width */
736 #define DMAC_DCMD_SWDH_MASK (0x03 << DMAC_DCMD_SWDH_BIT)
737 #define DMAC_DCMD_SWDH_32 (0 << DMAC_DCMD_SWDH_BIT)
738 #define DMAC_DCMD_SWDH_8 (1 << DMAC_DCMD_SWDH_BIT)
739 #define DMAC_DCMD_SWDH_16 (2 << DMAC_DCMD_SWDH_BIT)
740 #define DMAC_DCMD_DWDH_BIT 12 /* dest port width */
741 #define DMAC_DCMD_DWDH_MASK (0x03 << DMAC_DCMD_DWDH_BIT)
742 #define DMAC_DCMD_DWDH_32 (0 << DMAC_DCMD_DWDH_BIT)
743 #define DMAC_DCMD_DWDH_8 (1 << DMAC_DCMD_DWDH_BIT)
744 #define DMAC_DCMD_DWDH_16 (2 << DMAC_DCMD_DWDH_BIT)
745 #define DMAC_DCMD_DS_BIT 8 /* transfer data size of a data unit */
746 #define DMAC_DCMD_DS_MASK (0x07 << DMAC_DCMD_DS_BIT)
747 #define DMAC_DCMD_DS_32BIT (0 << DMAC_DCMD_DS_BIT)
748 #define DMAC_DCMD_DS_8BIT (1 << DMAC_DCMD_DS_BIT)
749 #define DMAC_DCMD_DS_16BIT (2 << DMAC_DCMD_DS_BIT)
750 #define DMAC_DCMD_DS_16BYTE (3 << DMAC_DCMD_DS_BIT)
751 #define DMAC_DCMD_DS_32BYTE (4 << DMAC_DCMD_DS_BIT)
752 #define DMAC_DCMD_TM (1 << 7) /* transfer mode: 0-single 1-block */
753 #define DMAC_DCMD_DES_V (1 << 4) /* descriptor valid flag */
754 #define DMAC_DCMD_DES_VM (1 << 3) /* descriptor valid mask: 1:support V-bit */
755 #define DMAC_DCMD_DES_VIE (1 << 2) /* DMA valid error interrupt enable */
756 #define DMAC_DCMD_TIE (1 << 1) /* DMA transfer interrupt enable */
757 #define DMAC_DCMD_LINK (1 << 0) /* descriptor link enable */
759 // DMA descriptor address register
760 #define DMAC_DDA_BASE_BIT 12 /* descriptor base address */
761 #define DMAC_DDA_BASE_MASK (0x0fffff << DMAC_DDA_BASE_BIT)
762 #define DMAC_DDA_OFFSET_BIT 4 /* descriptor offset address */
763 #define DMAC_DDA_OFFSET_MASK (0x0ff << DMAC_DDA_OFFSET_BIT)
765 // DMA control register
766 #define DMAC_DMACR_PR_BIT 8 /* channel priority mode */
767 #define DMAC_DMACR_PR_MASK (0x03 << DMAC_DMACR_PR_BIT)
768 #define DMAC_DMACR_PR_012345 (0 << DMAC_DMACR_PR_BIT)
769 #define DMAC_DMACR_PR_023145 (1 << DMAC_DMACR_PR_BIT)
770 #define DMAC_DMACR_PR_201345 (2 << DMAC_DMACR_PR_BIT)
771 #define DMAC_DMACR_PR_RR (3 << DMAC_DMACR_PR_BIT) /* round robin */
772 #define DMAC_DMACR_HLT (1 << 3) /* DMA halt flag */
773 #define DMAC_DMACR_AR (1 << 2) /* address error flag */
774 #define DMAC_DMACR_DMAE (1 << 0) /* DMA enable bit */
776 // DMA doorbell register
777 #define DMAC_DMADBR_DB5 (1 << 5) /* doorbell for channel 5 */
778 #define DMAC_DMADBR_DB4 (1 << 5) /* doorbell for channel 4 */
779 #define DMAC_DMADBR_DB3 (1 << 5) /* doorbell for channel 3 */
780 #define DMAC_DMADBR_DB2 (1 << 5) /* doorbell for channel 2 */
781 #define DMAC_DMADBR_DB1 (1 << 5) /* doorbell for channel 1 */
782 #define DMAC_DMADBR_DB0 (1 << 5) /* doorbell for channel 0 */
784 // DMA doorbell set register
785 #define DMAC_DMADBSR_DBS5 (1 << 5) /* enable doorbell for channel 5 */
786 #define DMAC_DMADBSR_DBS4 (1 << 5) /* enable doorbell for channel 4 */
787 #define DMAC_DMADBSR_DBS3 (1 << 5) /* enable doorbell for channel 3 */
788 #define DMAC_DMADBSR_DBS2 (1 << 5) /* enable doorbell for channel 2 */
789 #define DMAC_DMADBSR_DBS1 (1 << 5) /* enable doorbell for channel 1 */
790 #define DMAC_DMADBSR_DBS0 (1 << 5) /* enable doorbell for channel 0 */
792 // DMA interrupt pending register
793 #define DMAC_DMAIPR_CIRQ5 (1 << 5) /* irq pending status for channel 5 */
794 #define DMAC_DMAIPR_CIRQ4 (1 << 4) /* irq pending status for channel 4 */
795 #define DMAC_DMAIPR_CIRQ3 (1 << 3) /* irq pending status for channel 3 */
796 #define DMAC_DMAIPR_CIRQ2 (1 << 2) /* irq pending status for channel 2 */
797 #define DMAC_DMAIPR_CIRQ1 (1 << 1) /* irq pending status for channel 1 */
798 #define DMAC_DMAIPR_CIRQ0 (1 << 0) /* irq pending status for channel 0 */
801 /*************************************************************************
802 * GPIO (General-Purpose I/O Ports)
803 *************************************************************************/
804 #define MAX_GPIO_NUM 128
806 //n = 0,1,2,3
807 #define GPIO_PXPIN(n) (GPIO_BASE + (0x00 + (n)*0x100)) /* PIN Level Register */
808 #define GPIO_PXDAT(n) (GPIO_BASE + (0x10 + (n)*0x100)) /* Port Data Register */
809 #define GPIO_PXDATS(n) (GPIO_BASE + (0x14 + (n)*0x100)) /* Port Data Set Register */
810 #define GPIO_PXDATC(n) (GPIO_BASE + (0x18 + (n)*0x100)) /* Port Data Clear Register */
811 #define GPIO_PXIM(n) (GPIO_BASE + (0x20 + (n)*0x100)) /* Interrupt Mask Register */
812 #define GPIO_PXIMS(n) (GPIO_BASE + (0x24 + (n)*0x100)) /* Interrupt Mask Set Reg */
813 #define GPIO_PXIMC(n) (GPIO_BASE + (0x28 + (n)*0x100)) /* Interrupt Mask Clear Reg */
814 #define GPIO_PXPE(n) (GPIO_BASE + (0x30 + (n)*0x100)) /* Pull Enable Register */
815 #define GPIO_PXPES(n) (GPIO_BASE + (0x34 + (n)*0x100)) /* Pull Enable Set Reg. */
816 #define GPIO_PXPEC(n) (GPIO_BASE + (0x38 + (n)*0x100)) /* Pull Enable Clear Reg. */
817 #define GPIO_PXFUN(n) (GPIO_BASE + (0x40 + (n)*0x100)) /* Function Register */
818 #define GPIO_PXFUNS(n) (GPIO_BASE + (0x44 + (n)*0x100)) /* Function Set Register */
819 #define GPIO_PXFUNC(n) (GPIO_BASE + (0x48 + (n)*0x100)) /* Function Clear Register */
820 #define GPIO_PXSEL(n) (GPIO_BASE + (0x50 + (n)*0x100)) /* Select Register */
821 #define GPIO_PXSELS(n) (GPIO_BASE + (0x54 + (n)*0x100)) /* Select Set Register */
822 #define GPIO_PXSELC(n) (GPIO_BASE + (0x58 + (n)*0x100)) /* Select Clear Register */
823 #define GPIO_PXDIR(n) (GPIO_BASE + (0x60 + (n)*0x100)) /* Direction Register */
824 #define GPIO_PXDIRS(n) (GPIO_BASE + (0x64 + (n)*0x100)) /* Direction Set Register */
825 #define GPIO_PXDIRC(n) (GPIO_BASE + (0x68 + (n)*0x100)) /* Direction Clear Register */
826 #define GPIO_PXTRG(n) (GPIO_BASE + (0x70 + (n)*0x100)) /* Trigger Register */
827 #define GPIO_PXTRGS(n) (GPIO_BASE + (0x74 + (n)*0x100)) /* Trigger Set Register */
828 #define GPIO_PXTRGC(n) (GPIO_BASE + (0x78 + (n)*0x100)) /* Trigger Set Register */
829 #define GPIO_PXFLG(n) (GPIO_BASE + (0x80 + (n)*0x100)) /* Port Flag Register */
830 #define GPIO_PXFLGC(n) (GPIO_BASE + (0x14 + (n)*0x100)) /* Port Flag clear Register */
832 #define REG_GPIO_PXPIN(n) REG32(GPIO_PXPIN((n))) /* PIN level */
833 #define REG_GPIO_PXDAT(n) REG32(GPIO_PXDAT((n))) /* 1: interrupt pending */
834 #define REG_GPIO_PXDATS(n) REG32(GPIO_PXDATS((n)))
835 #define REG_GPIO_PXDATC(n) REG32(GPIO_PXDATC((n)))
836 #define REG_GPIO_PXIM(n) REG32(GPIO_PXIM((n))) /* 1: mask pin interrupt */
837 #define REG_GPIO_PXIMS(n) REG32(GPIO_PXIMS((n)))
838 #define REG_GPIO_PXIMC(n) REG32(GPIO_PXIMC((n)))
839 #define REG_GPIO_PXPE(n) REG32(GPIO_PXPE((n))) /* 1: disable pull up/down */
840 #define REG_GPIO_PXPES(n) REG32(GPIO_PXPES((n)))
841 #define REG_GPIO_PXPEC(n) REG32(GPIO_PXPEC((n)))
842 #define REG_GPIO_PXFUN(n) REG32(GPIO_PXFUN((n))) /* 0:GPIO or intr, 1:FUNC */
843 #define REG_GPIO_PXFUNS(n) REG32(GPIO_PXFUNS((n)))
844 #define REG_GPIO_PXFUNC(n) REG32(GPIO_PXFUNC((n)))
845 #define REG_GPIO_PXSEL(n) REG32(GPIO_PXSEL((n))) /* 0:GPIO/Fun0,1:intr/fun1*/
846 #define REG_GPIO_PXSELS(n) REG32(GPIO_PXSELS((n)))
847 #define REG_GPIO_PXSELC(n) REG32(GPIO_PXSELC((n)))
848 #define REG_GPIO_PXDIR(n) REG32(GPIO_PXDIR((n))) /* 0:input/low-level-trig/falling-edge-trig, 1:output/high-level-trig/rising-edge-trig */
849 #define REG_GPIO_PXDIRS(n) REG32(GPIO_PXDIRS((n)))
850 #define REG_GPIO_PXDIRC(n) REG32(GPIO_PXDIRC((n)))
851 #define REG_GPIO_PXTRG(n) REG32(GPIO_PXTRG((n))) /* 0:level-trigger, 1:edge-trigger */
852 #define REG_GPIO_PXTRGS(n) REG32(GPIO_PXTRGS((n)))
853 #define REG_GPIO_PXTRGC(n) REG32(GPIO_PXTRGC((n)))
854 #define REG_GPIO_PXFLG(n) REG32(GPIO_PXFLG((n))) /* interrupt flag */
855 #define REG_GPIO_PXFLGC(n) REG32(GPIO_PXFLGC((n))) /* interrupt flag */
858 /*************************************************************************
859 * UART
860 *************************************************************************/
862 #define IRDA_BASE UART0_BASE
863 #define UART_BASE UART0_BASE
864 #define UART_OFF 0x1000
866 /* Register Offset */
867 #define OFF_RDR (0x00) /* R 8b H'xx */
868 #define OFF_TDR (0x00) /* W 8b H'xx */
869 #define OFF_DLLR (0x00) /* RW 8b H'00 */
870 #define OFF_DLHR (0x04) /* RW 8b H'00 */
871 #define OFF_IER (0x04) /* RW 8b H'00 */
872 #define OFF_ISR (0x08) /* R 8b H'01 */
873 #define OFF_FCR (0x08) /* W 8b H'00 */
874 #define OFF_LCR (0x0C) /* RW 8b H'00 */
875 #define OFF_MCR (0x10) /* RW 8b H'00 */
876 #define OFF_LSR (0x14) /* R 8b H'00 */
877 #define OFF_MSR (0x18) /* R 8b H'00 */
878 #define OFF_SPR (0x1C) /* RW 8b H'00 */
879 #define OFF_SIRCR (0x20) /* RW 8b H'00, UART0 */
880 #define OFF_UMR (0x24) /* RW 8b H'00, UART M Register */
881 #define OFF_UACR (0x28) /* RW 8b H'00, UART Add Cycle Register */
883 /* Register Address */
884 #define UART0_RDR (UART0_BASE + OFF_RDR)
885 #define UART0_TDR (UART0_BASE + OFF_TDR)
886 #define UART0_DLLR (UART0_BASE + OFF_DLLR)
887 #define UART0_DLHR (UART0_BASE + OFF_DLHR)
888 #define UART0_IER (UART0_BASE + OFF_IER)
889 #define UART0_ISR (UART0_BASE + OFF_ISR)
890 #define UART0_FCR (UART0_BASE + OFF_FCR)
891 #define UART0_LCR (UART0_BASE + OFF_LCR)
892 #define UART0_MCR (UART0_BASE + OFF_MCR)
893 #define UART0_LSR (UART0_BASE + OFF_LSR)
894 #define UART0_MSR (UART0_BASE + OFF_MSR)
895 #define UART0_SPR (UART0_BASE + OFF_SPR)
896 #define UART0_SIRCR (UART0_BASE + OFF_SIRCR)
897 #define UART0_UMR (UART0_BASE + OFF_UMR)
898 #define UART0_UACR (UART0_BASE + OFF_UACR)
901 * Define macros for UART_IER
902 * UART Interrupt Enable Register
904 #define UART_IER_RIE (1 << 0) /* 0: receive fifo "full" interrupt disable */
905 #define UART_IER_TIE (1 << 1) /* 0: transmit fifo "empty" interrupt disable */
906 #define UART_IER_RLIE (1 << 2) /* 0: receive line status interrupt disable */
907 #define UART_IER_MIE (1 << 3) /* 0: modem status interrupt disable */
908 #define UART_IER_RTIE (1 << 4) /* 0: receive timeout interrupt disable */
911 * Define macros for UART_ISR
912 * UART Interrupt Status Register
914 #define UART_ISR_IP (1 << 0) /* 0: interrupt is pending 1: no interrupt */
915 #define UART_ISR_IID (7 << 1) /* Source of Interrupt */
916 #define UART_ISR_IID_MSI (0 << 1) /* Modem status interrupt */
917 #define UART_ISR_IID_THRI (1 << 1) /* Transmitter holding register empty */
918 #define UART_ISR_IID_RDI (2 << 1) /* Receiver data interrupt */
919 #define UART_ISR_IID_RLSI (3 << 1) /* Receiver line status interrupt */
920 #define UART_ISR_FFMS (3 << 6) /* FIFO mode select, set when UART_FCR.FE is set to 1 */
921 #define UART_ISR_FFMS_NO_FIFO (0 << 6)
922 #define UART_ISR_FFMS_FIFO_MODE (3 << 6)
925 * Define macros for UART_FCR
926 * UART FIFO Control Register
928 #define UART_FCR_FE (1 << 0) /* 0: non-FIFO mode 1: FIFO mode */
929 #define UART_FCR_RFLS (1 << 1) /* write 1 to flush receive FIFO */
930 #define UART_FCR_TFLS (1 << 2) /* write 1 to flush transmit FIFO */
931 #define UART_FCR_DMS (1 << 3) /* 0: disable DMA mode */
932 #define UART_FCR_UUE (1 << 4) /* 0: disable UART */
933 #define UART_FCR_RTRG (3 << 6) /* Receive FIFO Data Trigger */
934 #define UART_FCR_RTRG_1 (0 << 6)
935 #define UART_FCR_RTRG_4 (1 << 6)
936 #define UART_FCR_RTRG_8 (2 << 6)
937 #define UART_FCR_RTRG_15 (3 << 6)
940 * Define macros for UART_LCR
941 * UART Line Control Register
943 #define UART_LCR_WLEN (3 << 0) /* word length */
944 #define UART_LCR_WLEN_5 (0 << 0)
945 #define UART_LCR_WLEN_6 (1 << 0)
946 #define UART_LCR_WLEN_7 (2 << 0)
947 #define UART_LCR_WLEN_8 (3 << 0)
948 #define UART_LCR_STOP (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8
949 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
950 #define UART_LCR_STOP_1 (0 << 2) /* 0: 1 stop bit when word length is 5,6,7,8
951 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
952 #define UART_LCR_STOP_2 (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8
953 1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
955 #define UART_LCR_PE (1 << 3) /* 0: parity disable */
956 #define UART_LCR_PROE (1 << 4) /* 0: even parity 1: odd parity */
957 #define UART_LCR_SPAR (1 << 5) /* 0: sticky parity disable */
958 #define UART_LCR_SBRK (1 << 6) /* write 0 normal, write 1 send break */
959 #define UART_LCR_DLAB (1 << 7) /* 0: access UART_RDR/TDR/IER 1: access UART_DLLR/DLHR */
962 * Define macros for UART_LSR
963 * UART Line Status Register
965 #define UART_LSR_DR (1 << 0) /* 0: receive FIFO is empty 1: receive data is ready */
966 #define UART_LSR_ORER (1 << 1) /* 0: no overrun error */
967 #define UART_LSR_PER (1 << 2) /* 0: no parity error */
968 #define UART_LSR_FER (1 << 3) /* 0; no framing error */
969 #define UART_LSR_BRK (1 << 4) /* 0: no break detected 1: receive a break signal */
970 #define UART_LSR_TDRQ (1 << 5) /* 1: transmit FIFO half "empty" */
971 #define UART_LSR_TEMT (1 << 6) /* 1: transmit FIFO and shift registers empty */
972 #define UART_LSR_RFER (1 << 7) /* 0: no receive error 1: receive error in FIFO mode */
975 * Define macros for UART_MCR
976 * UART Modem Control Register
978 #define UART_MCR_DTR (1 << 0) /* 0: DTR_ ouput high */
979 #define UART_MCR_RTS (1 << 1) /* 0: RTS_ output high */
980 #define UART_MCR_OUT1 (1 << 2) /* 0: UART_MSR.RI is set to 0 and RI_ input high */
981 #define UART_MCR_OUT2 (1 << 3) /* 0: UART_MSR.DCD is set to 0 and DCD_ input high */
982 #define UART_MCR_LOOP (1 << 4) /* 0: normal 1: loopback mode */
983 #define UART_MCR_MCE (1 << 7) /* 0: modem function is disable */
986 * Define macros for UART_MSR
987 * UART Modem Status Register
989 #define UART_MSR_DCTS (1 << 0) /* 0: no change on CTS_ pin since last read of UART_MSR */
990 #define UART_MSR_DDSR (1 << 1) /* 0: no change on DSR_ pin since last read of UART_MSR */
991 #define UART_MSR_DRI (1 << 2) /* 0: no change on RI_ pin since last read of UART_MSR */
992 #define UART_MSR_DDCD (1 << 3) /* 0: no change on DCD_ pin since last read of UART_MSR */
993 #define UART_MSR_CTS (1 << 4) /* 0: CTS_ pin is high */
994 #define UART_MSR_DSR (1 << 5) /* 0: DSR_ pin is high */
995 #define UART_MSR_RI (1 << 6) /* 0: RI_ pin is high */
996 #define UART_MSR_DCD (1 << 7) /* 0: DCD_ pin is high */
999 * Define macros for SIRCR
1000 * Slow IrDA Control Register
1002 #define SIRCR_TSIRE (1 << 0) /* 0: transmitter is in UART mode 1: IrDA mode */
1003 #define SIRCR_RSIRE (1 << 1) /* 0: receiver is in UART mode 1: IrDA mode */
1004 #define SIRCR_TPWS (1 << 2) /* 0: transmit 0 pulse width is 3/16 of bit length
1005 1: 0 pulse width is 1.6us for 115.2Kbps */
1006 #define SIRCR_TXPL (1 << 3) /* 0: encoder generates a positive pulse for 0 */
1007 #define SIRCR_RXPL (1 << 4) /* 0: decoder interprets positive pulse as 0 */
1010 /*************************************************************************
1011 * AIC (AC97/I2S Controller)
1012 *************************************************************************/
1013 #define AIC_FR (AIC_BASE + 0x000)
1014 #define AIC_CR (AIC_BASE + 0x004)
1015 #define AIC_ACCR1 (AIC_BASE + 0x008)
1016 #define AIC_ACCR2 (AIC_BASE + 0x00C)
1017 #define AIC_I2SCR (AIC_BASE + 0x010)
1018 #define AIC_SR (AIC_BASE + 0x014)
1019 #define AIC_ACSR (AIC_BASE + 0x018)
1020 #define AIC_I2SSR (AIC_BASE + 0x01C)
1021 #define AIC_ACCAR (AIC_BASE + 0x020)
1022 #define AIC_ACCDR (AIC_BASE + 0x024)
1023 #define AIC_ACSAR (AIC_BASE + 0x028)
1024 #define AIC_ACSDR (AIC_BASE + 0x02C)
1025 #define AIC_I2SDIV (AIC_BASE + 0x030)
1026 #define AIC_DR (AIC_BASE + 0x034)
1028 #define REG_AIC_FR REG32(AIC_FR)
1029 #define REG_AIC_CR REG32(AIC_CR)
1030 #define REG_AIC_ACCR1 REG32(AIC_ACCR1)
1031 #define REG_AIC_ACCR2 REG32(AIC_ACCR2)
1032 #define REG_AIC_I2SCR REG32(AIC_I2SCR)
1033 #define REG_AIC_SR REG32(AIC_SR)
1034 #define REG_AIC_ACSR REG32(AIC_ACSR)
1035 #define REG_AIC_I2SSR REG32(AIC_I2SSR)
1036 #define REG_AIC_ACCAR REG32(AIC_ACCAR)
1037 #define REG_AIC_ACCDR REG32(AIC_ACCDR)
1038 #define REG_AIC_ACSAR REG32(AIC_ACSAR)
1039 #define REG_AIC_ACSDR REG32(AIC_ACSDR)
1040 #define REG_AIC_I2SDIV REG32(AIC_I2SDIV)
1041 #define REG_AIC_DR REG32(AIC_DR)
1043 /* AIC Controller Configuration Register (AIC_FR) */
1045 #define AIC_FR_RFTH_BIT 12 /* Receive FIFO Threshold */
1046 #define AIC_FR_RFTH_MASK (0xf << AIC_FR_RFTH_BIT)
1047 #define AIC_FR_TFTH_BIT 8 /* Transmit FIFO Threshold */
1048 #define AIC_FR_TFTH_MASK (0xf << AIC_FR_TFTH_BIT)
1049 #define AIC_FR_ICDC (1 << 5) /* External(0) or Internal CODEC(1) */
1050 #define AIC_FR_AUSEL (1 << 4) /* AC97(0) or I2S/MSB-justified(1) */
1051 #define AIC_FR_RST (1 << 3) /* AIC registers reset */
1052 #define AIC_FR_BCKD (1 << 2) /* I2S BIT_CLK direction, 0:input,1:output */
1053 #define AIC_FR_SYNCD (1 << 1) /* I2S SYNC direction, 0:input,1:output */
1054 #define AIC_FR_ENB (1 << 0) /* AIC enable bit */
1056 /* AIC Controller Common Control Register (AIC_CR) */
1058 #define AIC_CR_OSS_BIT 19 /* Output Sample Size from memory (AIC V2 only) */
1059 #define AIC_CR_OSS_MASK (0x7 << AIC_CR_OSS_BIT)
1060 #define AIC_CR_OSS_8BIT (0x0 << AIC_CR_OSS_BIT)
1061 #define AIC_CR_OSS_16BIT (0x1 << AIC_CR_OSS_BIT)
1062 #define AIC_CR_OSS_18BIT (0x2 << AIC_CR_OSS_BIT)
1063 #define AIC_CR_OSS_20BIT (0x3 << AIC_CR_OSS_BIT)
1064 #define AIC_CR_OSS_24BIT (0x4 << AIC_CR_OSS_BIT)
1065 #define AIC_CR_ISS_BIT 16 /* Input Sample Size from memory (AIC V2 only) */
1066 #define AIC_CR_ISS_MASK (0x7 << AIC_CR_ISS_BIT)
1067 #define AIC_CR_ISS_8BIT (0x0 << AIC_CR_ISS_BIT)
1068 #define AIC_CR_ISS_16BIT (0x1 << AIC_CR_ISS_BIT)
1069 #define AIC_CR_ISS_18BIT (0x2 << AIC_CR_ISS_BIT)
1070 #define AIC_CR_ISS_20BIT (0x3 << AIC_CR_ISS_BIT)
1071 #define AIC_CR_ISS_24BIT (0x4 << AIC_CR_ISS_BIT)
1072 #define AIC_CR_RDMS (1 << 15) /* Receive DMA enable */
1073 #define AIC_CR_TDMS (1 << 14) /* Transmit DMA enable */
1074 #define AIC_CR_M2S (1 << 11) /* Mono to Stereo enable */
1075 #define AIC_CR_ENDSW (1 << 10) /* Endian switch enable */
1076 #define AIC_CR_AVSTSU (1 << 9) /* Signed <-> Unsigned toggle enable */
1077 #define AIC_CR_FLUSH (1 << 8) /* Flush FIFO */
1078 #define AIC_CR_EROR (1 << 6) /* Enable ROR interrupt */
1079 #define AIC_CR_ETUR (1 << 5) /* Enable TUR interrupt */
1080 #define AIC_CR_ERFS (1 << 4) /* Enable RFS interrupt */
1081 #define AIC_CR_ETFS (1 << 3) /* Enable TFS interrupt */
1082 #define AIC_CR_ENLBF (1 << 2) /* Enable Loopback Function */
1083 #define AIC_CR_ERPL (1 << 1) /* Enable Playback Function */
1084 #define AIC_CR_EREC (1 << 0) /* Enable Record Function */
1086 /* AIC Controller AC-link Control Register 1 (AIC_ACCR1) */
1088 #define AIC_ACCR1_RS_BIT 16 /* Receive Valid Slots */
1089 #define AIC_ACCR1_RS_MASK (0x3ff << AIC_ACCR1_RS_BIT)
1090 #define AIC_ACCR1_RS_SLOT12 (1 << 25) /* Slot 12 valid bit */
1091 #define AIC_ACCR1_RS_SLOT11 (1 << 24) /* Slot 11 valid bit */
1092 #define AIC_ACCR1_RS_SLOT10 (1 << 23) /* Slot 10 valid bit */
1093 #define AIC_ACCR1_RS_SLOT9 (1 << 22) /* Slot 9 valid bit, LFE */
1094 #define AIC_ACCR1_RS_SLOT8 (1 << 21) /* Slot 8 valid bit, Surround Right */
1095 #define AIC_ACCR1_RS_SLOT7 (1 << 20) /* Slot 7 valid bit, Surround Left */
1096 #define AIC_ACCR1_RS_SLOT6 (1 << 19) /* Slot 6 valid bit, PCM Center */
1097 #define AIC_ACCR1_RS_SLOT5 (1 << 18) /* Slot 5 valid bit */
1098 #define AIC_ACCR1_RS_SLOT4 (1 << 17) /* Slot 4 valid bit, PCM Right */
1099 #define AIC_ACCR1_RS_SLOT3 (1 << 16) /* Slot 3 valid bit, PCM Left */
1100 #define AIC_ACCR1_XS_BIT 0 /* Transmit Valid Slots */
1101 #define AIC_ACCR1_XS_MASK (0x3ff << AIC_ACCR1_XS_BIT)
1102 #define AIC_ACCR1_XS_SLOT12 (1 << 9) /* Slot 12 valid bit */
1103 #define AIC_ACCR1_XS_SLOT11 (1 << 8) /* Slot 11 valid bit */
1104 #define AIC_ACCR1_XS_SLOT10 (1 << 7) /* Slot 10 valid bit */
1105 #define AIC_ACCR1_XS_SLOT9 (1 << 6) /* Slot 9 valid bit, LFE */
1106 #define AIC_ACCR1_XS_SLOT8 (1 << 5) /* Slot 8 valid bit, Surround Right */
1107 #define AIC_ACCR1_XS_SLOT7 (1 << 4) /* Slot 7 valid bit, Surround Left */
1108 #define AIC_ACCR1_XS_SLOT6 (1 << 3) /* Slot 6 valid bit, PCM Center */
1109 #define AIC_ACCR1_XS_SLOT5 (1 << 2) /* Slot 5 valid bit */
1110 #define AIC_ACCR1_XS_SLOT4 (1 << 1) /* Slot 4 valid bit, PCM Right */
1111 #define AIC_ACCR1_XS_SLOT3 (1 << 0) /* Slot 3 valid bit, PCM Left */
1113 /* AIC Controller AC-link Control Register 2 (AIC_ACCR2) */
1115 #define AIC_ACCR2_ERSTO (1 << 18) /* Enable RSTO interrupt */
1116 #define AIC_ACCR2_ESADR (1 << 17) /* Enable SADR interrupt */
1117 #define AIC_ACCR2_ECADT (1 << 16) /* Enable CADT interrupt */
1118 #define AIC_ACCR2_OASS_BIT 8 /* Output Sample Size for AC-link */
1119 #define AIC_ACCR2_OASS_MASK (0x3 << AIC_ACCR2_OASS_BIT)
1120 #define AIC_ACCR2_OASS_20BIT (0 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 20-bit */
1121 #define AIC_ACCR2_OASS_18BIT (1 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 18-bit */
1122 #define AIC_ACCR2_OASS_16BIT (2 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 16-bit */
1123 #define AIC_ACCR2_OASS_8BIT (3 << AIC_ACCR2_OASS_BIT) /* Output Audio Sample Size is 8-bit */
1124 #define AIC_ACCR2_IASS_BIT 6 /* Output Sample Size for AC-link */
1125 #define AIC_ACCR2_IASS_MASK (0x3 << AIC_ACCR2_IASS_BIT)
1126 #define AIC_ACCR2_IASS_20BIT (0 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 20-bit */
1127 #define AIC_ACCR2_IASS_18BIT (1 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 18-bit */
1128 #define AIC_ACCR2_IASS_16BIT (2 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 16-bit */
1129 #define AIC_ACCR2_IASS_8BIT (3 << AIC_ACCR2_IASS_BIT) /* Input Audio Sample Size is 8-bit */
1130 #define AIC_ACCR2_SO (1 << 3) /* SDATA_OUT output value */
1131 #define AIC_ACCR2_SR (1 << 2) /* RESET# pin level */
1132 #define AIC_ACCR2_SS (1 << 1) /* SYNC pin level */
1133 #define AIC_ACCR2_SA (1 << 0) /* SYNC and SDATA_OUT alternation */
1135 /* AIC Controller I2S/MSB-justified Control Register (AIC_I2SCR) */
1137 #define AIC_I2SCR_STPBK (1 << 12) /* Stop BIT_CLK for I2S/MSB-justified */
1138 #define AIC_I2SCR_WL_BIT 1 /* Input/Output Sample Size for I2S/MSB-justified */
1139 #define AIC_I2SCR_WL_MASK (0x7 << AIC_I2SCR_WL_BIT)
1140 #define AIC_I2SCR_WL_24BIT (0 << AIC_I2SCR_WL_BIT) /* Word Length is 24 bit */
1141 #define AIC_I2SCR_WL_20BIT (1 << AIC_I2SCR_WL_BIT) /* Word Length is 20 bit */
1142 #define AIC_I2SCR_WL_18BIT (2 << AIC_I2SCR_WL_BIT) /* Word Length is 18 bit */
1143 #define AIC_I2SCR_WL_16BIT (3 << AIC_I2SCR_WL_BIT) /* Word Length is 16 bit */
1144 #define AIC_I2SCR_WL_8BIT (4 << AIC_I2SCR_WL_BIT) /* Word Length is 8 bit */
1145 #define AIC_I2SCR_AMSL (1 << 0) /* 0:I2S, 1:MSB-justified */
1147 /* AIC Controller FIFO Status Register (AIC_SR) */
1149 #define AIC_SR_RFL_BIT 24 /* Receive FIFO Level */
1150 #define AIC_SR_RFL_MASK (0x3f << AIC_SR_RFL_BIT)
1151 #define AIC_SR_TFL_BIT 8 /* Transmit FIFO level */
1152 #define AIC_SR_TFL_MASK (0x3f << AIC_SR_TFL_BIT)
1153 #define AIC_SR_ROR (1 << 6) /* Receive FIFO Overrun */
1154 #define AIC_SR_TUR (1 << 5) /* Transmit FIFO Underrun */
1155 #define AIC_SR_RFS (1 << 4) /* Receive FIFO Service Request */
1156 #define AIC_SR_TFS (1 << 3) /* Transmit FIFO Service Request */
1158 /* AIC Controller AC-link Status Register (AIC_ACSR) */
1160 #define AIC_ACSR_SLTERR (1 << 21) /* Slot Error Flag */
1161 #define AIC_ACSR_CRDY (1 << 20) /* External CODEC Ready Flag */
1162 #define AIC_ACSR_CLPM (1 << 19) /* External CODEC low power mode flag */
1163 #define AIC_ACSR_RSTO (1 << 18) /* External CODEC regs read status timeout */
1164 #define AIC_ACSR_SADR (1 << 17) /* External CODEC regs status addr and data received */
1165 #define AIC_ACSR_CADT (1 << 16) /* Command Address and Data Transmitted */
1167 /* AIC Controller I2S/MSB-justified Status Register (AIC_I2SSR) */
1169 #define AIC_I2SSR_BSY (1 << 2) /* AIC Busy in I2S/MSB-justified format */
1171 /* AIC Controller AC97 codec Command Address Register (AIC_ACCAR) */
1173 #define AIC_ACCAR_CAR_BIT 0
1174 #define AIC_ACCAR_CAR_MASK (0xfffff << AIC_ACCAR_CAR_BIT)
1176 /* AIC Controller AC97 codec Command Data Register (AIC_ACCDR) */
1178 #define AIC_ACCDR_CDR_BIT 0
1179 #define AIC_ACCDR_CDR_MASK (0xfffff << AIC_ACCDR_CDR_BIT)
1181 /* AIC Controller AC97 codec Status Address Register (AIC_ACSAR) */
1183 #define AIC_ACSAR_SAR_BIT 0
1184 #define AIC_ACSAR_SAR_MASK (0xfffff << AIC_ACSAR_SAR_BIT)
1186 /* AIC Controller AC97 codec Status Data Register (AIC_ACSDR) */
1188 #define AIC_ACSDR_SDR_BIT 0
1189 #define AIC_ACSDR_SDR_MASK (0xfffff << AIC_ACSDR_SDR_BIT)
1191 /* AIC Controller I2S/MSB-justified Clock Divider Register (AIC_I2SDIV) */
1193 #define AIC_I2SDIV_DIV_BIT 0
1194 #define AIC_I2SDIV_DIV_MASK (0x7f << AIC_I2SDIV_DIV_BIT)
1195 #define AIC_I2SDIV_BITCLK_3072KHZ (0x0C << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 3.072MHz */
1196 #define AIC_I2SDIV_BITCLK_2836KHZ (0x0D << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 2.836MHz */
1197 #define AIC_I2SDIV_BITCLK_1418KHZ (0x1A << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.418MHz */
1198 #define AIC_I2SDIV_BITCLK_1024KHZ (0x24 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 1.024MHz */
1199 #define AIC_I2SDIV_BITCLK_7089KHZ (0x34 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 708.92KHz */
1200 #define AIC_I2SDIV_BITCLK_512KHZ (0x48 << AIC_I2SDIV_DIV_BIT) /* BIT_CLK of 512.00KHz */
1203 /*************************************************************************
1204 * ICDC (Internal CODEC)
1205 *************************************************************************/
1206 #define ICDC_CR (ICDC_BASE + 0x0400) /* ICDC Control Register */
1207 #define ICDC_APWAIT (ICDC_BASE + 0x0404) /* Anti-Pop WAIT Stage Timing Control Register */
1208 #define ICDC_APPRE (ICDC_BASE + 0x0408) /* Anti-Pop HPEN-PRE Stage Timing Control Register */
1209 #define ICDC_APHPEN (ICDC_BASE + 0x040C) /* Anti-Pop HPEN Stage Timing Control Register */
1210 #define ICDC_APSR (ICDC_BASE + 0x0410) /* Anti-Pop Status Register */
1211 #define ICDC_CDCCR1 (ICDC_BASE + 0x0080)
1212 #define ICDC_CDCCR2 (ICDC_BASE + 0x0084)
1214 #define REG_ICDC_CR REG32(ICDC_CR)
1215 #define REG_ICDC_APWAIT REG32(ICDC_APWAIT)
1216 #define REG_ICDC_APPRE REG32(ICDC_APPRE)
1217 #define REG_ICDC_APHPEN REG32(ICDC_APHPEN)
1218 #define REG_ICDC_APSR REG32(ICDC_APSR)
1219 #define REG_ICDC_CDCCR1 REG32(ICDC_CDCCR1)
1220 #define REG_ICDC_CDCCR2 REG32(ICDC_CDCCR2)
1222 /* ICDC Control Register */
1223 #define ICDC_CR_LINVOL_BIT 24 /* LINE Input Volume Gain: GAIN=LINVOL*1.5-34.5 */
1224 #define ICDC_CR_LINVOL_MASK (0x1f << ICDC_CR_LINVOL_BIT)
1225 #define ICDC_CR_ASRATE_BIT 20 /* Audio Sample Rate */
1226 #define ICDC_CR_ASRATE_MASK (0x0f << ICDC_CR_ASRATE_BIT)
1227 #define ICDC_CR_ASRATE_8000 (0x0 << ICDC_CR_ASRATE_BIT)
1228 #define ICDC_CR_ASRATE_11025 (0x1 << ICDC_CR_ASRATE_BIT)
1229 #define ICDC_CR_ASRATE_12000 (0x2 << ICDC_CR_ASRATE_BIT)
1230 #define ICDC_CR_ASRATE_16000 (0x3 << ICDC_CR_ASRATE_BIT)
1231 #define ICDC_CR_ASRATE_22050 (0x4 << ICDC_CR_ASRATE_BIT)
1232 #define ICDC_CR_ASRATE_24000 (0x5 << ICDC_CR_ASRATE_BIT)
1233 #define ICDC_CR_ASRATE_32000 (0x6 << ICDC_CR_ASRATE_BIT)
1234 #define ICDC_CR_ASRATE_44100 (0x7 << ICDC_CR_ASRATE_BIT)
1235 #define ICDC_CR_ASRATE_48000 (0x8 << ICDC_CR_ASRATE_BIT)
1236 #define ICDC_CR_MICBG_BIT 18 /* MIC Boost Gain */
1237 #define ICDC_CR_MICBG_MASK (0x3 << ICDC_CR_MICBG_BIT)
1238 #define ICDC_CR_MICBG_0DB (0x0 << ICDC_CR_MICBG_BIT)
1239 #define ICDC_CR_MICBG_6DB (0x1 << ICDC_CR_MICBG_BIT)
1240 #define ICDC_CR_MICBG_12DB (0x2 << ICDC_CR_MICBG_BIT)
1241 #define ICDC_CR_MICBG_20DB (0x3 << ICDC_CR_MICBG_BIT)
1242 #define ICDC_CR_HPVOL_BIT 16 /* Headphone Volume Gain */
1243 #define ICDC_CR_HPVOL_MASK (0x3 << ICDC_CR_HPVOL_BIT)
1244 #define ICDC_CR_HPVOL_0DB (0x0 << ICDC_CR_HPVOL_BIT)
1245 #define ICDC_CR_HPVOL_2DB (0x1 << ICDC_CR_HPVOL_BIT)
1246 #define ICDC_CR_HPVOL_4DB (0x2 << ICDC_CR_HPVOL_BIT)
1247 #define ICDC_CR_HPVOL_6DB (0x3 << ICDC_CR_HPVOL_BIT)
1248 #define ICDC_CR_ELINEIN (1 << 13) /* Enable LINE Input */
1249 #define ICDC_CR_EMIC (1 << 12) /* Enable MIC Input */
1250 #define ICDC_CR_SW1ON (1 << 11) /* Switch 1 in CODEC is on */
1251 #define ICDC_CR_EADC (1 << 10) /* Enable ADC */
1252 #define ICDC_CR_SW2ON (1 << 9) /* Switch 2 in CODEC is on */
1253 #define ICDC_CR_EDAC (1 << 8) /* Enable DAC */
1254 #define ICDC_CR_HPMUTE (1 << 5) /* Headphone Mute */
1255 #define ICDC_CR_HPTON (1 << 4) /* Headphone Amplifier Trun On */
1256 #define ICDC_CR_HPTOFF (1 << 3) /* Headphone Amplifier Trun Off */
1257 #define ICDC_CR_TAAP (1 << 2) /* Turn Around of the Anti-Pop Procedure */
1258 #define ICDC_CR_EAP (1 << 1) /* Enable Anti-Pop Procedure */
1259 #define ICDC_CR_SUSPD (1 << 0) /* CODEC Suspend */
1261 /* Anti-Pop WAIT Stage Timing Control Register */
1262 #define ICDC_APWAIT_WAITSN_BIT 0
1263 #define ICDC_APWAIT_WAITSN_MASK (0x7ff << ICDC_APWAIT_WAITSN_BIT)
1265 /* Anti-Pop HPEN-PRE Stage Timing Control Register */
1266 #define ICDC_APPRE_PRESN_BIT 0
1267 #define ICDC_APPRE_PRESN_MASK (0x1ff << ICDC_APPRE_PRESN_BIT)
1269 /* Anti-Pop HPEN Stage Timing Control Register */
1270 #define ICDC_APHPEN_HPENSN_BIT 0
1271 #define ICDC_APHPEN_HPENSN_MASK (0x3fff << ICDC_APHPEN_HPENSN_BIT)
1273 /* Anti-Pop Status Register */
1274 #define ICDC_SR_HPST_BIT 14 /* Headphone Amplifier State */
1275 #define ICDC_SR_HPST_MASK (0x7 << ICDC_SR_HPST_BIT)
1276 #define ICDC_SR_HPST_HP_OFF (0x0 << ICDC_SR_HPST_BIT) /* HP amplifier is off */
1277 #define ICDC_SR_HPST_TON_WAIT (0x1 << ICDC_SR_HPST_BIT) /* wait state in turn-on */
1278 #define ICDC_SR_HPST_TON_PRE (0x2 << ICDC_SR_HPST_BIT) /* pre-enable state in turn-on */
1279 #define ICDC_SR_HPST_TON_HPEN (0x3 << ICDC_SR_HPST_BIT) /* HP enable state in turn-on */
1280 #define ICDC_SR_HPST_TOFF_HPEN (0x4 << ICDC_SR_HPST_BIT) /* HP enable state in turn-off */
1281 #define ICDC_SR_HPST_TOFF_PRE (0x5 << ICDC_SR_HPST_BIT) /* pre-enable state in turn-off */
1282 #define ICDC_SR_HPST_TOFF_WAIT (0x6 << ICDC_SR_HPST_BIT) /* wait state in turn-off */
1283 #define ICDC_SR_HPST_HP_ON (0x7 << ICDC_SR_HPST_BIT) /* HP amplifier is on */
1284 #define ICDC_SR_SNCNT_BIT 0 /* Sample Number Counter */
1285 #define ICDC_SR_SNCNT_MASK (0x3fff << ICDC_SR_SNCNT_BIT)
1287 #define ICDC_CDCCR1_ELININ (1 << 29)
1288 #define ICDC_CDCCR1_EMIC (1 << 28)
1289 #define ICDC_CDCCR1_SW1ON (1 << 27)
1290 #define ICDC_CDCCR1_EADC (1 << 26)
1291 #define ICDC_CDCCR1_SW2ON (1 << 25)
1292 #define ICDC_CDCCR1_EDAC (1 << 24)
1293 #define ICDC_CDCCR1_PDVR (1 << 20)
1294 #define ICDC_CDCCR1_PDVRA (1 << 19)
1295 #define ICDC_CDCCR1_VRPLD (1 << 18)
1296 #define ICDC_CDCCR1_VRCGL (1 << 17)
1297 #define ICDC_CDCCR1_VRCGH (1 << 16)
1298 #define ICDC_CDCCR1_HPMUTE (1 << 14)
1299 #define ICDC_CDCCR1_HPOV0 (1 << 13)
1300 #define ICDC_CDCCR1_HPCG (1 << 12)
1301 #define ICDC_CDCCR1_HPPLDM (1 << 11)
1302 #define ICDC_CDCCR1_HPPLDR (1 << 10)
1303 #define ICDC_CDCCR1_PDHPM (1 << 9)
1304 #define ICDC_CDCCR1_PDHP (1 << 8)
1305 #define ICDC_CDCCR1_SUSPD (1 << 1)
1306 #define ICDC_CDCCR1_RST (1 << 0)
1308 #define ICDC_CDCCR2_AINVOL(n) ((n & 0x1F) << 16)
1309 #define ICDC_CDCCR2_SMPR(n) ((n & 0xF) << 8)
1310 #define ICDC_CDCCR2_MICBG(n) ((n & 0x3) << 4)
1311 #define ICDC_CDCCR2_HPVOL(n) ((n & 0x3) << 0)
1313 #define ICDC_CDCCR2_SMPR_8 (0)
1314 #define ICDC_CDCCR2_SMPR_11 (1)
1315 #define ICDC_CDCCR2_SMPR_12 (2)
1316 #define ICDC_CDCCR2_SMPR_16 (3)
1317 #define ICDC_CDCCR2_SMPR_22 (4)
1318 #define ICDC_CDCCR2_SMPR_24 (5)
1319 #define ICDC_CDCCR2_SMPR_32 (6)
1320 #define ICDC_CDCCR2_SMPR_44 (7)
1321 #define ICDC_CDCCR2_SMPR_48 (8)
1323 #define ICDC_CDCCR2_HPVOL_0 (0)
1324 #define ICDC_CDCCR2_HPVOL_2 (1)
1325 #define ICDC_CDCCR2_HPVOL_4 (2)
1326 #define ICDC_CDCCR2_HPVOL_6 (3)
1329 /*************************************************************************
1330 * I2C
1331 *************************************************************************/
1332 #define I2C_DR (I2C_BASE + 0x000)
1333 #define I2C_CR (I2C_BASE + 0x004)
1334 #define I2C_SR (I2C_BASE + 0x008)
1335 #define I2C_GR (I2C_BASE + 0x00C)
1337 #define REG_I2C_DR REG8(I2C_DR)
1338 #define REG_I2C_CR REG8(I2C_CR)
1339 #define REG_I2C_SR REG8(I2C_SR)
1340 #define REG_I2C_GR REG16(I2C_GR)
1342 /* I2C Control Register (I2C_CR) */
1344 #define I2C_CR_IEN (1 << 4)
1345 #define I2C_CR_STA (1 << 3)
1346 #define I2C_CR_STO (1 << 2)
1347 #define I2C_CR_AC (1 << 1)
1348 #define I2C_CR_I2CE (1 << 0)
1350 /* I2C Status Register (I2C_SR) */
1352 #define I2C_SR_STX (1 << 4)
1353 #define I2C_SR_BUSY (1 << 3)
1354 #define I2C_SR_TEND (1 << 2)
1355 #define I2C_SR_DRF (1 << 1)
1356 #define I2C_SR_ACKF (1 << 0)
1359 /*************************************************************************
1360 * SSI
1361 *************************************************************************/
1362 #define SSI_DR (SSI_BASE + 0x000)
1363 #define SSI_CR0 (SSI_BASE + 0x004)
1364 #define SSI_CR1 (SSI_BASE + 0x008)
1365 #define SSI_SR (SSI_BASE + 0x00C)
1366 #define SSI_ITR (SSI_BASE + 0x010)
1367 #define SSI_ICR (SSI_BASE + 0x014)
1368 #define SSI_GR (SSI_BASE + 0x018)
1370 #define REG_SSI_DR REG32(SSI_DR)
1371 #define REG_SSI_CR0 REG16(SSI_CR0)
1372 #define REG_SSI_CR1 REG32(SSI_CR1)
1373 #define REG_SSI_SR REG32(SSI_SR)
1374 #define REG_SSI_ITR REG16(SSI_ITR)
1375 #define REG_SSI_ICR REG8(SSI_ICR)
1376 #define REG_SSI_GR REG16(SSI_GR)
1378 /* SSI Data Register (SSI_DR) */
1380 #define SSI_DR_GPC_BIT 0
1381 #define SSI_DR_GPC_MASK (0x1ff << SSI_DR_GPC_BIT)
1383 /* SSI Control Register 0 (SSI_CR0) */
1385 #define SSI_CR0_SSIE (1 << 15)
1386 #define SSI_CR0_TIE (1 << 14)
1387 #define SSI_CR0_RIE (1 << 13)
1388 #define SSI_CR0_TEIE (1 << 12)
1389 #define SSI_CR0_REIE (1 << 11)
1390 #define SSI_CR0_LOOP (1 << 10)
1391 #define SSI_CR0_RFINE (1 << 9)
1392 #define SSI_CR0_RFINC (1 << 8)
1393 #define SSI_CR0_FSEL (1 << 6)
1394 #define SSI_CR0_TFLUSH (1 << 2)
1395 #define SSI_CR0_RFLUSH (1 << 1)
1396 #define SSI_CR0_DISREV (1 << 0)
1398 /* SSI Control Register 1 (SSI_CR1) */
1400 #define SSI_CR1_FRMHL_BIT 30
1401 #define SSI_CR1_FRMHL_MASK (0x3 << SSI_CR1_FRMHL_BIT)
1402 #define SSI_CR1_FRMHL_CELOW_CE2LOW (0 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is low valid */
1403 #define SSI_CR1_FRMHL_CEHIGH_CE2LOW (1 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is low valid */
1404 #define SSI_CR1_FRMHL_CELOW_CE2HIGH (2 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is low valid and SSI_CE2_ is high valid */
1405 #define SSI_CR1_FRMHL_CEHIGH_CE2HIGH (3 << SSI_CR1_FRMHL_BIT) /* SSI_CE_ is high valid and SSI_CE2_ is high valid */
1406 #define SSI_CR1_TFVCK_BIT 28
1407 #define SSI_CR1_TFVCK_MASK (0x3 << SSI_CR1_TFVCK_BIT)
1408 #define SSI_CR1_TFVCK_0 (0 << SSI_CR1_TFVCK_BIT)
1409 #define SSI_CR1_TFVCK_1 (1 << SSI_CR1_TFVCK_BIT)
1410 #define SSI_CR1_TFVCK_2 (2 << SSI_CR1_TFVCK_BIT)
1411 #define SSI_CR1_TFVCK_3 (3 << SSI_CR1_TFVCK_BIT)
1412 #define SSI_CR1_TCKFI_BIT 26
1413 #define SSI_CR1_TCKFI_MASK (0x3 << SSI_CR1_TCKFI_BIT)
1414 #define SSI_CR1_TCKFI_0 (0 << SSI_CR1_TCKFI_BIT)
1415 #define SSI_CR1_TCKFI_1 (1 << SSI_CR1_TCKFI_BIT)
1416 #define SSI_CR1_TCKFI_2 (2 << SSI_CR1_TCKFI_BIT)
1417 #define SSI_CR1_TCKFI_3 (3 << SSI_CR1_TCKFI_BIT)
1418 #define SSI_CR1_LFST (1 << 25)
1419 #define SSI_CR1_ITFRM (1 << 24)
1420 #define SSI_CR1_UNFIN (1 << 23)
1421 #define SSI_CR1_MULTS (1 << 22)
1422 #define SSI_CR1_FMAT_BIT 20
1423 #define SSI_CR1_FMAT_MASK (0x3 << SSI_CR1_FMAT_BIT)
1424 #define SSI_CR1_FMAT_SPI (0 << SSI_CR1_FMAT_BIT) /* Motorola¡¯s SPI format */
1425 #define SSI_CR1_FMAT_SSP (1 << SSI_CR1_FMAT_BIT) /* TI's SSP format */
1426 #define SSI_CR1_FMAT_MW1 (2 << SSI_CR1_FMAT_BIT) /* National Microwire 1 format */
1427 #define SSI_CR1_FMAT_MW2 (3 << SSI_CR1_FMAT_BIT) /* National Microwire 2 format */
1428 #define SSI_CR1_TTRG_BIT 16
1429 #define SSI_CR1_TTRG_MASK (0xf << SSI_CR1_TTRG_BIT)
1430 #define SSI_CR1_TTRG_1 (0 << SSI_CR1_TTRG_BIT)
1431 #define SSI_CR1_TTRG_8 (1 << SSI_CR1_TTRG_BIT)
1432 #define SSI_CR1_TTRG_16 (2 << SSI_CR1_TTRG_BIT)
1433 #define SSI_CR1_TTRG_24 (3 << SSI_CR1_TTRG_BIT)
1434 #define SSI_CR1_TTRG_32 (4 << SSI_CR1_TTRG_BIT)
1435 #define SSI_CR1_TTRG_40 (5 << SSI_CR1_TTRG_BIT)
1436 #define SSI_CR1_TTRG_48 (6 << SSI_CR1_TTRG_BIT)
1437 #define SSI_CR1_TTRG_56 (7 << SSI_CR1_TTRG_BIT)
1438 #define SSI_CR1_TTRG_64 (8 << SSI_CR1_TTRG_BIT)
1439 #define SSI_CR1_TTRG_72 (9 << SSI_CR1_TTRG_BIT)
1440 #define SSI_CR1_TTRG_80 (10<< SSI_CR1_TTRG_BIT)
1441 #define SSI_CR1_TTRG_88 (11<< SSI_CR1_TTRG_BIT)
1442 #define SSI_CR1_TTRG_96 (12<< SSI_CR1_TTRG_BIT)
1443 #define SSI_CR1_TTRG_104 (13<< SSI_CR1_TTRG_BIT)
1444 #define SSI_CR1_TTRG_112 (14<< SSI_CR1_TTRG_BIT)
1445 #define SSI_CR1_TTRG_120 (15<< SSI_CR1_TTRG_BIT)
1446 #define SSI_CR1_MCOM_BIT 12
1447 #define SSI_CR1_MCOM_MASK (0xf << SSI_CR1_MCOM_BIT)
1448 #define SSI_CR1_MCOM_1BIT (0x0 << SSI_CR1_MCOM_BIT) /* 1-bit command selected */
1449 #define SSI_CR1_MCOM_2BIT (0x1 << SSI_CR1_MCOM_BIT) /* 2-bit command selected */
1450 #define SSI_CR1_MCOM_3BIT (0x2 << SSI_CR1_MCOM_BIT) /* 3-bit command selected */
1451 #define SSI_CR1_MCOM_4BIT (0x3 << SSI_CR1_MCOM_BIT) /* 4-bit command selected */
1452 #define SSI_CR1_MCOM_5BIT (0x4 << SSI_CR1_MCOM_BIT) /* 5-bit command selected */
1453 #define SSI_CR1_MCOM_6BIT (0x5 << SSI_CR1_MCOM_BIT) /* 6-bit command selected */
1454 #define SSI_CR1_MCOM_7BIT (0x6 << SSI_CR1_MCOM_BIT) /* 7-bit command selected */
1455 #define SSI_CR1_MCOM_8BIT (0x7 << SSI_CR1_MCOM_BIT) /* 8-bit command selected */
1456 #define SSI_CR1_MCOM_9BIT (0x8 << SSI_CR1_MCOM_BIT) /* 9-bit command selected */
1457 #define SSI_CR1_MCOM_10BIT (0x9 << SSI_CR1_MCOM_BIT) /* 10-bit command selected */
1458 #define SSI_CR1_MCOM_11BIT (0xA << SSI_CR1_MCOM_BIT) /* 11-bit command selected */
1459 #define SSI_CR1_MCOM_12BIT (0xB << SSI_CR1_MCOM_BIT) /* 12-bit command selected */
1460 #define SSI_CR1_MCOM_13BIT (0xC << SSI_CR1_MCOM_BIT) /* 13-bit command selected */
1461 #define SSI_CR1_MCOM_14BIT (0xD << SSI_CR1_MCOM_BIT) /* 14-bit command selected */
1462 #define SSI_CR1_MCOM_15BIT (0xE << SSI_CR1_MCOM_BIT) /* 15-bit command selected */
1463 #define SSI_CR1_MCOM_16BIT (0xF << SSI_CR1_MCOM_BIT) /* 16-bit command selected */
1464 #define SSI_CR1_RTRG_BIT 8
1465 #define SSI_CR1_RTRG_MASK (0xf << SSI_CR1_RTRG_BIT)
1466 #define SSI_CR1_RTRG_1 (0 << SSI_CR1_RTRG_BIT)
1467 #define SSI_CR1_RTRG_8 (1 << SSI_CR1_RTRG_BIT)
1468 #define SSI_CR1_RTRG_16 (2 << SSI_CR1_RTRG_BIT)
1469 #define SSI_CR1_RTRG_24 (3 << SSI_CR1_RTRG_BIT)
1470 #define SSI_CR1_RTRG_32 (4 << SSI_CR1_RTRG_BIT)
1471 #define SSI_CR1_RTRG_40 (5 << SSI_CR1_RTRG_BIT)
1472 #define SSI_CR1_RTRG_48 (6 << SSI_CR1_RTRG_BIT)
1473 #define SSI_CR1_RTRG_56 (7 << SSI_CR1_RTRG_BIT)
1474 #define SSI_CR1_RTRG_64 (8 << SSI_CR1_RTRG_BIT)
1475 #define SSI_CR1_RTRG_72 (9 << SSI_CR1_RTRG_BIT)
1476 #define SSI_CR1_RTRG_80 (10<< SSI_CR1_RTRG_BIT)
1477 #define SSI_CR1_RTRG_88 (11<< SSI_CR1_RTRG_BIT)
1478 #define SSI_CR1_RTRG_96 (12<< SSI_CR1_RTRG_BIT)
1479 #define SSI_CR1_RTRG_104 (13<< SSI_CR1_RTRG_BIT)
1480 #define SSI_CR1_RTRG_112 (14<< SSI_CR1_RTRG_BIT)
1481 #define SSI_CR1_RTRG_120 (15<< SSI_CR1_RTRG_BIT)
1482 #define SSI_CR1_FLEN_BIT 4
1483 #define SSI_CR1_FLEN_MASK (0xf << SSI_CR1_FLEN_BIT)
1484 #define SSI_CR1_FLEN_2BIT (0x0 << SSI_CR1_FLEN_BIT)
1485 #define SSI_CR1_FLEN_3BIT (0x1 << SSI_CR1_FLEN_BIT)
1486 #define SSI_CR1_FLEN_4BIT (0x2 << SSI_CR1_FLEN_BIT)
1487 #define SSI_CR1_FLEN_5BIT (0x3 << SSI_CR1_FLEN_BIT)
1488 #define SSI_CR1_FLEN_6BIT (0x4 << SSI_CR1_FLEN_BIT)
1489 #define SSI_CR1_FLEN_7BIT (0x5 << SSI_CR1_FLEN_BIT)
1490 #define SSI_CR1_FLEN_8BIT (0x6 << SSI_CR1_FLEN_BIT)
1491 #define SSI_CR1_FLEN_9BIT (0x7 << SSI_CR1_FLEN_BIT)
1492 #define SSI_CR1_FLEN_10BIT (0x8 << SSI_CR1_FLEN_BIT)
1493 #define SSI_CR1_FLEN_11BIT (0x9 << SSI_CR1_FLEN_BIT)
1494 #define SSI_CR1_FLEN_12BIT (0xA << SSI_CR1_FLEN_BIT)
1495 #define SSI_CR1_FLEN_13BIT (0xB << SSI_CR1_FLEN_BIT)
1496 #define SSI_CR1_FLEN_14BIT (0xC << SSI_CR1_FLEN_BIT)
1497 #define SSI_CR1_FLEN_15BIT (0xD << SSI_CR1_FLEN_BIT)
1498 #define SSI_CR1_FLEN_16BIT (0xE << SSI_CR1_FLEN_BIT)
1499 #define SSI_CR1_FLEN_17BIT (0xF << SSI_CR1_FLEN_BIT)
1500 #define SSI_CR1_PHA (1 << 1)
1501 #define SSI_CR1_POL (1 << 0)
1503 /* SSI Status Register (SSI_SR) */
1505 #define SSI_SR_TFIFONUM_BIT 16
1506 #define SSI_SR_TFIFONUM_MASK (0xff << SSI_SR_TFIFONUM_BIT)
1507 #define SSI_SR_RFIFONUM_BIT 8
1508 #define SSI_SR_RFIFONUM_MASK (0xff << SSI_SR_RFIFONUM_BIT)
1509 #define SSI_SR_END (1 << 7)
1510 #define SSI_SR_BUSY (1 << 6)
1511 #define SSI_SR_TFF (1 << 5)
1512 #define SSI_SR_RFE (1 << 4)
1513 #define SSI_SR_TFHE (1 << 3)
1514 #define SSI_SR_RFHF (1 << 2)
1515 #define SSI_SR_UNDR (1 << 1)
1516 #define SSI_SR_OVER (1 << 0)
1518 /* SSI Interval Time Control Register (SSI_ITR) */
1520 #define SSI_ITR_CNTCLK (1 << 15)
1521 #define SSI_ITR_IVLTM_BIT 0
1522 #define SSI_ITR_IVLTM_MASK (0x7fff << SSI_ITR_IVLTM_BIT)
1525 /*************************************************************************
1526 * MSC
1527 *************************************************************************/
1528 #define MSC_STRPCL (MSC_BASE + 0x000)
1529 #define MSC_STAT (MSC_BASE + 0x004)
1530 #define MSC_CLKRT (MSC_BASE + 0x008)
1531 #define MSC_CMDAT (MSC_BASE + 0x00C)
1532 #define MSC_RESTO (MSC_BASE + 0x010)
1533 #define MSC_RDTO (MSC_BASE + 0x014)
1534 #define MSC_BLKLEN (MSC_BASE + 0x018)
1535 #define MSC_NOB (MSC_BASE + 0x01C)
1536 #define MSC_SNOB (MSC_BASE + 0x020)
1537 #define MSC_IMASK (MSC_BASE + 0x024)
1538 #define MSC_IREG (MSC_BASE + 0x028)
1539 #define MSC_CMD (MSC_BASE + 0x02C)
1540 #define MSC_ARG (MSC_BASE + 0x030)
1541 #define MSC_RES (MSC_BASE + 0x034)
1542 #define MSC_RXFIFO (MSC_BASE + 0x038)
1543 #define MSC_TXFIFO (MSC_BASE + 0x03C)
1545 #define REG_MSC_STRPCL REG16(MSC_STRPCL)
1546 #define REG_MSC_STAT REG32(MSC_STAT)
1547 #define REG_MSC_CLKRT REG16(MSC_CLKRT)
1548 #define REG_MSC_CMDAT REG32(MSC_CMDAT)
1549 #define REG_MSC_RESTO REG16(MSC_RESTO)
1550 #define REG_MSC_RDTO REG16(MSC_RDTO)
1551 #define REG_MSC_BLKLEN REG16(MSC_BLKLEN)
1552 #define REG_MSC_NOB REG16(MSC_NOB)
1553 #define REG_MSC_SNOB REG16(MSC_SNOB)
1554 #define REG_MSC_IMASK REG16(MSC_IMASK)
1555 #define REG_MSC_IREG REG16(MSC_IREG)
1556 #define REG_MSC_CMD REG8(MSC_CMD)
1557 #define REG_MSC_ARG REG32(MSC_ARG)
1558 #define REG_MSC_RES REG16(MSC_RES)
1559 #define REG_MSC_RXFIFO REG32(MSC_RXFIFO)
1560 #define REG_MSC_TXFIFO REG32(MSC_TXFIFO)
1562 /* MSC Clock and Control Register (MSC_STRPCL) */
1564 #define MSC_STRPCL_EXIT_MULTIPLE (1 << 7)
1565 #define MSC_STRPCL_EXIT_TRANSFER (1 << 6)
1566 #define MSC_STRPCL_START_READWAIT (1 << 5)
1567 #define MSC_STRPCL_STOP_READWAIT (1 << 4)
1568 #define MSC_STRPCL_RESET (1 << 3)
1569 #define MSC_STRPCL_START_OP (1 << 2)
1570 #define MSC_STRPCL_CLOCK_CONTROL_BIT 0
1571 #define MSC_STRPCL_CLOCK_CONTROL_MASK (0x3 << MSC_STRPCL_CLOCK_CONTROL_BIT)
1572 #define MSC_STRPCL_CLOCK_CONTROL_STOP (0x1 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Stop MMC/SD clock */
1573 #define MSC_STRPCL_CLOCK_CONTROL_START (0x2 << MSC_STRPCL_CLOCK_CONTROL_BIT) /* Start MMC/SD clock */
1575 /* MSC Status Register (MSC_STAT) */
1577 #define MSC_STAT_IS_RESETTING (1 << 15)
1578 #define MSC_STAT_SDIO_INT_ACTIVE (1 << 14)
1579 #define MSC_STAT_PRG_DONE (1 << 13)
1580 #define MSC_STAT_DATA_TRAN_DONE (1 << 12)
1581 #define MSC_STAT_END_CMD_RES (1 << 11)
1582 #define MSC_STAT_DATA_FIFO_AFULL (1 << 10)
1583 #define MSC_STAT_IS_READWAIT (1 << 9)
1584 #define MSC_STAT_CLK_EN (1 << 8)
1585 #define MSC_STAT_DATA_FIFO_FULL (1 << 7)
1586 #define MSC_STAT_DATA_FIFO_EMPTY (1 << 6)
1587 #define MSC_STAT_CRC_RES_ERR (1 << 5)
1588 #define MSC_STAT_CRC_READ_ERROR (1 << 4)
1589 #define MSC_STAT_CRC_WRITE_ERROR_BIT 2
1590 #define MSC_STAT_CRC_WRITE_ERROR_MASK (0x3 << MSC_STAT_CRC_WRITE_ERROR_BIT)
1591 #define MSC_STAT_CRC_WRITE_ERROR_NO (0 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No error on transmission of data */
1592 #define MSC_STAT_CRC_WRITE_ERROR (1 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* Card observed erroneous transmission of data */
1593 #define MSC_STAT_CRC_WRITE_ERROR_NOSTS (2 << MSC_STAT_CRC_WRITE_ERROR_BIT) /* No CRC status is sent back */
1594 #define MSC_STAT_TIME_OUT_RES (1 << 1)
1595 #define MSC_STAT_TIME_OUT_READ (1 << 0)
1597 /* MSC Bus Clock Control Register (MSC_CLKRT) */
1599 #define MSC_CLKRT_CLK_RATE_BIT 0
1600 #define MSC_CLKRT_CLK_RATE_MASK (0x7 << MSC_CLKRT_CLK_RATE_BIT)
1601 #define MSC_CLKRT_CLK_RATE_DIV_1 (0x0 << MSC_CLKRT_CLK_RATE_BIT) /* CLK_SRC */
1602 #define MSC_CLKRT_CLK_RATE_DIV_2 (0x1 << MSC_CLKRT_CLK_RATE_BIT) /* 1/2 of CLK_SRC */
1603 #define MSC_CLKRT_CLK_RATE_DIV_4 (0x2 << MSC_CLKRT_CLK_RATE_BIT) /* 1/4 of CLK_SRC */
1604 #define MSC_CLKRT_CLK_RATE_DIV_8 (0x3 << MSC_CLKRT_CLK_RATE_BIT) /* 1/8 of CLK_SRC */
1605 #define MSC_CLKRT_CLK_RATE_DIV_16 (0x4 << MSC_CLKRT_CLK_RATE_BIT) /* 1/16 of CLK_SRC */
1606 #define MSC_CLKRT_CLK_RATE_DIV_32 (0x5 << MSC_CLKRT_CLK_RATE_BIT) /* 1/32 of CLK_SRC */
1607 #define MSC_CLKRT_CLK_RATE_DIV_64 (0x6 << MSC_CLKRT_CLK_RATE_BIT) /* 1/64 of CLK_SRC */
1608 #define MSC_CLKRT_CLK_RATE_DIV_128 (0x7 << MSC_CLKRT_CLK_RATE_BIT) /* 1/128 of CLK_SRC */
1610 /* MSC Command Sequence Control Register (MSC_CMDAT) */
1612 #define MSC_CMDAT_IO_ABORT (1 << 11)
1613 #define MSC_CMDAT_BUS_WIDTH_BIT 9
1614 #define MSC_CMDAT_BUS_WIDTH_MASK (0x3 << MSC_CMDAT_BUS_WIDTH_BIT)
1615 #define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) /* 1-bit data bus */
1616 #define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) /* 4-bit data bus */
1617 #define CMDAT_BUS_WIDTH1 (0x0 << MSC_CMDAT_BUS_WIDTH_BIT)
1618 #define CMDAT_BUS_WIDTH4 (0x2 << MSC_CMDAT_BUS_WIDTH_BIT)
1619 #define MSC_CMDAT_DMA_EN (1 << 8)
1620 #define MSC_CMDAT_INIT (1 << 7)
1621 #define MSC_CMDAT_BUSY (1 << 6)
1622 #define MSC_CMDAT_STREAM_BLOCK (1 << 5)
1623 #define MSC_CMDAT_WRITE (1 << 4)
1624 #define MSC_CMDAT_READ (0 << 4)
1625 #define MSC_CMDAT_DATA_EN (1 << 3)
1626 #define MSC_CMDAT_RESPONSE_BIT 0
1627 #define MSC_CMDAT_RESPONSE_MASK (0x7 << MSC_CMDAT_RESPONSE_BIT)
1628 #define MSC_CMDAT_RESPONSE_NONE (0x0 << MSC_CMDAT_RESPONSE_BIT) /* No response */
1629 #define MSC_CMDAT_RESPONSE_R1 (0x1 << MSC_CMDAT_RESPONSE_BIT) /* Format R1 and R1b */
1630 #define MSC_CMDAT_RESPONSE_R2 (0x2 << MSC_CMDAT_RESPONSE_BIT) /* Format R2 */
1631 #define MSC_CMDAT_RESPONSE_R3 (0x3 << MSC_CMDAT_RESPONSE_BIT) /* Format R3 */
1632 #define MSC_CMDAT_RESPONSE_R4 (0x4 << MSC_CMDAT_RESPONSE_BIT) /* Format R4 */
1633 #define MSC_CMDAT_RESPONSE_R5 (0x5 << MSC_CMDAT_RESPONSE_BIT) /* Format R5 */
1634 #define MSC_CMDAT_RESPONSE_R6 (0x6 << MSC_CMDAT_RESPONSE_BIT) /* Format R6 */
1636 #define CMDAT_DMA_EN (1 << 8)
1637 #define CMDAT_INIT (1 << 7)
1638 #define CMDAT_BUSY (1 << 6)
1639 #define CMDAT_STREAM (1 << 5)
1640 #define CMDAT_WRITE (1 << 4)
1641 #define CMDAT_DATA_EN (1 << 3)
1643 /* MSC Interrupts Mask Register (MSC_IMASK) */
1645 #define MSC_IMASK_SDIO (1 << 7)
1646 #define MSC_IMASK_TXFIFO_WR_REQ (1 << 6)
1647 #define MSC_IMASK_RXFIFO_RD_REQ (1 << 5)
1648 #define MSC_IMASK_END_CMD_RES (1 << 2)
1649 #define MSC_IMASK_PRG_DONE (1 << 1)
1650 #define MSC_IMASK_DATA_TRAN_DONE (1 << 0)
1653 /* MSC Interrupts Status Register (MSC_IREG) */
1655 #define MSC_IREG_SDIO (1 << 7)
1656 #define MSC_IREG_TXFIFO_WR_REQ (1 << 6)
1657 #define MSC_IREG_RXFIFO_RD_REQ (1 << 5)
1658 #define MSC_IREG_END_CMD_RES (1 << 2)
1659 #define MSC_IREG_PRG_DONE (1 << 1)
1660 #define MSC_IREG_DATA_TRAN_DONE (1 << 0)
1663 /*************************************************************************
1664 * EMC (External Memory Controller)
1665 *************************************************************************/
1666 #define EMC_BCR (EMC_BASE + 0x0) /* BCR */
1668 #define EMC_SMCR0 (EMC_BASE + 0x10) /* Static Memory Control Register 0 */
1669 #define EMC_SMCR1 (EMC_BASE + 0x14) /* Static Memory Control Register 1 */
1670 #define EMC_SMCR2 (EMC_BASE + 0x18) /* Static Memory Control Register 2 */
1671 #define EMC_SMCR3 (EMC_BASE + 0x1c) /* Static Memory Control Register 3 */
1672 #define EMC_SMCR4 (EMC_BASE + 0x20) /* Static Memory Control Register 4 */
1673 #define EMC_SACR0 (EMC_BASE + 0x30) /* Static Memory Bank 0 Addr Config Reg */
1674 #define EMC_SACR1 (EMC_BASE + 0x34) /* Static Memory Bank 1 Addr Config Reg */
1675 #define EMC_SACR2 (EMC_BASE + 0x38) /* Static Memory Bank 2 Addr Config Reg */
1676 #define EMC_SACR3 (EMC_BASE + 0x3c) /* Static Memory Bank 3 Addr Config Reg */
1677 #define EMC_SACR4 (EMC_BASE + 0x40) /* Static Memory Bank 4 Addr Config Reg */
1679 #define EMC_NFCSR (EMC_BASE + 0x050) /* NAND Flash Control/Status Register */
1680 #define EMC_NFECR (EMC_BASE + 0x100) /* NAND Flash ECC Control Register */
1681 #define EMC_NFECC (EMC_BASE + 0x104) /* NAND Flash ECC Data Register */
1682 #define EMC_NFPAR0 (EMC_BASE + 0x108) /* NAND Flash RS Parity 0 Register */
1683 #define EMC_NFPAR1 (EMC_BASE + 0x10c) /* NAND Flash RS Parity 1 Register */
1684 #define EMC_NFPAR2 (EMC_BASE + 0x110) /* NAND Flash RS Parity 2 Register */
1685 #define EMC_NFINTS (EMC_BASE + 0x114) /* NAND Flash Interrupt Status Register */
1686 #define EMC_NFINTE (EMC_BASE + 0x118) /* NAND Flash Interrupt Enable Register */
1687 #define EMC_NFERR0 (EMC_BASE + 0x11c) /* NAND Flash RS Error Report 0 Register */
1688 #define EMC_NFERR1 (EMC_BASE + 0x120) /* NAND Flash RS Error Report 1 Register */
1689 #define EMC_NFERR2 (EMC_BASE + 0x124) /* NAND Flash RS Error Report 2 Register */
1690 #define EMC_NFERR3 (EMC_BASE + 0x128) /* NAND Flash RS Error Report 3 Register */
1692 #define EMC_DMCR (EMC_BASE + 0x80) /* DRAM Control Register */
1693 #define EMC_RTCSR (EMC_BASE + 0x84) /* Refresh Time Control/Status Register */
1694 #define EMC_RTCNT (EMC_BASE + 0x88) /* Refresh Timer Counter */
1695 #define EMC_RTCOR (EMC_BASE + 0x8c) /* Refresh Time Constant Register */
1696 #define EMC_DMAR0 (EMC_BASE + 0x90) /* SDRAM Bank 0 Addr Config Register */
1697 #define EMC_SDMR0 (EMC_BASE + 0xa000) /* Mode Register of SDRAM bank 0 */
1699 #define REG_EMC_BCR REG32(EMC_BCR)
1701 #define REG_EMC_SMCR0 REG32(EMC_SMCR0)
1702 #define REG_EMC_SMCR1 REG32(EMC_SMCR1)
1703 #define REG_EMC_SMCR2 REG32(EMC_SMCR2)
1704 #define REG_EMC_SMCR3 REG32(EMC_SMCR3)
1705 #define REG_EMC_SMCR4 REG32(EMC_SMCR4)
1706 #define REG_EMC_SACR0 REG32(EMC_SACR0)
1707 #define REG_EMC_SACR1 REG32(EMC_SACR1)
1708 #define REG_EMC_SACR2 REG32(EMC_SACR2)
1709 #define REG_EMC_SACR3 REG32(EMC_SACR3)
1710 #define REG_EMC_SACR4 REG32(EMC_SACR4)
1712 #define REG_EMC_NFCSR REG32(EMC_NFCSR)
1713 #define REG_EMC_NFECR REG32(EMC_NFECR)
1714 #define REG_EMC_NFECC REG32(EMC_NFECC)
1715 #define REG_EMC_NFPAR0 REG32(EMC_NFPAR0)
1716 #define REG_EMC_NFPAR1 REG32(EMC_NFPAR1)
1717 #define REG_EMC_NFPAR2 REG32(EMC_NFPAR2)
1718 #define REG_EMC_NFINTS REG32(EMC_NFINTS)
1719 #define REG_EMC_NFINTE REG32(EMC_NFINTE)
1720 #define REG_EMC_NFERR0 REG32(EMC_NFERR0)
1721 #define REG_EMC_NFERR1 REG32(EMC_NFERR1)
1722 #define REG_EMC_NFERR2 REG32(EMC_NFERR2)
1723 #define REG_EMC_NFERR3 REG32(EMC_NFERR3)
1725 #define REG_EMC_DMCR REG32(EMC_DMCR)
1726 #define REG_EMC_RTCSR REG16(EMC_RTCSR)
1727 #define REG_EMC_RTCNT REG16(EMC_RTCNT)
1728 #define REG_EMC_RTCOR REG16(EMC_RTCOR)
1729 #define REG_EMC_DMAR0 REG32(EMC_DMAR0)
1731 /* Static Memory Control Register */
1732 #define EMC_SMCR_STRV_BIT 24
1733 #define EMC_SMCR_STRV_MASK (0x0f << EMC_SMCR_STRV_BIT)
1734 #define EMC_SMCR_TAW_BIT 20
1735 #define EMC_SMCR_TAW_MASK (0x0f << EMC_SMCR_TAW_BIT)
1736 #define EMC_SMCR_TBP_BIT 16
1737 #define EMC_SMCR_TBP_MASK (0x0f << EMC_SMCR_TBP_BIT)
1738 #define EMC_SMCR_TAH_BIT 12
1739 #define EMC_SMCR_TAH_MASK (0x07 << EMC_SMCR_TAH_BIT)
1740 #define EMC_SMCR_TAS_BIT 8
1741 #define EMC_SMCR_TAS_MASK (0x07 << EMC_SMCR_TAS_BIT)
1742 #define EMC_SMCR_BW_BIT 6
1743 #define EMC_SMCR_BW_MASK (0x03 << EMC_SMCR_BW_BIT) /* Bus Width? */
1744 #define EMC_SMCR_BW_8BIT (0 << EMC_SMCR_BW_BIT)
1745 #define EMC_SMCR_BW_16BIT (1 << EMC_SMCR_BW_BIT)
1746 #define EMC_SMCR_BW_32BIT (2 << EMC_SMCR_BW_BIT)
1747 #define EMC_SMCR_BCM (1 << 3)
1748 #define EMC_SMCR_BL_BIT 1
1749 #define EMC_SMCR_BL_MASK (0x03 << EMC_SMCR_BL_BIT) /* Bus Latency? */
1750 #define EMC_SMCR_BL_4 (0 << EMC_SMCR_BL_BIT)
1751 #define EMC_SMCR_BL_8 (1 << EMC_SMCR_BL_BIT)
1752 #define EMC_SMCR_BL_16 (2 << EMC_SMCR_BL_BIT)
1753 #define EMC_SMCR_BL_32 (3 << EMC_SMCR_BL_BIT)
1754 #define EMC_SMCR_SMT (1 << 0)
1756 /* Static Memory Bank Addr Config Reg */
1757 #define EMC_SACR_BASE_BIT 8
1758 #define EMC_SACR_BASE_MASK (0xff << EMC_SACR_BASE_BIT)
1759 #define EMC_SACR_MASK_BIT 0
1760 #define EMC_SACR_MASK_MASK (0xff << EMC_SACR_MASK_BIT)
1762 /* NAND Flash Control/Status Register */
1763 #define EMC_NFCSR_NFCE4 (1 << 7) /* NAND Flash Enable */
1764 #define EMC_NFCSR_NFE4 (1 << 6) /* NAND Flash FCE# Assertion Enable */
1765 #define EMC_NFCSR_NFCE3 (1 << 5)
1766 #define EMC_NFCSR_NFE3 (1 << 4)
1767 #define EMC_NFCSR_NFCE2 (1 << 3)
1768 #define EMC_NFCSR_NFE2 (1 << 2)
1769 #define EMC_NFCSR_NFCE1 (1 << 1)
1770 #define EMC_NFCSR_NFE1 (1 << 0)
1771 #define EMC_NFCSR_NFE(n) (1 << (((n)-1)*2))
1772 #define EMC_NFCSR_NFCE(n) (1 << (((n)*2)-1))
1774 /* NAND Flash ECC Control Register */
1775 #define EMC_NFECR_PRDY (1 << 4) /* Parity Ready */
1776 #define EMC_NFECR_RS_DECODING (0 << 3) /* RS is in decoding phase */
1777 #define EMC_NFECR_RS_ENCODING (1 << 3) /* RS is in encoding phase */
1778 #define EMC_NFECR_HAMMING (0 << 2) /* Select HAMMING Correction Algorithm */
1779 #define EMC_NFECR_RS (1 << 2) /* Select RS Correction Algorithm */
1780 #define EMC_NFECR_ERST (1 << 1) /* ECC Reset */
1781 #define EMC_NFECR_ECCE (1 << 0) /* ECC Enable */
1783 /* NAND Flash ECC Data Register */
1784 #define EMC_NFECC_ECC2_BIT 16
1785 #define EMC_NFECC_ECC2_MASK (0xff << EMC_NFECC_ECC2_BIT)
1786 #define EMC_NFECC_ECC1_BIT 8
1787 #define EMC_NFECC_ECC1_MASK (0xff << EMC_NFECC_ECC1_BIT)
1788 #define EMC_NFECC_ECC0_BIT 0
1789 #define EMC_NFECC_ECC0_MASK (0xff << EMC_NFECC_ECC0_BIT)
1791 /* NAND Flash Interrupt Status Register */
1792 #define EMC_NFINTS_ERRCNT_BIT 29 /* Error Count */
1793 #define EMC_NFINTS_ERRCNT_MASK (0x7 << EMC_NFINTS_ERRCNT_BIT)
1794 #define EMC_NFINTS_PADF (1 << 4) /* Padding Finished */
1795 #define EMC_NFINTS_DECF (1 << 3) /* Decoding Finished */
1796 #define EMC_NFINTS_ENCF (1 << 2) /* Encoding Finished */
1797 #define EMC_NFINTS_UNCOR (1 << 1) /* Uncorrectable Error Occurred */
1798 #define EMC_NFINTS_ERR (1 << 0) /* Error Occurred */
1800 /* NAND Flash Interrupt Enable Register */
1801 #define EMC_NFINTE_PADFE (1 << 4) /* Padding Finished Interrupt Enable */
1802 #define EMC_NFINTE_DECFE (1 << 3) /* Decoding Finished Interrupt Enable */
1803 #define EMC_NFINTE_ENCFE (1 << 2) /* Encoding Finished Interrupt Enable */
1804 #define EMC_NFINTE_UNCORE (1 << 1) /* Uncorrectable Error Occurred Intr Enable */
1805 #define EMC_NFINTE_ERRE (1 << 0) /* Error Occurred Interrupt */
1807 /* NAND Flash RS Error Report Register */
1808 #define EMC_NFERR_INDEX_BIT 16 /* Error Symbol Index */
1809 #define EMC_NFERR_INDEX_MASK (0x1ff << EMC_NFERR_INDEX_BIT)
1810 #define EMC_NFERR_MASK_BIT 0 /* Error Symbol Value */
1811 #define EMC_NFERR_MASK_MASK (0x1ff << EMC_NFERR_MASK_BIT)
1814 /* DRAM Control Register */
1815 #define EMC_DMCR_BW_BIT 31
1816 #define EMC_DMCR_BW (1 << EMC_DMCR_BW_BIT)
1817 #define EMC_DMCR_CA_BIT 26
1818 #define EMC_DMCR_CA_MASK (0x07 << EMC_DMCR_CA_BIT)
1819 #define EMC_DMCR_CA_8 (0 << EMC_DMCR_CA_BIT)
1820 #define EMC_DMCR_CA_9 (1 << EMC_DMCR_CA_BIT)
1821 #define EMC_DMCR_CA_10 (2 << EMC_DMCR_CA_BIT)
1822 #define EMC_DMCR_CA_11 (3 << EMC_DMCR_CA_BIT)
1823 #define EMC_DMCR_CA_12 (4 << EMC_DMCR_CA_BIT)
1824 #define EMC_DMCR_RMODE (1 << 25)
1825 #define EMC_DMCR_RFSH (1 << 24)
1826 #define EMC_DMCR_MRSET (1 << 23)
1827 #define EMC_DMCR_RA_BIT 20
1828 #define EMC_DMCR_RA_MASK (0x03 << EMC_DMCR_RA_BIT)
1829 #define EMC_DMCR_RA_11 (0 << EMC_DMCR_RA_BIT)
1830 #define EMC_DMCR_RA_12 (1 << EMC_DMCR_RA_BIT)
1831 #define EMC_DMCR_RA_13 (2 << EMC_DMCR_RA_BIT)
1832 #define EMC_DMCR_BA_BIT 19
1833 #define EMC_DMCR_BA (1 << EMC_DMCR_BA_BIT)
1834 #define EMC_DMCR_PDM (1 << 18)
1835 #define EMC_DMCR_EPIN (1 << 17)
1836 #define EMC_DMCR_TRAS_BIT 13
1837 #define EMC_DMCR_TRAS_MASK (0x07 << EMC_DMCR_TRAS_BIT)
1838 #define EMC_DMCR_RCD_BIT 11
1839 #define EMC_DMCR_RCD_MASK (0x03 << EMC_DMCR_RCD_BIT)
1840 #define EMC_DMCR_TPC_BIT 8
1841 #define EMC_DMCR_TPC_MASK (0x07 << EMC_DMCR_TPC_BIT)
1842 #define EMC_DMCR_TRWL_BIT 5
1843 #define EMC_DMCR_TRWL_MASK (0x03 << EMC_DMCR_TRWL_BIT)
1844 #define EMC_DMCR_TRC_BIT 2
1845 #define EMC_DMCR_TRC_MASK (0x07 << EMC_DMCR_TRC_BIT)
1846 #define EMC_DMCR_TCL_BIT 0
1847 #define EMC_DMCR_TCL_MASK (0x03 << EMC_DMCR_TCL_BIT)
1849 /* Refresh Time Control/Status Register */
1850 #define EMC_RTCSR_CMF (1 << 7)
1851 #define EMC_RTCSR_CKS_BIT 0
1852 #define EMC_RTCSR_CKS_MASK (0x07 << EMC_RTCSR_CKS_BIT)
1853 #define EMC_RTCSR_CKS_DISABLE (0 << EMC_RTCSR_CKS_BIT)
1854 #define EMC_RTCSR_CKS_4 (1 << EMC_RTCSR_CKS_BIT)
1855 #define EMC_RTCSR_CKS_16 (2 << EMC_RTCSR_CKS_BIT)
1856 #define EMC_RTCSR_CKS_64 (3 << EMC_RTCSR_CKS_BIT)
1857 #define EMC_RTCSR_CKS_256 (4 << EMC_RTCSR_CKS_BIT)
1858 #define EMC_RTCSR_CKS_1024 (5 << EMC_RTCSR_CKS_BIT)
1859 #define EMC_RTCSR_CKS_2048 (6 << EMC_RTCSR_CKS_BIT)
1860 #define EMC_RTCSR_CKS_4096 (7 << EMC_RTCSR_CKS_BIT)
1862 /* SDRAM Bank Address Configuration Register */
1863 #define EMC_DMAR_BASE_BIT 8
1864 #define EMC_DMAR_BASE_MASK (0xff << EMC_DMAR_BASE_BIT)
1865 #define EMC_DMAR_MASK_BIT 0
1866 #define EMC_DMAR_MASK_MASK (0xff << EMC_DMAR_MASK_BIT)
1868 /* Mode Register of SDRAM bank 0 */
1869 #define EMC_SDMR_BM (1 << 9) /* Write Burst Mode */
1870 #define EMC_SDMR_OM_BIT 7 /* Operating Mode */
1871 #define EMC_SDMR_OM_MASK (3 << EMC_SDMR_OM_BIT)
1872 #define EMC_SDMR_OM_NORMAL (0 << EMC_SDMR_OM_BIT)
1873 #define EMC_SDMR_CAS_BIT 4 /* CAS Latency */
1874 #define EMC_SDMR_CAS_MASK (7 << EMC_SDMR_CAS_BIT)
1875 #define EMC_SDMR_CAS_1 (1 << EMC_SDMR_CAS_BIT)
1876 #define EMC_SDMR_CAS_2 (2 << EMC_SDMR_CAS_BIT)
1877 #define EMC_SDMR_CAS_3 (3 << EMC_SDMR_CAS_BIT)
1878 #define EMC_SDMR_BT_BIT 3 /* Burst Type */
1879 #define EMC_SDMR_BT_MASK (1 << EMC_SDMR_BT_BIT)
1880 #define EMC_SDMR_BT_SEQ (0 << EMC_SDMR_BT_BIT) /* Sequential */
1881 #define EMC_SDMR_BT_INT (1 << EMC_SDMR_BT_BIT) /* Interleave */
1882 #define EMC_SDMR_BL_BIT 0 /* Burst Length */
1883 #define EMC_SDMR_BL_MASK (7 << EMC_SDMR_BL_BIT)
1884 #define EMC_SDMR_BL_1 (0 << EMC_SDMR_BL_BIT)
1885 #define EMC_SDMR_BL_2 (1 << EMC_SDMR_BL_BIT)
1886 #define EMC_SDMR_BL_4 (2 << EMC_SDMR_BL_BIT)
1887 #define EMC_SDMR_BL_8 (3 << EMC_SDMR_BL_BIT)
1889 #define EMC_SDMR_CAS2_16BIT \
1890 (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
1891 #define EMC_SDMR_CAS2_32BIT \
1892 (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
1893 #define EMC_SDMR_CAS3_16BIT \
1894 (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
1895 #define EMC_SDMR_CAS3_32BIT \
1896 (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
1899 /*************************************************************************
1900 * CIM
1901 *************************************************************************/
1902 #define CIM_CFG (CIM_BASE + 0x0000)
1903 #define CIM_CTRL (CIM_BASE + 0x0004)
1904 #define CIM_STATE (CIM_BASE + 0x0008)
1905 #define CIM_IID (CIM_BASE + 0x000C)
1906 #define CIM_RXFIFO (CIM_BASE + 0x0010)
1907 #define CIM_DA (CIM_BASE + 0x0020)
1908 #define CIM_FA (CIM_BASE + 0x0024)
1909 #define CIM_FID (CIM_BASE + 0x0028)
1910 #define CIM_CMD (CIM_BASE + 0x002C)
1912 #define REG_CIM_CFG REG32(CIM_CFG)
1913 #define REG_CIM_CTRL REG32(CIM_CTRL)
1914 #define REG_CIM_STATE REG32(CIM_STATE)
1915 #define REG_CIM_IID REG32(CIM_IID)
1916 #define REG_CIM_RXFIFO REG32(CIM_RXFIFO)
1917 #define REG_CIM_DA REG32(CIM_DA)
1918 #define REG_CIM_FA REG32(CIM_FA)
1919 #define REG_CIM_FID REG32(CIM_FID)
1920 #define REG_CIM_CMD REG32(CIM_CMD)
1922 /* CIM Configuration Register (CIM_CFG) */
1924 #define CIM_CFG_INV_DAT (1 << 15)
1925 #define CIM_CFG_VSP (1 << 14)
1926 #define CIM_CFG_HSP (1 << 13)
1927 #define CIM_CFG_PCP (1 << 12)
1928 #define CIM_CFG_DUMMY_ZERO (1 << 9)
1929 #define CIM_CFG_EXT_VSYNC (1 << 8)
1930 #define CIM_CFG_PACK_BIT 4
1931 #define CIM_CFG_PACK_MASK (0x7 << CIM_CFG_PACK_BIT)
1932 #define CIM_CFG_PACK_0 (0 << CIM_CFG_PACK_BIT)
1933 #define CIM_CFG_PACK_1 (1 << CIM_CFG_PACK_BIT)
1934 #define CIM_CFG_PACK_2 (2 << CIM_CFG_PACK_BIT)
1935 #define CIM_CFG_PACK_3 (3 << CIM_CFG_PACK_BIT)
1936 #define CIM_CFG_PACK_4 (4 << CIM_CFG_PACK_BIT)
1937 #define CIM_CFG_PACK_5 (5 << CIM_CFG_PACK_BIT)
1938 #define CIM_CFG_PACK_6 (6 << CIM_CFG_PACK_BIT)
1939 #define CIM_CFG_PACK_7 (7 << CIM_CFG_PACK_BIT)
1940 #define CIM_CFG_DSM_BIT 0
1941 #define CIM_CFG_DSM_MASK (0x3 << CIM_CFG_DSM_BIT)
1942 #define CIM_CFG_DSM_CPM (0 << CIM_CFG_DSM_BIT) /* CCIR656 Progressive Mode */
1943 #define CIM_CFG_DSM_CIM (1 << CIM_CFG_DSM_BIT) /* CCIR656 Interlace Mode */
1944 #define CIM_CFG_DSM_GCM (2 << CIM_CFG_DSM_BIT) /* Gated Clock Mode */
1945 #define CIM_CFG_DSM_NGCM (3 << CIM_CFG_DSM_BIT) /* Non-Gated Clock Mode */
1947 /* CIM Control Register (CIM_CTRL) */
1949 #define CIM_CTRL_MCLKDIV_BIT 24
1950 #define CIM_CTRL_MCLKDIV_MASK (0xff << CIM_CTRL_MCLKDIV_BIT)
1951 #define CIM_CTRL_FRC_BIT 16
1952 #define CIM_CTRL_FRC_MASK (0xf << CIM_CTRL_FRC_BIT)
1953 #define CIM_CTRL_FRC_1 (0x0 << CIM_CTRL_FRC_BIT) /* Sample every frame */
1954 #define CIM_CTRL_FRC_2 (0x1 << CIM_CTRL_FRC_BIT) /* Sample 1/2 frame */
1955 #define CIM_CTRL_FRC_3 (0x2 << CIM_CTRL_FRC_BIT) /* Sample 1/3 frame */
1956 #define CIM_CTRL_FRC_4 (0x3 << CIM_CTRL_FRC_BIT) /* Sample 1/4 frame */
1957 #define CIM_CTRL_FRC_5 (0x4 << CIM_CTRL_FRC_BIT) /* Sample 1/5 frame */
1958 #define CIM_CTRL_FRC_6 (0x5 << CIM_CTRL_FRC_BIT) /* Sample 1/6 frame */
1959 #define CIM_CTRL_FRC_7 (0x6 << CIM_CTRL_FRC_BIT) /* Sample 1/7 frame */
1960 #define CIM_CTRL_FRC_8 (0x7 << CIM_CTRL_FRC_BIT) /* Sample 1/8 frame */
1961 #define CIM_CTRL_FRC_9 (0x8 << CIM_CTRL_FRC_BIT) /* Sample 1/9 frame */
1962 #define CIM_CTRL_FRC_10 (0x9 << CIM_CTRL_FRC_BIT) /* Sample 1/10 frame */
1963 #define CIM_CTRL_FRC_11 (0xA << CIM_CTRL_FRC_BIT) /* Sample 1/11 frame */
1964 #define CIM_CTRL_FRC_12 (0xB << CIM_CTRL_FRC_BIT) /* Sample 1/12 frame */
1965 #define CIM_CTRL_FRC_13 (0xC << CIM_CTRL_FRC_BIT) /* Sample 1/13 frame */
1966 #define CIM_CTRL_FRC_14 (0xD << CIM_CTRL_FRC_BIT) /* Sample 1/14 frame */
1967 #define CIM_CTRL_FRC_15 (0xE << CIM_CTRL_FRC_BIT) /* Sample 1/15 frame */
1968 #define CIM_CTRL_FRC_16 (0xF << CIM_CTRL_FRC_BIT) /* Sample 1/16 frame */
1969 #define CIM_CTRL_VDDM (1 << 13)
1970 #define CIM_CTRL_DMA_SOFM (1 << 12)
1971 #define CIM_CTRL_DMA_EOFM (1 << 11)
1972 #define CIM_CTRL_DMA_STOPM (1 << 10)
1973 #define CIM_CTRL_RXF_TRIGM (1 << 9)
1974 #define CIM_CTRL_RXF_OFM (1 << 8)
1975 #define CIM_CTRL_RXF_TRIG_BIT 4
1976 #define CIM_CTRL_RXF_TRIG_MASK (0x7 << CIM_CTRL_RXF_TRIG_BIT)
1977 #define CIM_CTRL_RXF_TRIG_4 (0 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 4 */
1978 #define CIM_CTRL_RXF_TRIG_8 (1 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 8 */
1979 #define CIM_CTRL_RXF_TRIG_12 (2 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 12 */
1980 #define CIM_CTRL_RXF_TRIG_16 (3 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 16 */
1981 #define CIM_CTRL_RXF_TRIG_20 (4 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 20 */
1982 #define CIM_CTRL_RXF_TRIG_24 (5 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 24 */
1983 #define CIM_CTRL_RXF_TRIG_28 (6 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 28 */
1984 #define CIM_CTRL_RXF_TRIG_32 (7 << CIM_CTRL_RXF_TRIG_BIT) /* RXFIFO Trigger Value is 32 */
1985 #define CIM_CTRL_DMA_EN (1 << 2)
1986 #define CIM_CTRL_RXF_RST (1 << 1)
1987 #define CIM_CTRL_ENA (1 << 0)
1989 /* CIM State Register (CIM_STATE) */
1991 #define CIM_STATE_DMA_SOF (1 << 6)
1992 #define CIM_STATE_DMA_EOF (1 << 5)
1993 #define CIM_STATE_DMA_STOP (1 << 4)
1994 #define CIM_STATE_RXF_OF (1 << 3)
1995 #define CIM_STATE_RXF_TRIG (1 << 2)
1996 #define CIM_STATE_RXF_EMPTY (1 << 1)
1997 #define CIM_STATE_VDD (1 << 0)
1999 /* CIM DMA Command Register (CIM_CMD) */
2001 #define CIM_CMD_SOFINT (1 << 31)
2002 #define CIM_CMD_EOFINT (1 << 30)
2003 #define CIM_CMD_STOP (1 << 28)
2004 #define CIM_CMD_LEN_BIT 0
2005 #define CIM_CMD_LEN_MASK (0xffffff << CIM_CMD_LEN_BIT)
2008 /*************************************************************************
2009 * SADC (Smart A/D Controller)
2010 *************************************************************************/
2012 #define SADC_ENA (SADC_BASE + 0x00) /* ADC Enable Register */
2013 #define SADC_CFG (SADC_BASE + 0x04) /* ADC Configure Register */
2014 #define SADC_CTRL (SADC_BASE + 0x08) /* ADC Control Register */
2015 #define SADC_STATE (SADC_BASE + 0x0C) /* ADC Status Register*/
2016 #define SADC_SAMETIME (SADC_BASE + 0x10) /* ADC Same Point Time Register */
2017 #define SADC_WAITTIME (SADC_BASE + 0x14) /* ADC Wait Time Register */
2018 #define SADC_TSDAT (SADC_BASE + 0x18) /* ADC Touch Screen Data Register */
2019 #define SADC_BATDAT (SADC_BASE + 0x1C) /* ADC PBAT Data Register */
2020 #define SADC_SADDAT (SADC_BASE + 0x20) /* ADC SADCIN Data Register */
2022 #define REG_SADC_ENA REG8(SADC_ENA)
2023 #define REG_SADC_CFG REG32(SADC_CFG)
2024 #define REG_SADC_CTRL REG8(SADC_CTRL)
2025 #define REG_SADC_STATE REG8(SADC_STATE)
2026 #define REG_SADC_SAMETIME REG16(SADC_SAMETIME)
2027 #define REG_SADC_WAITTIME REG16(SADC_WAITTIME)
2028 #define REG_SADC_TSDAT REG32(SADC_TSDAT)
2029 #define REG_SADC_BATDAT REG16(SADC_BATDAT)
2030 #define REG_SADC_SADDAT REG16(SADC_SADDAT)
2032 /* ADC Enable Register */
2033 #define SADC_ENA_ADEN (1 << 7) /* Touch Screen Enable */
2034 #define SADC_ENA_TSEN (1 << 2) /* Touch Screen Enable */
2035 #define SADC_ENA_PBATEN (1 << 1) /* PBAT Enable */
2036 #define SADC_ENA_SADCINEN (1 << 0) /* SADCIN Enable */
2038 /* ADC Configure Register */
2039 #define SADC_CFG_CLKOUT_NUM_BIT 16
2040 #define SADC_CFG_CLKOUT_NUM_MASK (0x7 << SADC_CFG_CLKOUT_NUM_BIT)
2041 #define SADC_CFG_TS_DMA (1 << 15) /* Touch Screen DMA Enable */
2042 #define SADC_CFG_XYZ_BIT 13 /* XYZ selection */
2043 #define SADC_CFG_XYZ_MASK (0x3 << SADC_CFG_XYZ_BIT)
2044 #define SADC_CFG_XY (0 << SADC_CFG_XYZ_BIT)
2045 #define SADC_CFG_XYZ (1 << SADC_CFG_XYZ_BIT)
2046 #define SADC_CFG_XYZ1Z2 (2 << SADC_CFG_XYZ_BIT)
2047 #define SADC_CFG_SNUM_BIT 10 /* Sample Number */
2048 #define SADC_CFG_SNUM_MASK (0x7 << SADC_CFG_SNUM_BIT)
2049 #define SADC_CFG_SNUM_1 (0x0 << SADC_CFG_SNUM_BIT)
2050 #define SADC_CFG_SNUM_2 (0x1 << SADC_CFG_SNUM_BIT)
2051 #define SADC_CFG_SNUM_3 (0x2 << SADC_CFG_SNUM_BIT)
2052 #define SADC_CFG_SNUM_4 (0x3 << SADC_CFG_SNUM_BIT)
2053 #define SADC_CFG_SNUM_5 (0x4 << SADC_CFG_SNUM_BIT)
2054 #define SADC_CFG_SNUM_6 (0x5 << SADC_CFG_SNUM_BIT)
2055 #define SADC_CFG_SNUM_8 (0x6 << SADC_CFG_SNUM_BIT)
2056 #define SADC_CFG_SNUM_9 (0x7 << SADC_CFG_SNUM_BIT)
2057 #define SADC_CFG_CLKDIV_BIT 5 /* AD Converter frequency clock divider */
2058 #define SADC_CFG_CLKDIV_MASK (0x1f << SADC_CFG_CLKDIV_BIT)
2059 #define SADC_CFG_PBAT_HIGH (0 << 4) /* PBAT >= 2.5V */
2060 #define SADC_CFG_PBAT_LOW (1 << 4) /* PBAT < 2.5V */
2061 #define SADC_CFG_CMD_BIT 0 /* ADC Command */
2062 #define SADC_CFG_CMD_MASK (0xf << SADC_CFG_CMD_BIT)
2063 #define SADC_CFG_CMD_X_SE (0x0 << SADC_CFG_CMD_BIT) /* X Single-End */
2064 #define SADC_CFG_CMD_Y_SE (0x1 << SADC_CFG_CMD_BIT) /* Y Single-End */
2065 #define SADC_CFG_CMD_X_DIFF (0x2 << SADC_CFG_CMD_BIT) /* X Differential */
2066 #define SADC_CFG_CMD_Y_DIFF (0x3 << SADC_CFG_CMD_BIT) /* Y Differential */
2067 #define SADC_CFG_CMD_Z1_DIFF (0x4 << SADC_CFG_CMD_BIT) /* Z1 Differential */
2068 #define SADC_CFG_CMD_Z2_DIFF (0x5 << SADC_CFG_CMD_BIT) /* Z2 Differential */
2069 #define SADC_CFG_CMD_Z3_DIFF (0x6 << SADC_CFG_CMD_BIT) /* Z3 Differential */
2070 #define SADC_CFG_CMD_Z4_DIFF (0x7 << SADC_CFG_CMD_BIT) /* Z4 Differential */
2071 #define SADC_CFG_CMD_TP_SE (0x8 << SADC_CFG_CMD_BIT) /* Touch Pressure */
2072 #define SADC_CFG_CMD_PBATH_SE (0x9 << SADC_CFG_CMD_BIT) /* PBAT >= 2.5V */
2073 #define SADC_CFG_CMD_PBATL_SE (0xa << SADC_CFG_CMD_BIT) /* PBAT < 2.5V */
2074 #define SADC_CFG_CMD_SADCIN_SE (0xb << SADC_CFG_CMD_BIT) /* Measure SADCIN */
2075 #define SADC_CFG_CMD_INT_PEN (0xc << SADC_CFG_CMD_BIT) /* INT_PEN Enable */
2077 /* ADC Control Register */
2078 #define SADC_CTRL_PENDM (1 << 4) /* Pen Down Interrupt Mask */
2079 #define SADC_CTRL_PENUM (1 << 3) /* Pen Up Interrupt Mask */
2080 #define SADC_CTRL_TSRDYM (1 << 2) /* Touch Screen Data Ready Interrupt Mask */
2081 #define SADC_CTRL_PBATRDYM (1 << 1) /* PBAT Data Ready Interrupt Mask */
2082 #define SADC_CTRL_SRDYM (1 << 0) /* SADCIN Data Ready Interrupt Mask */
2084 /* ADC Status Register */
2085 #define SADC_STATE_TSBUSY (1 << 7) /* TS A/D is working */
2086 #define SADC_STATE_PBATBUSY (1 << 6) /* PBAT A/D is working */
2087 #define SADC_STATE_SBUSY (1 << 5) /* SADCIN A/D is working */
2088 #define SADC_STATE_PEND (1 << 4) /* Pen Down Interrupt Flag */
2089 #define SADC_STATE_PENU (1 << 3) /* Pen Up Interrupt Flag */
2090 #define SADC_STATE_TSRDY (1 << 2) /* Touch Screen Data Ready Interrupt Flag */
2091 #define SADC_STATE_PBATRDY (1 << 1) /* PBAT Data Ready Interrupt Flag */
2092 #define SADC_STATE_SRDY (1 << 0) /* SADCIN Data Ready Interrupt Flag */
2094 /* ADC Touch Screen Data Register */
2095 #define SADC_TSDAT_DATA0_BIT 0
2096 #define SADC_TSDAT_DATA0_MASK (0xfff << SADC_TSDAT_DATA0_BIT)
2097 #define SADC_TSDAT_TYPE0 (1 << 15)
2098 #define SADC_TSDAT_DATA1_BIT 16
2099 #define SADC_TSDAT_DATA1_MASK (0xfff << SADC_TSDAT_DATA1_BIT)
2100 #define SADC_TSDAT_TYPE1 (1 << 31)
2103 /*************************************************************************
2104 * SLCD (Smart LCD Controller)
2105 *************************************************************************/
2107 #define SLCD_CFG (SLCD_BASE + 0xA0) /* SLCD Configure Register */
2108 #define SLCD_CTRL (SLCD_BASE + 0xA4) /* SLCD Control Register */
2109 #define SLCD_STATE (SLCD_BASE + 0xA8) /* SLCD Status Register */
2110 #define SLCD_DATA (SLCD_BASE + 0xAC) /* SLCD Data Register */
2111 #define SLCD_FIFO (SLCD_BASE + 0xB0) /* SLCD FIFO Register */
2113 #define REG_SLCD_CFG REG32(SLCD_CFG)
2114 #define REG_SLCD_CTRL REG8(SLCD_CTRL)
2115 #define REG_SLCD_STATE REG8(SLCD_STATE)
2116 #define REG_SLCD_DATA REG32(SLCD_DATA)
2117 #define REG_SLCD_FIFO REG32(SLCD_FIFO)
2119 /* SLCD Configure Register */
2120 #define SLCD_CFG_BURST_BIT 14
2121 #define SLCD_CFG_BURST_MASK (0x3 << SLCD_CFG_BURST_BIT)
2122 #define SLCD_CFG_BURST_4_WORD (0 << SLCD_CFG_BURST_BIT)
2123 #define SLCD_CFG_BURST_8_WORD (1 << SLCD_CFG_BURST_BIT)
2124 #define SLCD_CFG_DWIDTH_BIT 10
2125 #define SLCD_CFG_DWIDTH_MASK (0x7 << SLCD_CFG_DWIDTH_BIT)
2126 #define SLCD_CFG_DWIDTH_18 (0 << SLCD_CFG_DWIDTH_BIT)
2127 #define SLCD_CFG_DWIDTH_16 (1 << SLCD_CFG_DWIDTH_BIT)
2128 #define SLCD_CFG_DWIDTH_8_x3 (2 << SLCD_CFG_DWIDTH_BIT)
2129 #define SLCD_CFG_DWIDTH_8_x2 (3 << SLCD_CFG_DWIDTH_BIT)
2130 #define SLCD_CFG_DWIDTH_8_x1 (4 << SLCD_CFG_DWIDTH_BIT)
2131 #define SLCD_CFG_DWIDTH_9_x2 (7 << SLCD_CFG_DWIDTH_BIT)
2132 #define SLCD_CFG_CWIDTH_BIT 8
2133 #define SLCD_CFG_CWIDTH_MASK (0x3 << SLCD_CFG_CWIDTH_BIT)
2134 #define SLCD_CFG_CWIDTH_16BIT (0 << SLCD_CFG_CWIDTH_BIT)
2135 #define SLCD_CFG_CWIDTH_8BIT (1 << SLCD_CFG_CWIDTH_BIT)
2136 #define SLCD_CFG_CWIDTH_18BIT (2 << SLCD_CFG_CWIDTH_BIT)
2137 #define SLCD_CFG_CS_ACTIVE_LOW (0 << 4)
2138 #define SLCD_CFG_CS_ACTIVE_HIGH (1 << 4)
2139 #define SLCD_CFG_RS_CMD_LOW (0 << 3)
2140 #define SLCD_CFG_RS_CMD_HIGH (1 << 3)
2141 #define SLCD_CFG_CLK_ACTIVE_FALLING (0 << 1)
2142 #define SLCD_CFG_CLK_ACTIVE_RISING (1 << 1)
2143 #define SLCD_CFG_TYPE_PARALLEL (0 << 0)
2144 #define SLCD_CFG_TYPE_SERIAL (1 << 0)
2146 /* SLCD Control Register */
2147 #define SLCD_CTRL_DMA_EN (1 << 0)
2149 /* SLCD Status Register */
2150 #define SLCD_STATE_BUSY (1 << 0)
2152 /* SLCD Data Register */
2153 #define SLCD_DATA_RS_DATA (0 << 31)
2154 #define SLCD_DATA_RS_COMMAND (1 << 31)
2156 /* SLCD FIFO Register */
2157 #define SLCD_FIFO_RS_DATA (0 << 31)
2158 #define SLCD_FIFO_RS_COMMAND (1 << 31)
2161 /*************************************************************************
2162 * LCD (LCD Controller)
2163 *************************************************************************/
2164 #define LCD_CFG (LCD_BASE + 0x00) /* LCD Configure Register */
2165 #define LCD_VSYNC (LCD_BASE + 0x04) /* Vertical Synchronize Register */
2166 #define LCD_HSYNC (LCD_BASE + 0x08) /* Horizontal Synchronize Register */
2167 #define LCD_VAT (LCD_BASE + 0x0c) /* Virtual Area Setting Register */
2168 #define LCD_DAH (LCD_BASE + 0x10) /* Display Area Horizontal Start/End Point */
2169 #define LCD_DAV (LCD_BASE + 0x14) /* Display Area Vertical Start/End Point */
2170 #define LCD_PS (LCD_BASE + 0x18) /* PS Signal Setting */
2171 #define LCD_CLS (LCD_BASE + 0x1c) /* CLS Signal Setting */
2172 #define LCD_SPL (LCD_BASE + 0x20) /* SPL Signal Setting */
2173 #define LCD_REV (LCD_BASE + 0x24) /* REV Signal Setting */
2174 #define LCD_CTRL (LCD_BASE + 0x30) /* LCD Control Register */
2175 #define LCD_STATE (LCD_BASE + 0x34) /* LCD Status Register */
2176 #define LCD_IID (LCD_BASE + 0x38) /* Interrupt ID Register */
2177 #define LCD_DA0 (LCD_BASE + 0x40) /* Descriptor Address Register 0 */
2178 #define LCD_SA0 (LCD_BASE + 0x44) /* Source Address Register 0 */
2179 #define LCD_FID0 (LCD_BASE + 0x48) /* Frame ID Register 0 */
2180 #define LCD_CMD0 (LCD_BASE + 0x4c) /* DMA Command Register 0 */
2181 #define LCD_DA1 (LCD_BASE + 0x50) /* Descriptor Address Register 1 */
2182 #define LCD_SA1 (LCD_BASE + 0x54) /* Source Address Register 1 */
2183 #define LCD_FID1 (LCD_BASE + 0x58) /* Frame ID Register 1 */
2184 #define LCD_CMD1 (LCD_BASE + 0x5c) /* DMA Command Register 1 */
2186 #define REG_LCD_CFG REG32(LCD_CFG)
2187 #define REG_LCD_VSYNC REG32(LCD_VSYNC)
2188 #define REG_LCD_HSYNC REG32(LCD_HSYNC)
2189 #define REG_LCD_VAT REG32(LCD_VAT)
2190 #define REG_LCD_DAH REG32(LCD_DAH)
2191 #define REG_LCD_DAV REG32(LCD_DAV)
2192 #define REG_LCD_PS REG32(LCD_PS)
2193 #define REG_LCD_CLS REG32(LCD_CLS)
2194 #define REG_LCD_SPL REG32(LCD_SPL)
2195 #define REG_LCD_REV REG32(LCD_REV)
2196 #define REG_LCD_CTRL REG32(LCD_CTRL)
2197 #define REG_LCD_STATE REG32(LCD_STATE)
2198 #define REG_LCD_IID REG32(LCD_IID)
2199 #define REG_LCD_DA0 REG32(LCD_DA0)
2200 #define REG_LCD_SA0 REG32(LCD_SA0)
2201 #define REG_LCD_FID0 REG32(LCD_FID0)
2202 #define REG_LCD_CMD0 REG32(LCD_CMD0)
2203 #define REG_LCD_DA1 REG32(LCD_DA1)
2204 #define REG_LCD_SA1 REG32(LCD_SA1)
2205 #define REG_LCD_FID1 REG32(LCD_FID1)
2206 #define REG_LCD_CMD1 REG32(LCD_CMD1)
2208 /* LCD Configure Register */
2209 #define LCD_CFG_LCDPIN_BIT 31 /* LCD pins selection */
2210 #define LCD_CFG_LCDPIN_MASK (0x1 << LCD_CFG_LCDPIN_BIT)
2211 #define LCD_CFG_LCDPIN_LCD (0x0 << LCD_CFG_LCDPIN_BIT)
2212 #define LCD_CFG_LCDPIN_SLCD (0x1 << LCD_CFG_LCDPIN_BIT)
2213 #define LCD_CFG_PSM (1 << 23) /* PS signal mode */
2214 #define LCD_CFG_CLSM (1 << 22) /* CLS signal mode */
2215 #define LCD_CFG_SPLM (1 << 21) /* SPL signal mode */
2216 #define LCD_CFG_REVM (1 << 20) /* REV signal mode */
2217 #define LCD_CFG_HSYNM (1 << 19) /* HSYNC signal mode */
2218 #define LCD_CFG_PCLKM (1 << 18) /* PCLK signal mode */
2219 #define LCD_CFG_INVDAT (1 << 17) /* Inverse output data */
2220 #define LCD_CFG_SYNDIR_IN (1 << 16) /* VSYNC&HSYNC direction */
2221 #define LCD_CFG_PSP (1 << 15) /* PS pin reset state */
2222 #define LCD_CFG_CLSP (1 << 14) /* CLS pin reset state */
2223 #define LCD_CFG_SPLP (1 << 13) /* SPL pin reset state */
2224 #define LCD_CFG_REVP (1 << 12) /* REV pin reset state */
2225 #define LCD_CFG_HSP (1 << 11) /* HSYNC pority:0-active high,1-active low */
2226 #define LCD_CFG_PCP (1 << 10) /* PCLK pority:0-rising,1-falling */
2227 #define LCD_CFG_DEP (1 << 9) /* DE pority:0-active high,1-active low */
2228 #define LCD_CFG_VSP (1 << 8) /* VSYNC pority:0-rising,1-falling */
2229 #define LCD_CFG_PDW_BIT 4 /* STN pins utilization */
2230 #define LCD_CFG_PDW_MASK (0x3 << LCD_DEV_PDW_BIT)
2231 #define LCD_CFG_PDW_1 (0 << LCD_CFG_PDW_BIT) /* LCD_D[0] */
2232 #define LCD_CFG_PDW_2 (1 << LCD_CFG_PDW_BIT) /* LCD_D[0:1] */
2233 #define LCD_CFG_PDW_4 (2 << LCD_CFG_PDW_BIT) /* LCD_D[0:3]/LCD_D[8:11] */
2234 #define LCD_CFG_PDW_8 (3 << LCD_CFG_PDW_BIT) /* LCD_D[0:7]/LCD_D[8:15] */
2235 #define LCD_CFG_MODE_BIT 0 /* Display Device Mode Select */
2236 #define LCD_CFG_MODE_MASK (0x0f << LCD_CFG_MODE_BIT)
2237 #define LCD_CFG_MODE_GENERIC_TFT (0 << LCD_CFG_MODE_BIT) /* 16,18 bit TFT */
2238 #define LCD_CFG_MODE_SPECIAL_TFT_1 (1 << LCD_CFG_MODE_BIT)
2239 #define LCD_CFG_MODE_SPECIAL_TFT_2 (2 << LCD_CFG_MODE_BIT)
2240 #define LCD_CFG_MODE_SPECIAL_TFT_3 (3 << LCD_CFG_MODE_BIT)
2241 #define LCD_CFG_MODE_NONINTER_CCIR656 (4 << LCD_CFG_MODE_BIT)
2242 #define LCD_CFG_MODE_INTER_CCIR656 (5 << LCD_CFG_MODE_BIT)
2243 #define LCD_CFG_MODE_SINGLE_CSTN (8 << LCD_CFG_MODE_BIT)
2244 #define LCD_CFG_MODE_SINGLE_MSTN (9 << LCD_CFG_MODE_BIT)
2245 #define LCD_CFG_MODE_DUAL_CSTN (10 << LCD_CFG_MODE_BIT)
2246 #define LCD_CFG_MODE_DUAL_MSTN (11 << LCD_CFG_MODE_BIT)
2247 #define LCD_CFG_MODE_SERIAL_TFT (12 << LCD_CFG_MODE_BIT)
2248 #define LCD_CFG_MODE_GENERIC_18BIT_TFT (13 << LCD_CFG_MODE_BIT)
2249 /* JZ47XX defines */
2250 #define LCD_CFG_MODE_SHARP_HR (1 << LCD_CFG_MODE_BIT)
2251 #define LCD_CFG_MODE_CASIO_TFT (2 << LCD_CFG_MODE_BIT)
2252 #define LCD_CFG_MODE_SAMSUNG_ALPHA (3 << LCD_CFG_MODE_BIT)
2256 /* Vertical Synchronize Register */
2257 #define LCD_VSYNC_VPS_BIT 16 /* VSYNC pulse start in line clock, fixed to 0 */
2258 #define LCD_VSYNC_VPS_MASK (0xffff << LCD_VSYNC_VPS_BIT)
2259 #define LCD_VSYNC_VPE_BIT 0 /* VSYNC pulse end in line clock */
2260 #define LCD_VSYNC_VPE_MASK (0xffff << LCD_VSYNC_VPS_BIT)
2262 /* Horizontal Synchronize Register */
2263 #define LCD_HSYNC_HPS_BIT 16 /* HSYNC pulse start position in dot clock */
2264 #define LCD_HSYNC_HPS_MASK (0xffff << LCD_HSYNC_HPS_BIT)
2265 #define LCD_HSYNC_HPE_BIT 0 /* HSYNC pulse end position in dot clock */
2266 #define LCD_HSYNC_HPE_MASK (0xffff << LCD_HSYNC_HPE_BIT)
2268 /* Virtual Area Setting Register */
2269 #define LCD_VAT_HT_BIT 16 /* Horizontal Total size in dot clock */
2270 #define LCD_VAT_HT_MASK (0xffff << LCD_VAT_HT_BIT)
2271 #define LCD_VAT_VT_BIT 0 /* Vertical Total size in dot clock */
2272 #define LCD_VAT_VT_MASK (0xffff << LCD_VAT_VT_BIT)
2274 /* Display Area Horizontal Start/End Point Register */
2275 #define LCD_DAH_HDS_BIT 16 /* Horizontal display area start in dot clock */
2276 #define LCD_DAH_HDS_MASK (0xffff << LCD_DAH_HDS_BIT)
2277 #define LCD_DAH_HDE_BIT 0 /* Horizontal display area end in dot clock */
2278 #define LCD_DAH_HDE_MASK (0xffff << LCD_DAH_HDE_BIT)
2280 /* Display Area Vertical Start/End Point Register */
2281 #define LCD_DAV_VDS_BIT 16 /* Vertical display area start in line clock */
2282 #define LCD_DAV_VDS_MASK (0xffff << LCD_DAV_VDS_BIT)
2283 #define LCD_DAV_VDE_BIT 0 /* Vertical display area end in line clock */
2284 #define LCD_DAV_VDE_MASK (0xffff << LCD_DAV_VDE_BIT)
2286 /* PS Signal Setting */
2287 #define LCD_PS_PSS_BIT 16 /* PS signal start position in dot clock */
2288 #define LCD_PS_PSS_MASK (0xffff << LCD_PS_PSS_BIT)
2289 #define LCD_PS_PSE_BIT 0 /* PS signal end position in dot clock */
2290 #define LCD_PS_PSE_MASK (0xffff << LCD_PS_PSE_BIT)
2292 /* CLS Signal Setting */
2293 #define LCD_CLS_CLSS_BIT 16 /* CLS signal start position in dot clock */
2294 #define LCD_CLS_CLSS_MASK (0xffff << LCD_CLS_CLSS_BIT)
2295 #define LCD_CLS_CLSE_BIT 0 /* CLS signal end position in dot clock */
2296 #define LCD_CLS_CLSE_MASK (0xffff << LCD_CLS_CLSE_BIT)
2298 /* SPL Signal Setting */
2299 #define LCD_SPL_SPLS_BIT 16 /* SPL signal start position in dot clock */
2300 #define LCD_SPL_SPLS_MASK (0xffff << LCD_SPL_SPLS_BIT)
2301 #define LCD_SPL_SPLE_BIT 0 /* SPL signal end position in dot clock */
2302 #define LCD_SPL_SPLE_MASK (0xffff << LCD_SPL_SPLE_BIT)
2304 /* REV Signal Setting */
2305 #define LCD_REV_REVS_BIT 16 /* REV signal start position in dot clock */
2306 #define LCD_REV_REVS_MASK (0xffff << LCD_REV_REVS_BIT)
2308 /* LCD Control Register */
2309 #define LCD_CTRL_BST_BIT 28 /* Burst Length Selection */
2310 #define LCD_CTRL_BST_MASK (0x03 << LCD_CTRL_BST_BIT)
2311 #define LCD_CTRL_BST_4 (0 << LCD_CTRL_BST_BIT) /* 4-word */
2312 #define LCD_CTRL_BST_8 (1 << LCD_CTRL_BST_BIT) /* 8-word */
2313 #define LCD_CTRL_BST_16 (2 << LCD_CTRL_BST_BIT) /* 16-word */
2314 #define LCD_CTRL_RGB565 (0 << 27) /* RGB565 mode */
2315 #define LCD_CTRL_RGB555 (1 << 27) /* RGB555 mode */
2316 #define LCD_CTRL_OFUP (1 << 26) /* Output FIFO underrun protection enable */
2317 #define LCD_CTRL_FRC_BIT 24 /* STN FRC Algorithm Selection */
2318 #define LCD_CTRL_FRC_MASK (0x03 << LCD_CTRL_FRC_BIT)
2319 #define LCD_CTRL_FRC_16 (0 << LCD_CTRL_FRC_BIT) /* 16 grayscale */
2320 #define LCD_CTRL_FRC_4 (1 << LCD_CTRL_FRC_BIT) /* 4 grayscale */
2321 #define LCD_CTRL_FRC_2 (2 << LCD_CTRL_FRC_BIT) /* 2 grayscale */
2322 #define LCD_CTRL_PDD_BIT 16 /* Load Palette Delay Counter */
2323 #define LCD_CTRL_PDD_MASK (0xff << LCD_CTRL_PDD_BIT)
2324 #define LCD_CTRL_EOFM (1 << 13) /* EOF interrupt mask */
2325 #define LCD_CTRL_SOFM (1 << 12) /* SOF interrupt mask */
2326 #define LCD_CTRL_OFUM (1 << 11) /* Output FIFO underrun interrupt mask */
2327 #define LCD_CTRL_IFUM0 (1 << 10) /* Input FIFO 0 underrun interrupt mask */
2328 #define LCD_CTRL_IFUM1 (1 << 9) /* Input FIFO 1 underrun interrupt mask */
2329 #define LCD_CTRL_LDDM (1 << 8) /* LCD disable done interrupt mask */
2330 #define LCD_CTRL_QDM (1 << 7) /* LCD quick disable done interrupt mask */
2331 #define LCD_CTRL_BEDN (1 << 6) /* Endian selection */
2332 #define LCD_CTRL_PEDN (1 << 5) /* Endian in byte:0-msb first, 1-lsb first */
2333 #define LCD_CTRL_DIS (1 << 4) /* Disable indicate bit */
2334 #define LCD_CTRL_ENA (1 << 3) /* LCD enable bit */
2335 #define LCD_CTRL_BPP_BIT 0 /* Bits Per Pixel */
2336 #define LCD_CTRL_BPP_MASK (0x07 << LCD_CTRL_BPP_BIT)
2337 #define LCD_CTRL_BPP_1 (0 << LCD_CTRL_BPP_BIT) /* 1 bpp */
2338 #define LCD_CTRL_BPP_2 (1 << LCD_CTRL_BPP_BIT) /* 2 bpp */
2339 #define LCD_CTRL_BPP_4 (2 << LCD_CTRL_BPP_BIT) /* 4 bpp */
2340 #define LCD_CTRL_BPP_8 (3 << LCD_CTRL_BPP_BIT) /* 8 bpp */
2341 #define LCD_CTRL_BPP_16 (4 << LCD_CTRL_BPP_BIT) /* 15/16 bpp */
2342 #define LCD_CTRL_BPP_18_24 (5 << LCD_CTRL_BPP_BIT) /* 18/24/32 bpp */
2344 /* LCD Status Register */
2345 #define LCD_STATE_QD (1 << 7) /* Quick Disable Done */
2346 #define LCD_STATE_EOF (1 << 5) /* EOF Flag */
2347 #define LCD_STATE_SOF (1 << 4) /* SOF Flag */
2348 #define LCD_STATE_OFU (1 << 3) /* Output FIFO Underrun */
2349 #define LCD_STATE_IFU0 (1 << 2) /* Input FIFO 0 Underrun */
2350 #define LCD_STATE_IFU1 (1 << 1) /* Input FIFO 1 Underrun */
2351 #define LCD_STATE_LDD (1 << 0) /* LCD Disabled */
2353 /* DMA Command Register */
2354 #define LCD_CMD_SOFINT (1 << 31)
2355 #define LCD_CMD_EOFINT (1 << 30)
2356 #define LCD_CMD_PAL (1 << 28)
2357 #define LCD_CMD_LEN_BIT 0
2358 #define LCD_CMD_LEN_MASK (0xffffff << LCD_CMD_LEN_BIT)
2361 /*************************************************************************
2362 * USB Device
2363 *************************************************************************/
2364 #define USB_BASE UDC_BASE
2366 #define USB_REG_FADDR (USB_BASE + 0x00) /* Function Address 8-bit */
2367 #define USB_REG_POWER (USB_BASE + 0x01) /* Power Managemetn 8-bit */
2368 #define USB_REG_INTRIN (USB_BASE + 0x02) /* Interrupt IN 16-bit */
2369 #define USB_REG_INTROUT (USB_BASE + 0x04) /* Interrupt OUT 16-bit */
2370 #define USB_REG_INTRINE (USB_BASE + 0x06) /* Intr IN enable 16-bit */
2371 #define USB_REG_INTROUTE (USB_BASE + 0x08) /* Intr OUT enable 16-bit */
2372 #define USB_REG_INTRUSB (USB_BASE + 0x0a) /* Interrupt USB 8-bit */
2373 #define USB_REG_INTRUSBE (USB_BASE + 0x0b) /* Interrupt USB Enable 8-bit */
2374 #define USB_REG_FRAME (USB_BASE + 0x0c) /* Frame number 16-bit */
2375 #define USB_REG_INDEX (USB_BASE + 0x0e) /* Index register 8-bit */
2376 #define USB_REG_TESTMODE (USB_BASE + 0x0f) /* USB test mode 8-bit */
2378 #define USB_REG_CSR0 (USB_BASE + 0x12) /* EP0 CSR 8-bit */
2379 #define USB_REG_COUNT0 (USB_BASE + 0x18) /* bytes in EP0 FIFO 16-bit */
2380 #define USB_REG_INMAXP (USB_BASE + 0x10) /* EP1-2 IN Max Pkt Size 16-bit */
2381 #define USB_REG_INCSR (USB_BASE + 0x12) /* EP1-2 IN CSR LSB 8/16bit */
2382 #define USB_REG_INCSRH (USB_BASE + 0x13) /* EP1-2 IN CSR MSB 8-bit */
2383 #define USB_REG_OUTMAXP (USB_BASE + 0x14) /* EP1 OUT Max Pkt Size 16-bit */
2384 #define USB_REG_OUTCSR (USB_BASE + 0x16) /* EP1 OUT CSR LSB 8/16bit */
2385 #define USB_REG_OUTCSRH (USB_BASE + 0x17) /* EP1 OUT CSR MSB 8-bit */
2386 #define USB_REG_OUTCOUNT (USB_BASE + 0x18) /* bytes in EP0/1 OUT FIFO 16-bit */
2388 #define USB_FIFO_EP0 (USB_BASE + 0x20)
2389 #define USB_FIFO_EP1 (USB_BASE + 0x24)
2390 #define USB_FIFO_EP2 (USB_BASE + 0x28)
2392 #define USB_REG_EPINFO (USB_BASE + 0x78) /* Endpoint information */
2393 #define USB_REG_RAMINFO (USB_BASE + 0x79) /* RAM information */
2395 #define USB_REG_INTR (USB_BASE + 0x200) /* DMA pending interrupts 8-bit */
2396 #define USB_REG_CNTL1 (USB_BASE + 0x204) /* DMA channel 1 control 32-bit */
2397 #define USB_REG_ADDR1 (USB_BASE + 0x208) /* DMA channel 1 AHB memory addr 32-bit */
2398 #define USB_REG_COUNT1 (USB_BASE + 0x20c) /* DMA channel 1 byte count 32-bit */
2399 #define USB_REG_CNTL2 (USB_BASE + 0x214) /* DMA channel 2 control 32-bit */
2400 #define USB_REG_ADDR2 (USB_BASE + 0x218) /* DMA channel 2 AHB memory addr 32-bit */
2401 #define USB_REG_COUNT2 (USB_BASE + 0x21c) /* DMA channel 2 byte count 32-bit */
2403 #define REG_USB_REG_FADDR REG8(USB_REG_FADDR)
2404 #define REG_USB_REG_POWER REG8(USB_REG_POWER)
2405 #define REG_USB_REG_INTRIN REG16(USB_REG_INTRIN)
2406 #define REG_USB_REG_INTROUT REG16(USB_REG_INTROUT)
2407 #define REG_USB_REG_INTRINE REG16(USB_REG_INTRINE)
2408 #define REG_USB_REG_INTROUTE REG16(USB_REG_INTROUTE)
2409 #define REG_USB_REG_INTRUSB REG8(USB_REG_INTRUSB)
2410 #define REG_USB_REG_INTRUSBE REG8(USB_REG_INTRUSBE)
2411 #define REG_USB_REG_FRAME REG16(USB_REG_FRAME)
2412 #define REG_USB_REG_INDEX REG8(USB_REG_INDEX)
2413 #define REG_USB_REG_TESTMODE REG8(USB_REG_TESTMODE)
2415 #define REG_USB_REG_CSR0 REG8(USB_REG_CSR0)
2416 #define REG_USB_REG_COUNT0 REG16(USB_REG_COUNT0)
2417 #define REG_USB_REG_INMAXP REG16(USB_REG_INMAXP)
2418 #define REG_USB_REG_INCSR REG16(USB_REG_INCSR)
2419 #define REG_USB_REG_INCSRH REG8(USB_REG_INCSRH)
2420 #define REG_USB_REG_OUTMAXP REG16(USB_REG_OUTMAXP)
2421 #define REG_USB_REG_OUTCSR REG16(USB_REG_OUTCSR)
2422 #define REG_USB_REG_OUTCSRH REG8(USB_REG_OUTCSRH)
2423 #define REG_USB_REG_OUTCOUNT REG16(USB_REG_OUTCOUNT)
2425 #define REG_USB_FIFO_EP0 REG32(USB_FIFO_EP0)
2426 #define REG_USB_FIFO_EP1 REG32(USB_FIFO_EP1)
2427 #define REG_USB_FIFO_EP2 REG32(USB_FIFO_EP2)
2429 #define REG_USB_REG_INTR REG8(USB_REG_INTR)
2430 #define REG_USB_REG_CNTL1 REG32(USB_REG_CNTL1)
2431 #define REG_USB_REG_ADDR1 REG32(USB_REG_ADDR1)
2432 #define REG_USB_REG_COUNT1 REG32(USB_REG_COUNT1)
2433 #define REG_USB_REG_CNTL2 REG32(USB_REG_CNTL2)
2434 #define REG_USB_REG_ADDR2 REG32(USB_REG_ADDR2)
2435 #define REG_USB_REG_COUNT2 REG32(USB_REG_COUNT2)
2437 #define REG_USB_REG_EPINFO REG16(USB_REG_EPINFO)
2438 #define REG_USB_REG_RAMINFO REG8(USB_REG_RAMINFO)
2441 /* Power register bit masks */
2442 #define USB_POWER_SUSPENDM 0x01
2443 #define USB_POWER_RESUME 0x04
2444 #define USB_POWER_HSMODE 0x10
2445 #define USB_POWER_HSENAB 0x20
2446 #define USB_POWER_SOFTCONN 0x40
2448 /* Interrupt register bit masks */
2449 #define USB_INTR_SUSPEND 0x01
2450 #define USB_INTR_RESUME 0x02
2451 #define USB_INTR_RESET 0x04
2453 #define USB_INTR_EP0 0x0001
2454 #define USB_INTR_INEP1 0x0002
2455 #define USB_INTR_INEP2 0x0004
2456 #define USB_INTR_OUTEP1 0x0002
2457 #define USB_INTR_OUTEP2 0x0004
2459 #define USB_INTR_EP(n) ((n)==0 ? 1 : ((n)*2))
2461 /* CSR0 bit masks */
2462 #define USB_CSR0_OUTPKTRDY 0x01
2463 #define USB_CSR0_INPKTRDY 0x02
2464 #define USB_CSR0_SENTSTALL 0x04
2465 #define USB_CSR0_DATAEND 0x08
2466 #define USB_CSR0_SETUPEND 0x10
2467 #define USB_CSR0_SENDSTALL 0x20
2468 #define USB_CSR0_SVDOUTPKTRDY 0x40
2469 #define USB_CSR0_SVDSETUPEND 0x80
2471 /* Endpoint CSR register bits */
2472 #define USB_INCSRH_AUTOSET 0x80
2473 #define USB_INCSRH_ISO 0x40
2474 #define USB_INCSRH_MODE 0x20
2475 #define USB_INCSRH_DMAREQENAB 0x10
2476 #define USB_INCSRH_FRCDATATOG 0x08
2477 #define USB_INCSRH_DMAREQMODE 0x04
2478 #define USB_INCSR_CDT 0x40
2479 #define USB_INCSR_SENTSTALL 0x20
2480 #define USB_INCSR_SENDSTALL 0x10
2481 #define USB_INCSR_FF 0x08
2482 #define USB_INCSR_UNDERRUN 0x04
2483 #define USB_INCSR_FFNOTEMPT 0x02
2484 #define USB_INCSR_INPKTRDY 0x01
2485 #define USB_OUTCSRH_AUTOCLR 0x80
2486 #define USB_OUTCSRH_ISO 0x40
2487 #define USB_OUTCSRH_DMAREQENAB 0x20
2488 #define USB_OUTCSRH_DNYT 0x10
2489 #define USB_OUTCSRH_DMAREQMODE 0x08
2490 #define USB_OUTCSR_CDT 0x80
2491 #define USB_OUTCSR_SENTSTALL 0x40
2492 #define USB_OUTCSR_SENDSTALL 0x20
2493 #define USB_OUTCSR_FF 0x10
2494 #define USB_OUTCSR_DATAERR 0x08
2495 #define USB_OUTCSR_OVERRUN 0x04
2496 #define USB_OUTCSR_FFFULL 0x02
2497 #define USB_OUTCSR_OUTPKTRDY 0x01
2499 /* Testmode register bits */
2500 #define USB_TEST_SE0NAK 0x01
2501 #define USB_TEST_J 0x02
2502 #define USB_TEST_K 0x04
2503 #define USB_TEST_PACKET 0x08
2504 #define USB_TEST_FORCE_HS 0x10
2505 #define USB_TEST_FORCE_FS 0x20
2506 #define USB_TEST_ALL ( USB_TEST_SE0NAK | USB_TEST_J \
2507 | USB_TEST_K | USB_TEST_PACKET \
2508 | USB_TEST_FORCE_HS | USB_TEST_FORCE_FS)
2510 /* DMA control bits */
2511 #define USB_CNTL_ENA 0x01
2512 #define USB_CNTL_DIR_IN 0x02
2513 #define USB_CNTL_MODE_1 0x04
2514 #define USB_CNTL_INTR_EN 0x08
2515 #define USB_CNTL_EP(n) ((n) << 4)
2516 #define USB_CNTL_BURST_0 (0 << 9)
2517 #define USB_CNTL_BURST_4 (1 << 9)
2518 #define USB_CNTL_BURST_8 (2 << 9)
2519 #define USB_CNTL_BURST_16 (3 << 9)
2521 /* DMA interrupt bits */
2522 #define USB_INTR_DMA_BULKIN 1
2523 #define USB_INTR_DMA_BULKOUT 2
2526 //----------------------------------------------------------------------
2528 // Module Operation Definitions
2530 //----------------------------------------------------------------------
2531 #ifndef __ASSEMBLY__
2533 /***************************************************************************
2534 * GPIO
2535 ***************************************************************************/
2537 //------------------------------------------------------
2538 // GPIO Pins Description
2540 // PORT 0:
2542 // PIN/BIT N FUNC0 FUNC1
2543 // 0 D0 -
2544 // 1 D1 -
2545 // 2 D2 -
2546 // 3 D3 -
2547 // 4 D4 -
2548 // 5 D5 -
2549 // 6 D6 -
2550 // 7 D7 -
2551 // 8 D8 -
2552 // 9 D9 -
2553 // 10 D10 -
2554 // 11 D11 -
2555 // 12 D12 -
2556 // 13 D13 -
2557 // 14 D14 -
2558 // 15 D15 -
2559 // 16 D16 -
2560 // 17 D17 -
2561 // 18 D18 -
2562 // 19 D19 -
2563 // 20 D20 -
2564 // 21 D21 -
2565 // 22 D22 -
2566 // 23 D23 -
2567 // 24 D24 -
2568 // 25 D25 -
2569 // 26 D26 -
2570 // 27 D27 -
2571 // 28 D28 -
2572 // 29 D29 -
2573 // 30 D30 -
2574 // 31 D31 -
2576 //------------------------------------------------------
2577 // PORT 1:
2579 // PIN/BIT N FUNC0 FUNC1
2580 // 0 A0 -
2581 // 1 A1 -
2582 // 2 A2 -
2583 // 3 A3 -
2584 // 4 A4 -
2585 // 5 A5 -
2586 // 6 A6 -
2587 // 7 A7 -
2588 // 8 A8 -
2589 // 9 A9 -
2590 // 10 A10 -
2591 // 11 A11 -
2592 // 12 A12 -
2593 // 13 A13 -
2594 // 14 A14 -
2595 // 15 A15/CL -
2596 // 16 A16/AL -
2597 // 17 LCD_CLS A21
2598 // 18 LCD_SPL A22
2599 // 19 DCS# -
2600 // 20 RAS# -
2601 // 21 CAS# -
2602 // 22 RDWE#/BUFD# -
2603 // 23 CKE -
2604 // 24 CKO -
2605 // 25 CS1# -
2606 // 26 CS2# -
2607 // 27 CS3# -
2608 // 28 CS4# -
2609 // 29 RD# -
2610 // 30 WR# -
2611 // 31 WE0# -
2613 // Note: PIN15&16 are CL&AL when connecting to NAND flash.
2614 //------------------------------------------------------
2615 // PORT 2:
2617 // PIN/BIT N FUNC0 FUNC1
2618 // 0 LCD_D0 -
2619 // 1 LCD_D1 -
2620 // 2 LCD_D2 -
2621 // 3 LCD_D3 -
2622 // 4 LCD_D4 -
2623 // 5 LCD_D5 -
2624 // 6 LCD_D6 -
2625 // 7 LCD_D7 -
2626 // 8 LCD_D8 -
2627 // 9 LCD_D9 -
2628 // 10 LCD_D10 -
2629 // 11 LCD_D11 -
2630 // 12 LCD_D12 -
2631 // 13 LCD_D13 -
2632 // 14 LCD_D14 -
2633 // 15 LCD_D15 -
2634 // 16 LCD_D16 -
2635 // 17 LCD_D17 -
2636 // 18 LCD_PCLK -
2637 // 19 LCD_HSYNC -
2638 // 20 LCD_VSYNC -
2639 // 21 LCD_DE -
2640 // 22 LCD_PS A19
2641 // 23 LCD_REV A20
2642 // 24 WE1# -
2643 // 25 WE2# -
2644 // 26 WE3# -
2645 // 27 WAIT# -
2646 // 28 FRE# -
2647 // 29 FWE# -
2648 // 30(NOTE:FRB#) - -
2649 // 31 - -
2651 // NOTE(1): PIN30 is used for FRB# when connecting to NAND flash.
2652 //------------------------------------------------------
2653 // PORT 3:
2655 // PIN/BIT N FUNC0 FUNC1
2656 // 0 CIM_D0 -
2657 // 1 CIM_D1 -
2658 // 2 CIM_D2 -
2659 // 3 CIM_D3 -
2660 // 4 CIM_D4 -
2661 // 5 CIM_D5 -
2662 // 6 CIM_D6 -
2663 // 7 CIM_D7 -
2664 // 8 MSC_CMD -
2665 // 9 MSC_CLK -
2666 // 10 MSC_D0 -
2667 // 11 MSC_D1 -
2668 // 12 MSC_D2 -
2669 // 13 MSC_D3 -
2670 // 14 CIM_MCLK -
2671 // 15 CIM_PCLK -
2672 // 16 CIM_VSYNC -
2673 // 17 CIM_HSYNC -
2674 // 18 SSI_CLK SCLK_RSTN
2675 // 19 SSI_CE0# BIT_CLK(AIC)
2676 // 20 SSI_DT SDATA_OUT(AIC)
2677 // 21 SSI_DR SDATA_IN(AIC)
2678 // 22 SSI_CE1#&GPC SYNC(AIC)
2679 // 23 PWM0 I2C_SDA
2680 // 24 PWM1 I2C_SCK
2681 // 25 PWM2 UART0_TxD
2682 // 26 PWM3 UART0_RxD
2683 // 27 PWM4 A17
2684 // 28 PWM5 A18
2685 // 29 - -
2686 // 30 PWM6 UART0_CTS/UART1_RxD
2687 // 31 PWM7 UART0_RTS/UART1_TxD
2689 //////////////////////////////////////////////////////////
2692 * p is the port number (0,1,2,3)
2693 * o is the pin offset (0-31) inside the port
2694 * n is the absolute number of a pin (0-127), regardless of the port
2697 //-------------------------------------------
2698 // Function Pins Mode
2700 #define __gpio_as_func0(n) \
2701 do { \
2702 unsigned int p, o; \
2703 p = (n) / 32; \
2704 o = (n) % 32; \
2705 REG_GPIO_PXFUNS(p) = (1 << o); \
2706 REG_GPIO_PXSELC(p) = (1 << o); \
2707 } while (0)
2709 #define __gpio_as_func1(n) \
2710 do { \
2711 unsigned int p, o; \
2712 p = (n) / 32; \
2713 o = (n) % 32; \
2714 REG_GPIO_PXFUNS(p) = (1 << o); \
2715 REG_GPIO_PXSELS(p) = (1 << o); \
2716 } while (0)
2719 * D0 ~ D31, A0 ~ A16, DCS#, RAS#, CAS#, CKE#,
2720 * RDWE#, CKO#, WE0#, WE1#, WE2#, WE3#
2722 #define __gpio_as_sdram_32bit() \
2723 do { \
2724 REG_GPIO_PXFUNS(0) = 0xffffffff; \
2725 REG_GPIO_PXSELC(0) = 0xffffffff; \
2726 REG_GPIO_PXPES(0) = 0xffffffff; \
2727 REG_GPIO_PXFUNS(1) = 0x81f9ffff; \
2728 REG_GPIO_PXSELC(1) = 0x81f9ffff; \
2729 REG_GPIO_PXPES(1) = 0x81f9ffff; \
2730 REG_GPIO_PXFUNS(2) = 0x07000000; \
2731 REG_GPIO_PXSELC(2) = 0x07000000; \
2732 REG_GPIO_PXPES(2) = 0x07000000; \
2733 } while (0)
2735 //#ifdef JZ4740_PAVO
2736 #ifdef JZ4740_4740
2738 * D0 ~ D15, A0 ~ A16, DCS#, RAS#, CAS#, CKE#,
2739 * RDWE#, CKO#, WE0#, WE1#, WE2#, WE3#
2741 #define __gpio_as_sdram_16bit() \
2742 do { \
2743 REG_GPIO_PXFUNS(0) = 0x0000ffff; \
2744 REG_GPIO_PXFUNS(0) = 0x0000ffff; \
2745 REG_GPIO_PXPES(0) = 0x0000ffff; \
2746 REG_GPIO_PXFUNS(1) = 0x81f9ffff; \
2747 REG_GPIO_PXSELC(1) = 0x81f9ffff; \
2748 REG_GPIO_PXPES(1) = 0x81f9ffff; \
2749 REG_GPIO_PXFUNS(2) = 0x07000000; \
2750 REG_GPIO_PXSELC(2) = 0x07000000; \
2751 REG_GPIO_PXPES(2) = 0x07000000; \
2752 } while (0)
2754 #endif
2756 //#ifdef JZ4740_VIRGO
2757 #ifdef JZ4740_4720
2759 * D0 ~ D15, A0 ~ A16, DCS#, RAS#, CAS#, CKE#,
2760 * RDWE#, CKO#, WE0#, WE1#, WE2#, WE3#
2762 #define __gpio_as_sdram_16bit() \
2763 do { \
2764 REG_GPIO_PXFUNS(0) = 0x5442bfaa; \
2765 REG_GPIO_PXSELC(0) = 0x5442bfaa; \
2766 REG_GPIO_PXPES(0) = 0x5442bfaa; \
2767 REG_GPIO_PXFUNS(1) = 0x81f9ffff; \
2768 REG_GPIO_PXSELC(1) = 0x81f9ffff; \
2769 REG_GPIO_PXPES(1) = 0x81f9ffff; \
2770 REG_GPIO_PXFUNS(2) = 0x01000000; \
2771 REG_GPIO_PXSELC(2) = 0x01000000; \
2772 REG_GPIO_PXPES(2) = 0x01000000; \
2773 } while (0)
2774 #endif
2777 #ifdef JZ4740_4725
2779 * D0 ~ D15, A0 ~ A16, DCS#, RAS#, CAS#, CKE#,
2780 * RDWE#, CKO#, WE0#, WE1#, WE2#, WE3#
2782 #define __jz4725__gpio_as_sdram_16bit() \
2783 do { \
2784 REG_GPIO_PXFUNS(0) = 0x0000ffff; \
2785 REG_GPIO_PXSELC(0) = 0x0000ffff; \
2786 REG_GPIO_PXPES(0) = 0x0000ffff; \
2787 REG_GPIO_PXFUNS(1) = 0x81f9ffff; \
2788 REG_GPIO_PXSELC(1) = 0x81f9ffff; \
2789 REG_GPIO_PXPES(1) = 0x81f9ffff; \
2790 REG_GPIO_PXFUNS(2) = 0x07000000; \
2791 REG_GPIO_PXSELC(2) = 0x07000000; \
2792 REG_GPIO_PXPES(2) = 0x07000000; \
2793 } while (0)
2794 #endif
2796 * CS1#, CLE, ALE, FRE#, FWE#, FRB#, RDWE#/BUFD#
2798 #define __gpio_as_nand() \
2799 do { \
2800 REG_GPIO_PXFUNS(1) = 0x02018000; \
2801 REG_GPIO_PXSELC(1) = 0x02018000; \
2802 REG_GPIO_PXPES(1) = 0x02018000; \
2803 REG_GPIO_PXFUNS(2) = 0x30000000; \
2804 REG_GPIO_PXSELC(2) = 0x30000000; \
2805 REG_GPIO_PXPES(2) = 0x30000000; \
2806 REG_GPIO_PXFUNC(2) = 0x40000000; \
2807 REG_GPIO_PXSELC(2) = 0x40000000; \
2808 REG_GPIO_PXDIRC(2) = 0x40000000; \
2809 REG_GPIO_PXPES(2) = 0x40000000; \
2810 REG_GPIO_PXFUNS(1) = 0x00400000; \
2811 REG_GPIO_PXSELC(1) = 0x00400000; \
2812 } while (0)
2815 * CS4#, RD#, WR#, WAIT#, A0 ~ A22, D0 ~ D7
2817 #define __gpio_as_nor_8bit() \
2818 do { \
2819 REG_GPIO_PXFUNS(0) = 0x000000ff; \
2820 REG_GPIO_PXSELC(0) = 0x000000ff; \
2821 REG_GPIO_PXPES(0) = 0x000000ff; \
2822 REG_GPIO_PXFUNS(1) = 0x7041ffff; \
2823 REG_GPIO_PXSELC(1) = 0x7041ffff; \
2824 REG_GPIO_PXPES(1) = 0x7041ffff; \
2825 REG_GPIO_PXFUNS(1) = 0x00060000; \
2826 REG_GPIO_PXSELS(1) = 0x00060000; \
2827 REG_GPIO_PXPES(1) = 0x00060000; \
2828 REG_GPIO_PXFUNS(2) = 0x08000000; \
2829 REG_GPIO_PXSELC(2) = 0x08000000; \
2830 REG_GPIO_PXPES(2) = 0x08000000; \
2831 REG_GPIO_PXFUNS(2) = 0x00c00000; \
2832 REG_GPIO_PXSELS(2) = 0x00c00000; \
2833 REG_GPIO_PXPES(2) = 0x00c00000; \
2834 REG_GPIO_PXFUNS(3) = 0x18000000; \
2835 REG_GPIO_PXSELS(3) = 0x18000000; \
2836 REG_GPIO_PXPES(3) = 0x18000000; \
2837 } while (0)
2840 * CS4#, RD#, WR#, WAIT#, A0 ~ A22, D0 ~ D15
2842 #define __gpio_as_nor_16bit() \
2843 do { \
2844 REG_GPIO_PXFUNS(0) = 0x0000ffff; \
2845 REG_GPIO_PXSELC(0) = 0x0000ffff; \
2846 REG_GPIO_PXPES(0) = 0x0000ffff; \
2847 REG_GPIO_PXFUNS(1) = 0x7041ffff; \
2848 REG_GPIO_PXSELC(1) = 0x7041ffff; \
2849 REG_GPIO_PXPES(1) = 0x7041ffff; \
2850 REG_GPIO_PXFUNS(1) = 0x00060000; \
2851 REG_GPIO_PXSELS(1) = 0x00060000; \
2852 REG_GPIO_PXPES(1) = 0x00060000; \
2853 REG_GPIO_PXFUNS(2) = 0x08000000; \
2854 REG_GPIO_PXSELC(2) = 0x08000000; \
2855 REG_GPIO_PXPES(2) = 0x08000000; \
2856 REG_GPIO_PXFUNS(2) = 0x00c00000; \
2857 REG_GPIO_PXSELS(2) = 0x00c00000; \
2858 REG_GPIO_PXPES(2) = 0x00c00000; \
2859 REG_GPIO_PXFUNS(3) = 0x18000000; \
2860 REG_GPIO_PXSELS(3) = 0x18000000; \
2861 REG_GPIO_PXPES(3) = 0x18000000; \
2862 } while (0)
2865 * UART0_TxD, UART_RxD0
2867 #define __gpio_as_uart0() \
2868 do { \
2869 REG_GPIO_PXFUNS(3) = 0x06000000; \
2870 REG_GPIO_PXSELS(3) = 0x06000000; \
2871 REG_GPIO_PXPES(3) = 0x06000000; \
2872 } while (0)
2875 * UART1_TxD, UART1_RxD1
2877 #define __gpio_as_uart1() \
2878 do { \
2879 REG_GPIO_PXFUNS(3) = 0xc0000000; \
2880 REG_GPIO_PXSELS(3) = 0xc0000000; \
2881 REG_GPIO_PXPES(3) = 0xc0000000; \
2882 } while (0)
2885 * LCD_D0~LCD_D15, LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE
2887 #define __gpio_as_lcd_16bit() \
2888 do { \
2889 REG_GPIO_PXFUNS(2) = 0x003cffff; \
2890 REG_GPIO_PXSELC(2) = 0x003cffff; \
2891 REG_GPIO_PXPES(2) = 0x003cffff; \
2892 } while (0)
2895 * LCD_D0~LCD_D17, LCD_PCLK, LCD_HSYNC, LCD_VSYNC, LCD_DE
2897 #define __gpio_as_lcd_18bit() \
2898 do { \
2899 REG_GPIO_PXFUNS(2) = 0x003fffff; \
2900 REG_GPIO_PXSELC(2) = 0x003fffff; \
2901 REG_GPIO_PXPES(2) = 0x003fffff; \
2902 } while (0)
2905 /* LCD_D0~LCD_D7, SLCD_RS, SLCD_CS */
2906 #define __gpio_as_slcd_8bit() \
2907 do { \
2908 REG_GPIO_PXFUNS(2) = 0x001800ff; \
2909 REG_GPIO_PXSELC(2) = 0x001800ff; \
2910 } while (0)
2912 /* LCD_D0~LCD_D7, SLCD_RS, SLCD_CS */
2913 #define __gpio_as_slcd_9bit() \
2914 do { \
2915 REG_GPIO_PXFUNS(2) = 0x001801ff; \
2916 REG_GPIO_PXSELC(2) = 0x001801ff; \
2917 } while (0)
2919 /* LCD_D0~LCD_D15, SLCD_RS, SLCD_CS */
2920 #define __gpio_as_slcd_16bit() \
2921 do { \
2922 REG_GPIO_PXFUNS(2) = 0x0018ffff; \
2923 REG_GPIO_PXSELC(2) = 0x0018ffff; \
2924 } while (0)
2926 /* LCD_D0~LCD_D17, SLCD_RS, SLCD_CS */
2927 #define __gpio_as_slcd_18bit() \
2928 do { \
2929 REG_GPIO_PXFUNS(2) = 0x001bffff; \
2930 REG_GPIO_PXSELC(2) = 0x001bffff; \
2931 } while (0)
2934 * CIM_D0~CIM_D7, CIM_MCLK, CIM_PCLK, CIM_VSYNC, CIM_HSYNC
2936 #define __gpio_as_cim() \
2937 do { \
2938 REG_GPIO_PXFUNS(3) = 0x0003c0ff; \
2939 REG_GPIO_PXSELC(3) = 0x0003c0ff; \
2940 REG_GPIO_PXPES(3) = 0x0003c0ff; \
2941 } while (0)
2944 * SDATA_OUT, SDATA_IN, BIT_CLK, SYNC, SCLK_RESET
2946 #define __gpio_as_aic() \
2947 do { \
2948 REG_GPIO_PXFUNS(3) = 0x007c0000; \
2949 REG_GPIO_PXSELS(3) = 0x007c0000; \
2950 REG_GPIO_PXPES(3) = 0x007c0000; \
2951 } while (0)
2954 * MSC_CMD, MSC_CLK, MSC_D0 ~ MSC_D3
2956 #define __gpio_as_msc() \
2957 do { \
2958 REG_GPIO_PXFUNS(3) = 0x00003f00; \
2959 REG_GPIO_PXSELC(3) = 0x00003f00; \
2960 REG_GPIO_PXPES(3) = 0x00003f00; \
2961 } while (0)
2964 * SSI_CS0, SSI_CLK, SSI_DT, SSI_DR
2966 #define __gpio_as_ssi() \
2967 do { \
2968 REG_GPIO_PXFUNS(3) = 0x003c0000; \
2969 REG_GPIO_PXSELC(3) = 0x003c0000; \
2970 REG_GPIO_PXPES(3) = 0x003c0000; \
2971 } while (0)
2974 * I2C_SCK, I2C_SDA
2976 #define __gpio_as_i2c() \
2977 do { \
2978 REG_GPIO_PXFUNS(3) = 0x01800000; \
2979 REG_GPIO_PXSELS(3) = 0x01800000; \
2980 REG_GPIO_PXPES(3) = 0x01800000; \
2981 } while (0)
2984 * PWM0
2986 #define __gpio_as_pwm0() \
2987 do { \
2988 REG_GPIO_PXFUNS(3) = 0x00800000; \
2989 REG_GPIO_PXSELC(3) = 0x00800000; \
2990 REG_GPIO_PXPES(3) = 0x00800000; \
2991 } while (0)
2994 * PWM1
2996 #define __gpio_as_pwm1() \
2997 do { \
2998 REG_GPIO_PXFUNS(3) = 0x01000000; \
2999 REG_GPIO_PXSELC(3) = 0x01000000; \
3000 REG_GPIO_PXPES(3) = 0x01000000; \
3001 } while (0)
3004 * PWM2
3006 #define __gpio_as_pwm2() \
3007 do { \
3008 REG_GPIO_PXFUNS(3) = 0x02000000; \
3009 REG_GPIO_PXSELC(3) = 0x02000000; \
3010 REG_GPIO_PXPES(3) = 0x02000000; \
3011 } while (0)
3014 * PWM3
3016 #define __gpio_as_pwm3() \
3017 do { \
3018 REG_GPIO_PXFUNS(3) = 0x04000000; \
3019 REG_GPIO_PXSELC(3) = 0x04000000; \
3020 REG_GPIO_PXPES(3) = 0x04000000; \
3021 } while (0)
3024 * PWM4
3026 #define __gpio_as_pwm4() \
3027 do { \
3028 REG_GPIO_PXFUNS(3) = 0x08000000; \
3029 REG_GPIO_PXSELC(3) = 0x08000000; \
3030 REG_GPIO_PXPES(3) = 0x08000000; \
3031 } while (0)
3034 * PWM5
3036 #define __gpio_as_pwm5() \
3037 do { \
3038 REG_GPIO_PXFUNS(3) = 0x10000000; \
3039 REG_GPIO_PXSELC(3) = 0x10000000; \
3040 REG_GPIO_PXPES(3) = 0x10000000; \
3041 } while (0)
3044 * PWM6
3046 #define __gpio_as_pwm6() \
3047 do { \
3048 REG_GPIO_PXFUNS(3) = 0x40000000; \
3049 REG_GPIO_PXSELC(3) = 0x40000000; \
3050 REG_GPIO_PXPES(3) = 0x40000000; \
3051 } while (0)
3054 * PWM7
3056 #define __gpio_as_pwm7() \
3057 do { \
3058 REG_GPIO_PXFUNS(3) = 0x80000000; \
3059 REG_GPIO_PXSELC(3) = 0x80000000; \
3060 REG_GPIO_PXPES(3) = 0x80000000; \
3061 } while (0)
3064 * n = 0 ~ 7
3066 #define ___gpio_as_pwm(n) __gpio_as_pwm ## n()
3067 #define __gpio_as_pwm(n) ___gpio_as_pwm(n)
3069 //-------------------------------------------
3070 // GPIO or Interrupt Mode
3072 #define __gpio_get_port(p) (REG_GPIO_PXPIN(p))
3074 #define __gpio_port_as_output(p, o) \
3075 do { \
3076 REG_GPIO_PXFUNC(p) = (1 << (o)); \
3077 REG_GPIO_PXSELC(p) = (1 << (o)); \
3078 REG_GPIO_PXDIRS(p) = (1 << (o)); \
3079 } while (0)
3081 #define __gpio_port_as_input(p, o) \
3082 do { \
3083 REG_GPIO_PXFUNC(p) = (1 << (o)); \
3084 REG_GPIO_PXSELC(p) = (1 << (o)); \
3085 REG_GPIO_PXDIRC(p) = (1 << (o)); \
3086 } while (0)
3088 #define __gpio_as_output(n) \
3089 do { \
3090 unsigned int p, o; \
3091 p = (n) / 32; \
3092 o = (n) % 32; \
3093 __gpio_port_as_output(p, o); \
3094 } while (0)
3096 #define __gpio_as_input(n) \
3097 do { \
3098 unsigned int p, o; \
3099 p = (n) / 32; \
3100 o = (n) % 32; \
3101 __gpio_port_as_input(p, o); \
3102 } while (0)
3104 #define __gpio_set_pin(n) \
3105 do { \
3106 unsigned int p, o; \
3107 p = (n) / 32; \
3108 o = (n) % 32; \
3109 REG_GPIO_PXDATS(p) = (1 << o); \
3110 } while (0)
3112 #define __gpio_clear_pin(n) \
3113 do { \
3114 unsigned int p, o; \
3115 p = (n) / 32; \
3116 o = (n) % 32; \
3117 REG_GPIO_PXDATC(p) = (1 << o); \
3118 } while (0)
3120 #define __gpio_get_pin(n) \
3121 ({ \
3122 unsigned int p, o, v; \
3123 p = (n) / 32; \
3124 o = (n) % 32; \
3125 if (__gpio_get_port(p) & (1 << o)) \
3126 v = 1; \
3127 else \
3128 v = 0; \
3129 v; \
3132 #define __gpio_as_irq_high_level(n) \
3133 do { \
3134 unsigned int p, o; \
3135 p = (n) / 32; \
3136 o = (n) % 32; \
3137 REG_GPIO_PXIMS(p) = (1 << o); \
3138 REG_GPIO_PXTRGC(p) = (1 << o); \
3139 REG_GPIO_PXFUNC(p) = (1 << o); \
3140 REG_GPIO_PXSELS(p) = (1 << o); \
3141 REG_GPIO_PXDIRS(p) = (1 << o); \
3142 REG_GPIO_PXFLGC(p) = (1 << o); \
3143 REG_GPIO_PXIMC(p) = (1 << o); \
3144 } while (0)
3146 #define __gpio_as_irq_low_level(n) \
3147 do { \
3148 unsigned int p, o; \
3149 p = (n) / 32; \
3150 o = (n) % 32; \
3151 REG_GPIO_PXIMS(p) = (1 << o); \
3152 REG_GPIO_PXTRGC(p) = (1 << o); \
3153 REG_GPIO_PXFUNC(p) = (1 << o); \
3154 REG_GPIO_PXSELS(p) = (1 << o); \
3155 REG_GPIO_PXDIRC(p) = (1 << o); \
3156 REG_GPIO_PXFLGC(p) = (1 << o); \
3157 REG_GPIO_PXIMC(p) = (1 << o); \
3158 } while (0)
3160 #define __gpio_as_irq_rise_edge(n) \
3161 do { \
3162 unsigned int p, o; \
3163 p = (n) / 32; \
3164 o = (n) % 32; \
3165 REG_GPIO_PXIMS(p) = (1 << o); \
3166 REG_GPIO_PXTRGS(p) = (1 << o); \
3167 REG_GPIO_PXFUNC(p) = (1 << o); \
3168 REG_GPIO_PXSELS(p) = (1 << o); \
3169 REG_GPIO_PXDIRS(p) = (1 << o); \
3170 REG_GPIO_PXFLGC(p) = (1 << o); \
3171 REG_GPIO_PXIMC(p) = (1 << o); \
3172 } while (0)
3174 #define __gpio_as_irq_fall_edge(n) \
3175 do { \
3176 unsigned int p, o; \
3177 p = (n) / 32; \
3178 o = (n) % 32; \
3179 REG_GPIO_PXIMS(p) = (1 << o); \
3180 REG_GPIO_PXTRGS(p) = (1 << o); \
3181 REG_GPIO_PXFUNC(p) = (1 << o); \
3182 REG_GPIO_PXSELS(p) = (1 << o); \
3183 REG_GPIO_PXDIRC(p) = (1 << o); \
3184 REG_GPIO_PXFLGC(p) = (1 << o); \
3185 REG_GPIO_PXIMC(p) = (1 << o); \
3186 } while (0)
3188 #define __gpio_mask_irq(n) \
3189 do { \
3190 unsigned int p, o; \
3191 p = (n) / 32; \
3192 o = (n) % 32; \
3193 REG_GPIO_PXIMS(p) = (1 << o); \
3194 } while (0)
3196 #define __gpio_unmask_irq(n) \
3197 do { \
3198 unsigned int p, o; \
3199 p = (n) / 32; \
3200 o = (n) % 32; \
3201 REG_GPIO_PXIMC(p) = (1 << o); \
3202 } while (0)
3204 #define __gpio_ack_irq(n) \
3205 do { \
3206 unsigned int p, o; \
3207 p = (n) / 32; \
3208 o = (n) % 32; \
3209 REG_GPIO_PXFLGC(p) = (1 << o); \
3210 } while (0)
3212 #define __gpio_get_irq() \
3213 ({ \
3214 unsigned int p, i, tmp, v = 0; \
3215 for (p = 3; p >= 0; p--) { \
3216 tmp = REG_GPIO_PXFLG(p); \
3217 for (i = 0; i < 32; i++) \
3218 if (tmp & (1 << i)) \
3219 v = (32*p + i); \
3221 v; \
3224 #define __gpio_group_irq(n) \
3225 ({ \
3226 register int tmp, i; \
3227 tmp = REG_GPIO_PXFLG((n)); \
3228 for (i=31;i>=0;i--) \
3229 if (tmp & (1 << i)) \
3230 break; \
3231 i; \
3234 #define __gpio_enable_pull(n) \
3235 do { \
3236 unsigned int p, o; \
3237 p = (n) / 32; \
3238 o = (n) % 32; \
3239 REG_GPIO_PXPEC(p) = (1 << o); \
3240 } while (0)
3242 #define __gpio_disable_pull(n) \
3243 do { \
3244 unsigned int p, o; \
3245 p = (n) / 32; \
3246 o = (n) % 32; \
3247 REG_GPIO_PXPES(p) = (1 << o); \
3248 } while (0)
3251 /***************************************************************************
3252 * CPM
3253 ***************************************************************************/
3254 #define __cpm_get_pllm() \
3255 ((REG_CPM_CPPCR & CPM_CPPCR_PLLM_MASK) >> CPM_CPPCR_PLLM_BIT)
3256 #define __cpm_get_plln() \
3257 ((REG_CPM_CPPCR & CPM_CPPCR_PLLN_MASK) >> CPM_CPPCR_PLLN_BIT)
3258 #define __cpm_get_pllod() \
3259 ((REG_CPM_CPPCR & CPM_CPPCR_PLLOD_MASK) >> CPM_CPPCR_PLLOD_BIT)
3261 #define __cpm_get_cdiv() \
3262 ((REG_CPM_CPCCR & CPM_CPCCR_CDIV_MASK) >> CPM_CPCCR_CDIV_BIT)
3263 #define __cpm_get_hdiv() \
3264 ((REG_CPM_CPCCR & CPM_CPCCR_HDIV_MASK) >> CPM_CPCCR_HDIV_BIT)
3265 #define __cpm_get_pdiv() \
3266 ((REG_CPM_CPCCR & CPM_CPCCR_PDIV_MASK) >> CPM_CPCCR_PDIV_BIT)
3267 #define __cpm_get_mdiv() \
3268 ((REG_CPM_CPCCR & CPM_CPCCR_MDIV_MASK) >> CPM_CPCCR_MDIV_BIT)
3269 #define __cpm_get_ldiv() \
3270 ((REG_CPM_CPCCR & CPM_CPCCR_LDIV_MASK) >> CPM_CPCCR_LDIV_BIT)
3271 #define __cpm_get_udiv() \
3272 ((REG_CPM_CPCCR & CPM_CPCCR_UDIV_MASK) >> CPM_CPCCR_UDIV_BIT)
3273 #define __cpm_get_i2sdiv() \
3274 ((REG_CPM_I2SCDR & CPM_I2SCDR_I2SDIV_MASK) >> CPM_I2SCDR_I2SDIV_BIT)
3275 #define __cpm_get_pixdiv() \
3276 ((REG_CPM_LPCDR & CPM_LPCDR_PIXDIV_MASK) >> CPM_LPCDR_PIXDIV_BIT)
3277 #define __cpm_get_mscdiv() \
3278 ((REG_CPM_MSCCDR & CPM_MSCCDR_MSCDIV_MASK) >> CPM_MSCCDR_MSCDIV_BIT)
3280 #define __cpm_set_cdiv(v) \
3281 (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_CDIV_MASK) | ((v) << (CPM_CPCCR_CDIV_BIT)))
3282 #define __cpm_set_hdiv(v) \
3283 (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_HDIV_MASK) | ((v) << (CPM_CPCCR_HDIV_BIT)))
3284 #define __cpm_set_pdiv(v) \
3285 (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_PDIV_MASK) | ((v) << (CPM_CPCCR_PDIV_BIT)))
3286 #define __cpm_set_mdiv(v) \
3287 (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_MDIV_MASK) | ((v) << (CPM_CPCCR_MDIV_BIT)))
3288 #define __cpm_set_ldiv(v) \
3289 (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_LDIV_MASK) | ((v) << (CPM_CPCCR_LDIV_BIT)))
3290 #define __cpm_set_udiv(v) \
3291 (REG_CPM_CPCCR = (REG_CPM_CPCCR & ~CPM_CPCCR_UDIV_MASK) | ((v) << (CPM_CPCCR_UDIV_BIT)))
3292 #define __cpm_set_i2sdiv(v) \
3293 (REG_CPM_I2SCDR = (REG_CPM_I2SCDR & ~CPM_I2SCDR_I2SDIV_MASK) | ((v) << (CPM_I2SCDR_I2SDIV_BIT)))
3294 #define __cpm_set_pixdiv(v) \
3295 (REG_CPM_LPCDR = (REG_CPM_LPCDR & ~CPM_LPCDR_PIXDIV_MASK) | ((v) << (CPM_LPCDR_PIXDIV_BIT)))
3296 #define __cpm_set_mscdiv(v) \
3297 (REG_CPM_MSCCDR = (REG_CPM_MSCCDR & ~CPM_MSCCDR_MSCDIV_MASK) | ((v) << (CPM_MSCCDR_MSCDIV_BIT)))
3299 #define __cpm_select_i2sclk_exclk() (REG_CPM_CPCCR &= ~CPM_CPCCR_I2CS)
3300 #define __cpm_select_i2sclk_pll() (REG_CPM_CPCCR |= CPM_CPCCR_I2CS)
3301 #define __cpm_enable_cko() (REG_CPM_CPCCR |= CPM_CPCCR_CLKOEN)
3302 #define __cpm_select_usbclk_exclk() (REG_CPM_CPCCR &= ~CPM_CPCCR_UCS)
3303 #define __cpm_select_usbclk_pll() (REG_CPM_CPCCR |= CPM_CPCCR_UCS)
3304 #define __cpm_enable_pll_change() (REG_CPM_CPCCR |= CPM_CPCCR_CE)
3305 #define __cpm_pllout_direct() (REG_CPM_CPCCR |= CPM_CPCCR_PCS)
3306 #define __cpm_pllout_div2() (REG_CPM_CPCCR &= ~CPM_CPCCR_PCS)
3308 #define __cpm_pll_is_on() (REG_CPM_CPPCR & CPM_CPPCR_PLLS)
3309 #define __cpm_pll_bypass() (REG_CPM_CPPCR |= CPM_CPPCR_PLLBP)
3310 #define __cpm_pll_enable() (REG_CPM_CPPCR |= CPM_CPPCR_PLLEN)
3312 #define __cpm_get_cclk_doze_duty() \
3313 ((REG_CPM_LCR & CPM_LCR_DOZE_DUTY_MASK) >> CPM_LCR_DOZE_DUTY_BIT)
3314 #define __cpm_set_cclk_doze_duty(v) \
3315 (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_DOZE_DUTY_MASK) | ((v) << (CPM_LCR_DOZE_DUTY_BIT)))
3317 #define __cpm_doze_mode() (REG_CPM_LCR |= CPM_LCR_DOZE_ON)
3318 #define __cpm_idle_mode() \
3319 (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_IDLE)
3320 #define __cpm_sleep_mode() \
3321 (REG_CPM_LCR = (REG_CPM_LCR & ~CPM_LCR_LPM_MASK) | CPM_LCR_LPM_SLEEP)
3323 #define __cpm_stop_all() (REG_CPM_CLKGR = 0xffff)
3324 #define __cpm_stop_uart1() (REG_CPM_CLKGR |= CPM_CLKGR_UART1)
3325 #define __cpm_stop_uhc() (REG_CPM_CLKGR |= CPM_CLKGR_UHC)
3326 #define __cpm_stop_ipu() (REG_CPM_CLKGR |= CPM_CLKGR_IPU)
3327 #define __cpm_stop_dmac() (REG_CPM_CLKGR |= CPM_CLKGR_DMAC)
3328 #define __cpm_stop_udc() (REG_CPM_CLKGR |= CPM_CLKGR_UDC)
3329 #define __cpm_stop_lcd() (REG_CPM_CLKGR |= CPM_CLKGR_LCD)
3330 #define __cpm_stop_cim() (REG_CPM_CLKGR |= CPM_CLKGR_CIM)
3331 #define __cpm_stop_sadc() (REG_CPM_CLKGR |= CPM_CLKGR_SADC)
3332 #define __cpm_stop_msc() (REG_CPM_CLKGR |= CPM_CLKGR_MSC)
3333 #define __cpm_stop_aic1() (REG_CPM_CLKGR |= CPM_CLKGR_AIC1)
3334 #define __cpm_stop_aic2() (REG_CPM_CLKGR |= CPM_CLKGR_AIC2)
3335 #define __cpm_stop_ssi() (REG_CPM_CLKGR |= CPM_CLKGR_SSI)
3336 #define __cpm_stop_i2c() (REG_CPM_CLKGR |= CPM_CLKGR_I2C)
3337 #define __cpm_stop_rtc() (REG_CPM_CLKGR |= CPM_CLKGR_RTC)
3338 #define __cpm_stop_tcu() (REG_CPM_CLKGR |= CPM_CLKGR_TCU)
3339 #define __cpm_stop_uart0() (REG_CPM_CLKGR |= CPM_CLKGR_UART0)
3341 #define __cpm_start_all() (REG_CPM_CLKGR = 0x0)
3342 #define __cpm_start_uart1() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART1)
3343 #define __cpm_start_uhc() (REG_CPM_CLKGR &= ~CPM_CLKGR_UHC)
3344 #define __cpm_start_ipu() (REG_CPM_CLKGR &= ~CPM_CLKGR_IPU)
3345 #define __cpm_start_dmac() (REG_CPM_CLKGR &= ~CPM_CLKGR_DMAC)
3346 #define __cpm_start_udc() (REG_CPM_CLKGR &= ~CPM_CLKGR_UDC)
3347 #define __cpm_start_lcd() (REG_CPM_CLKGR &= ~CPM_CLKGR_LCD)
3348 #define __cpm_start_cim() (REG_CPM_CLKGR &= ~CPM_CLKGR_CIM)
3349 #define __cpm_start_sadc() (REG_CPM_CLKGR &= ~CPM_CLKGR_SADC)
3350 #define __cpm_start_msc() (REG_CPM_CLKGR &= ~CPM_CLKGR_MSC)
3351 #define __cpm_start_aic1() (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC1)
3352 #define __cpm_start_aic2() (REG_CPM_CLKGR &= ~CPM_CLKGR_AIC2)
3353 #define __cpm_start_ssi() (REG_CPM_CLKGR &= ~CPM_CLKGR_SSI)
3354 #define __cpm_start_i2c() (REG_CPM_CLKGR &= ~CPM_CLKGR_I2C)
3355 #define __cpm_start_rtc() (REG_CPM_CLKGR &= ~CPM_CLKGR_RTC)
3356 #define __cpm_start_tcu() (REG_CPM_CLKGR &= ~CPM_CLKGR_TCU)
3357 #define __cpm_start_uart0() (REG_CPM_CLKGR &= ~CPM_CLKGR_UART0)
3359 #define __cpm_get_o1st() \
3360 ((REG_CPM_SCR & CPM_SCR_O1ST_MASK) >> CPM_SCR_O1ST_BIT)
3361 #define __cpm_set_o1st(v) \
3362 (REG_CPM_SCR = (REG_CPM_SCR & ~CPM_SCR_O1ST_MASK) | ((v) << (CPM_SCR_O1ST_BIT)))
3363 #define __cpm_suspend_usbphy() (REG_CPM_SCR |= CPM_SCR_USBPHY_SUSPEND)
3364 #define __cpm_suspend_usbhost() (REG_CPM_SCR |= CPM_SCR_USBHOST_SUSPEND)
3365 #define __cpm_enable_osc_in_sleep() (REG_CPM_SCR |= CPM_SCR_OSC_ENABLE)
3367 #ifdef CFG_EXTAL
3368 #define JZ_EXTAL CFG_EXTAL
3369 #else
3370 #define JZ_EXTAL 3686400
3371 #warning Default EXTCLK is used!
3372 #endif
3373 #define JZ_EXTAL2 32768 /* RTC clock */
3375 /* PLL output frequency */
3376 static __inline__ unsigned int __cpm_get_pllout(void)
3378 unsigned long m, n, no, pllout;
3379 unsigned long cppcr = REG_CPM_CPPCR;
3380 unsigned long od[4] = {1, 2, 2, 4};
3382 if ((cppcr & CPM_CPPCR_PLLEN) && !(cppcr & CPM_CPPCR_PLLBP))
3384 m = __cpm_get_pllm() + 2;
3385 n = __cpm_get_plln() + 2;
3386 no = od[__cpm_get_pllod()];
3387 pllout = ((JZ_EXTAL) / (n * no)) * m;
3389 else
3390 pllout = JZ_EXTAL;
3392 return pllout;
3395 /* PLL output frequency for MSC/I2S/LCD/USB */
3396 static __inline__ unsigned int __cpm_get_pllout2(void)
3398 if (REG_CPM_CPCCR & CPM_CPCCR_PCS)
3399 return __cpm_get_pllout();
3400 else
3401 return __cpm_get_pllout()/2;
3404 /* CPU core clock */
3405 static __inline__ unsigned int __cpm_get_cclk(void)
3407 int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
3409 return __cpm_get_pllout() / div[__cpm_get_cdiv()];
3412 /* AHB system bus clock */
3413 static __inline__ unsigned int __cpm_get_hclk(void)
3415 int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
3417 return __cpm_get_pllout() / div[__cpm_get_hdiv()];
3420 /* Memory bus clock */
3421 static __inline__ unsigned int __cpm_get_mclk(void)
3423 int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
3425 return __cpm_get_pllout() / div[__cpm_get_mdiv()];
3428 /* APB peripheral bus clock */
3429 static __inline__ unsigned int __cpm_get_pclk(void)
3431 int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
3433 return __cpm_get_pllout() / div[__cpm_get_pdiv()];
3436 /* LCDC module clock */
3437 static __inline__ unsigned int __cpm_get_lcdclk(void)
3439 return __cpm_get_pllout2() / (__cpm_get_ldiv() + 1);
3442 /* LCD pixel clock */
3443 static __inline__ unsigned int __cpm_get_pixclk(void)
3445 return __cpm_get_pllout2() / (__cpm_get_pixdiv() + 1);
3448 /* I2S clock */
3449 static __inline__ unsigned int __cpm_get_i2sclk(void)
3451 if (REG_CPM_CPCCR & CPM_CPCCR_I2CS)
3452 return __cpm_get_pllout2() / (__cpm_get_i2sdiv() + 1);
3453 else
3454 return JZ_EXTAL;
3457 /* USB clock */
3458 static __inline__ unsigned int __cpm_get_usbclk(void)
3460 if (REG_CPM_CPCCR & CPM_CPCCR_UCS)
3461 return __cpm_get_pllout2() / (__cpm_get_udiv() + 1);
3462 else
3463 return JZ_EXTAL;
3466 /* MSC clock */
3467 static __inline__ unsigned int __cpm_get_mscclk(void)
3469 return __cpm_get_pllout2() / (__cpm_get_mscdiv() + 1);
3472 /* EXTAL clock for UART,I2C,SSI,TCU,USB-PHY */
3473 static __inline__ unsigned int __cpm_get_extalclk(void)
3475 return JZ_EXTAL;
3478 /* RTC clock for CPM,INTC,RTC,TCU,WDT */
3479 static __inline__ unsigned int __cpm_get_rtcclk(void)
3481 return JZ_EXTAL2;
3485 * Output 24MHz for SD and 16MHz for MMC.
3487 static __inline__ void __cpm_select_msc_clk(int sd)
3489 unsigned int pllout2 = __cpm_get_pllout2();
3490 unsigned int div = 0;
3492 if (sd)
3493 div = pllout2 / 24000000;
3494 else
3495 div = pllout2 / 16000000;
3497 REG_CPM_MSCCDR = div - 1;
3501 * Output 48MHz for SD and 16MHz for MMC.
3503 static __inline__ void __cpm_select_msc_hs_clk(int sd)
3505 unsigned int pllout2 = __cpm_get_pllout2();
3506 unsigned int div = 0;
3508 if (sd)
3509 div = pllout2 / 48000000;
3510 else
3511 div = pllout2 / 16000000;
3513 REG_CPM_MSCCDR = div - 1;
3516 /***************************************************************************
3517 * TCU
3518 ***************************************************************************/
3519 // where 'n' is the TCU channel
3520 #define __tcu_select_extalclk(n) \
3521 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_EXT_EN)
3522 #define __tcu_select_rtcclk(n) \
3523 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_RTC_EN)
3524 #define __tcu_select_pclk(n) \
3525 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~(TCU_TCSR_EXT_EN | TCU_TCSR_RTC_EN | TCU_TCSR_PCK_EN)) | TCU_TCSR_PCK_EN)
3527 #define __tcu_select_clk_div1(n) \
3528 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE1)
3529 #define __tcu_select_clk_div4(n) \
3530 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE4)
3531 #define __tcu_select_clk_div16(n) \
3532 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE16)
3533 #define __tcu_select_clk_div64(n) \
3534 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE64)
3535 #define __tcu_select_clk_div256(n) \
3536 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE256)
3537 #define __tcu_select_clk_div1024(n) \
3538 (REG_TCU_TCSR((n)) = (REG_TCU_TCSR((n)) & ~TCU_TCSR_PRESCALE_MASK) | TCU_TCSR_PRESCALE1024)
3540 #define __tcu_enable_pwm_output(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_EN )
3541 #define __tcu_disable_pwm_output(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_EN )
3543 #define __tcu_init_pwm_output_high(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_INITL_HIGH )
3544 #define __tcu_init_pwm_output_low(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_INITL_HIGH )
3546 #define __tcu_set_pwm_output_shutdown_graceful(n) ( REG_TCU_TCSR((n)) &= ~TCU_TCSR_PWM_SD )
3547 #define __tcu_set_pwm_output_shutdown_abrupt(n) ( REG_TCU_TCSR((n)) |= TCU_TCSR_PWM_SD )
3549 #define __tcu_start_counter(n) ( REG_TCU_TESR |= (1 << (n)) )
3550 #define __tcu_stop_counter(n) ( REG_TCU_TECR |= (1 << (n)) )
3552 #define __tcu_half_match_flag(n) ( REG_TCU_TFR & (1 << ((n) + 16)) )
3553 #define __tcu_full_match_flag(n) ( REG_TCU_TFR & (1 << (n)) )
3554 #define __tcu_set_half_match_flag(n) ( REG_TCU_TFSR = (1 << ((n) + 16)) )
3555 #define __tcu_set_full_match_flag(n) ( REG_TCU_TFSR = (1 << (n)) )
3556 #define __tcu_clear_half_match_flag(n) ( REG_TCU_TFCR = (1 << ((n) + 16)) )
3557 #define __tcu_clear_full_match_flag(n) ( REG_TCU_TFCR = (1 << (n)) )
3558 #define __tcu_mask_half_match_irq(n) ( REG_TCU_TMSR = (1 << ((n) + 16)) )
3559 #define __tcu_mask_full_match_irq(n) ( REG_TCU_TMSR = (1 << (n)) )
3560 #define __tcu_unmask_half_match_irq(n) ( REG_TCU_TMCR = (1 << ((n) + 16)) )
3561 #define __tcu_unmask_full_match_irq(n) ( REG_TCU_TMCR = (1 << (n)) )
3563 #define __tcu_wdt_clock_stopped() ( REG_TCU_TSR & TCU_TSSR_WDTSC )
3564 #define __tcu_timer_clock_stopped(n) ( REG_TCU_TSR & (1 << (n)) )
3566 #define __tcu_start_wdt_clock() ( REG_TCU_TSCR = TCU_TSSR_WDTSC )
3567 #define __tcu_start_timer_clock(n) ( REG_TCU_TSCR = (1 << (n)) )
3569 #define __tcu_stop_wdt_clock() ( REG_TCU_TSSR = TCU_TSSR_WDTSC )
3570 #define __tcu_stop_timer_clock(n) ( REG_TCU_TSSR = (1 << (n)) )
3572 #define __tcu_get_count(n) ( REG_TCU_TCNT((n)) )
3573 #define __tcu_set_count(n,v) ( REG_TCU_TCNT((n)) = (v) )
3574 #define __tcu_set_full_data(n,v) ( REG_TCU_TDFR((n)) = (v) )
3575 #define __tcu_set_half_data(n,v) ( REG_TCU_TDHR((n)) = (v) )
3578 /***************************************************************************
3579 * WDT
3580 ***************************************************************************/
3581 #define __wdt_start() ( REG_WDT_TCER |= WDT_TCER_TCEN )
3582 #define __wdt_stop() ( REG_WDT_TCER &= ~WDT_TCER_TCEN )
3583 #define __wdt_set_count(v) ( REG_WDT_TCNT = (v) )
3584 #define __wdt_set_data(v) ( REG_WDT_TDR = (v) )
3586 #define __wdt_select_extalclk() \
3587 (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_EXT_EN)
3588 #define __wdt_select_rtcclk() \
3589 (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_RTC_EN)
3590 #define __wdt_select_pclk() \
3591 (REG_WDT_TCSR = (REG_WDT_TCSR & ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN)) | WDT_TCSR_PCK_EN)
3593 #define __wdt_select_clk_div1() \
3594 (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE1)
3595 #define __wdt_select_clk_div4() \
3596 (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE4)
3597 #define __wdt_select_clk_div16() \
3598 (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE16)
3599 #define __wdt_select_clk_div64() \
3600 (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE64)
3601 #define __wdt_select_clk_div256() \
3602 (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE256)
3603 #define __wdt_select_clk_div1024() \
3604 (REG_WDT_TCSR = (REG_WDT_TCSR & ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE1024)
3607 /***************************************************************************
3608 * UART
3609 ***************************************************************************/
3611 #define __uart_enable() ( REG8(UART0_FCR) |= UARTFCR_UUE | UARTFCR_FE )
3612 #define __uart_disable() ( REG8(UART0_FCR) = ~UARTFCR_UUE )
3614 #define __uart_enable_transmit_irq() ( REG8(UART0_IER) |= UARTIER_TIE )
3615 #define __uart_disable_transmit_irq() ( REG8(UART0_IER) &= ~UARTIER_TIE )
3617 #define __uart_enable_receive_irq() \
3618 ( REG8(UART0_IER) |= UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE )
3619 #define __uart_disable_receive_irq() \
3620 ( REG8(UART0_IER) &= ~(UARTIER_RIE | UARTIER_RLIE | UARTIER_RTIE) )
3622 #define __uart_enable_loopback() ( REG8(UART0_MCR) |= UARTMCR_LOOP )
3623 #define __uart_disable_loopback() ( REG8(UART0_MCR) &= ~UARTMCR_LOOP )
3625 #define __uart_set_8n1() ( REG8(UART0_LCR) = UARTLCR_WLEN_8 )
3627 #define __uart_set_baud(devclk, baud) \
3628 do { \
3629 REG8(UART0_LCR) |= UARTLCR_DLAB; \
3630 REG8(UART0_DLLR) = (devclk / 16 / baud) & 0xff; \
3631 REG8(UART0_DLHR) = ((devclk / 16 / baud) >> 8) & 0xff; \
3632 REG8(UART0_LCR) &= ~UARTLCR_DLAB; \
3633 } while (0)
3635 #define __uart_parity_error() ( (REG8(UART0_LSR) & UARTLSR_PER) != 0 )
3636 #define __uart_clear_errors() \
3637 ( REG8(UART0_LSR) &= ~(UARTLSR_ORER | UARTLSR_BRK | UARTLSR_FER | UARTLSR_PER | UARTLSR_RFER) )
3639 #define __uart_transmit_fifo_empty() ( (REG8(UART0_LSR) & UARTLSR_TDRQ) != 0 )
3640 #define __uart_transmit_end() ( (REG8(UART0_LSR) & UARTLSR_TEMT) != 0 )
3641 #define __uart_transmit_char(ch) ( REG8(UART0_TDR) = (ch) )
3642 #define __uart_receive_fifo_full() ( (REG8(UART0_LSR) & UARTLSR_DR) != 0 )
3643 #define __uart_receive_ready() ( (REG8(UART0_LSR) & UARTLSR_DR) != 0 )
3644 #define __uart_receive_char() REG8(UART0_RDR)
3645 #define __uart_disable_irda() ( REG8(UART0_SIRCR) &= ~(SIRCR_TSIRE | SIRCR_RSIRE) )
3646 #define __uart_enable_irda() \
3647 /* Tx high pulse as 0, Rx low pulse as 0 */ \
3648 ( REG8(UART0_SIRCR) = SIRCR_TSIRE | SIRCR_RSIRE | SIRCR_RXPL | SIRCR_TPWS )
3651 /***************************************************************************
3652 * DMAC
3653 ***************************************************************************/
3655 /* n is the DMA channel (0 - 5) */
3657 #define __dmac_enable_module() \
3658 ( REG_DMAC_DMACR |= DMAC_DMACR_DMAE | DMAC_DMACR_PR_RR )
3659 #define __dmac_disable_module() \
3660 ( REG_DMAC_DMACR &= ~DMAC_DMACR_DMAE )
3662 /* p=0,1,2,3 */
3663 #define __dmac_set_priority(p) \
3664 do { \
3665 REG_DMAC_DMACR &= ~DMAC_DMACR_PR_MASK; \
3666 REG_DMAC_DMACR |= ((p) << DMAC_DMACR_PR_BIT); \
3667 } while (0)
3669 #define __dmac_test_halt_error() ( REG_DMAC_DMACR & DMAC_DMACR_HLT )
3670 #define __dmac_test_addr_error() ( REG_DMAC_DMACR & DMAC_DMACR_AR )
3672 #define __dmac_enable_descriptor(n) \
3673 ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_NDES )
3674 #define __dmac_disable_descriptor(n) \
3675 ( REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_NDES )
3677 #define __dmac_enable_channel(n) \
3678 ( REG_DMAC_DCCSR((n)) |= DMAC_DCCSR_EN )
3679 #define __dmac_disable_channel(n) \
3680 ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_EN )
3681 #define __dmac_channel_enabled(n) \
3682 ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_EN )
3684 #define __dmac_channel_enable_irq(n) \
3685 ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_TIE )
3686 #define __dmac_channel_disable_irq(n) \
3687 ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TIE )
3689 #define __dmac_channel_transmit_halt_detected(n) \
3690 ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_HLT )
3691 #define __dmac_channel_transmit_end_detected(n) \
3692 ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_TT )
3693 #define __dmac_channel_address_error_detected(n) \
3694 ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_AR )
3695 #define __dmac_channel_count_terminated_detected(n) \
3696 ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_CT )
3697 #define __dmac_channel_descriptor_invalid_detected(n) \
3698 ( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_INV )
3700 #define __dmac_channel_clear_transmit_halt(n) \
3701 ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_HLT )
3702 #define __dmac_channel_clear_transmit_end(n) \
3703 ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_TT )
3704 #define __dmac_channel_clear_address_error(n) \
3705 ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_AR )
3706 #define __dmac_channel_clear_count_terminated(n) \
3707 ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_CT )
3708 #define __dmac_channel_clear_descriptor_invalid(n) \
3709 ( REG_DMAC_DCCSR((n)) &= ~DMAC_DCCSR_INV )
3711 #define __dmac_channel_set_single_mode(n) \
3712 ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_TM )
3713 #define __dmac_channel_set_block_mode(n) \
3714 ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_TM )
3716 #define __dmac_channel_set_transfer_unit_32bit(n) \
3717 do { \
3718 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
3719 REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BIT; \
3720 } while (0)
3722 #define __dmac_channel_set_transfer_unit_16bit(n) \
3723 do { \
3724 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
3725 REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BIT; \
3726 } while (0)
3728 #define __dmac_channel_set_transfer_unit_8bit(n) \
3729 do { \
3730 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
3731 REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_8BIT; \
3732 } while (0)
3734 #define __dmac_channel_set_transfer_unit_16byte(n) \
3735 do { \
3736 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
3737 REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_16BYTE; \
3738 } while (0)
3740 #define __dmac_channel_set_transfer_unit_32byte(n) \
3741 do { \
3742 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DS_MASK; \
3743 REG_DMAC_DCMD((n)) |= DMAC_DCMD_DS_32BYTE; \
3744 } while (0)
3746 /* w=8,16,32 */
3747 #define __dmac_channel_set_dest_port_width(n,w) \
3748 do { \
3749 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DWDH_MASK; \
3750 REG_DMAC_DCMD((n)) |= DMAC_DCMD_DWDH_##w; \
3751 } while (0)
3753 /* w=8,16,32 */
3754 #define __dmac_channel_set_src_port_width(n,w) \
3755 do { \
3756 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SWDH_MASK; \
3757 REG_DMAC_DCMD((n)) |= DMAC_DCMD_SWDH_##w; \
3758 } while (0)
3760 /* v=0-15 */
3761 #define __dmac_channel_set_rdil(n,v) \
3762 do { \
3763 REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_RDIL_MASK; \
3764 REG_DMAC_DCMD((n)) |= ((v) << DMAC_DCMD_RDIL_BIT); \
3765 } while (0)
3767 #define __dmac_channel_dest_addr_fixed(n) \
3768 ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_DAI )
3769 #define __dmac_channel_dest_addr_increment(n) \
3770 ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_DAI )
3772 #define __dmac_channel_src_addr_fixed(n) \
3773 ( REG_DMAC_DCMD((n)) &= ~DMAC_DCMD_SAI )
3774 #define __dmac_channel_src_addr_increment(n) \
3775 ( REG_DMAC_DCMD((n)) |= DMAC_DCMD_SAI )
3777 #define __dmac_channel_set_doorbell(n) \
3778 ( REG_DMAC_DMADBSR = (1 << (n)) )
3780 #define __dmac_channel_irq_detected(n) ( REG_DMAC_DMAIPR & (1 << (n)) )
3781 #define __dmac_channel_ack_irq(n) ( REG_DMAC_DMAIPR &= ~(1 << (n)) )
3783 static __inline__ int __dmac_get_irq(void)
3785 int i;
3786 for (i = 0; i < MAX_DMA_NUM; i++)
3787 if (__dmac_channel_irq_detected(i))
3788 return i;
3789 return -1;
3793 /***************************************************************************
3794 * AIC (AC'97 & I2S Controller)
3795 ***************************************************************************/
3797 #define __aic_enable() ( REG_AIC_FR |= AIC_FR_ENB )
3798 #define __aic_disable() ( REG_AIC_FR &= ~AIC_FR_ENB )
3800 #define __aic_select_ac97() ( REG_AIC_FR &= ~AIC_FR_AUSEL )
3801 #define __aic_select_i2s() ( REG_AIC_FR |= AIC_FR_AUSEL )
3803 #define __i2s_as_master() ( REG_AIC_FR |= AIC_FR_BCKD | AIC_FR_SYNCD )
3804 #define __i2s_as_slave() ( REG_AIC_FR &= ~(AIC_FR_BCKD | AIC_FR_SYNCD) )
3805 #define __aic_reset_status() ( REG_AIC_FR & AIC_FR_RST )
3807 #define __aic_reset() \
3808 do { \
3809 REG_AIC_FR |= AIC_FR_RST; \
3810 } while(0)
3813 #define __aic_set_transmit_trigger(n) \
3814 do { \
3815 REG_AIC_FR &= ~AIC_FR_TFTH_MASK; \
3816 REG_AIC_FR |= ((n) << AIC_FR_TFTH_BIT); \
3817 } while(0)
3819 #define __aic_set_receive_trigger(n) \
3820 do { \
3821 REG_AIC_FR &= ~AIC_FR_RFTH_MASK; \
3822 REG_AIC_FR |= ((n) << AIC_FR_RFTH_BIT); \
3823 } while(0)
3825 #define __aic_enable_record() ( REG_AIC_CR |= AIC_CR_EREC )
3826 #define __aic_disable_record() ( REG_AIC_CR &= ~AIC_CR_EREC )
3827 #define __aic_enable_replay() ( REG_AIC_CR |= AIC_CR_ERPL )
3828 #define __aic_disable_replay() ( REG_AIC_CR &= ~AIC_CR_ERPL )
3829 #define __aic_enable_loopback() ( REG_AIC_CR |= AIC_CR_ENLBF )
3830 #define __aic_disable_loopback() ( REG_AIC_CR &= ~AIC_CR_ENLBF )
3832 #define __aic_flush_fifo() ( REG_AIC_CR |= AIC_CR_FLUSH )
3833 #define __aic_unflush_fifo() ( REG_AIC_CR &= ~AIC_CR_FLUSH )
3835 #define __aic_enable_transmit_intr() \
3836 ( REG_AIC_CR |= (AIC_CR_ETFS | AIC_CR_ETUR) )
3837 #define __aic_disable_transmit_intr() \
3838 ( REG_AIC_CR &= ~(AIC_CR_ETFS | AIC_CR_ETUR) )
3839 #define __aic_enable_receive_intr() \
3840 ( REG_AIC_CR |= (AIC_CR_ERFS | AIC_CR_EROR) )
3841 #define __aic_disable_receive_intr() \
3842 ( REG_AIC_CR &= ~(AIC_CR_ERFS | AIC_CR_EROR) )
3844 #define __aic_enable_transmit_dma() ( REG_AIC_CR |= AIC_CR_TDMS )
3845 #define __aic_disable_transmit_dma() ( REG_AIC_CR &= ~AIC_CR_TDMS )
3846 #define __aic_enable_receive_dma() ( REG_AIC_CR |= AIC_CR_RDMS )
3847 #define __aic_disable_receive_dma() ( REG_AIC_CR &= ~AIC_CR_RDMS )
3849 #define __aic_enable_mono2stereo() ( REG_AIC_CR |= AIC_CR_M2S )
3850 #define __aic_disable_mono2stereo() ( REG_AIC_CR &= ~AIC_CR_M2S )
3851 #define __aic_enable_byteswap() ( REG_AIC_CR |= AIC_CR_ENDSW )
3852 #define __aic_disable_byteswap() ( REG_AIC_CR &= ~AIC_CR_ENDSW )
3853 #define __aic_enable_unsignadj() ( REG_AIC_CR |= AIC_CR_AVSTSU )
3854 #define __aic_disable_unsignadj() ( REG_AIC_CR &= ~AIC_CR_AVSTSU )
3856 #define AC97_PCM_XS_L_FRONT AIC_ACCR1_XS_SLOT3
3857 #define AC97_PCM_XS_R_FRONT AIC_ACCR1_XS_SLOT4
3858 #define AC97_PCM_XS_CENTER AIC_ACCR1_XS_SLOT6
3859 #define AC97_PCM_XS_L_SURR AIC_ACCR1_XS_SLOT7
3860 #define AC97_PCM_XS_R_SURR AIC_ACCR1_XS_SLOT8
3861 #define AC97_PCM_XS_LFE AIC_ACCR1_XS_SLOT9
3863 #define AC97_PCM_RS_L_FRONT AIC_ACCR1_RS_SLOT3
3864 #define AC97_PCM_RS_R_FRONT AIC_ACCR1_RS_SLOT4
3865 #define AC97_PCM_RS_CENTER AIC_ACCR1_RS_SLOT6
3866 #define AC97_PCM_RS_L_SURR AIC_ACCR1_RS_SLOT7
3867 #define AC97_PCM_RS_R_SURR AIC_ACCR1_RS_SLOT8
3868 #define AC97_PCM_RS_LFE AIC_ACCR1_RS_SLOT9
3870 #define __ac97_set_xs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK )
3871 #define __ac97_set_xs_mono() \
3872 do { \
3873 REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \
3874 REG_AIC_ACCR1 |= AC97_PCM_XS_R_FRONT; \
3875 } while(0)
3876 #define __ac97_set_xs_stereo() \
3877 do { \
3878 REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \
3879 REG_AIC_ACCR1 |= AC97_PCM_XS_L_FRONT | AC97_PCM_XS_R_FRONT; \
3880 } while(0)
3882 /* In fact, only stereo is support now. */
3883 #define __ac97_set_rs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK )
3884 #define __ac97_set_rs_mono() \
3885 do { \
3886 REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \
3887 REG_AIC_ACCR1 |= AC97_PCM_RS_R_FRONT; \
3888 } while(0)
3889 #define __ac97_set_rs_stereo() \
3890 do { \
3891 REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \
3892 REG_AIC_ACCR1 |= AC97_PCM_RS_L_FRONT | AC97_PCM_RS_R_FRONT; \
3893 } while(0)
3895 #define __ac97_warm_reset_codec() \
3896 do { \
3897 REG_AIC_ACCR2 |= AIC_ACCR2_SA; \
3898 REG_AIC_ACCR2 |= AIC_ACCR2_SS; \
3899 udelay(2); \
3900 REG_AIC_ACCR2 &= ~AIC_ACCR2_SS; \
3901 REG_AIC_ACCR2 &= ~AIC_ACCR2_SA; \
3902 } while (0)
3904 #define __ac97_cold_reset_codec() \
3905 do { \
3906 REG_AIC_ACCR2 |= AIC_ACCR2_SR; \
3907 udelay(2); \
3908 REG_AIC_ACCR2 &= ~AIC_ACCR2_SR; \
3909 } while (0)
3911 /* n=8,16,18,20 */
3912 #define __ac97_set_iass(n) \
3913 ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_IASS_MASK) | AIC_ACCR2_IASS_##n##BIT )
3914 #define __ac97_set_oass(n) \
3915 ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_OASS_MASK) | AIC_ACCR2_OASS_##n##BIT )
3917 #define __i2s_select_i2s() ( REG_AIC_I2SCR &= ~AIC_I2SCR_AMSL )
3918 #define __i2s_select_msbjustified() ( REG_AIC_I2SCR |= AIC_I2SCR_AMSL )
3920 /* n=8,16,18,20,24 */
3921 /*#define __i2s_set_sample_size(n) \
3922 ( REG_AIC_I2SCR |= (REG_AIC_I2SCR & ~AIC_I2SCR_WL_MASK) | AIC_I2SCR_WL_##n##BIT )*/
3924 #define __i2s_set_oss_sample_size(n) \
3925 ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_OSS_MASK) | AIC_CR_OSS_##n##BIT )
3926 #define __i2s_set_iss_sample_size(n) \
3927 ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_ISS_MASK) | AIC_CR_ISS_##n##BIT )
3929 #define __i2s_stop_bitclk() ( REG_AIC_I2SCR |= AIC_I2SCR_STPBK )
3930 #define __i2s_start_bitclk() ( REG_AIC_I2SCR &= ~AIC_I2SCR_STPBK )
3932 #define __aic_transmit_request() ( REG_AIC_SR & AIC_SR_TFS )
3933 #define __aic_receive_request() ( REG_AIC_SR & AIC_SR_RFS )
3934 #define __aic_transmit_underrun() ( REG_AIC_SR & AIC_SR_TUR )
3935 #define __aic_receive_overrun() ( REG_AIC_SR & AIC_SR_ROR )
3937 #define __aic_clear_errors() ( REG_AIC_SR &= ~(AIC_SR_TUR | AIC_SR_ROR) )
3939 #define __aic_get_transmit_resident() \
3940 ( (REG_AIC_SR & AIC_SR_TFL_MASK) >> AIC_SR_TFL_BIT )
3941 #define __aic_get_receive_count() \
3942 ( (REG_AIC_SR & AIC_SR_RFL_MASK) >> AIC_SR_RFL_BIT )
3944 #define __ac97_command_transmitted() ( REG_AIC_ACSR & AIC_ACSR_CADT )
3945 #define __ac97_status_received() ( REG_AIC_ACSR & AIC_ACSR_SADR )
3946 #define __ac97_status_receive_timeout() ( REG_AIC_ACSR & AIC_ACSR_RSTO )
3947 #define __ac97_codec_is_low_power_mode() ( REG_AIC_ACSR & AIC_ACSR_CLPM )
3948 #define __ac97_codec_is_ready() ( REG_AIC_ACSR & AIC_ACSR_CRDY )
3949 #define __ac97_slot_error_detected() ( REG_AIC_ACSR & AIC_ACSR_SLTERR )
3950 #define __ac97_clear_slot_error() ( REG_AIC_ACSR &= ~AIC_ACSR_SLTERR )
3952 #define __i2s_is_busy() ( REG_AIC_I2SSR & AIC_I2SSR_BSY )
3954 #define CODEC_READ_CMD (1 << 19)
3955 #define CODEC_WRITE_CMD (0 << 19)
3956 #define CODEC_REG_INDEX_BIT 12
3957 #define CODEC_REG_INDEX_MASK (0x7f << CODEC_REG_INDEX_BIT) /* 18:12 */
3958 #define CODEC_REG_DATA_BIT 4
3959 #define CODEC_REG_DATA_MASK (0x0ffff << 4) /* 19:4 */
3961 #define __ac97_out_rcmd_addr(reg) \
3962 do { \
3963 REG_AIC_ACCAR = CODEC_READ_CMD | ((reg) << CODEC_REG_INDEX_BIT); \
3964 } while (0)
3966 #define __ac97_out_wcmd_addr(reg) \
3967 do { \
3968 REG_AIC_ACCAR = CODEC_WRITE_CMD | ((reg) << CODEC_REG_INDEX_BIT); \
3969 } while (0)
3971 #define __ac97_out_data(value) \
3972 do { \
3973 REG_AIC_ACCDR = ((value) << CODEC_REG_DATA_BIT); \
3974 } while (0)
3976 #define __ac97_in_data() \
3977 ( (REG_AIC_ACSDR & CODEC_REG_DATA_MASK) >> CODEC_REG_DATA_BIT )
3979 #define __ac97_in_status_addr() \
3980 ( (REG_AIC_ACSAR & CODEC_REG_INDEX_MASK) >> CODEC_REG_INDEX_BIT )
3982 #define __i2s_set_sample_rate(i2sclk, sync) \
3983 ( REG_AIC_I2SDIV = ((i2sclk) / (4*64)) / (sync) )
3985 #define __aic_write_tfifo(v) ( REG_AIC_DR = (v) )
3986 #define __aic_read_rfifo() ( REG_AIC_DR )
3988 #define __aic_internal_codec() ( REG_AIC_FR |= AIC_FR_ICDC )
3989 #define __aic_external_codec() ( REG_AIC_FR &= ~AIC_FR_ICDC )
3991 #define AIC_FR_LSMP (1 << 6)
3992 #define __aic_play_lastsample() ( REG_AIC_FR |= AIC_FR_LSMP )
3994 // Define next ops for AC97 compatible
3997 #define AC97_ACSR AIC_ACSR
3999 #define __ac97_enable() __aic_enable(); __aic_select_ac97()
4000 #define __ac97_disable() __aic_disable()
4001 #define __ac97_reset() __aic_reset()
4003 #define __ac97_set_transmit_trigger(n) __aic_set_transmit_trigger(n)
4004 #define __ac97_set_receive_trigger(n) __aic_set_receive_trigger(n)
4006 #define __ac97_enable_record() __aic_enable_record()
4007 #define __ac97_disable_record() __aic_disable_record()
4008 #define __ac97_enable_replay() __aic_enable_replay()
4009 #define __ac97_disable_replay() __aic_disable_replay()
4010 #define __ac97_enable_loopback() __aic_enable_loopback()
4011 #define __ac97_disable_loopback() __aic_disable_loopback()
4013 #define __ac97_enable_transmit_dma() __aic_enable_transmit_dma()
4014 #define __ac97_disable_transmit_dma() __aic_disable_transmit_dma()
4015 #define __ac97_enable_receive_dma() __aic_enable_receive_dma()
4016 #define __ac97_disable_receive_dma() __aic_disable_receive_dma()
4018 #define __ac97_transmit_request() __aic_transmit_request()
4019 #define __ac97_receive_request() __aic_receive_request()
4020 #define __ac97_transmit_underrun() __aic_transmit_underrun()
4021 #define __ac97_receive_overrun() __aic_receive_overrun()
4023 #define __ac97_clear_errors() __aic_clear_errors()
4025 #define __ac97_get_transmit_resident() __aic_get_transmit_resident()
4026 #define __ac97_get_receive_count() __aic_get_receive_count()
4028 #define __ac97_enable_transmit_intr() __aic_enable_transmit_intr()
4029 #define __ac97_disable_transmit_intr() __aic_disable_transmit_intr()
4030 #define __ac97_enable_receive_intr() __aic_enable_receive_intr()
4031 #define __ac97_disable_receive_intr() __aic_disable_receive_intr()
4033 #define __ac97_write_tfifo(v) __aic_write_tfifo(v)
4034 #define __ac97_read_rfifo() __aic_read_rfifo()
4037 // Define next ops for I2S compatible
4040 #define I2S_ACSR AIC_I2SSR
4042 #define __i2s_enable() __aic_enable(); __aic_select_i2s()
4043 #define __i2s_disable() __aic_disable()
4044 #define __i2s_reset() __aic_reset()
4046 #define __i2s_set_transmit_trigger(n) __aic_set_transmit_trigger(n)
4047 #define __i2s_set_receive_trigger(n) __aic_set_receive_trigger(n)
4049 #define __i2s_enable_record() __aic_enable_record()
4050 #define __i2s_disable_record() __aic_disable_record()
4051 #define __i2s_enable_replay() __aic_enable_replay()
4052 #define __i2s_disable_replay() __aic_disable_replay()
4053 #define __i2s_enable_loopback() __aic_enable_loopback()
4054 #define __i2s_disable_loopback() __aic_disable_loopback()
4056 #define __i2s_enable_transmit_dma() __aic_enable_transmit_dma()
4057 #define __i2s_disable_transmit_dma() __aic_disable_transmit_dma()
4058 #define __i2s_enable_receive_dma() __aic_enable_receive_dma()
4059 #define __i2s_disable_receive_dma() __aic_disable_receive_dma()
4061 #define __i2s_transmit_request() __aic_transmit_request()
4062 #define __i2s_receive_request() __aic_receive_request()
4063 #define __i2s_transmit_underrun() __aic_transmit_underrun()
4064 #define __i2s_receive_overrun() __aic_receive_overrun()
4066 #define __i2s_clear_errors() __aic_clear_errors()
4068 #define __i2s_get_transmit_resident() __aic_get_transmit_resident()
4069 #define __i2s_get_receive_count() __aic_get_receive_count()
4071 #define __i2s_enable_transmit_intr() __aic_enable_transmit_intr()
4072 #define __i2s_disable_transmit_intr() __aic_disable_transmit_intr()
4073 #define __i2s_enable_receive_intr() __aic_enable_receive_intr()
4074 #define __i2s_disable_receive_intr() __aic_disable_receive_intr()
4076 #define __i2s_write_tfifo(v) __aic_write_tfifo(v)
4077 #define __i2s_read_rfifo() __aic_read_rfifo()
4079 #define __i2s_reset_codec() \
4080 do { \
4081 } while (0)
4084 /***************************************************************************
4085 * ICDC
4086 ***************************************************************************/
4087 #define __i2s_internal_codec() __aic_internal_codec()
4088 #define __i2s_external_codec() __aic_external_codec()
4090 /***************************************************************************
4091 * INTC
4092 ***************************************************************************/
4093 #define __intc_unmask_irq(n) ( REG_INTC_IMCR = (1 << (n)) )
4094 #define __intc_mask_irq(n) ( REG_INTC_IMSR = (1 << (n)) )
4095 #define __intc_ack_irq(n) ( REG_INTC_IPR = (1 << (n)) )
4098 /***************************************************************************
4099 * I2C
4100 ***************************************************************************/
4102 #define __i2c_enable() ( REG_I2C_CR |= I2C_CR_I2CE )
4103 #define __i2c_disable() ( REG_I2C_CR &= ~I2C_CR_I2CE )
4105 #define __i2c_send_start() ( REG_I2C_CR |= I2C_CR_STA )
4106 #define __i2c_send_stop() ( REG_I2C_CR |= I2C_CR_STO )
4107 #define __i2c_send_ack() ( REG_I2C_CR &= ~I2C_CR_AC )
4108 #define __i2c_send_nack() ( REG_I2C_CR |= I2C_CR_AC )
4110 #define __i2c_set_drf() ( REG_I2C_SR |= I2C_SR_DRF )
4111 #define __i2c_clear_drf() ( REG_I2C_SR &= ~I2C_SR_DRF )
4112 #define __i2c_check_drf() ( REG_I2C_SR & I2C_SR_DRF )
4114 #define __i2c_received_ack() ( !(REG_I2C_SR & I2C_SR_ACKF) )
4115 #define __i2c_is_busy() ( REG_I2C_SR & I2C_SR_BUSY )
4116 #define __i2c_transmit_ended() ( REG_I2C_SR & I2C_SR_TEND )
4118 #define __i2c_set_clk(dev_clk, i2c_clk) \
4119 ( REG_I2C_GR = (dev_clk) / (16*(i2c_clk)) - 1 )
4121 #define __i2c_read() ( REG_I2C_DR )
4122 #define __i2c_write(val) ( REG_I2C_DR = (val) )
4125 /***************************************************************************
4126 * MSC
4127 ***************************************************************************/
4129 #define __msc_start_op() \
4130 ( REG_MSC_STRPCL = MSC_STRPCL_START_OP | MSC_STRPCL_CLOCK_CONTROL_START )
4132 #define __msc_set_resto(to) ( REG_MSC_RESTO = to )
4133 #define __msc_set_rdto(to) ( REG_MSC_RDTO = to )
4134 #define __msc_set_cmd(cmd) ( REG_MSC_CMD = cmd )
4135 #define __msc_set_arg(arg) ( REG_MSC_ARG = arg )
4136 #define __msc_set_nob(nob) ( REG_MSC_NOB = nob )
4137 #define __msc_get_nob() ( REG_MSC_NOB )
4138 #define __msc_set_blklen(len) ( REG_MSC_BLKLEN = len )
4139 #define __msc_set_cmdat(cmdat) ( REG_MSC_CMDAT = cmdat )
4140 #define __msc_set_cmdat_ioabort() ( REG_MSC_CMDAT |= MSC_CMDAT_IO_ABORT )
4141 #define __msc_clear_cmdat_ioabort() ( REG_MSC_CMDAT &= ~MSC_CMDAT_IO_ABORT )
4143 #define __msc_set_cmdat_bus_width1() \
4144 do { \
4145 REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \
4146 REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_1BIT; \
4147 } while(0)
4149 #define __msc_set_cmdat_bus_width4() \
4150 do { \
4151 REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \
4152 REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_4BIT; \
4153 } while(0)
4155 #define __msc_set_cmdat_dma_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DMA_EN )
4156 #define __msc_set_cmdat_init() ( REG_MSC_CMDAT |= MSC_CMDAT_INIT )
4157 #define __msc_set_cmdat_busy() ( REG_MSC_CMDAT |= MSC_CMDAT_BUSY )
4158 #define __msc_set_cmdat_stream() ( REG_MSC_CMDAT |= MSC_CMDAT_STREAM_BLOCK )
4159 #define __msc_set_cmdat_block() ( REG_MSC_CMDAT &= ~MSC_CMDAT_STREAM_BLOCK )
4160 #define __msc_set_cmdat_read() ( REG_MSC_CMDAT &= ~MSC_CMDAT_WRITE_READ )
4161 #define __msc_set_cmdat_write() ( REG_MSC_CMDAT |= MSC_CMDAT_WRITE_READ )
4162 #define __msc_set_cmdat_data_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DATA_EN )
4164 /* r is MSC_CMDAT_RESPONSE_FORMAT_Rx or MSC_CMDAT_RESPONSE_FORMAT_NONE */
4165 #define __msc_set_cmdat_res_format(r) \
4166 do { \
4167 REG_MSC_CMDAT &= ~MSC_CMDAT_RESPONSE_FORMAT_MASK; \
4168 REG_MSC_CMDAT |= (r); \
4169 } while(0)
4171 #define __msc_clear_cmdat() \
4172 REG_MSC_CMDAT &= ~( MSC_CMDAT_IO_ABORT | MSC_CMDAT_DMA_EN | MSC_CMDAT_INIT| \
4173 MSC_CMDAT_BUSY | MSC_CMDAT_STREAM_BLOCK | MSC_CMDAT_WRITE_READ | \
4174 MSC_CMDAT_DATA_EN | MSC_CMDAT_RESPONSE_FORMAT_MASK )
4176 #define __msc_get_imask() ( REG_MSC_IMASK )
4177 #define __msc_mask_all_intrs() ( REG_MSC_IMASK = 0xff )
4178 #define __msc_unmask_all_intrs() ( REG_MSC_IMASK = 0x00 )
4179 #define __msc_mask_rd() ( REG_MSC_IMASK |= MSC_IMASK_RXFIFO_RD_REQ )
4180 #define __msc_unmask_rd() ( REG_MSC_IMASK &= ~MSC_IMASK_RXFIFO_RD_REQ )
4181 #define __msc_mask_wr() ( REG_MSC_IMASK |= MSC_IMASK_TXFIFO_WR_REQ )
4182 #define __msc_unmask_wr() ( REG_MSC_IMASK &= ~MSC_IMASK_TXFIFO_WR_REQ )
4183 #define __msc_mask_endcmdres() ( REG_MSC_IMASK |= MSC_IMASK_END_CMD_RES )
4184 #define __msc_unmask_endcmdres() ( REG_MSC_IMASK &= ~MSC_IMASK_END_CMD_RES )
4185 #define __msc_mask_datatrandone() ( REG_MSC_IMASK |= MSC_IMASK_DATA_TRAN_DONE )
4186 #define __msc_unmask_datatrandone() ( REG_MSC_IMASK &= ~MSC_IMASK_DATA_TRAN_DONE )
4187 #define __msc_mask_prgdone() ( REG_MSC_IMASK |= MSC_IMASK_PRG_DONE )
4188 #define __msc_unmask_prgdone() ( REG_MSC_IMASK &= ~MSC_IMASK_PRG_DONE )
4190 /* n=0,1,2,3,4,5,6,7 */
4191 #define __msc_set_clkrt(n) \
4192 do { \
4193 REG_MSC_CLKRT = n; \
4194 } while(0)
4196 #define __msc_get_ireg() ( REG_MSC_IREG )
4197 #define __msc_ireg_rd() ( REG_MSC_IREG & MSC_IREG_RXFIFO_RD_REQ )
4198 #define __msc_ireg_wr() ( REG_MSC_IREG & MSC_IREG_TXFIFO_WR_REQ )
4199 #define __msc_ireg_end_cmd_res() ( REG_MSC_IREG & MSC_IREG_END_CMD_RES )
4200 #define __msc_ireg_data_tran_done() ( REG_MSC_IREG & MSC_IREG_DATA_TRAN_DONE )
4201 #define __msc_ireg_prg_done() ( REG_MSC_IREG & MSC_IREG_PRG_DONE )
4202 #define __msc_ireg_clear_end_cmd_res() ( REG_MSC_IREG = MSC_IREG_END_CMD_RES )
4203 #define __msc_ireg_clear_data_tran_done() ( REG_MSC_IREG = MSC_IREG_DATA_TRAN_DONE )
4204 #define __msc_ireg_clear_prg_done() ( REG_MSC_IREG = MSC_IREG_PRG_DONE )
4206 #define __msc_get_stat() ( REG_MSC_STAT )
4207 #define __msc_stat_not_end_cmd_res() ( (REG_MSC_STAT & MSC_STAT_END_CMD_RES) == 0)
4208 #define __msc_stat_crc_err() \
4209 ( REG_MSC_STAT & (MSC_STAT_CRC_RES_ERR | MSC_STAT_CRC_READ_ERROR | MSC_STAT_CRC_WRITE_ERROR_YES) )
4210 #define __msc_stat_res_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_RES_ERR )
4211 #define __msc_stat_rd_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_READ_ERROR )
4212 #define __msc_stat_wr_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_WRITE_ERROR_YES )
4213 #define __msc_stat_resto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_RES )
4214 #define __msc_stat_rdto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_READ )
4216 #define __msc_rd_resfifo() ( REG_MSC_RES )
4217 #define __msc_rd_rxfifo() ( REG_MSC_RXFIFO )
4218 #define __msc_wr_txfifo(v) ( REG_MSC_TXFIFO = v )
4220 #define __msc_reset() \
4221 do { \
4222 REG_MSC_STRPCL = MSC_STRPCL_RESET; \
4223 while (REG_MSC_STAT & MSC_STAT_IS_RESETTING); \
4224 } while (0)
4226 #define __msc_start_clk() \
4227 do { \
4228 REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_START; \
4229 } while (0)
4231 #define __msc_stop_clk() \
4232 do { \
4233 REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_STOP; \
4234 } while (0)
4236 #define MMC_CLK 19169200
4237 #define SD_CLK 24576000
4239 /* msc_clk should little than pclk and little than clk retrieve from card */
4240 #define __msc_calc_clk_divisor(type,dev_clk,msc_clk,lv) \
4241 do { \
4242 unsigned int rate, pclk, i; \
4243 pclk = dev_clk; \
4244 rate = type?SD_CLK:MMC_CLK; \
4245 if (msc_clk && msc_clk < pclk) \
4246 pclk = msc_clk; \
4247 i = 0; \
4248 while (pclk < rate) \
4250 i ++; \
4251 rate >>= 1; \
4253 lv = i; \
4254 } while(0)
4256 /* divide rate to little than or equal to 400kHz */
4257 #define __msc_calc_slow_clk_divisor(type, lv) \
4258 do { \
4259 unsigned int rate, i; \
4260 rate = (type?SD_CLK:MMC_CLK)/1000/400; \
4261 i = 0; \
4262 while (rate > 0) \
4264 rate >>= 1; \
4265 i ++; \
4267 lv = i; \
4268 } while(0)
4271 /***************************************************************************
4272 * SSI
4273 ***************************************************************************/
4275 #define __ssi_enable() ( REG_SSI_CR0 |= SSI_CR0_SSIE )
4276 #define __ssi_disable() ( REG_SSI_CR0 &= ~SSI_CR0_SSIE )
4277 #define __ssi_select_ce() ( REG_SSI_CR0 &= ~SSI_CR0_FSEL )
4279 #define __ssi_normal_mode() ( REG_SSI_ITR &= ~SSI_ITR_IVLTM_MASK )
4281 #define __ssi_select_ce2() \
4282 do { \
4283 REG_SSI_CR0 |= SSI_CR0_FSEL; \
4284 REG_SSI_CR1 &= ~SSI_CR1_MULTS; \
4285 } while (0)
4287 #define __ssi_select_gpc() \
4288 do { \
4289 REG_SSI_CR0 &= ~SSI_CR0_FSEL; \
4290 REG_SSI_CR1 |= SSI_CR1_MULTS; \
4291 } while (0)
4293 #define __ssi_enable_tx_intr() \
4294 ( REG_SSI_CR0 |= SSI_CR0_TIE | SSI_CR0_TEIE )
4296 #define __ssi_disable_tx_intr() \
4297 ( REG_SSI_CR0 &= ~(SSI_CR0_TIE | SSI_CR0_TEIE) )
4299 #define __ssi_enable_rx_intr() \
4300 ( REG_SSI_CR0 |= SSI_CR0_RIE | SSI_CR0_REIE )
4302 #define __ssi_disable_rx_intr() \
4303 ( REG_SSI_CR0 &= ~(SSI_CR0_RIE | SSI_CR0_REIE) )
4305 #define __ssi_enable_loopback() ( REG_SSI_CR0 |= SSI_CR0_LOOP )
4306 #define __ssi_disable_loopback() ( REG_SSI_CR0 &= ~SSI_CR0_LOOP )
4308 #define __ssi_enable_receive() ( REG_SSI_CR0 &= ~SSI_CR0_DISREV )
4309 #define __ssi_disable_receive() ( REG_SSI_CR0 |= SSI_CR0_DISREV )
4311 #define __ssi_finish_receive() \
4312 ( REG_SSI_CR0 |= (SSI_CR0_RFINE | SSI_CR0_RFINC) )
4314 #define __ssi_disable_recvfinish() \
4315 ( REG_SSI_CR0 &= ~(SSI_CR0_RFINE | SSI_CR0_RFINC) )
4317 #define __ssi_flush_txfifo() ( REG_SSI_CR0 |= SSI_CR0_TFLUSH )
4318 #define __ssi_flush_rxfifo() ( REG_SSI_CR0 |= SSI_CR0_RFLUSH )
4320 #define __ssi_flush_fifo() \
4321 ( REG_SSI_CR0 |= SSI_CR0_TFLUSH | SSI_CR0_RFLUSH )
4323 #define __ssi_finish_transmit() ( REG_SSI_CR1 &= ~SSI_CR1_UNFIN )
4325 #define __ssi_spi_format() \
4326 do { \
4327 REG_SSI_CR1 &= ~SSI_CR1_FMAT_MASK; \
4328 REG_SSI_CR1 |= SSI_CR1_FMAT_SPI; \
4329 REG_SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK);\
4330 REG_SSI_CR1 |= (SSI_CR1_TFVCK_1 | SSI_CR1_TCKFI_1); \
4331 } while (0)
4333 /* TI's SSP format, must clear SSI_CR1.UNFIN */
4334 #define __ssi_ssp_format() \
4335 do { \
4336 REG_SSI_CR1 &= ~(SSI_CR1_FMAT_MASK | SSI_CR1_UNFIN); \
4337 REG_SSI_CR1 |= SSI_CR1_FMAT_SSP; \
4338 } while (0)
4340 /* National's Microwire format, must clear SSI_CR0.RFINE, and set max delay */
4341 #define __ssi_microwire_format() \
4342 do { \
4343 REG_SSI_CR1 &= ~SSI_CR1_FMAT_MASK; \
4344 REG_SSI_CR1 |= SSI_CR1_FMAT_MW1; \
4345 REG_SSI_CR1 &= ~(SSI_CR1_TFVCK_MASK|SSI_CR1_TCKFI_MASK);\
4346 REG_SSI_CR1 |= (SSI_CR1_TFVCK_3 | SSI_CR1_TCKFI_3); \
4347 REG_SSI_CR0 &= ~SSI_CR0_RFINE; \
4348 } while (0)
4350 /* CE# level (FRMHL), CE# in interval time (ITFRM),
4351 clock phase and polarity (PHA POL),
4352 interval time (SSIITR), interval characters/frame (SSIICR) */
4354 /* frmhl,endian,mcom,flen,pha,pol MASK */
4355 #define SSICR1_MISC_MASK \
4356 ( SSI_CR1_FRMHL_MASK | SSI_CR1_LFST | SSI_CR1_MCOM_MASK \
4357 | SSI_CR1_FLEN_MASK | SSI_CR1_PHA | SSI_CR1_POL ) \
4359 #define __ssi_spi_set_misc(frmhl,endian,flen,mcom,pha,pol) \
4360 do { \
4361 REG_SSI_CR1 &= ~SSICR1_MISC_MASK; \
4362 REG_SSI_CR1 |= ((frmhl) << 30) | ((endian) << 25) | \
4363 (((mcom) - 1) << 12) | (((flen) - 2) << 4) | \
4364 ((pha) << 1) | (pol); \
4365 } while(0)
4367 /* Transfer with MSB or LSB first */
4368 #define __ssi_set_msb() ( REG_SSI_CR1 &= ~SSI_CR1_LFST )
4369 #define __ssi_set_lsb() ( REG_SSI_CR1 |= SSI_CR1_LFST )
4371 #define __ssi_set_frame_length(n) \
4372 REG_SSI_CR1 = (REG_SSI_CR1 & ~SSI_CR1_FLEN_MASK) | (((n) - 2) << 4)
4374 /* n = 1 - 16 */
4375 #define __ssi_set_microwire_command_length(n) \
4376 ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_MCOM_MASK) | SSI_CR1_MCOM_##n##BIT) )
4378 /* Set the clock phase for SPI */
4379 #define __ssi_set_spi_clock_phase(n) \
4380 ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_PHA) | (n&0x1)) )
4382 /* Set the clock polarity for SPI */
4383 #define __ssi_set_spi_clock_polarity(n) \
4384 ( REG_SSI_CR1 = ((REG_SSI_CR1 & ~SSI_CR1_POL) | (n&0x1)) )
4386 /* n = ix8 */
4387 #define __ssi_set_tx_trigger(n) \
4388 do { \
4389 REG_SSI_CR1 &= ~SSI_CR1_TTRG_MASK; \
4390 REG_SSI_CR1 |= SSI_CR1_TTRG_##n; \
4391 } while (0)
4393 /* n = ix8 */
4394 #define __ssi_set_rx_trigger(n) \
4395 do { \
4396 REG_SSI_CR1 &= ~SSI_CR1_RTRG_MASK; \
4397 REG_SSI_CR1 |= SSI_CR1_RTRG_##n; \
4398 } while (0)
4400 #define __ssi_get_txfifo_count() \
4401 ( (REG_SSI_SR & SSI_SR_TFIFONUM_MASK) >> SSI_SR_TFIFONUM_BIT )
4403 #define __ssi_get_rxfifo_count() \
4404 ( (REG_SSI_SR & SSI_SR_RFIFONUM_MASK) >> SSI_SR_RFIFONUM_BIT )
4406 #define __ssi_clear_errors() \
4407 ( REG_SSI_SR &= ~(SSI_SR_UNDR | SSI_SR_OVER) )
4409 #define __ssi_transfer_end() ( REG_SSI_SR & SSI_SR_END )
4410 #define __ssi_is_busy() ( REG_SSI_SR & SSI_SR_BUSY )
4412 #define __ssi_txfifo_full() ( REG_SSI_SR & SSI_SR_TFF )
4413 #define __ssi_rxfifo_empty() ( REG_SSI_SR & SSI_SR_RFE )
4414 #define __ssi_rxfifo_noempty() ( REG_SSI_SR & SSI_SR_RFHF )
4416 #define __ssi_set_clk(dev_clk, ssi_clk) \
4417 ( REG_SSI_GR = (dev_clk) / (2*(ssi_clk)) - 1 )
4419 #define __ssi_receive_data() REG_SSI_DR
4420 #define __ssi_transmit_data(v) ( REG_SSI_DR = (v) )
4423 /***************************************************************************
4424 * CIM
4425 ***************************************************************************/
4427 #define __cim_enable() ( REG_CIM_CTRL |= CIM_CTRL_ENA )
4428 #define __cim_disable() ( REG_CIM_CTRL &= ~CIM_CTRL_ENA )
4430 #define __cim_input_data_inverse() ( REG_CIM_CFG |= CIM_CFG_INV_DAT )
4431 #define __cim_input_data_normal() ( REG_CIM_CFG &= ~CIM_CFG_INV_DAT )
4433 #define __cim_vsync_active_low() ( REG_CIM_CFG |= CIM_CFG_VSP )
4434 #define __cim_vsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_VSP )
4436 #define __cim_hsync_active_low() ( REG_CIM_CFG |= CIM_CFG_HSP )
4437 #define __cim_hsync_active_high() ( REG_CIM_CFG &= ~CIM_CFG_HSP )
4439 #define __cim_sample_data_at_pclk_falling_edge() \
4440 ( REG_CIM_CFG |= CIM_CFG_PCP )
4441 #define __cim_sample_data_at_pclk_rising_edge() \
4442 ( REG_CIM_CFG &= ~CIM_CFG_PCP )
4444 #define __cim_enable_dummy_zero() ( REG_CIM_CFG |= CIM_CFG_DUMMY_ZERO )
4445 #define __cim_disable_dummy_zero() ( REG_CIM_CFG &= ~CIM_CFG_DUMMY_ZERO )
4447 #define __cim_select_external_vsync() ( REG_CIM_CFG |= CIM_CFG_EXT_VSYNC )
4448 #define __cim_select_internal_vsync() ( REG_CIM_CFG &= ~CIM_CFG_EXT_VSYNC )
4450 /* n=0-7 */
4451 #define __cim_set_data_packing_mode(n) \
4452 do { \
4453 REG_CIM_CFG &= ~CIM_CFG_PACK_MASK; \
4454 REG_CIM_CFG |= (CIM_CFG_PACK_##n); \
4455 } while (0)
4457 #define __cim_enable_ccir656_progressive_mode() \
4458 do { \
4459 REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \
4460 REG_CIM_CFG |= CIM_CFG_DSM_CPM; \
4461 } while (0)
4463 #define __cim_enable_ccir656_interlace_mode() \
4464 do { \
4465 REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \
4466 REG_CIM_CFG |= CIM_CFG_DSM_CIM; \
4467 } while (0)
4469 #define __cim_enable_gated_clock_mode() \
4470 do { \
4471 REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \
4472 REG_CIM_CFG |= CIM_CFG_DSM_GCM; \
4473 } while (0)
4475 #define __cim_enable_nongated_clock_mode() \
4476 do { \
4477 REG_CIM_CFG &= ~CIM_CFG_DSM_MASK; \
4478 REG_CIM_CFG |= CIM_CFG_DSM_NGCM; \
4479 } while (0)
4481 /* sclk:system bus clock
4482 * mclk: CIM master clock
4484 #define __cim_set_master_clk(sclk, mclk) \
4485 do { \
4486 REG_CIM_CTRL &= ~CIM_CTRL_MCLKDIV_MASK; \
4487 REG_CIM_CTRL |= (((sclk)/(mclk) - 1) << CIM_CTRL_MCLKDIV_BIT); \
4488 } while (0)
4490 #define __cim_enable_sof_intr() \
4491 ( REG_CIM_CTRL |= CIM_CTRL_DMA_SOFM )
4492 #define __cim_disable_sof_intr() \
4493 ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_SOFM )
4495 #define __cim_enable_eof_intr() \
4496 ( REG_CIM_CTRL |= CIM_CTRL_DMA_EOFM )
4497 #define __cim_disable_eof_intr() \
4498 ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EOFM )
4500 #define __cim_enable_stop_intr() \
4501 ( REG_CIM_CTRL |= CIM_CTRL_DMA_STOPM )
4502 #define __cim_disable_stop_intr() \
4503 ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_STOPM )
4505 #define __cim_enable_trig_intr() \
4506 ( REG_CIM_CTRL |= CIM_CTRL_RXF_TRIGM )
4507 #define __cim_disable_trig_intr() \
4508 ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIGM )
4510 #define __cim_enable_rxfifo_overflow_intr() \
4511 ( REG_CIM_CTRL |= CIM_CTRL_RXF_OFM )
4512 #define __cim_disable_rxfifo_overflow_intr() \
4513 ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_OFM )
4515 /* n=1-16 */
4516 #define __cim_set_frame_rate(n) \
4517 do { \
4518 REG_CIM_CTRL &= ~CIM_CTRL_FRC_MASK; \
4519 REG_CIM_CTRL |= CIM_CTRL_FRC_##n; \
4520 } while (0)
4522 #define __cim_enable_dma() ( REG_CIM_CTRL |= CIM_CTRL_DMA_EN )
4523 #define __cim_disable_dma() ( REG_CIM_CTRL &= ~CIM_CTRL_DMA_EN )
4525 #define __cim_reset_rxfifo() ( REG_CIM_CTRL |= CIM_CTRL_RXF_RST )
4526 #define __cim_unreset_rxfifo() ( REG_CIM_CTRL &= ~CIM_CTRL_RXF_RST )
4528 /* n=4,8,12,16,20,24,28,32 */
4529 #define __cim_set_rxfifo_trigger(n) \
4530 do { \
4531 REG_CIM_CTRL &= ~CIM_CTRL_RXF_TRIG_MASK; \
4532 REG_CIM_CTRL |= CIM_CTRL_RXF_TRIG_##n; \
4533 } while (0)
4535 #define __cim_clear_state() ( REG_CIM_STATE = 0 )
4537 #define __cim_disable_done() ( REG_CIM_STATE & CIM_STATE_VDD )
4538 #define __cim_rxfifo_empty() ( REG_CIM_STATE & CIM_STATE_RXF_EMPTY )
4539 #define __cim_rxfifo_reach_trigger() ( REG_CIM_STATE & CIM_STATE_RXF_TRIG )
4540 #define __cim_rxfifo_overflow() ( REG_CIM_STATE & CIM_STATE_RXF_OF )
4541 #define __cim_clear_rxfifo_overflow() ( REG_CIM_STATE &= ~CIM_STATE_RXF_OF )
4542 #define __cim_dma_stop() ( REG_CIM_STATE & CIM_STATE_DMA_STOP )
4543 #define __cim_dma_eof() ( REG_CIM_STATE & CIM_STATE_DMA_EOF )
4544 #define __cim_dma_sof() ( REG_CIM_STATE & CIM_STATE_DMA_SOF )
4546 #define __cim_get_iid() ( REG_CIM_IID )
4547 #define __cim_get_image_data() ( REG_CIM_RXFIFO )
4548 #define __cim_get_dam_cmd() ( REG_CIM_CMD )
4550 #define __cim_set_da(a) ( REG_CIM_DA = (a) )
4552 /***************************************************************************
4553 * LCD
4554 ***************************************************************************/
4555 #define __lcd_as_smart_lcd() ( REG_LCD_CFG |= (1<<LCD_CFG_LCDPIN_BIT) )
4556 #define __lcd_as_general_lcd() ( REG_LCD_CFG &= ~(1<<LCD_CFG_LCDPIN_BIT) )
4558 #define __lcd_set_dis() ( REG_LCD_CTRL |= LCD_CTRL_DIS )
4559 #define __lcd_clr_dis() ( REG_LCD_CTRL &= ~LCD_CTRL_DIS )
4561 #define __lcd_set_ena() ( REG_LCD_CTRL |= LCD_CTRL_ENA )
4562 #define __lcd_clr_ena() ( REG_LCD_CTRL &= ~LCD_CTRL_ENA )
4564 /* n=1,2,4,8,16 */
4565 #define __lcd_set_bpp(n) \
4566 ( REG_LCD_CTRL = (REG_LCD_CTRL & ~LCD_CTRL_BPP_MASK) | LCD_CTRL_BPP_##n )
4568 /* n=4,8,16 */
4569 #define __lcd_set_burst_length(n) \
4570 do { \
4571 REG_LCD_CTRL &= ~LCD_CTRL_BST_MASK; \
4572 REG_LCD_CTRL |= LCD_CTRL_BST_n##; \
4573 } while (0)
4575 #define __lcd_select_rgb565() ( REG_LCD_CTRL &= ~LCD_CTRL_RGB555 )
4576 #define __lcd_select_rgb555() ( REG_LCD_CTRL |= LCD_CTRL_RGB555 )
4578 #define __lcd_set_ofup() ( REG_LCD_CTRL |= LCD_CTRL_OFUP )
4579 #define __lcd_clr_ofup() ( REG_LCD_CTRL &= ~LCD_CTRL_OFUP )
4581 /* n=2,4,16 */
4582 #define __lcd_set_stn_frc(n) \
4583 do { \
4584 REG_LCD_CTRL &= ~LCD_CTRL_FRC_MASK; \
4585 REG_LCD_CTRL |= LCD_CTRL_FRC_n##; \
4586 } while (0)
4589 #define __lcd_pixel_endian_little() ( REG_LCD_CTRL |= LCD_CTRL_PEDN )
4590 #define __lcd_pixel_endian_big() ( REG_LCD_CTRL &= ~LCD_CTRL_PEDN )
4592 #define __lcd_reverse_byte_endian() ( REG_LCD_CTRL |= LCD_CTRL_BEDN )
4593 #define __lcd_normal_byte_endian() ( REG_LCD_CTRL &= ~LCD_CTRL_BEDN )
4595 #define __lcd_enable_eof_intr() ( REG_LCD_CTRL |= LCD_CTRL_EOFM )
4596 #define __lcd_disable_eof_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_EOFM )
4598 #define __lcd_enable_sof_intr() ( REG_LCD_CTRL |= LCD_CTRL_SOFM )
4599 #define __lcd_disable_sof_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_SOFM )
4601 #define __lcd_enable_ofu_intr() ( REG_LCD_CTRL |= LCD_CTRL_OFUM )
4602 #define __lcd_disable_ofu_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_OFUM )
4604 #define __lcd_enable_ifu0_intr() ( REG_LCD_CTRL |= LCD_CTRL_IFUM0 )
4605 #define __lcd_disable_ifu0_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_IFUM0 )
4607 #define __lcd_enable_ifu1_intr() ( REG_LCD_CTRL |= LCD_CTRL_IFUM1 )
4608 #define __lcd_disable_ifu1_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_IFUM1 )
4610 #define __lcd_enable_ldd_intr() ( REG_LCD_CTRL |= LCD_CTRL_LDDM )
4611 #define __lcd_disable_ldd_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_LDDM )
4613 #define __lcd_enable_qd_intr() ( REG_LCD_CTRL |= LCD_CTRL_QDM )
4614 #define __lcd_disable_qd_intr() ( REG_LCD_CTRL &= ~LCD_CTRL_QDM )
4617 /* LCD status register indication */
4619 #define __lcd_quick_disable_done() ( REG_LCD_STATE & LCD_STATE_QD )
4620 #define __lcd_disable_done() ( REG_LCD_STATE & LCD_STATE_LDD )
4621 #define __lcd_infifo0_underrun() ( REG_LCD_STATE & LCD_STATE_IFU0 )
4622 #define __lcd_infifo1_underrun() ( REG_LCD_STATE & LCD_STATE_IFU1 )
4623 #define __lcd_outfifo_underrun() ( REG_LCD_STATE & LCD_STATE_OFU )
4624 #define __lcd_start_of_frame() ( REG_LCD_STATE & LCD_STATE_SOF )
4625 #define __lcd_end_of_frame() ( REG_LCD_STATE & LCD_STATE_EOF )
4627 #define __lcd_clr_outfifounderrun() ( REG_LCD_STATE &= ~LCD_STATE_OFU )
4628 #define __lcd_clr_sof() ( REG_LCD_STATE &= ~LCD_STATE_SOF )
4629 #define __lcd_clr_eof() ( REG_LCD_STATE &= ~LCD_STATE_EOF )
4631 #define __lcd_panel_white() ( REG_LCD_CFG |= LCD_CFG_WHITE )
4632 #define __lcd_panel_black() ( REG_LCD_CFG &= ~LCD_CFG_WHITE )
4634 /* n=1,2,4,8 for single mono-STN
4635 * n=4,8 for dual mono-STN
4637 #define __lcd_set_panel_datawidth(n) \
4638 do { \
4639 REG_LCD_CFG &= ~LCD_CFG_PDW_MASK; \
4640 REG_LCD_CFG |= LCD_CFG_PDW_n##; \
4641 } while (0)
4643 /* m=LCD_CFG_MODE_GENERUIC_TFT_xxx */
4644 #define __lcd_set_panel_mode(m) \
4645 do { \
4646 REG_LCD_CFG &= ~LCD_CFG_MODE_MASK; \
4647 REG_LCD_CFG |= (m); \
4648 } while(0)
4650 /* n = 0-255 */
4651 #define __lcd_disable_ac_bias() ( REG_LCD_IO = 0xff )
4652 #define __lcd_set_ac_bias(n) \
4653 do { \
4654 REG_LCD_IO &= ~LCD_IO_ACB_MASK; \
4655 REG_LCD_IO |= ((n) << LCD_IO_ACB_BIT); \
4656 } while(0)
4658 #define __lcd_io_set_dir() ( REG_LCD_IO |= LCD_IO_DIR )
4659 #define __lcd_io_clr_dir() ( REG_LCD_IO &= ~LCD_IO_DIR )
4661 #define __lcd_io_set_dep() ( REG_LCD_IO |= LCD_IO_DEP )
4662 #define __lcd_io_clr_dep() ( REG_LCD_IO &= ~LCD_IO_DEP )
4664 #define __lcd_io_set_vsp() ( REG_LCD_IO |= LCD_IO_VSP )
4665 #define __lcd_io_clr_vsp() ( REG_LCD_IO &= ~LCD_IO_VSP )
4667 #define __lcd_io_set_hsp() ( REG_LCD_IO |= LCD_IO_HSP )
4668 #define __lcd_io_clr_hsp() ( REG_LCD_IO &= ~LCD_IO_HSP )
4670 #define __lcd_io_set_pcp() ( REG_LCD_IO |= LCD_IO_PCP )
4671 #define __lcd_io_clr_pcp() ( REG_LCD_IO &= ~LCD_IO_PCP )
4673 #define __lcd_vsync_get_vps() \
4674 ( (REG_LCD_VSYNC & LCD_VSYNC_VPS_MASK) >> LCD_VSYNC_VPS_BIT )
4676 #define __lcd_vsync_get_vpe() \
4677 ( (REG_LCD_VSYNC & LCD_VSYNC_VPE_MASK) >> LCD_VSYNC_VPE_BIT )
4678 #define __lcd_vsync_set_vpe(n) \
4679 do { \
4680 REG_LCD_VSYNC &= ~LCD_VSYNC_VPE_MASK; \
4681 REG_LCD_VSYNC |= (n) << LCD_VSYNC_VPE_BIT; \
4682 } while (0)
4684 #define __lcd_hsync_get_hps() \
4685 ( (REG_LCD_HSYNC & LCD_HSYNC_HPS_MASK) >> LCD_HSYNC_HPS_BIT )
4686 #define __lcd_hsync_set_hps(n) \
4687 do { \
4688 REG_LCD_HSYNC &= ~LCD_HSYNC_HPS_MASK; \
4689 REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPS_BIT; \
4690 } while (0)
4692 #define __lcd_hsync_get_hpe() \
4693 ( (REG_LCD_HSYNC & LCD_HSYNC_HPE_MASK) >> LCD_VSYNC_HPE_BIT )
4694 #define __lcd_hsync_set_hpe(n) \
4695 do { \
4696 REG_LCD_HSYNC &= ~LCD_HSYNC_HPE_MASK; \
4697 REG_LCD_HSYNC |= (n) << LCD_HSYNC_HPE_BIT; \
4698 } while (0)
4700 #define __lcd_vat_get_ht() \
4701 ( (REG_LCD_VAT & LCD_VAT_HT_MASK) >> LCD_VAT_HT_BIT )
4702 #define __lcd_vat_set_ht(n) \
4703 do { \
4704 REG_LCD_VAT &= ~LCD_VAT_HT_MASK; \
4705 REG_LCD_VAT |= (n) << LCD_VAT_HT_BIT; \
4706 } while (0)
4708 #define __lcd_vat_get_vt() \
4709 ( (REG_LCD_VAT & LCD_VAT_VT_MASK) >> LCD_VAT_VT_BIT )
4710 #define __lcd_vat_set_vt(n) \
4711 do { \
4712 REG_LCD_VAT &= ~LCD_VAT_VT_MASK; \
4713 REG_LCD_VAT |= (n) << LCD_VAT_VT_BIT; \
4714 } while (0)
4716 #define __lcd_dah_get_hds() \
4717 ( (REG_LCD_DAH & LCD_DAH_HDS_MASK) >> LCD_DAH_HDS_BIT )
4718 #define __lcd_dah_set_hds(n) \
4719 do { \
4720 REG_LCD_DAH &= ~LCD_DAH_HDS_MASK; \
4721 REG_LCD_DAH |= (n) << LCD_DAH_HDS_BIT; \
4722 } while (0)
4724 #define __lcd_dah_get_hde() \
4725 ( (REG_LCD_DAH & LCD_DAH_HDE_MASK) >> LCD_DAH_HDE_BIT )
4726 #define __lcd_dah_set_hde(n) \
4727 do { \
4728 REG_LCD_DAH &= ~LCD_DAH_HDE_MASK; \
4729 REG_LCD_DAH |= (n) << LCD_DAH_HDE_BIT; \
4730 } while (0)
4732 #define __lcd_dav_get_vds() \
4733 ( (REG_LCD_DAV & LCD_DAV_VDS_MASK) >> LCD_DAV_VDS_BIT )
4734 #define __lcd_dav_set_vds(n) \
4735 do { \
4736 REG_LCD_DAV &= ~LCD_DAV_VDS_MASK; \
4737 REG_LCD_DAV |= (n) << LCD_DAV_VDS_BIT; \
4738 } while (0)
4740 #define __lcd_dav_get_vde() \
4741 ( (REG_LCD_DAV & LCD_DAV_VDE_MASK) >> LCD_DAV_VDE_BIT )
4742 #define __lcd_dav_set_vde(n) \
4743 do { \
4744 REG_LCD_DAV &= ~LCD_DAV_VDE_MASK; \
4745 REG_LCD_DAV |= (n) << LCD_DAV_VDE_BIT; \
4746 } while (0)
4748 #define __lcd_cmd0_set_sofint() ( REG_LCD_CMD0 |= LCD_CMD_SOFINT )
4749 #define __lcd_cmd0_clr_sofint() ( REG_LCD_CMD0 &= ~LCD_CMD_SOFINT )
4750 #define __lcd_cmd1_set_sofint() ( REG_LCD_CMD1 |= LCD_CMD_SOFINT )
4751 #define __lcd_cmd1_clr_sofint() ( REG_LCD_CMD1 &= ~LCD_CMD_SOFINT )
4753 #define __lcd_cmd0_set_eofint() ( REG_LCD_CMD0 |= LCD_CMD_EOFINT )
4754 #define __lcd_cmd0_clr_eofint() ( REG_LCD_CMD0 &= ~LCD_CMD_EOFINT )
4755 #define __lcd_cmd1_set_eofint() ( REG_LCD_CMD1 |= LCD_CMD_EOFINT )
4756 #define __lcd_cmd1_clr_eofint() ( REG_LCD_CMD1 &= ~LCD_CMD_EOFINT )
4758 #define __lcd_cmd0_set_pal() ( REG_LCD_CMD0 |= LCD_CMD_PAL )
4759 #define __lcd_cmd0_clr_pal() ( REG_LCD_CMD0 &= ~LCD_CMD_PAL )
4761 #define __lcd_cmd0_get_len() \
4762 ( (REG_LCD_CMD0 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT )
4763 #define __lcd_cmd1_get_len() \
4764 ( (REG_LCD_CMD1 & LCD_CMD_LEN_MASK) >> LCD_CMD_LEN_BIT )
4766 /***************************************************************************
4767 * RTC ops
4768 ***************************************************************************/
4770 #define __rtc_write_ready() ( REG_RTC_RCR & RTC_RCR_WRDY )
4771 #define __rtc_enabled() \
4772 do{ \
4773 while(!__rtc_write_ready()); \
4774 REG_RTC_RCR |= RTC_RCR_RTCE ; \
4775 }while(0) \
4777 #define __rtc_disabled() \
4778 do{ \
4779 while(!__rtc_write_ready()); \
4780 REG_RTC_RCR &= ~RTC_RCR_RTCE; \
4781 }while(0)
4782 #define __rtc_enable_alarm() \
4783 do{ \
4784 while(!__rtc_write_ready()); \
4785 REG_RTC_RCR |= RTC_RCR_AE; \
4786 }while(0)
4788 #define __rtc_disable_alarm() \
4789 do{ \
4790 while(!__rtc_write_ready()); \
4791 REG_RTC_RCR &= ~RTC_RCR_AE; \
4792 }while(0)
4794 #define __rtc_enable_alarm_irq() \
4795 do{ \
4796 while(!__rtc_write_ready()); \
4797 REG_RTC_RCR |= RTC_RCR_AIE; \
4798 }while(0)
4800 #define __rtc_disable_alarm_irq() \
4801 do{ \
4802 while(!__rtc_write_ready()); \
4803 REG_RTC_RCR &= ~RTC_RCR_AIE; \
4804 }while(0)
4805 #define __rtc_enable_Hz_irq() \
4806 do{ \
4807 while(!__rtc_write_ready()); \
4808 REG_RTC_RCR |= RTC_RCR_HZIE; \
4809 }while(0)
4811 #define __rtc_disable_Hz_irq() \
4812 do{ \
4813 while(!__rtc_write_ready()); \
4814 REG_RTC_RCR &= ~RTC_RCR_HZIE; \
4815 }while(0)
4816 #define __rtc_get_1Hz_flag() \
4817 do{ \
4818 while(!__rtc_write_ready()); \
4819 ((REG_RTC_RCR >> RTC_RCR_HZ) & 0x1); \
4820 }while(0)
4821 #define __rtc_clear_1Hz_flag() \
4822 do{ \
4823 while(!__rtc_write_ready()); \
4824 REG_RTC_RCR &= ~RTC_RCR_HZ; \
4825 }while(0)
4826 #define __rtc_get_alarm_flag() \
4827 do{ \
4828 while(!__rtc_write_ready()); \
4829 ((REG_RTC_RCR >> RTC_RCR_AF) & 0x1); \
4830 while(0)
4832 ///( (REG_RTC_RCR >> RTC_RCR_AF_BIT) & 0x1 )
4834 #define __rtc_clear_alarm_flag() \
4835 do{ \
4836 while(!__rtc_write_ready()); \
4837 REG_RTC_RCR &= ~RTC_RCR_AF; \
4838 }while(0)
4839 //do
4840 #define __rtc_get_second() \
4841 ({ \
4842 while(!__rtc_write_ready());\
4843 REG_RTC_RSR; \
4845 //while(0)
4847 #define __rtc_set_second(v) \
4848 do{ \
4849 while(!__rtc_write_ready()); \
4850 REG_RTC_RSR = v; \
4851 while(!__rtc_write_ready());\
4852 }while(0)
4854 #define __rtc_get_alarm_second() \
4855 do{ \
4856 while(!__rtc_write_ready()); \
4857 REG_RTC_RSAR; \
4858 }while(0)
4861 #define __rtc_set_alarm_second(v) \
4862 do{ \
4863 while(!__rtc_write_ready()); \
4864 REG_RTC_RSAR = v; \
4865 }while(0)
4867 #define __rtc_RGR_is_locked() \
4868 ({ \
4869 while(!__rtc_write_ready()); \
4870 REG_RTC_RGR >> RTC_RGR_LOCK; \
4872 #define __rtc_lock_RGR() \
4873 do{ \
4874 while(!__rtc_write_ready()); \
4875 REG_RTC_RGR |= RTC_RGR_LOCK; \
4876 }while(0)
4878 #define __rtc_unlock_RGR() \
4879 do{ \
4880 while(!__rtc_write_ready()); \
4881 REG_RTC_RGR &= ~RTC_RGR_LOCK; \
4882 }while(0)
4884 #define __rtc_get_adjc_val() \
4885 do{ \
4886 while(!__rtc_write_ready()); \
4887 ( (REG_RTC_RGR & RTC_RGR_ADJC_MASK) >> RTC_RGR_ADJC_BIT ); \
4888 }while(0)
4889 #define __rtc_set_adjc_val(v) \
4890 do{ \
4891 while(!__rtc_write_ready()); \
4892 REG_RTC_RGR = (REG_RTC_RGR & (~RTC_RGR_ADJC_MASK)) |(v << RTC_RGR_ADJC_BIT); \
4893 }while(0)
4895 #define __rtc_get_nc1Hz_val() \
4896 ( (REG_RTC_RGR & RTC_RGR_NC1HZ_MASK) >> RTC_RGR_NC1HZ_BIT )
4898 #define __rtc_set_nc1Hz_val(v) \
4899 do{ \
4900 while(!__rtc_write_ready()); \
4901 REG_RTC_RGR = (REG_RTC_RGR & (~RTC_RGR_NC1HZ_MASK)) | (v << RTC_RGR_NC1HZ_BIT);\
4902 }while(0)
4903 #define __rtc_power_down() \
4904 do{ \
4905 while(!__rtc_write_ready()); \
4906 REG_RTC_HCR |= RTC_HCR_PD; \
4907 }while(0)
4909 #define __rtc_get_hwfcr_val() \
4910 do{ \
4911 while(!__rtc_write_ready()); \
4912 REG_RTC_HWFCR & RTC_HWFCR_MASK; \
4913 }while(0)
4914 #define __rtc_set_hwfcr_val(v) \
4915 do{ \
4916 while(!__rtc_write_ready()); \
4917 REG_RTC_HWFCR = (v) & RTC_HWFCR_MASK; \
4918 }while(0)
4920 #define __rtc_get_hrcr_val() \
4921 do{ \
4922 while(!__rtc_write_ready()); \
4923 ( REG_RTC_HRCR & RTC_HRCR_MASK ); \
4924 }while(0)
4925 #define __rtc_set_hrcr_val(v) \
4926 do{ \
4927 while(!__rtc_write_ready()); \
4928 ( REG_RTC_HRCR = (v) & RTC_HRCR_MASK ); \
4929 }while(0)
4931 #define __rtc_enable_alarm_wakeup() \
4932 do{ \
4933 while(!__rtc_write_ready()); \
4934 ( REG_RTC_HWCR |= RTC_HWCR_EALM ); \
4935 }while(0)
4937 #define __rtc_disable_alarm_wakeup() \
4938 do{ \
4939 while(!__rtc_write_ready()); \
4940 ( REG_RTC_HWCR &= ~RTC_HWCR_EALM ); \
4941 }while(0)
4943 #define __rtc_status_hib_reset_occur() \
4944 ({ \
4945 (REG_RTC_HWRSR & RTC_HWRSR_HR); \
4947 #define __rtc_status_ppr_reset_occur() \
4948 do{ \
4949 while(!__rtc_write_ready()); \
4950 ( (REG_RTC_HWRSR & RTC_HWRSR_PPR) & 0x1 ); \
4951 }while(0)
4952 #define __rtc_status_wakeup_pin_waken_up() \
4953 do{ \
4954 while(!__rtc_write_ready()); \
4955 ( (REG_RTC_HWRSR >> RTC_HWRSR_PIN) & 0x1 ); \
4956 }while(0)
4957 #define __rtc_status_alarm_waken_up() \
4958 do{ \
4959 while(!__rtc_write_ready()); \
4960 ( (REG_RTC_HWRSR >> RTC_HWRSR_ALM) & 0x1 ); \
4961 }while(0)
4962 #define __rtc_clear_hib_stat_all() \
4963 do{ \
4964 while(!__rtc_write_ready()); \
4965 ( REG_RTC_HWRSR = 0 ); \
4966 }while(0)
4968 #define __rtc_get_scratch_pattern() \
4969 ({ while(!__rtc_write_ready()); \
4970 (REG_RTC_HSPR);})
4971 #define __rtc_set_scratch_pattern(n) \
4972 do{ \
4973 while(!__rtc_write_ready()); \
4974 (REG_RTC_HSPR = n ); \
4975 }while(0)
4978 #endif /* !__ASSEMBLY__ */
4981 #ifndef _IPU_H_
4982 #define _IPU_H_
4984 // IPU_REG_BASE
4985 #define IPU_P_BASE 0x13080000
4986 #define IPU_V_BASE 0xB3080000
4987 #define IPU__SIZE 0x00001000
4989 struct ipu_module
4991 unsigned int reg_ctrl; // 0x0
4992 unsigned int reg_status; // 0x4
4993 unsigned int reg_d_fmt; // 0x8
4994 unsigned int reg_y_addr; // 0xc
4995 unsigned int reg_u_addr; // 0x10
4996 unsigned int reg_v_addr; // 0x14
4997 unsigned int reg_in_fm_gs; // 0x18
4998 unsigned int reg_y_stride; // 0x1c
4999 unsigned int reg_uv_stride; // 0x20
5000 unsigned int reg_out_addr; // 0x24
5001 unsigned int reg_out_gs; // 0x28
5002 unsigned int reg_out_stride; // 0x2c
5003 unsigned int rsz_coef_index; // 0x30
5004 unsigned int reg_csc_c0_coef; // 0x34
5005 unsigned int reg_csc_c1_coef; // 0x38
5006 unsigned int reg_csc_c2_coef; // 0x3c
5007 unsigned int reg_csc_c3_coef; // 0x40
5008 unsigned int reg_csc_c4_coef; // 0x44
5009 unsigned int hrsz_coef_lut[20]; // 0x48
5010 unsigned int vrsz_coef_lut[20]; // 0x98
5013 typedef struct
5015 unsigned int coef;
5016 unsigned short int in_n;
5017 unsigned short int out_n;
5018 } rsz_lut;
5020 struct Ration2m
5022 float ratio;
5023 int n, m;
5027 // Register offset
5028 #define REG_CTRL 0x0
5029 #define REG_STATUS 0x4
5030 #define REG_D_FMT 0x8
5031 #define REG_Y_ADDR 0xc
5032 #define REG_U_ADDR 0x10
5033 #define REG_V_ADDR 0x14
5034 #define REG_IN_FM_GS 0x18
5035 #define REG_Y_STRIDE 0x1c
5036 #define REG_UV_STRIDE 0x20
5037 #define REG_OUT_ADDR 0x24
5038 #define REG_OUT_GS 0x28
5039 #define REG_OUT_STRIDE 0x2c
5040 #define REG_RSZ_COEF_INDEX 0x30
5041 #define REG_CSC_C0_COEF 0x34
5042 #define REG_CSC_C1_COEF 0x38
5043 #define REG_CSC_C2_COEF 0x3c
5044 #define REG_CSC_C3_COEF 0x40
5045 #define REG_CSC_C4_COEF 0x44
5046 #define HRSZ_LUT_BASE 0x48
5047 #define VRSZ_LUT_BASE 0x98
5049 // REG_CTRL field define
5050 #define IPU_EN (1 << 0)
5051 #define RSZ_EN (1 << 1)
5052 #define FM_IRQ_EN (1 << 2)
5053 #define IPU_RESET (1 << 3)
5054 #define H_UP_SCALE (1 << 8)
5055 #define V_UP_SCALE (1 << 9)
5056 #define H_SCALE_SHIFT (8)
5057 #define V_SCALE_SHIFT (9)
5059 // REG_STATUS field define
5060 #define OUT_END (1 << 0)
5062 // REG_D_FMT field define
5063 #define INFMT_YUV420 (0 << 0)
5064 #define INFMT_YUV422 (1 << 0)
5065 #define INFMT_YUV444 (2 << 0)
5066 #define INFMT_YUV411 (3 << 0)
5067 #define INFMT_YCbCr420 (4 << 0)
5068 #define INFMT_YCbCr422 (5 << 0)
5069 #define INFMT_YCbCr444 (6 << 0)
5070 #define INFMT_YCbCr411 (7 << 0)
5071 #define INFMT_MASK (7)
5073 #define OUTFMT_RGB555 (0 << 16)
5074 #define OUTFMT_RGB565 (1 << 16)
5075 #define OUTFMT_RGB888 (2 << 16)
5076 #define OUTFMT_MASK (3 << 16)
5078 // REG_IN_FM_GS field define
5079 #define IN_FM_W(val) ((val) << 16)
5080 #define IN_FM_H(val) ((val) << 0)
5082 // REG_IN_FM_GS field define
5083 #define OUT_FM_W(val) ((val) << 16)
5084 #define OUT_FM_H(val) ((val) << 0)
5086 // REG_UV_STRIDE field define
5087 #define U_STRIDE(val) ((val) << 16)
5088 #define V_STRIDE(val) ((val) << 0)
5090 #define VE_IDX_SFT 0
5091 #define HE_IDX_SFT 16
5093 // RSZ_LUT_FIELD
5094 #define OUT_N_SFT 0
5095 #define OUT_N_MSK 0x1
5096 #define IN_N_SFT 1
5097 #define IN_N_MSK 0x1
5098 #define W_COEF_SFT 2
5099 #define W_COEF_MSK 0xFF
5101 // function about REG_CTRL
5102 #define IPU_STOP_IPU() \
5103 REG32(IPU_V_BASE + REG_CTRL) &= ~IPU_EN;
5105 #define IPU_RUN_IPU() \
5106 REG32(IPU_V_BASE + REG_CTRL) |= IPU_EN;
5108 #define IPU_RESET_IPU() \
5109 REG32(IPU_V_BASE + REG_CTRL) |= IPU_RESET;
5111 #define IPU_DISABLE_IRQ() \
5112 REG32(IPU_V_BASE + REG_CTRL) &= ~FM_IRQ_EN;
5114 #define IPU_ENABLE_IRQ() \
5115 REG32(IPU_V_BASE + REG_CTRL) |= FM_IRQ_EN;
5117 #define IPU_DISABLE_RSIZE() \
5118 REG32(IPU_V_BASE + REG_CTRL) &= ~RSZ_EN;
5120 #define IPU_ENABLE_RSIZE() \
5121 REG32(IPU_V_BASE + REG_CTRL) |= RSZ_EN;
5123 #define IPU_IS_ENABLED() \
5124 (REG32(IPU_V_BASE + REG_CTRL) & IPU_EN)
5126 // function about REG_STATUS
5127 #define IPU_CLEAR_END_FLAG() \
5128 REG32(IPU_V_BASE + REG_STATUS) &= ~OUT_END;
5130 #define IPU_POLLING_END_FLAG() \
5131 (REG32(IPU_V_BASE + REG_STATUS) & OUT_END)
5133 #define IPU_SET_INFMT(fmt) \
5134 REG32(IPU_V_BASE + REG_D_FMT) = (REG32(IPU_V_BASE + REG_D_FMT) & ~INFMT_MASK) | (fmt);
5136 #define IPU_SET_OUTFMT(fmt) \
5137 REG32(IPU_V_BASE + REG_D_FMT) = (REG32(IPU_V_BASE + REG_D_FMT) & ~OUTFMT_MASK) | (fmt);
5139 #define IPU_SET_IN_FM(w, h) \
5140 REG32(IPU_V_BASE + REG_IN_FM_GS) = IN_FM_W(w) | IN_FM_H(h);
5142 #define IPU_SET_Y_STRIDE(stride) \
5143 REG32(IPU_V_BASE + REG_Y_STRIDE) = (stride);
5145 #define IPU_SET_UV_STRIDE(u, v) \
5146 REG32(IPU_V_BASE + REG_UV_STRIDE) = U_STRIDE(u) | V_STRIDE(v);
5148 #define IPU_SET_Y_ADDR(addr) \
5149 REG32(IPU_V_BASE + REG_Y_ADDR) = (addr);
5151 #define IPU_SET_U_ADDR(addr) \
5152 REG32(IPU_V_BASE + REG_U_ADDR) = (addr);
5154 #define IPU_SET_V_ADDR(addr) \
5155 REG32(IPU_V_BASE + REG_V_ADDR) = (addr);
5157 #define IPU_SET_OUT_ADDR(addr) \
5158 REG32(IPU_V_BASE + REG_OUT_ADDR) = (addr);
5160 #define IPU_SET_OUT_FM(w, h) \
5161 REG32(IPU_V_BASE + REG_OUT_GS) = OUT_FM_W(w) | OUT_FM_H(h);
5163 #define IPU_SET_OUT_STRIDE(stride) \
5164 REG32(IPU_V_BASE + REG_OUT_STRIDE) = (stride);
5166 #define IPU_SET_CSC_C0_COEF(coef) \
5167 REG32(IPU_V_BASE + REG_CSC_C0_COEF) = (coef);
5169 #define IPU_SET_CSC_C1_COEF(coef) \
5170 REG32(IPU_V_BASE + REG_CSC_C1_COEF) = (coef);
5172 #define IPU_SET_CSC_C2_COEF(coef) \
5173 REG32(IPU_V_BASE + REG_CSC_C2_COEF) = (coef);
5175 #define IPU_SET_CSC_C3_COEF(coef) \
5176 REG32(IPU_V_BASE + REG_CSC_C3_COEF) = (coef);
5178 #define IPU_SET_CSC_C4_COEF(coef) \
5179 REG32(IPU_V_BASE + REG_CSC_C4_COEF) = (coef);
5181 /* YCbCr */
5182 /* parameter
5183 R = 1.164 * (Y - 16) + 1.596 * (cr - 128) {C0, C1}
5184 G = 1.164 * (Y - 16) - 0.392 * (cb -128) - 0.813 * (cr - 128) {C0, C2, C3}
5185 B = 1.164 * (Y - 16) + 2.017 * (cb - 128) {C0, C4}
5187 #define YCBCR_CSC_C0 0x4A8 /* 1.164 * 1024 */
5188 #define YCBCR_CSC_C1 0x662 /* 1.596 * 1024 */
5189 #define YCBCR_CSC_C2 0x191 /* 0.392 * 1024 */
5190 #define YCBCR_CSC_C3 0x341 /* 0.813 * 1024 */
5191 #define YCBCR_CSC_C4 0x811 /* 2.017 * 1024 */
5194 /* YUV */
5195 /* parameter
5196 R = 1 * (Y – 0) + 1.4026 * (V - 128) {C0, C1}
5197 G = 1 * (Y – 0) – 0.3444 * (U - 128) – 0.7144 * (V - 128) {C0, C2, C3}
5198 B = 1 * (Y – 0) + 1.7730 * (U - 128) {C0, C4}
5200 #define YUV_CSC_C0 0x400
5201 #define YUV_CSC_C1 0x59C
5202 #define YUV_CSC_C2 0x161
5203 #define YUV_CSC_C3 0x2DC
5204 #define YUV_CSC_C4 0x718
5206 #endif /* _IPU_H_ */
5208 /* Rockbox USB defines */
5209 #define USB_NUM_ENDPOINTS 3
5210 #define USB_DEVBSS_ATTR IBSS_ATTR
5212 /* Timer frequency */
5213 #define TIMER_FREQ (CFG_EXTAL) /* For full precision! */
5215 #define CPUFREQ_NORMAL 112000000 /* CPU clock: 112 MHz */
5216 #define CPUFREQ_DEFAULT 112000000 /* CPU clock: 112 MHz */
5217 #define CPUFREQ_MAX 336000000 /* CPU clock: 336 MHz */
5219 #endif /* __JZ4740_H__ */