FS#8961 - Anti-Aliased Fonts.
[kugel-rb.git] / firmware / export / as3525.h
blobcf8d11ba051d1cde6ce9e87b2e9cb8a1fc42c0f5
1 /*
2 * (C) Copyright 2006
3 * Copyright (C) 2006 Austriamicrosystems, by thomas.luo
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
20 #ifndef __AS3525_H__
21 #define __AS3525_H__
23 #define UART_CHANNELS 1
26 #if MEMORYSIZE <= 2
27 /* we put the codec buffer in IRAM */
28 #define AMS_LOWMEM
29 #endif
31 /* Virtual addresses */
32 /* Do not apply to the bootloader, which uses physical addresses (no MMU) */
33 #define DRAM_ORIG 0x30000000
34 #define IRAM_ORIG (DRAM_ORIG + DRAM_SIZE) /* IRAM is mapped just next to DRAM */
36 #define DRAM_SIZE (MEMORYSIZE * 0x100000)
37 #define IRAM_SIZE 0x50000
40 /* AS352X only supports 512 Byte HW ECC */
41 #define ECCSIZE 512
42 #define ECCBYTES 3
44 /* AS352X MMU Page Table Entries */
45 #define TTB_SIZE 0x4000
46 #define TTB_BASE_ADDR (DRAM_ORIG + DRAM_SIZE - TTB_SIZE)
49 /* AS352X device base addresses */
53 ------------------------------------------------------------------------
54 * AS352X Registers
56 ------------------------------------------------------------------------
61 /* AHB */
62 #define USB_BASE 0xC6000000
63 #define VIC_BASE 0xC6010000
64 #define DMAC_BASE 0xC6020000
65 #define MPMC_BASE 0xC6030000
66 #define MEMSTICK_BASE 0xC6040000
67 #define CF_IDE_BASE 0xC6050000
69 /* APB */
70 #define NAND_FLASH_BASE 0xC8000000
71 #define BIST_MANAGER_BASE 0xC8010000
72 #define SD_MCI_BASE 0xC8020000
73 #define TIMER_BASE 0xC8040000
74 #define WDT_BASE 0xC8050000
75 #define I2C_MS_BASE 0xC8060000
76 #define I2C_AUDIO_BASE 0xC8070000
77 #define SSP_BASE 0xC8080000
78 #define I2SIN_BASE 0xC8090000
79 #define I2SOUT_BASE 0xC80A0000
80 #define GPIOA_BASE 0xC80B0000
81 #define GPIOB_BASE 0xC80C0000
82 #define GPIOC_BASE 0xC80D0000
83 #define GPIOD_BASE 0xC80E0000
84 #define CGU_BASE 0xC80F0000
85 #define CCU_BASE 0xC8100000
86 #define UART0_BASE 0xC8110000
87 #define DBOP_BASE 0xC8120000
97 ------------------------------------------------------------------------
98 * AS352X control registers
100 ------------------------------------------------------------------------
103 #define CCU_SRC (*(volatile unsigned long *)(CCU_BASE + 0x00))
104 #define CCU_SRL (*(volatile unsigned long *)(CCU_BASE + 0x04))
105 #define CCU_MEMMAP (*(volatile unsigned long *)(CCU_BASE + 0x08))
106 #define CCU_IO (*(volatile unsigned long *)(CCU_BASE + 0x0C))
107 #define CCU_SCON (*(volatile unsigned long *)(CCU_BASE + 0x10))
108 #define CCU_VERS (*(volatile unsigned long *)(CCU_BASE + 0x14))
109 #define CCU_SPARE1 (*(volatile unsigned long *)(CCU_BASE + 0x18))
110 #define CCU_SPARE2 (*(volatile unsigned long *)(CCU_BASE + 0x1C))
112 /* DBOP */
113 #define DBOP_TIMPOL_01 (*(volatile unsigned long *)(DBOP_BASE + 0x00))
114 #define DBOP_TIMPOL_23 (*(volatile unsigned long *)(DBOP_BASE + 0x04))
115 #define DBOP_CTRL (*(volatile unsigned long *)(DBOP_BASE + 0x08))
116 #define DBOP_STAT (*(volatile unsigned long *)(DBOP_BASE + 0x0C))
117 #define DBOP_DOUT (*(volatile unsigned short *)(DBOP_BASE + 0x10))
118 #define DBOP_DIN (*(volatile unsigned short*)(DBOP_BASE + 0x14))
122 * Reset Control Lines in CCU_SRC register
124 #define CCU_SRC_DBOP_EN ( 1 << 24 )
125 #define CCU_SRC_SPDIF_EN ( 1 << 22 )
126 #define CCU_SRC_TIMER_EN ( 1 << 21 )
127 #define CCU_SRC_SSP_EN ( 1 << 20 )
128 #define CCU_SRC_WDO_EN ( 1 << 19 )
129 #define CCU_SRC_IDE_EN ( 1 << 18 )
130 #define CCU_SRC_IDE_AHB_EN ( 1 << 17 )
131 #define CCU_SRC_UART0 ( 1 << 16 )
132 #define CCU_SRC_NAF_EN ( 1 << 15 )
133 #define CCU_SRC_SDMCI_EN ( 1 << 14 )
134 #define CCU_SRC_GPIO_EN ( 1 << 13 )
135 #define CCU_SRC_I2C_AUDIO_EN ( 1 << 12 )
136 #define CCU_SRC_I2C_EN ( 1 << 11 )
137 #define CCU_SRC_MST_EN ( 1 << 10 )
138 #define CCU_SRC_I2SIN ( 1 << 9 )
139 #define CCU_SRC_I2SOUT ( 1 << 8 )
140 #define CCU_SRC_USB_AHB_EN ( 1 << 7 )
141 #define CCU_SRC_USB_PHY_EN ( 1 << 6 )
142 #define CCU_SRC_DMAC_EN ( 1 << 5 )
143 #define CCU_SRC_VIC_EN ( 1 << 4 )
146 * Magic number for CCU_SRL for reset.
148 #define CCU_SRL_MAGIC_NUMBER 0x1A720212
151 * Chip select lines for NAF. Use these constants to select/deselct the
152 CE lines
153 * for NAND flashes in Register CCU_IO.
155 #define CCU_IO_NAF_CE_LINE_0 ( 0 << 7 )
156 #define CCU_IO_NAF_CE_LINE_1 ( 1 << 7 )
157 #define CCU_IO_NAF_CE_LINE_2 ( 2 << 7 )
158 #define CCU_IO_NAF_CE_LINE_3 ( 3 << 7 )
160 /* CCU IO Select/Deselect IDE */
161 #define CCU_IO_IDE ( 1 << 5 )
163 /* CCU IO Select/desect I2C */
164 #define CCU_IO_I2C_MASTER_SLAVE ( 1 << 1 )
166 /* CCU IO Select/desect UART */
167 #define CCU_IO_UART0 ( 1 << 0 )
170 #define CCU_RESET_ALL_BUT_MEMORY \
171 ( CCU_SRC_DBOP_EN \
172 | CCU_SRC_SPDIF_EN \
173 | CCU_SRC_TIMER_EN \
174 | CCU_SRC_SSP_EN \
175 | CCU_SRC_WDO_EN \
176 | CCU_SRC_IDE_EN \
177 | CCU_SRC_IDE_AHB_EN \
178 | CCU_SRC_UART0 \
179 | CCU_SRC_NAF_EN \
180 | CCU_SRC_SDMCI_EN \
181 | CCU_SRC_GPIO_EN \
182 | CCU_SRC_I2C_AUDIO_EN \
183 | CCU_SRC_I2C_EN \
184 | CCU_SRC_MST_EN \
185 | CCU_SRC_I2SIN \
186 | CCU_SRC_I2SOUT \
187 | CCU_SRC_USB_AHB_EN \
188 | CCU_SRC_USB_PHY_EN \
189 | CCU_SRC_DMAC_EN \
190 | CCU_SRC_VIC_EN \
193 #define CCU_IO_UART ( 1 << 0 )
195 ------------------------------------------------------------------------
196 * AS352X clock control registers
198 ------------------------------------------------------------------------
201 #define CGU_PLLA (*(volatile unsigned long *)(CGU_BASE + 0x00))
202 #define CGU_PLLB (*(volatile unsigned long *)(CGU_BASE + 0x04))
203 #define CGU_PLLASUP (*(volatile unsigned long *)(CGU_BASE + 0x08))
204 #define CGU_PLLBSUP (*(volatile unsigned long *)(CGU_BASE + 0x0C))
205 #define CGU_PROC (*(volatile unsigned long *)(CGU_BASE + 0x10))
206 #define CGU_PERI (*(volatile unsigned long *)(CGU_BASE + 0x14))
207 #define CGU_AUDIO (*(volatile unsigned long *)(CGU_BASE + 0x18))
208 #define CGU_USB (*(volatile unsigned long *)(CGU_BASE + 0x1C))
209 #define CGU_INTCTRL (*(volatile unsigned long *)(CGU_BASE + 0x20))
210 #define CGU_IRQ (*(volatile unsigned long *)(CGU_BASE + 0x24))
211 #define CGU_COUNTA (*(volatile unsigned long *)(CGU_BASE + 0x28))
212 #define CGU_COUNTB (*(volatile unsigned long *)(CGU_BASE + 0x2C))
213 #define CGU_IDE (*(volatile unsigned long *)(CGU_BASE + 0x30))
214 #define CGU_MEMSTICK (*(volatile unsigned long *)(CGU_BASE + 0x34))
215 #define CGU_DBOP (*(volatile unsigned long *)(CGU_BASE + 0x38))
217 #define CGU_VIC_CLOCK_ENABLE ( 1 << 23 ) /* vic */
218 /* --- are disabled after reset --- */
219 #define CGU_DMA_CLOCK_ENABLE ( 1 << 22 ) /* dma */
220 #define CGU_USB_CLOCK_ENABLE ( 1 << 21 ) /* usb */
221 #define CGU_I2SOUT_APB_CLOCK_ENABLE ( 1 << 20 ) /* i2sout */
222 #define CGU_I2SIN_APB_CLOCK_ENABLE ( 1 << 19 ) /* i2sin */
223 #define CGU_I2C_MASTER_SLAVE_CLOCK_ENABLE ( 1 << 18 ) /* i2c master/slave */
224 #define CGU_I2C_AUDIO_MASTER_CLOCK_ENABLE ( 1 << 17 ) /* i2c audio master */
225 #define CGU_GPIO_CLOCK_ENABLE ( 1 << 16 ) /* gpio */
226 #define CGU_MCI_CLOCK_ENABLE ( 1 << 15 ) /* mmc + sd */
227 #define CGU_NAF_CLOCK_ENABLE ( 1 << 14 ) /* naf */
228 #define CGU_UART_APB_CLOCK_ENABLE ( 1 << 13 ) /* uart */
229 #define CGU_WDOCNT_CLOCK_ENABLE ( 1 << 12 ) /* watchdog counter */
230 #define CGU_WDOIF_CLOCK_ENABLE ( 1 << 11 ) /* watchdog timer module */
231 #define CGU_SSP_CLOCK_ENABLE ( 1 << 10 ) /* ssp */
232 #define CGU_TIMER1_CLOCK_ENABLE ( 1 << 9 ) /* timer 1 */
233 #define CGU_TIMER2_CLOCK_ENABLE ( 1 << 8 ) /* timer 2 */
234 #define CGU_TIMERIF_CLOCK_ENABLE ( 1 << 7 ) /* timer
235 interface */
237 /** ------------------------------------------------------------------
238 * Number of cycles to wait before cgu is safely locked.
240 #define CGU_LOCK_CNT 0xFF
242 /* FIFO depth is 16 for tx and rx fifo */
243 #define UART_FIFO_DEPTH 16
245 /* ------------------- UART Line Control Register bit fields -------------------- */
247 #define UART_LNCTL_DLSEN (1 << 7) /* Device latch select bit */
250 /* -------------- UART Interrupt Control Register bit fields --------------- */
252 #define UART_INTR_RXDRDY 0x1 /* Data ready interrupt */
253 #define UART_INTR_TXEMT 0x2 /* Transmit data empty interrupt */
254 #define UART_INTR_RXLINESTATUS 0x4 /* Receive line status interrupt */
256 /* ------------------- UART Line Status Register bit fields -------------------- */
258 #define UART_ERRORBITS 0x1E
259 #define UART_RX_DATA_READY (1 << 0)
260 #define UART_TX_HOLD_EMPTY (1 << 5)
262 /* ------------------- FIFO CNTL Register contants -------------------*/
264 #define UART_FIFO_EN (1 << 0) /* Enable the UART FIFO */
265 #define UART_TX_FIFO_RST (1 << 1) /* Enable the UART FIFO */
266 #define UART_RX_FIFO_RST (1 << 2)
267 #define UART_RXFIFO_TRIGLVL_1 (0 << 4) /* RX FIFO TRIGGER_LEVEL 1 */
268 #define UART_RXFIFO_TRIGLVL_4 0x08 /* RX FIFO TRIGGER_LEVEL 4 */
269 #define UART_RXFIFO_TRIGLVL_8 0x10 /* RX FIFO TRIGGER_LEVEL 8 */
270 #define UART_RXFIFO_TRIGLVL_14 0x18 /* RX FIFO TRIGGER_LEVEL 14 */
273 /* ------------------- FIFO status Register contants ------------------*/
274 #define UART_TX_FIFO_FULL (1 << 0)
275 #define UART_RX_FIFO_FULL (1 << 1)
276 #define UART_TX_FIFO_EMPTY (1 << 2)
277 #define UART_RX_FIFO_EMPTY (1 << 3)
280 /* ----------------------- defines ---------------------------------------- */
284 #define UART_DATA_REG (*(volatile unsigned long*)(UART0_BASE + 0x00)) /* Data register */
285 #define UART_DLO_REG (*(volatile unsigned long*)(UART0_BASE + 0x00)) /* Clock divider(lower byte) register */
286 #define UART_DHI_REG (*(volatile unsigned long*)(UART0_BASE + 0x04)) /* Clock divider(higher byte) register */
287 #define UART_INTEN_REG (*(volatile unsigned long*)(UART0_BASE + 0x04)) /* Interrupt enable register */
288 #define UART_INTSTATUS_REG (*(volatile unsigned long*)(UART0_BASE + 0x08)) /* Interrupt status register */
289 #define UART_FCTL_REG (*(volatile unsigned long*)(UART0_BASE + 0x0C)) /* Fifo control register */
290 #define UART_FSTATUS_REG (*(volatile unsigned long*)(UART0_BASE + 0x0C)) /* Fifo status register */
291 #define UART_LNCTL_REG (*(volatile unsigned long*)(UART0_BASE + 0x10)) /* Line control register */
292 #define UART_LNSTATUS_REG (*(volatile unsigned long*)(UART0_BASE + 0x14)) /* Line status register */
295 #define SD_MCI_POWER (*(volatile unsigned long*)(SD_MCI_BASE + 0x0))
298 #define TIMER1_LOAD (*(volatile unsigned long*)(TIMER_BASE + 0x00)) /* 32-bit width */
299 #define TIMER1_VALUE (*(volatile unsigned long*)(TIMER_BASE + 0x04)) /* 32 bit width */
300 #define TIMER1_CONTROL (*(volatile unsigned long*)(TIMER_BASE + 0x08)) /* 8 bit width */
301 #define TIMER1_INTCLR (*(volatile unsigned long*)(TIMER_BASE + 0x0C)) /* clears ir by write access */
302 #define TIMER1_RIS (*(volatile unsigned long*)(TIMER_BASE + 0x10)) /* 1 bit width */
303 #define TIMER1_MIS (*(volatile unsigned long*)(TIMER_BASE + 0x14)) /* 1 bit width */
304 #define TIMER1_BGLOAD (*(volatile unsigned long*)(TIMER_BASE + 0x18)) /* 32-bit width */
306 #define TIMER2_LOAD (*(volatile unsigned long*)(TIMER_BASE + 0x20)) /* 32-bit width */
307 #define TIMER2_VALUE (*(volatile unsigned long*)(TIMER_BASE + 0x24)) /* 32 bit width */
308 #define TIMER2_CONTROL (*(volatile unsigned long*)(TIMER_BASE + 0x28)) /* 8 bit width */
309 #define TIMER2_INTCLR (*(volatile unsigned long*)(TIMER_BASE + 0x2C)) /* clears ir by write access */
310 #define TIMER2_RIS (*(volatile unsigned long*)(TIMER_BASE + 0x30)) /* 1 bit width */
311 #define TIMER2_MIS (*(volatile unsigned long*)(TIMER_BASE + 0x34)) /* 1 bit width */
312 #define TIMER2_BGLOAD (*(volatile unsigned long*)(TIMER_BASE + 0x38)) /* 32-bit width */
315 * Counter/Timer control register bits
317 #define TIMER_ENABLE 0x80
318 #define TIMER_PERIODIC 0x40
319 #define TIMER_INT_ENABLE 0x20
320 #define TIMER_32_BIT 0x02
321 #define TIMER_ONE_SHOT 0x01
322 #define TIMER_PRESCALE_1 0x00
323 #define TIMER_PRESCALE_16 0x04
324 #define TIMER_PRESCALE_256 0x08
327 /* Watchdog registers */
328 #define WDT_LOAD (*(volatile unsigned long*)(WDT_BASE))
329 #define WDT_CONTROL (*(volatile unsigned long*)(WDT_BASE+8))
332 /* GPIO registers */
334 #define GPIOA_DIR (*(volatile unsigned char*)(GPIOA_BASE+0x400))
335 #define GPIOA_IS (*(volatile unsigned char*)(GPIOA_BASE+0x404))
336 #define GPIOA_IBE (*(volatile unsigned char*)(GPIOA_BASE+0x408))
337 #define GPIOA_IEV (*(volatile unsigned char*)(GPIOA_BASE+0x40C))
338 #define GPIOA_IE (*(volatile unsigned char*)(GPIOA_BASE+0x410))
339 #define GPIOA_RIS (*(volatile unsigned char*)(GPIOA_BASE+0x414))
340 #define GPIOA_MIS (*(volatile unsigned char*)(GPIOA_BASE+0x418))
341 #define GPIOA_IC (*(volatile unsigned char*)(GPIOA_BASE+0x41C))
342 #define GPIOA_AFSEL (*(volatile unsigned char*)(GPIOA_BASE+0x420))
343 #define GPIOA_PIN(a) (*(volatile unsigned char*)(GPIOA_BASE+(1<<((a)+2))))
344 #define GPIOA_DATA (*(volatile unsigned char*)(GPIOA_BASE+(0xff<<2)))
347 #define GPIOB_DIR (*(volatile unsigned char*)(GPIOB_BASE+0x400))
348 #define GPIOB_IS (*(volatile unsigned char*)(GPIOB_BASE+0x404))
349 #define GPIOB_IBE (*(volatile unsigned char*)(GPIOB_BASE+0x408))
350 #define GPIOB_IEV (*(volatile unsigned char*)(GPIOB_BASE+0x40C))
351 #define GPIOB_IE (*(volatile unsigned char*)(GPIOB_BASE+0x410))
352 #define GPIOB_RIS (*(volatile unsigned char*)(GPIOB_BASE+0x414))
353 #define GPIOB_MIS (*(volatile unsigned char*)(GPIOB_BASE+0x418))
354 #define GPIOB_IC (*(volatile unsigned char*)(GPIOB_BASE+0x41C))
355 #define GPIOB_AFSEL (*(volatile unsigned char*)(GPIOB_BASE+0x420))
356 #define GPIOB_PIN(a) (*(volatile unsigned char*)(GPIOB_BASE+(1<<((a)+2))))
357 #define GPIOB_DATA (*(volatile unsigned char*)(GPIOB_BASE+(0xff<<2)))
359 #define GPIOC_DIR (*(volatile unsigned char*)(GPIOC_BASE+0x400))
360 #define GPIOC_IS (*(volatile unsigned char*)(GPIOC_BASE+0x404))
361 #define GPIOC_IBE (*(volatile unsigned char*)(GPIOC_BASE+0x408))
362 #define GPIOC_IEV (*(volatile unsigned char*)(GPIOC_BASE+0x40C))
363 #define GPIOC_IE (*(volatile unsigned char*)(GPIOC_BASE+0x410))
364 #define GPIOC_RIS (*(volatile unsigned char*)(GPIOC_BASE+0x414))
365 #define GPIOC_MIS (*(volatile unsigned char*)(GPIOC_BASE+0x418))
366 #define GPIOC_IC (*(volatile unsigned char*)(GPIOC_BASE+0x41C))
367 #define GPIOC_AFSEL (*(volatile unsigned char*)(GPIOC_BASE+0x420))
368 #define GPIOC_PIN(a) (*(volatile unsigned char*)(GPIOC_BASE+(1<<((a)+2))))
369 #define GPIOC_DATA (*(volatile unsigned char*)(GPIOC_BASE+(0xff<<2)))
371 #define GPIOD_DIR (*(volatile unsigned char*)(GPIOD_BASE+0x400))
372 #define GPIOD_IS (*(volatile unsigned char*)(GPIOD_BASE+0x404))
373 #define GPIOD_IBE (*(volatile unsigned char*)(GPIOD_BASE+0x408))
374 #define GPIOD_IEV (*(volatile unsigned char*)(GPIOD_BASE+0x40C))
375 #define GPIOD_IE (*(volatile unsigned char*)(GPIOD_BASE+0x410))
376 #define GPIOD_RIS (*(volatile unsigned char*)(GPIOD_BASE+0x414))
377 #define GPIOD_MIS (*(volatile unsigned char*)(GPIOD_BASE+0x418))
378 #define GPIOD_IC (*(volatile unsigned char*)(GPIOD_BASE+0x41C))
379 #define GPIOD_AFSEL (*(volatile unsigned char*)(GPIOD_BASE+0x420))
380 #define GPIOD_PIN(a) (*(volatile unsigned char*)(GPIOD_BASE+(1<<((a)+2))))
381 #define GPIOD_DATA (*(volatile unsigned char*)(GPIOD_BASE+(0xff<<2)))
383 /* ARM PL172 Memory Controller registers */
385 #define MPMC_CONTROL (*(volatile unsigned long*)(MPMC_BASE+0x000))
386 #define MPMC_STATUS (*(volatile unsigned long*)(MPMC_BASE+0x004))
387 #define MPMC_CONFIG (*(volatile unsigned long*)(MPMC_BASE+0x008))
389 #define MPMC_DYNAMIC_CONTROL (*(volatile unsigned long*)(MPMC_BASE+0x020))
390 #define MPMC_DYNAMIC_REFRESH (*(volatile unsigned long*)(MPMC_BASE+0x024))
391 #define MPMC_DYNAMIC_READ_CONFIG (*(volatile unsigned long*)(MPMC_BASE+0x028))
392 #define MPMC_DYNAMIC_tRP (*(volatile unsigned long*)(MPMC_BASE+0x030))
393 #define MPMC_DYNAMIC_tRAS (*(volatile unsigned long*)(MPMC_BASE+0x034))
394 #define MPMC_DYNAMIC_tSREX (*(volatile unsigned long*)(MPMC_BASE+0x038))
395 #define MPMC_DYNAMIC_tAPR (*(volatile unsigned long*)(MPMC_BASE+0x03C))
396 #define MPMC_DYNAMIC_tDAL (*(volatile unsigned long*)(MPMC_BASE+0x040))
397 #define MPMC_DYNAMIC_tWR (*(volatile unsigned long*)(MPMC_BASE+0x044))
398 #define MPMC_DYNAMIC_tRC (*(volatile unsigned long*)(MPMC_BASE+0x048))
399 #define MPMC_DYNAMIC_tRFC (*(volatile unsigned long*)(MPMC_BASE+0x04C))
400 #define MPMC_DYNAMIC_tXSR (*(volatile unsigned long*)(MPMC_BASE+0x050))
401 #define MPMC_DYNAMIC_tRRD (*(volatile unsigned long*)(MPMC_BASE+0x054))
402 #define MPMC_DYNAMIC_tMRD (*(volatile unsigned long*)(MPMC_BASE+0x058))
404 #define MPMC_STATIC_EXTENDED_WAIT (*(volatile unsigned long*)(MPMC_BASE+0x080))
406 #define MPMC_DYNAMIC_CONFIG_0 (*(volatile unsigned long*)(MPMC_BASE+0x100))
407 #define MPMC_DYNAMIC_CONFIG_1 (*(volatile unsigned long*)(MPMC_BASE+0x120))
408 #define MPMC_DYNAMIC_CONFIG_2 (*(volatile unsigned long*)(MPMC_BASE+0x140))
409 #define MPMC_DYNAMIC_CONFIG_3 (*(volatile unsigned long*)(MPMC_BASE+0x160))
411 #define MPMC_DYNAMIC_RASCAS_0 (*(volatile unsigned long*)(MPMC_BASE+0x104))
412 #define MPMC_DYNAMIC_RASCAS_1 (*(volatile unsigned long*)(MPMC_BASE+0x124))
413 #define MPMC_DYNAMIC_RASCAS_2 (*(volatile unsigned long*)(MPMC_BASE+0x144))
414 #define MPMC_DYNAMIC_RASCAS_3 (*(volatile unsigned long*)(MPMC_BASE+0x164))
416 #define MPMC_PERIPH_ID2 (*(volatile unsigned long*)(MPMC_BASE+0xFE8))
418 /* VIC controller (PL190) registers */
420 #define VIC_IRQ_STATUS (*(volatile unsigned long*)(VIC_BASE+0x00))
421 #define VIC_FIQ_STATUS (*(volatile unsigned long*)(VIC_BASE+0x04))
422 #define VIC_RAW_INTR (*(volatile unsigned long*)(VIC_BASE+0x08))
423 #define VIC_INT_SELECT (*(volatile unsigned long*)(VIC_BASE+0x0C))
424 #define VIC_INT_ENABLE (*(volatile unsigned long*)(VIC_BASE+0x10))
425 #define VIC_INT_EN_CLEAR (*(volatile unsigned long*)(VIC_BASE+0x14))
426 #define VIC_SOFT_INT (*(volatile unsigned long*)(VIC_BASE+0x18))
427 #define VIC_SOFT_INT_CLEAR (*(volatile unsigned long*)(VIC_BASE+0x1C))
428 #define VIC_PROTECTION (*(volatile unsigned long*)(VIC_BASE+0x20))
429 #define VIC_VECT_ADDR (*(volatile unsigned long*)(VIC_BASE+0x30))
430 #define VIC_DEF_VECT_ADDR (*(volatile unsigned long*)(VIC_BASE+0x34))
431 #define VIC_VECT_ADDRS ((volatile unsigned long*)(VIC_BASE+0x100))
432 #define VIC_VECT_CNTLS ((volatile unsigned long*)(VIC_BASE+0x200))
434 /* Interrupt sources (for vectors setup) */
435 #define INT_SRC_WATCHDOG 0
436 #define INT_SRC_TIMER1 1
437 #define INT_SRC_TIMER2 2
438 #define INT_SRC_USB 3
439 #define INT_SRC_DMAC 4
440 #define INT_SRC_NAND 5
441 #define INT_SRC_IDE 6
442 #define INT_SRC_MCI0 7
443 #define INT_SRC_MCI1 8
444 #define INT_SRC_AUDIO 9
445 #define INT_SRC_SSP 10
446 #define INT_SRC_I2C_MS 11
447 #define INT_SRC_I2C_AUDIO 12
448 #define INT_SRC_I2SIN 13
449 #define INT_SRC_I2SOUT 14
450 #define INT_SRC_UART 15
451 #define INT_SRC_GPIOD 16
452 /* 17 reserved */
453 #define INT_SRC_CGU 18
454 #define INT_SRC_MEMORY_STICK 19
455 #define INT_SRC_DBOP 20
456 /* 21-28 reserved */
457 #define INT_SRC_GPIOA 29
458 #define INT_SRC_GPIOB 30
459 #define INT_SRC_GPIOC 31
461 /* Interrupt sources bitmask */
462 #define INTERRUPT_WATCHDOG (1<<0)
463 #define INTERRUPT_TIMER1 (1<<1)
464 #define INTERRUPT_TIMER2 (1<<2)
465 #define INTERRUPT_USB (1<<3)
466 #define INTERRUPT_DMAC (1<<4)
467 #define INTERRUPT_NAND (1<<5)
468 #define INTERRUPT_IDE (1<<6)
469 #define INTERRUPT_MCI0 (1<<7)
470 #define INTERRUPT_MCI1 (1<<8)
471 #define INTERRUPT_AUDIO (1<<9)
472 #define INTERRUPT_SSP (1<<10)
473 #define INTERRUPT_I2C_MS (1<<11)
474 #define INTERRUPT_I2C_AUDIO (1<<12)
475 #define INTERRUPT_I2SIN (1<<13)
476 #define INTERRUPT_I2SOUT (1<<14)
477 #define INTERRUPT_UART (1<<15)
478 #define INTERRUPT_GPIOD (1<<16)
479 /* 17 reserved */
480 #define INTERRUPT_CGU (1<<18)
481 #define INTERRUPT_MEMORY_STICK (1<<19)
482 #define INTERRUPT_DBOP (1<<20)
483 /* 21-28 reserved */
484 #define INTERRUPT_GPIOA (1<<29)
485 #define INTERRUPT_GPIOB (1<<30)
486 #define INTERRUPT_GPIOC (1<<31)
488 /* I2SOUT registers */
490 #define I2SOUT_CONTROL (*(volatile unsigned char*)(I2SOUT_BASE+0x00))
491 #define I2SOUT_MASK (*(volatile unsigned char*)(I2SOUT_BASE+0x04))
492 #define I2SOUT_RAW_STATUS (*(volatile unsigned char*)(I2SOUT_BASE+0x08))
493 #define I2SOUT_STATUS (*(volatile unsigned char*)(I2SOUT_BASE+0x0C))
494 #define I2SOUT_CLEAR (*(volatile unsigned char*)(I2SOUT_BASE+0x10))
495 #define I2SOUT_DATA (volatile unsigned long*)(I2SOUT_BASE+0x14)
497 /* PCM addresses for obtaining buffers will be what DMA is using (physical) */
498 #define HAVE_PCM_DMA_ADDRESS
500 /* Timer frequency */
501 #define TIMER_FREQ (24000000 / 16)
503 /* USB : TODO */
504 #define USB_NUM_ENDPOINTS 4
505 #define USB_DEVBSS_ATTR IBSS_ATTR
507 #endif /*__AS3525_H__*/