Correction to previous commit: fix condition to include backlight-target.h (not neede...
[kugel-rb.git] / firmware / target / arm / as3525 / sd-as3525v2.c
blob1f8044a18b7552c8818756fd864114d22db6a872
1 /***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
10 * Copyright (C) 2006 Daniel Ankers
11 * Copyright © 2008-2009 Rafaël Carré
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version 2
16 * of the License, or (at your option) any later version.
18 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
19 * KIND, either express or implied.
21 ****************************************************************************/
23 #include "config.h" /* for HAVE_MULTIVOLUME */
24 #include "fat.h"
25 #include "thread.h"
26 #include "led.h"
27 #include "sdmmc.h"
28 #include "system.h"
29 #include "kernel.h"
30 #include "cpu.h"
31 #include <stdio.h>
32 #include <stdlib.h>
33 #include <string.h>
34 #include "as3525v2.h"
35 #include "pl081.h" /* DMA controller */
36 #include "dma-target.h" /* DMA request lines */
37 #include "clock-target.h"
38 #include "panic.h"
39 #include "stdbool.h"
40 #include "ata_idle_notify.h"
41 #include "sd.h"
42 #include "usb.h"
44 #ifdef HAVE_HOTSWAP
45 #include "disk.h"
46 #endif
48 #if defined(SANSA_FUZEV2)
49 #include "backlight-target.h"
50 #endif
52 #include "lcd.h"
53 #include <stdarg.h>
54 #include "sysfont.h"
56 #define INTERNAL_AS3525 0 /* embedded SD card */
57 #define SD_SLOT_AS3525 1 /* SD slot if present */
59 /* Clipv2 Clip+ and Fuzev2 OF all occupy the same size */
60 #define AMS_OF_SIZE 0xf000
62 /* command flags */
63 #define MCI_NO_RESP (0<<0)
64 #define MCI_RESP (1<<0)
65 #define MCI_LONG_RESP (1<<1)
67 /* controller registers */
68 #define SD_BASE 0xC6070000
70 #define SD_REG(x) (*(volatile unsigned long *) (SD_BASE+x))
72 #define MCI_CTRL SD_REG(0x00)
74 /* control bits */
75 #define CTRL_RESET (1<<0)
76 #define FIFO_RESET (1<<1)
77 #define DMA_RESET (1<<2)
78 #define INT_ENABLE (1<<4)
79 #define DMA_ENABLE (1<<5)
80 #define READ_WAIT (1<<6)
81 #define SEND_IRQ_RESP (1<<7)
82 #define ABRT_READ_DATA (1<<8)
83 #define SEND_CCSD (1<<9)
84 #define SEND_AS_CCSD (1<<10)
85 #define EN_OD_PULLUP (1<<24)
88 #define MCI_PWREN SD_REG(0x04) /* power enable */
90 #define PWR_CRD_0 (1<<0)
91 #define PWR_CRD_1 (1<<1)
92 #define PWR_CRD_2 (1<<2)
93 #define PWR_CRD_3 (1<<3)
95 #define MCI_CLKDIV SD_REG(0x08) /* clock divider */
96 /* CLK_DIV_0 : bits 7:0
97 * CLK_DIV_1 : bits 15:8
98 * CLK_DIV_2 : bits 23:16
99 * CLK_DIV_3 : bits 31:24
102 #define MCI_CLKSRC SD_REG(0x0C) /* clock source */
103 /* CLK_SRC_CRD0: bits 1:0
104 * CLK_SRC_CRD1: bits 3:2
105 * CLK_SRC_CRD2: bits 5:4
106 * CLK_SRC_CRD3: bits 7:6
109 #define MCI_CLKENA SD_REG(0x10) /* clock enable */
111 #define CCLK_ENA_CRD0 (1<<0)
112 #define CCLK_ENA_CRD1 (1<<1)
113 #define CCLK_ENA_CRD2 (1<<2)
114 #define CCLK_ENA_CRD3 (1<<3)
115 #define CCLK_LP_CRD0 (1<<16) /* LP --> Low Power Mode? */
116 #define CCLK_LP_CRD1 (1<<17)
117 #define CCLK_LP_CRD2 (1<<18)
118 #define CCLK_LP_CRD3 (1<<19)
120 #define MCI_TMOUT SD_REG(0x14) /* timeout */
121 /* response timeout bits 0:7
122 * data timeout bits 8:31
125 #define MCI_CTYPE SD_REG(0x18) /* card type */
126 /* 1 bit per card, set = wide bus */
127 #define WIDTH4_CRD0 (1<<0)
128 #define WIDTH4_CRD1 (1<<1)
129 #define WIDTH4_CRD2 (1<<2)
130 #define WIDTH4_CRD3 (1<<3)
132 #define MCI_BLKSIZ SD_REG(0x1C) /* block size bits 0:15*/
133 #define MCI_BYTCNT SD_REG(0x20) /* byte count bits 0:31*/
134 #define MCI_MASK SD_REG(0x24) /* interrupt mask */
138 #define MCI_ARGUMENT SD_REG(0x28)
139 #define MCI_COMMAND SD_REG(0x2C)
141 /* command bits (bits 5:0 are the command index) */
142 #define CMD_RESP_EXP_BIT (1<<6)
143 #define CMD_RESP_LENGTH_BIT (1<<7)
144 #define CMD_CHECK_CRC_BIT (1<<8)
145 #define CMD_DATA_EXP_BIT (1<<9)
146 #define CMD_RW_BIT (1<<10)
147 #define CMD_TRANSMODE_BIT (1<<11)
148 #define CMD_SENT_AUTO_STOP_BIT (1<<12)
149 #define CMD_WAIT_PRV_DAT_BIT (1<<13)
150 #define CMD_ABRT_CMD_BIT (1<<14)
151 #define CMD_SEND_INIT_BIT (1<<15)
152 #define CMD_CARD_NO(x) ((x)<<16) /* 5 bits wide */
153 #define CMD_SEND_CLK_ONLY (1<<21)
154 #define CMD_READ_CEATA (1<<22)
155 #define CMD_CCS_EXPECTED (1<<23)
156 #define CMD_DONE_BIT (1<<31)
158 #define TRANSFER_CMD (cmd == SD_READ_MULTIPLE_BLOCK || \
159 cmd == SD_WRITE_MULTIPLE_BLOCK)
161 #define MCI_RESP0 SD_REG(0x30)
162 #define MCI_RESP1 SD_REG(0x34)
163 #define MCI_RESP2 SD_REG(0x38)
164 #define MCI_RESP3 SD_REG(0x3C)
166 #define MCI_MASK_STATUS SD_REG(0x40) /* masked interrupt status */
167 #define MCI_RAW_STATUS SD_REG(0x44) /* raw interrupt status, also used as
168 * status clear */
170 /* interrupt bits */ /* C D E (Cmd) (Data) (End) */
171 #define MCI_INT_CRDDET (1<<0) /* card detect */
172 #define MCI_INT_RE (1<<1) /* x response error */
173 #define MCI_INT_CD (1<<2) /* x command done */
174 #define MCI_INT_DTO (1<<3) /* x data transfer over */
175 #define MCI_INT_TXDR (1<<4) /* tx fifo data request */
176 #define MCI_INT_RXDR (1<<5) /* rx fifo data request */
177 #define MCI_INT_RCRC (1<<6) /* x response crc error */
178 #define MCI_INT_DCRC (1<<7) /* x data crc error */
179 #define MCI_INT_RTO (1<<8) /* x response timeout */
180 #define MCI_INT_DRTO (1<<9) /* x data read timeout */
181 #define MCI_INT_HTO (1<<10) /* x data starv timeout */
182 #define MCI_INT_FRUN (1<<11) /* x fifo over/underrun */
183 #define MCI_INT_HLE (1<<12) /* x x hw locked while error */
184 #define MCI_INT_SBE (1<<13) /* x start bit error */
185 #define MCI_INT_ACD (1<<14) /* auto command done */
186 #define MCI_INT_EBE (1<<15) /* x end bit error */
187 #define MCI_INT_SDIO (0xf<<16)
190 * STATUS register
191 * & 0xBA80 = MCI_INT_DCRC | MCI_INT_DRTO | MCI_INT_FRUN | \
192 * MCI_INT_HLE | MCI_INT_SBE | MCI_INT_EBE
193 * & 8 = MCI_INT_DTO
194 * & 0x428 = MCI_INT_DTO | MCI_INT_RXDR | MCI_INT_HTO
195 * & 0x418 = MCI_INT_DTO | MCI_INT_TXDR | MCI_INT_HTO
198 #define MCI_CMD_ERROR \
199 (MCI_INT_RE | \
200 MCI_INT_RCRC | \
201 MCI_INT_RTO | \
202 MCI_INT_HLE)
204 #define MCI_DATA_ERROR \
205 ( MCI_INT_DCRC | \
206 MCI_INT_DRTO | \
207 MCI_INT_HTO | \
208 MCI_INT_FRUN | \
209 MCI_INT_HLE | \
210 MCI_INT_SBE | \
211 MCI_INT_EBE)
213 #define MCI_STATUS SD_REG(0x48)
215 #define FIFO_RX_WM (1<<0)
216 #define FIFO_TX_WM (1<<1)
217 #define FIFO_EMPTY (1<<2)
218 #define FIFO_FULL (1<<3)
219 #define CMD_FSM_STATE_B0 (1<<4)
220 #define CMD_FSM_STATE_B1 (1<<5)
221 #define CMD_FSM_STATE_B2 (1<<6)
222 #define CMD_FSM_STATE_B3 (1<<7)
223 #define DATA_3_STAT (1<<8)
224 #define DATA_BUSY (1<<9)
225 #define DATA_STAT_MC_BUSY (1<<10)
226 #define RESP_IDX_B0 (1<<11)
227 #define RESP_IDX_B1 (1<<12)
228 #define RESP_IDX_B2 (1<<13)
229 #define RESP_IDX_B3 (1<<14)
230 #define RESP_IDX_B4 (1<<15)
231 #define RESP_IDX_B5 (1<<16)
232 #define FIFO_CNT_B00 (1<<17)
233 #define FIFO_CNT_B01 (1<<18)
234 #define FIFO_CNT_B02 (1<<19)
235 #define FIFO_CNT_B03 (1<<20)
236 #define FIFO_CNT_B04 (1<<21)
237 #define FIFO_CNT_B05 (1<<22)
238 #define FIFO_CNT_B06 (1<<23)
239 #define FIFO_CNT_B07 (1<<24)
240 #define FIFO_CNT_B08 (1<<25)
241 #define FIFO_CNT_B09 (1<<26)
242 #define FIFO_CNT_B10 (1<<27)
243 #define FIFO_CNT_B11 (1<<28)
244 #define FIFO_CNT_B12 (1<<29)
245 #define DMA_ACK (1<<30)
246 #define START_CMD (1<<31)
248 #define MCI_FIFOTH SD_REG(0x4C) /* FIFO threshold */
249 /* TX watermark : bits 11:0
250 * RX watermark : bits 27:16
251 * DMA MTRANS SIZE : bits 30:28
252 * bits 31, 15:12 : unused
254 #define MCI_FIFOTH_MASK 0x8000f000
256 #define MCI_CDETECT SD_REG(0x50) /* card detect */
258 #define CDETECT_CRD_0 (1<<0)
259 #define CDETECT_CRD_1 (1<<1)
260 #define CDETECT_CRD_2 (1<<2)
261 #define CDETECT_CRD_3 (1<<3)
263 #define MCI_WRTPRT SD_REG(0x54) /* write protect */
264 #define MCI_GPIO SD_REG(0x58)
265 #define MCI_TCBCNT SD_REG(0x5C) /* transferred CIU byte count (card)*/
266 #define MCI_TBBCNT SD_REG(0x60) /* transferred host/DMA to/from bytes (FIFO)*/
267 #define MCI_DEBNCE SD_REG(0x64) /* card detect debounce bits 23:0*/
268 #define MCI_USRID SD_REG(0x68) /* user id */
269 #define MCI_VERID SD_REG(0x6C) /* version id */
271 #define MCI_HCON SD_REG(0x70) /* hardware config */
272 /* bit 0 : card type
273 * bits 5:1 : maximum card index
274 * bit 6 : BUS TYPE
275 * bits 9:7 : DATA WIDTH
276 * bits 15:10 : ADDR WIDTH
277 * bits 17:16 : DMA IF
278 * bits 20:18 : DMA WIDTH
279 * bit 21 : FIFO RAM INSIDE
280 * bit 22 : IMPL HOLD REG
281 * bit 23 : SET CLK FALSE
282 * bits 25:24 : MAX CLK DIV IDX
283 * bit 26 : AREA OPTIM
286 #define MCI_BMOD SD_REG(0x80) /* bus mode */
287 /* bit 0 : SWR
288 * bit 1 : FB
289 * bits 6:2 : DSL
290 * bit 7 : DE
291 * bit 10:8 : PBL
294 #define MCI_PLDMND SD_REG(0x84) /* poll demand */
295 #define MCI_DBADDR SD_REG(0x88) /* descriptor base address */
296 #define MCI_IDSTS SD_REG(0x8C) /* internal DMAC status */
297 /* bit 0 : TI
298 * bit 1 : RI
299 * bit 2 : FBE
300 * bit 3 : unused
301 * bit 4 : DU
302 * bit 5 : CES
303 * bits 7:6 : unused
304 * bits 8 : NIS
305 * bit 9 : AIS
306 * bits 12:10 : EB
307 * bits 16:13 : FSM
310 #define MCI_IDINTEN SD_REG(0x90) /* internal DMAC interrupt enable */
311 /* bit 0 : TI
312 * bit 1 : RI
313 * bit 2 : FBE
314 * bit 3 : unused
315 * bit 4 : DU
316 * bit 5 : CES
317 * bits 7:6 : unused
318 * bits 8 : NI
319 * bit 9 : AI
321 #define MCI_DSCADDR SD_REG(0x94) /* current host descriptor address */
322 #define MCI_BUFADDR SD_REG(0x98) /* current host buffer address */
324 #define MCI_FIFO ((unsigned long *) (SD_BASE+0x100))
326 #define UNALIGNED_NUM_SECTORS 10
327 static unsigned char aligned_buffer[UNALIGNED_NUM_SECTORS* SD_BLOCK_SIZE] __attribute__((aligned(32))); /* align on cache line size */
328 static unsigned char *uncached_buffer = AS3525_UNCACHED_ADDR(&aligned_buffer[0]);
330 static tCardInfo card_info[NUM_DRIVES];
332 /* for compatibility */
333 static long last_disk_activity = -1;
335 #define MIN_YIELD_PERIOD 5 /* ticks */
336 static long next_yield = 0;
338 static long sd_stack [(DEFAULT_STACK_SIZE*2 + 0x200)/sizeof(long)];
339 static const char sd_thread_name[] = "ata/sd";
340 static struct mutex sd_mtx SHAREDBSS_ATTR;
341 static struct event_queue sd_queue;
342 #ifndef BOOTLOADER
343 bool sd_enabled = false;
344 #endif
346 static struct wakeup transfer_completion_signal;
347 static struct wakeup command_completion_signal;
348 static volatile bool retry;
349 static volatile int cmd_error;
351 #if defined(HAVE_MULTIDRIVE)
352 #define EXT_SD_BITS (1<<2)
353 #endif
355 static inline void mci_delay(void) { udelay(1000); }
357 void INT_NAND(void)
359 MCI_CTRL &= ~INT_ENABLE;
360 /* use raw status here as we need to check some Ints that are masked */
361 const int status = MCI_RAW_STATUS;
363 MCI_RAW_STATUS = status; /* clear status */
365 if(status & MCI_DATA_ERROR)
366 retry = true;
368 if( status & (MCI_INT_DTO|MCI_DATA_ERROR))
369 wakeup_signal(&transfer_completion_signal);
371 cmd_error = status & MCI_CMD_ERROR;
373 if(status & MCI_INT_CD)
374 wakeup_signal(&command_completion_signal);
376 MCI_CTRL |= INT_ENABLE;
379 static inline bool card_detect_target(void)
381 #if defined(HAVE_MULTIDRIVE)
382 #if defined(SANSA_FUZEV2)
383 return GPIOA_PIN(2);
384 #elif defined(SANSA_CLIPPLUS)
385 return !(GPIOA_PIN(2));
386 #else
387 #error "microSD pin not defined for your target"
388 #endif
389 #else
390 return false;
391 #endif
394 static bool send_cmd(const int drive, const int cmd, const int arg, const int flags,
395 unsigned long *response)
397 int card_no;
399 #if defined(HAVE_MULTIDRIVE)
400 if(sd_present(SD_SLOT_AS3525))
401 GPIOB_PIN(5) = (1-drive) << 5;
402 #endif
404 MCI_ARGUMENT = arg;
406 #if defined(SANSA_FUZEV2) || defined(SANSA_CLIPPLUS)
407 if (amsv2_variant == 1)
408 card_no = 1 << 16;
409 else
410 #endif
411 card_no = CMD_CARD_NO(drive);
413 /* Construct MCI_COMMAND */
414 MCI_COMMAND =
415 /*b5:0*/ cmd
416 /*b6 */ | ((flags & MCI_RESP) ? CMD_RESP_EXP_BIT: 0)
417 /*b7 */ | ((flags & MCI_LONG_RESP) ? CMD_RESP_LENGTH_BIT: 0)
418 /*b8 | CMD_CHECK_CRC_BIT unused */
419 /*b9 */ | (TRANSFER_CMD ? CMD_DATA_EXP_BIT: 0)
420 /*b10 */ | ((cmd == SD_WRITE_MULTIPLE_BLOCK) ? CMD_RW_BIT: 0)
421 /*b11 | CMD_TRANSMODE_BIT unused */
422 /*b12 | CMD_SENT_AUTO_STOP_BIT unused */
423 /*b13 */ | (TRANSFER_CMD ? CMD_WAIT_PRV_DAT_BIT: 0)
424 /*b14 | CMD_ABRT_CMD_BIT unused */
425 /*b15 | CMD_SEND_INIT_BIT unused */
426 /*b20:16 */ | card_no
427 /*b21 | CMD_SEND_CLK_ONLY unused */
428 /*b22 | CMD_READ_CEATA unused */
429 /*b23 | CMD_CCS_EXPECTED unused */
430 /*b31 */ | CMD_DONE_BIT;
432 #if defined(SANSA_FUZEV2)
433 if (amsv2_variant == 0)
435 extern int buttonlight_is_on;
436 if(buttonlight_is_on)
437 _buttonlight_on();
438 else
439 _buttonlight_off();
441 #endif
442 wakeup_wait(&command_completion_signal, TIMEOUT_BLOCK);
444 /* Handle command responses & errors */
445 if(flags & MCI_RESP)
447 if(cmd_error & (MCI_INT_RCRC | MCI_INT_RTO))
448 return false;
450 if(flags & MCI_LONG_RESP)
452 response[0] = MCI_RESP3;
453 response[1] = MCI_RESP2;
454 response[2] = MCI_RESP1;
455 response[3] = MCI_RESP0;
457 else
458 response[0] = MCI_RESP0;
460 return true;
463 static int sd_wait_for_tran_state(const int drive)
465 unsigned long response;
466 unsigned int timeout = current_tick + 5*HZ;
468 while (1)
470 while(!(send_cmd(drive, SD_SEND_STATUS, card_info[drive].rca, MCI_RESP, &response)));
472 if (((response >> 9) & 0xf) == SD_TRAN)
473 return 0;
475 if(TIME_AFTER(current_tick, timeout))
476 return -10 * ((response >> 9) & 0xf);
478 if (TIME_AFTER(current_tick, next_yield))
480 yield();
481 next_yield = current_tick + MIN_YIELD_PERIOD;
487 static int sd_init_card(const int drive)
489 unsigned long response;
490 long init_timeout;
491 bool sd_v2 = false;
493 /* assume 24 MHz clock / 60 = 400 kHz */
494 MCI_CLKDIV = (MCI_CLKDIV & ~(0xFF)) | 0x3C; /* CLK_DIV_0 : bits 7:0 */
496 /* 100 - 400kHz clock required for Identification Mode */
497 /* Start of Card Identification Mode ************************************/
499 /* CMD0 Go Idle */
500 if(!send_cmd(drive, SD_GO_IDLE_STATE, 0, MCI_NO_RESP, NULL))
501 return -1;
502 mci_delay();
504 /* CMD8 Check for v2 sd card. Must be sent before using ACMD41
505 Non v2 cards will not respond to this command*/
506 if(send_cmd(drive, SD_SEND_IF_COND, 0x1AA, MCI_RESP, &response))
507 if((response & 0xFFF) == 0x1AA)
508 sd_v2 = true;
510 /* timeout for initialization is 1sec, from SD Specification 2.00 */
511 init_timeout = current_tick + HZ;
513 do {
514 /* this timeout is the only valid error for this loop*/
515 if(TIME_AFTER(current_tick, init_timeout))
516 return -2;
518 /* app_cmd */
519 send_cmd(drive, SD_APP_CMD, 0, MCI_RESP, &response);
521 /* ACMD41 For v2 cards set HCS bit[30] & send host voltage range to all */
522 if(!send_cmd(drive, SD_APP_OP_COND, (0x00FF8000 | (sd_v2 ? 1<<30 : 0)),
523 MCI_RESP, &card_info[drive].ocr))
524 return -3;
525 } while(!(card_info[drive].ocr & (1<<31)) );
527 /* CMD2 send CID */
528 if(!send_cmd(drive, SD_ALL_SEND_CID, 0, MCI_RESP|MCI_LONG_RESP, card_info[drive].cid))
529 return -4;
531 /* CMD3 send RCA */
532 if(!send_cmd(drive, SD_SEND_RELATIVE_ADDR, 0, MCI_RESP, &card_info[drive].rca))
533 return -5;
535 #ifdef HAVE_MULTIDRIVE
536 /* Make sure we have 2 unique rca numbers */
537 if(card_info[INTERNAL_AS3525].rca == card_info[SD_SLOT_AS3525].rca)
538 if(!send_cmd(drive, SD_SEND_RELATIVE_ADDR, 0, MCI_RESP, &card_info[drive].rca))
539 return -6;
540 #endif
541 /* End of Card Identification Mode ************************************/
543 /* Attempt to switch cards to HS timings, non HS cards just ignore this */
544 /* CMD7 w/rca: Select card to put it in TRAN state */
545 if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_NO_RESP, NULL))
546 return -7;
548 if(sd_wait_for_tran_state(drive))
549 return -8;
551 /* CMD6 */
552 if(!send_cmd(drive, SD_SWITCH_FUNC, 0x80fffff1, MCI_NO_RESP, NULL))
553 return -9;
554 mci_delay();
556 /* We need to go back to STBY state now so we can read csd */
557 /* CMD7 w/rca=0: Deselect card to put it in STBY state */
558 if(!send_cmd(drive, SD_DESELECT_CARD, 0, MCI_NO_RESP, NULL))
559 return -10;
561 /* CMD9 send CSD */
562 if(!send_cmd(drive, SD_SEND_CSD, card_info[drive].rca,
563 MCI_RESP|MCI_LONG_RESP, card_info[drive].csd))
564 return -11;
566 sd_parse_csd(&card_info[drive]);
568 if(drive == INTERNAL_AS3525) /* The OF is stored in the first blocks */
569 card_info[INTERNAL_AS3525].numblocks -= AMS_OF_SIZE;
571 /* Card back to full speed */
572 MCI_CLKDIV &= ~(0xFF); /* CLK_DIV_0 : bits 7:0 = 0x00 */
574 /* CMD7 w/rca: Select card to put it in TRAN state */
575 if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_NO_RESP, NULL))
576 return -12;
578 #ifndef BOOTLOADER
579 /* Switch to to 4 bit widebus mode */
580 if(sd_wait_for_tran_state(drive) < 0)
581 return -13;
582 /* CMD55 */ /* Response is requested due to timing issue */
583 if(!send_cmd(drive, SD_APP_CMD, card_info[drive].rca, MCI_RESP, &response))
584 return -14;
585 /* ACMD6 */
586 if(!send_cmd(drive, SD_SET_BUS_WIDTH, 2, MCI_NO_RESP, NULL))
587 return -15;
588 mci_delay();
589 /* CMD55 */ /* Response is requested due to timing issue */
590 if(!send_cmd(drive, SD_APP_CMD, card_info[drive].rca, MCI_RESP, &response))
591 return -16;
592 /* ACMD42 */
593 if(!send_cmd(drive, SD_SET_CLR_CARD_DETECT, 0, MCI_NO_RESP, NULL))
594 return -17;
596 /* Now that card is widebus make controller aware */
597 #if defined(SANSA_FUZEV2) || defined(SANSA_CLIPPLUS)
598 if (amsv2_variant == 1)
599 MCI_CTYPE |= 1<<1;
600 else
601 #endif
602 MCI_CTYPE |= (1<<drive);
604 #endif /* ! BOOTLOADER */
606 /* Set low power mode */
607 #if defined(SANSA_FUZEV2) || defined(SANSA_CLIPPLUS)
608 if (amsv2_variant == 1)
609 MCI_CLKENA |= 1<<16;
610 else
611 #endif
612 MCI_CLKENA |= 1<<(drive + 16);
614 card_info[drive].initialized = 1;
616 return 0;
619 static void sd_thread(void) __attribute__((noreturn));
620 static void sd_thread(void)
622 struct queue_event ev;
623 bool idle_notified = false;
625 while (1)
627 queue_wait_w_tmo(&sd_queue, &ev, HZ);
629 switch ( ev.id )
631 #ifdef HAVE_HOTSWAP
632 case SYS_HOTSWAP_INSERTED:
633 case SYS_HOTSWAP_EXTRACTED:
635 int microsd_init = 1;
636 fat_lock(); /* lock-out FAT activity first -
637 prevent deadlocking via disk_mount that
638 would cause a reverse-order attempt with
639 another thread */
640 mutex_lock(&sd_mtx); /* lock-out card activity - direct calls
641 into driver that bypass the fat cache */
643 /* We now have exclusive control of fat cache and ata */
645 disk_unmount(SD_SLOT_AS3525); /* release "by force", ensure file
646 descriptors aren't leaked and any busy
647 ones are invalid if mounting */
648 /* Force card init for new card, re-init for re-inserted one or
649 * clear if the last attempt to init failed with an error. */
650 card_info[SD_SLOT_AS3525].initialized = 0;
652 if (ev.id == SYS_HOTSWAP_INSERTED)
654 sd_enable(true);
655 microsd_init = sd_init_card(SD_SLOT_AS3525);
656 if (microsd_init < 0) /* initialisation failed */
657 panicf("microSD init failed : %d", microsd_init);
659 microsd_init = disk_mount(SD_SLOT_AS3525); /* 0 if fail */
663 * Mount succeeded, or this was an EXTRACTED event,
664 * in both cases notify the system about the changed filesystems
666 if (microsd_init)
667 queue_broadcast(SYS_FS_CHANGED, 0);
668 /* Access is now safe */
669 mutex_unlock(&sd_mtx);
670 fat_unlock();
671 sd_enable(false);
673 break;
674 #endif
675 case SYS_TIMEOUT:
676 if (TIME_BEFORE(current_tick, last_disk_activity+(3*HZ)))
678 idle_notified = false;
680 else
682 /* never let a timer wrap confuse us */
683 next_yield = current_tick;
685 if (!idle_notified)
687 call_storage_idle_notifys(false);
688 idle_notified = true;
691 break;
693 case SYS_USB_CONNECTED:
694 usb_acknowledge(SYS_USB_CONNECTED_ACK);
695 /* Wait until the USB cable is extracted again */
696 usb_wait_for_disconnect(&sd_queue);
698 break;
699 case SYS_USB_DISCONNECTED:
700 usb_acknowledge(SYS_USB_DISCONNECTED_ACK);
701 break;
706 static void init_controller(void)
708 int hcon_numcards = ((MCI_HCON>>1) & 0x1F) + 1;
709 int card_mask = (1 << hcon_numcards) - 1;
710 int pwr_mask;
712 #if defined(SANSA_FUZEV2) || defined(SANSA_CLIPPLUS)
713 if (amsv2_variant == 1)
714 pwr_mask = 1 << 1;
715 else
716 #endif
717 pwr_mask = card_mask;
719 MCI_PWREN &= ~pwr_mask; /* power off all cards */
720 MCI_PWREN = pwr_mask; /* power up cards */
722 MCI_CTRL |= CTRL_RESET;
723 while(MCI_CTRL & CTRL_RESET)
726 MCI_RAW_STATUS = 0xffffffff; /* Clear all MCI Interrupts */
728 MCI_TMOUT = 0xffffffff; /* data b31:8, response b7:0 */
730 MCI_CTYPE = 0x0; /* all cards 1 bit bus for now */
732 MCI_CLKENA = card_mask; /* Enables card clocks */
734 MCI_ARGUMENT = 0;
735 MCI_COMMAND = CMD_DONE_BIT|CMD_SEND_CLK_ONLY|CMD_WAIT_PRV_DAT_BIT;
736 while(MCI_COMMAND & CMD_DONE_BIT)
739 MCI_DEBNCE = 0xfffff; /* default value */
741 /* Rx watermark = 63(sd reads) Tx watermark = 128 (sd writes) */
742 MCI_FIFOTH = (MCI_FIFOTH & MCI_FIFOTH_MASK) | 0x503f0080;
744 /* RCRC & RTO interrupts should be set together with the CD interrupt but
745 * in practice sometimes incorrectly precede the CD interrupt. If we leave
746 * them masked for now we can check them in the isr by reading raw status when
747 * the CD int is triggered.
749 MCI_MASK |= (MCI_DATA_ERROR | MCI_INT_DTO | MCI_INT_CD);
751 MCI_CTRL |= INT_ENABLE | DMA_ENABLE;
753 MCI_BLKSIZ = SD_BLOCK_SIZE;
756 int sd_init(void)
758 int ret;
760 bitset32(&CGU_PERI, CGU_MCI_CLOCK_ENABLE);
762 CGU_IDE = (1<<7) /* AHB interface enable */
763 | (AS3525_IDE_DIV << 2)
764 | 1; /* clock source = PLLA */
766 CGU_MEMSTICK = (1<<7) /* interface enable */
767 | (AS3525_MS_DIV << 2)
768 | 1; /* clock source = PLLA */
770 CGU_SDSLOT = (1<<7) /* interface enable */
771 | (AS3525_SDSLOT_DIV << 2)
772 | 1; /* clock source = PLLA */
774 wakeup_init(&transfer_completion_signal);
775 wakeup_init(&command_completion_signal);
777 #if defined(SANSA_FUZEV2) || defined(SANSA_CLIPPLUS)
778 if (amsv2_variant == 1)
779 GPIOB_DIR |= 1 << 5;
780 #endif
782 #ifdef HAVE_MULTIDRIVE
783 /* clear previous irq */
784 GPIOA_IC = EXT_SD_BITS;
785 /* enable edge detecting */
786 GPIOA_IS &= ~EXT_SD_BITS;
787 /* detect both raising and falling edges */
788 GPIOA_IBE |= EXT_SD_BITS;
789 /* enable the card detect interrupt */
790 GPIOA_IE |= EXT_SD_BITS;
791 #endif /* HAVE_MULTIDRIVE */
793 #ifndef SANSA_CLIPV2
794 /* Configure XPD for SD-MCI interface */
795 bitset32(&CCU_IO, 1<<2);
796 #endif
798 VIC_INT_ENABLE = INTERRUPT_NAND;
800 init_controller();
801 ret = sd_init_card(INTERNAL_AS3525);
802 if(ret < 0)
803 return ret;
805 /* init mutex */
806 mutex_init(&sd_mtx);
808 queue_init(&sd_queue, true);
809 create_thread(sd_thread, sd_stack, sizeof(sd_stack), 0,
810 sd_thread_name IF_PRIO(, PRIORITY_USER_INTERFACE) IF_COP(, CPU));
812 #ifndef BOOTLOADER
813 sd_enabled = true;
814 sd_enable(false);
815 #endif
816 return 0;
819 static int sd_transfer_sectors(IF_MD2(int drive,) unsigned long start,
820 int count, void* buf, bool write)
822 int ret = 0;
823 #ifndef HAVE_MULTIDRIVE
824 const int drive = 0;
825 #endif
826 bool aligned = !((uintptr_t)buf & (CACHEALIGN_SIZE - 1));
829 mutex_lock(&sd_mtx);
830 #ifndef BOOTLOADER
831 sd_enable(true);
832 led(true);
833 #endif
835 if (card_info[drive].initialized <= 0)
837 ret = sd_init_card(drive);
838 if (!(card_info[drive].initialized))
840 panicf("card not initialised (%d)", ret);
841 goto sd_transfer_error;
845 if(count < 0) /* XXX: why is it signed ? */
847 ret = -18;
848 goto sd_transfer_error;
850 if((start+count) > card_info[drive].numblocks)
852 ret = -19;
853 goto sd_transfer_error;
856 /* skip SanDisk OF */
857 if (drive == INTERNAL_AS3525)
858 start += AMS_OF_SIZE;
860 /* CMD7 w/rca: Select card to put it in TRAN state */
861 if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_NO_RESP, NULL))
862 return -20;
864 last_disk_activity = current_tick;
865 dma_retain();
867 if(aligned)
869 if(write)
870 clean_dcache_range(buf, count * SECTOR_SIZE);
871 else
872 dump_dcache_range(buf, count * SECTOR_SIZE);
875 const int cmd = write ? SD_WRITE_MULTIPLE_BLOCK : SD_READ_MULTIPLE_BLOCK;
879 void *dma_buf;
880 unsigned int transfer = count;
882 if(aligned)
884 dma_buf = AS3525_PHYSICAL_ADDR(buf);
886 else
888 dma_buf = aligned_buffer;
889 if(transfer > UNALIGNED_NUM_SECTORS)
890 transfer = UNALIGNED_NUM_SECTORS;
892 if(write)
893 memcpy(uncached_buffer, buf, transfer * SD_BLOCK_SIZE);
896 /* Interrupt handler might set this to true during transfer */
897 retry = false;
899 MCI_BYTCNT = transfer * SD_BLOCK_SIZE;
901 ret = sd_wait_for_tran_state(drive);
902 if (ret < 0)
904 static const char *st[9] = {
905 "IDLE", "RDY", "IDENT", "STBY", "TRAN", "DATA", "RCV",
906 "PRG", "DIS"};
907 if(ret <= -10)
908 panicf("wait for TRAN state failed (%s) %d",
909 st[(-ret / 10) % 9], drive);
910 else
911 panicf("wait for state failed");
912 goto sd_transfer_error;
915 int arg = start;
916 if(!(card_info[drive].ocr & (1<<30))) /* not SDHC */
917 arg *= SD_BLOCK_SIZE;
919 if(write)
920 dma_enable_channel(0, dma_buf, MCI_FIFO, DMA_PERI_SD,
921 DMAC_FLOWCTRL_PERI_MEM_TO_PERI, true, false, 0, DMA_S8, NULL);
922 else
923 dma_enable_channel(0, MCI_FIFO, dma_buf, DMA_PERI_SD,
924 DMAC_FLOWCTRL_PERI_PERI_TO_MEM, false, true, 0, DMA_S8, NULL);
926 unsigned long dummy; /* if we don't ask for a response, writing fails */
927 if(!send_cmd(drive, cmd, arg, MCI_RESP, &dummy))
928 panicf("%s multiple blocks failed", write ? "write" : "read");
930 wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK);
932 last_disk_activity = current_tick;
934 if(write)
936 /* wait for the card to exit programming state */
937 while(MCI_STATUS & DATA_BUSY) ;
940 if(!send_cmd(drive, SD_STOP_TRANSMISSION, 0, MCI_NO_RESP, NULL))
942 ret = -666;
943 panicf("STOP TRANSMISSION failed");
944 goto sd_transfer_error;
947 if(!retry)
949 if(!write && !aligned)
950 memcpy(buf, uncached_buffer, transfer * SD_BLOCK_SIZE);
951 buf += transfer * SD_BLOCK_SIZE;
952 start += transfer;
953 count -= transfer;
955 else /* reset controller if we had an error */
957 MCI_CTRL |= (FIFO_RESET|DMA_RESET);
958 while(MCI_CTRL & (FIFO_RESET|DMA_RESET))
962 } while(retry || count);
964 dma_release();
966 /* CMD lines are separate, not common, so we need to actively deselect */
967 /* CMD7 w/rca =0 : deselects card & puts it in STBY state */
968 if(!send_cmd(drive, SD_DESELECT_CARD, 0, MCI_NO_RESP, NULL))
969 return -21;
971 #ifndef BOOTLOADER
972 sd_enable(false);
973 led(false);
974 #endif
975 mutex_unlock(&sd_mtx);
976 return 0;
978 sd_transfer_error:
979 panicf("transfer error : %d",ret);
980 card_info[drive].initialized = 0;
981 return ret;
984 int sd_read_sectors(IF_MD2(int drive,) unsigned long start, int count,
985 void* buf)
987 return sd_transfer_sectors(IF_MD2(drive,) start, count, buf, false);
990 int sd_write_sectors(IF_MD2(int drive,) unsigned long start, int count,
991 const void* buf)
993 #if defined(BOOTLOADER) /* we don't need write support in bootloader */
994 #ifdef HAVE_MULTIDRIVE
995 (void) drive;
996 #endif
997 (void) start;
998 (void) count;
999 (void) buf;
1000 return -1;
1001 #else
1002 return sd_transfer_sectors(IF_MD2(drive,) start, count, (void*)buf, true);
1003 #endif /* defined(BOOTLOADER) */
1006 #ifndef BOOTLOADER
1007 long sd_last_disk_activity(void)
1009 return last_disk_activity;
1012 void sd_enable(bool on)
1014 if (on)
1016 bitset32(&CGU_PERI, CGU_MCI_CLOCK_ENABLE);
1017 CGU_IDE |= (1<<7); /* AHB interface enable */
1018 CGU_MEMSTICK |= (1<<7); /* interface enable */
1019 CGU_SDSLOT |= (1<<7); /* interface enable */
1021 else
1023 CGU_SDSLOT &= ~(1<<7); /* interface enable */
1024 CGU_MEMSTICK &= ~(1<<7); /* interface enable */
1025 CGU_IDE &= ~(1<<7); /* AHB interface enable */
1026 bitclr32(&CGU_PERI, CGU_MCI_CLOCK_ENABLE);
1030 tCardInfo *card_get_info_target(int card_no)
1032 return &card_info[card_no];
1034 #endif /* BOOTLOADER */
1036 #ifdef HAVE_HOTSWAP
1037 bool sd_removable(IF_MD_NONVOID(int drive))
1039 return (drive==1);
1042 bool sd_present(IF_MD_NONVOID(int drive))
1044 return (drive == 0) ? true : card_detect_target();
1047 static int sd1_oneshot_callback(struct timeout *tmo)
1049 (void)tmo;
1051 /* This is called only if the state was stable for 300ms - check state
1052 * and post appropriate event. */
1053 if (card_detect_target())
1055 queue_broadcast(SYS_HOTSWAP_INSERTED, 0);
1057 else
1058 queue_broadcast(SYS_HOTSWAP_EXTRACTED, 0);
1060 return 0;
1063 void sd_gpioa_isr(void)
1065 static struct timeout sd1_oneshot;
1066 if (GPIOA_MIS & EXT_SD_BITS)
1067 timeout_register(&sd1_oneshot, sd1_oneshot_callback, (3*HZ/10), 0);
1068 /* acknowledge interrupt */
1069 GPIOA_IC = EXT_SD_BITS;
1071 #endif /* HAVE_HOTSWAP */
1073 #ifdef CONFIG_STORAGE_MULTI
1074 int sd_num_drives(int first_drive)
1076 /* We don't care which logical drive number(s) we have been assigned */
1077 (void)first_drive;
1079 return NUM_DRIVES;
1081 #endif /* CONFIG_STORAGE_MULTI */