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[kugel-rb.git] / firmware / export / mc13783.h
blobe513fa1717ce0a2f4846a3ccba9ae9db41047685
1 /***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (c) 2008 by Michael Sevakis
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
16 *
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
19 *
20 ****************************************************************************/
21 #ifndef _MC13783_H_
22 #define _MC13783_H_
23
24 #include "spi-imx31.h"
25
26 enum mc13783_regs_enum
27 {
28 MC13783_INTERRUPT_STATUS0 = 0,
29 MC13783_INTERRUPT_MASK0 = 1,
30 MC13783_INTERRUPT_SENSE0 = 2,
31 MC13783_INTERRUPT_STATUS1 = 3,
32 MC13783_INTERRUPT_MASK1 = 4,
33 MC13783_INTERRUPT_SENSE1 = 5,
34 MC13783_POWER_UP_MODE_SENSE = 6,
35 MC13783_IDENTIFICATION = 7,
36 MC13783_SEMAPHORE = 8,
37 MC13783_ARBITRATION_PERIPHERAL_AUDIO = 9,
38 MC13783_ARBITRATION_SWITCHERS = 10,
39 MC13783_ARBITRATION_REGULATORS0 = 11,
40 MC13783_ARBITRATION_REGULATORS1 = 12,
41 MC13783_POWER_CONTROL0 = 13,
42 MC13783_POWER_CONTROL1 = 14,
43 MC13783_POWER_CONTROL2 = 15,
44 MC13783_REGEN_ASSIGNMENT = 16,
45 MC13783_CONTROL_SPARE = 17, /* x */
46 MC13783_MEMORYA = 18,
47 MC13783_MEMORYB = 19,
48 MC13783_RTC_TIME = 20,
49 MC13783_RTC_ALARM = 21,
50 MC13783_RTC_DAY = 22,
51 MC13783_RTC_DAY_ALARM = 23,
52 MC13783_SWITCHERS0 = 24,
53 MC13783_SWITCHERS1 = 25,
54 MC13783_SWITCHERS2 = 26,
55 MC13783_SWITCHERS3 = 27,
56 MC13783_SWITCHERS4 = 28,
57 MC13783_SWITCHERS5 = 29,
58 MC13783_REGULATOR_SETTING0 = 30,
59 MC13783_REGULATOR_SETTING1 = 31,
60 MC13783_REGULATOR_MODE0 = 32,
61 MC13783_REGULATOR_MODE1 = 33,
62 MC13783_POWER_MISCELLANEOUS = 34,
63 MC13783_POWER_SPARE = 35, /* x */
64 MC13783_AUDIO_RX0 = 36,
65 MC13783_AUDIO_RX1 = 37,
66 MC13783_AUDIO_TX = 38,
67 MC13783_SSI_NETWORK = 39,
68 MC13783_AUDIO_CODEC = 40,
69 MC13783_AUDIO_STEREO_DAC = 41,
70 MC13783_AUDIO_SPARE = 42, /* x */
71 MC13783_ADC0 = 43,
72 MC13783_ADC1 = 44,
73 MC13783_ADC2 = 45,
74 MC13783_ADC3 = 46,
75 MC13783_ADC4 = 47,
76 MC13783_CHARGER = 48,
77 MC13783_USB0 = 49,
78 MC13783_CHARGER_USB1 = 50,
79 MC13783_LED_CONTROL0 = 51,
80 MC13783_LED_CONTROL1 = 52,
81 MC13783_LED_CONTROL2 = 53,
82 MC13783_LED_CONTROL3 = 54,
83 MC13783_LED_CONTROL4 = 55,
84 MC13783_LED_CONTROL5 = 56,
85 MC13783_SPARE = 57, /* x */
86 MC13783_TRIM0 = 58, /* x */
87 MC13783_TRIM1 = 59, /* x */
88 MC13783_TEST0 = 60, /* x */
89 MC13783_TEST1 = 61, /* x */
90 MC13783_TEST2 = 62, /* x */
91 MC13783_TEST3 = 63, /* x */
92 MC13783_NUM_REGS = 64,
93 };
94 /* x = unused/reserved/not implemented */
95
96 /* INTERRUPT_STATUS0 (0) */
97 #define MC13783_ADCDONEI (0x1 << 0)
98 #define MC13783_ADCBISDONEI (0x1 << 1)
99 #define MC13783_TSI (0x1 << 2)
100 #define MC13783_WHIGHI (0x1 << 3)
101 #define MC13783_WLOWI (0x1 << 4)
102 #define MC13783_CHGDETI (0x1 << 6)
103 #define MC13783_CHGOVI (0x1 << 7)
104 #define MC13783_CHGREVI (0x1 << 8)
105 #define MC13783_CHGSHORTI (0x1 << 9)
106 #define MC13783_CCCVI (0x1 << 10)
107 #define MC13783_CHGCURRI (0x1 << 11)
108 #define MC13783_BPONII (0x1 << 12)
109 #define MC13783_LOBATLI (0x1 << 13)
110 #define MC13783_LOBATHI (0x1 << 14)
111 #define MC13783_UDPI (0x1 << 15)
112 #define MC13783_USBI (0x1 << 16)
113 #define MC13783_IDFLOATI (0x1 << 19)
114 #define MC13783_SE1I (0x1 << 21)
115 #define MC13783_CKDETI (0x1 << 22)
116 #define MC13783_UDMI (0x1 << 23)
117
118 /* INTERRUPT_MASK0 (1) */
119 #define MC13783_ADCDONEM (0x1 << 0)
120 #define MC13783_ADCBISDONEM (0x1 << 1)
121 #define MC13783_TSM (0x1 << 2)
122 #define MC13783_WHIGHM (0x1 << 3)
123 #define MC13783_WLOWM (0x1 << 4)
124 #define MC13783_CHGDETM (0x1 << 6)
125 #define MC13783_CHGOVM (0x1 << 7)
126 #define MC13783_CHGREVM (0x1 << 8)
127 #define MC13783_CHGSHORTM (0x1 << 9)
128 #define MC13783_CCCVM (0x1 << 10)
129 #define MC13783_CHGCURRM (0x1 << 11)
130 #define MC13783_BPONIM (0x1 << 12)
131 #define MC13783_LOBATLM (0x1 << 13)
132 #define MC13783_LOBATHM (0x1 << 14)
133 #define MC13783_UDPM (0x1 << 15)
134 #define MC13783_USBM (0x1 << 16)
135 #define MC13783_IDFLOATM (0x1 << 19)
136 #define MC13783_SE1M (0x1 << 21)
137 #define MC13783_CKDETM (0x1 << 22)
138 #define MC13783_UDMM (0x1 << 23)
139
140 /* INTERRUPT_SENSE0 (2) */
141 #define MC13783_CHGDETS (0x1 << 6)
142 #define MC13783_CHGOVS (0x1 << 7)
143 #define MC13783_CHGREVS (0x1 << 8)
144 #define MC13783_CHGSHORTS (0x1 << 9)
145 #define MC13783_CCCVS (0x1 << 10)
146 #define MC13783_CHGCURRS (0x1 << 11)
147 #define MC13783_BPONIS (0x1 << 12)
148 #define MC13783_LOBATLS (0x1 << 13)
149 #define MC13783_LOBATHS (0x1 << 14)
150 #define MC13783_UDPS (0x1 << 15)
151 #define MC13783_USB4V4S (0x1 << 16)
152 #define MC13783_USB2V0S (0x1 << 17)
153 #define MC13783_USB0V8S (0x1 << 18)
154 #define MC13783_IDFLOATS (0x1 << 19)
155 #define MC13783_SE1S (0x1 << 21)
156 #define MC13783_CKDETS (0x1 << 22)
157 #define MC13783_UDMS (0x1 << 23)
158
159 /* INTERRUPT_STATUS1 (3) */
160 #define MC13783_1HZI (0x1 << 0)
161 #define MC13783_TODAI (0x1 << 1)
162 #define MC13783_ONOFD1I (0x1 << 3) /* ON1B */
163 #define MC13783_ONOFD2I (0x1 << 4) /* ON2B */
164 #define MC13783_ONOFD3I (0x1 << 5) /* ON3B */
165 #define MC13783_SYSRSTI (0x1 << 6)
166 #define MC13783_RTCRSTI (0x1 << 7)
167 #define MC13783_PCII (0x1 << 8)
168 #define MC13783_WARMI (0x1 << 9)
169 #define MC13783_MEMHLDI (0x1 << 10)
170 #define MC13783_PWRRDYI (0x1 << 11)
171 #define MC13783_THWARNLI (0x1 << 12)
172 #define MC13783_THWARNHI (0x1 << 13)
173 #define MC13783_CLKI (0x1 << 14)
174 #define MC13783_SEMAFI (0x1 << 15)
175 #define MC13783_MC2BI (0x1 << 17)
176 #define MC13783_HSDETI (0x1 << 18)
177 #define MC13783_HSLI (0x1 << 19)
178 #define MC13783_ALSPTHI (0x1 << 20)
179 #define MC13783_AHSSHORTI (0x1 << 21)
180
181 /* INTERRUPT_MASK1 (4) */
182 #define MC13783_1HZM (0x1 << 0)
183 #define MC13783_TODAM (0x1 << 1)
184 #define MC13783_ONOFD1M (0x1 << 3) /* ON1B */
185 #define MC13783_ONOFD2M (0x1 << 4) /* ON2B */
186 #define MC13783_ONOFD3M (0x1 << 5) /* ON3B */
187 #define MC13783_SYSRSTM (0x1 << 6)
188 #define MC13783_RTCRSTM (0x1 << 7)
189 #define MC13783_PCIM (0x1 << 8)
190 #define MC13783_WARMM (0x1 << 9)
191 #define MC13783_MEMHLDM (0x1 << 10)
192 #define MC13783_PWRRDYM (0x1 << 11)
193 #define MC13783_THWARNLM (0x1 << 12)
194 #define MC13783_THWARNHM (0x1 << 13)
195 #define MC13783_CLKM (0x1 << 14)
196 #define MC13783_SEMAFM (0x1 << 15)
197 #define MC13783_MC2BM (0x1 << 17)
198 #define MC13783_HSDETM (0x1 << 18)
199 #define MC13783_HSLM (0x1 << 19)
200 #define MC13783_ALSPTHM (0x1 << 20)
201 #define MC13783_AHSSHORTM (0x1 << 21)
202
203 /* INTERRUPT_SENSE1 (5) */
204 #define MC13783_ONOFD1S (0x1 << 3) /* ON1B */
205 #define MC13783_ONOFD2S (0x1 << 4) /* ON2B */
206 #define MC13783_ONOFD3S (0x1 << 5) /* ON3B */
207 #define MC13783_PWRRDYS (0x1 << 11)
208 #define MC13783_THWARNLS (0x1 << 12)
209 #define MC13783_THWARNHS (0x1 << 13)
210 #define MC13783_CLKS (0x1 << 14)
211 #define MC13783_MC2BS (0x1 << 17)
212 #define MC13783_HSDETS (0x1 << 18)
213 #define MC13783_HSLS (0x1 << 19)
214 #define MC13783_ALSPTHS (0x1 << 20)
215 #define MC13783_AHSSHORTS (0x1 << 21)
216
217 /* POWER_UP_MODE_SENSE (6) */
218 #define MC13783_ICTESTS (0x1 << 0)
219 #define MC13783_CLKSELS (0x1 << 1)
220 #define MC13783_PUMS1S (0x3 << 2)
221 #define MC13783_PUMS1S_LOW (0x0 << 2)
222 #define MC13783_PUMS1S_OPEN (0x1 << 2)
223 #define MC13783_PUMS1S_HIGH (0x2 << 2)
224 #define MC13783_PUMS2S (0x3 << 4)
225 #define MC13783_PUMS2S_LOW (0x0 << 4)
226 #define MC13783_PUMS2S_OPEN (0x1 << 4)
227 #define MC13783_PUMS2S_HIGH (0x2 << 4)
228 #define MC13783_PUMS3S (0x3 << 6)
229 #define MC13783_PUMS3S_LOW (0x0 << 6)
230 #define MC13783_PUMS3S_OPEN (0x1 << 6)
231 #define MC13783_PUMS3S_HIGH (0x2 << 6)
232 #define MC13783_CHRGMOD0S (0x3 << 8)
233 #define MC13783_CHRGMOD0S_LOW (0x0 << 8)
234 #define MC13783_CHRGMOD0S_OPEN (0x1 << 8)
235 #define MC13783_CHRGMOD0S_HIGH (0x3 << 8)
236 #define MC13783_CHRGMOD1S (0x3 << 10)
237 #define MC13783_CHRGMOD1S_LOW (0x0 << 10)
238 #define MC13783_CHRGMOD1S_OPEN (0x1 << 10)
239 #define MC13783_CHRGMOD1S_HIGH (0x3 << 10)
240 #define MC13783_UMODS (0x3 << 12)
241 #define MC13783_UMODS_LOW_UMODS1_LOW (0x0 << 12)
242 #define MC13783_UMODS_OPEN_UMODS1_LOW (0x1 << 12)
243 #define MC13783_UMODS_DONTCARE_UMODS1_HIGH (0x2 << 12)
244 #define MC13783_UMODS_HIGH_UMODS1_LOW (0x3 << 12)
245 #define MC13783_USBENS (0x1 << 14)
246 #define MC13783_SW1ABS (0x1 << 15)
247 #define MC13783_SW2ABS (0x1 << 16)
248
249 /* IDENTIFICATION (7) */
250 #define MC13783_REVISION (0x1f << 0)
251 #define MC13783_REVISION_POS (0)
252 #define MC13783_ICID (0x7 << 6)
253 #define MC13783_ICID_POS (6)
254 #define MC13783_FIN (0x3 << 9)
255 #define MC13783_FIN_POS (9)
256 #define MC13783_FAB (0x3 << 12)
257 #define MC13783_FAB_POS (12)
258
259 /* SEMAPHORE (8) */
260 #define MC13783_SEMCTRLA (0x1 << 0)
261 #define MC13783_SEMCTRLB (0x1 << 2)
262 #define MC13783_SEMWRTA (0xf << 4)
263 #define MC13783_SEMWRTA_POS (4)
264 #define MC13783_SEMWRTB (0x3f << 8)
265 #define MC13783_SEMWRTB_POS (8)
266 #define MC13783_SEMRDA (0xf << 14)
267 #define MC13783_SEMRDA_POS (14)
268 #define MC13783_SEMRDB (0x3f << 18)
269 #define MC13783_SEMRDB_POS (18)
270
271 /* ARBITRATION_PERIPHERAL_AUDIO (9) */
272 #define MC13783_AUDIOTXSEL (0x3 << 0)
273 #define MC13783_AUDIOTXSEL_PRI_SPI (0x0 << 0)
274 #define MC13783_AUDIOTXSEL_SEC_SPI (0x1 << 0)
275 #define MC13783_AUDIOTXSEL_OR_SPI (0x2 << 0)
276 #define MC13783_AUDIOTXSEL_AND_SPI (0x3 << 0)
277 #define MC13783_TXGAINSEL (0x1 << 2)
278 #define MC13783_AUDIORXSEL (0x3 << 3)
279 #define MC13783_AUDIORXSEL_PRI_SPI (0x0 << 3)
280 #define MC13783_AUDIORXSEL_SEC_SPI (0x1 << 3)
281 #define MC13783_AUDIORXSEL_OR_SPI (0x2 << 3)
282 #define MC13783_AUDIORXSEL_AND_SPI (0x3 << 3)
283 #define MC13783_RXGAINSEL (0x1 << 5)
284 #define MC13783_AUDIOCDCSEL (0x1 << 6)
285 #define MC13783_AUDIOSTDCSEL (0x1 << 7)
286 #define MC13783_BIASSEL (0x3 << 8)
287 #define MC13783_BIASSEL_PRI_SPI (0x0 << 8)
288 #define MC13783_BIASSEL_SEC_SPI (0x1 << 8)
289 #define MC13783_BIASSEL_OR_SPI (0x2 << 8)
290 #define MC13783_BIASSEL_AND_SPI (0x3 << 8)
291 #define MC13783_RTCSEL (0x1 << 11)
292 #define MC13783_ADCSEL (0x3 << 12)
293 #define MC13783_ADCSEL_PRI1_SEC1 (0x0 << 12)
294 #define MC13783_ADCSEL_PRI2_SEC0 (0x1 << 12)
295 #define MC13783_ADCSEL_PRI0_SEC2 (0x2 << 12)
296 /* 0x3 = same as 0x0 */
297 #define MC13783_USBSEL (0x1 << 14)
298 #define MC13783_CHRGSEL (0x1 << 15)
299 #define MC13783_BLLEDSEL (0x1 << 16)
300 #define MC13783_TCLEDSEL (0x1 << 17)
301 #define MC13783_ADAPTSEL (0x1 << 18)
302
303 /* ARBITRATION_SWITCHERS (10) */
304 #define MC13783_SW1ASTBYAND (0x1 << 0)
305 #define MC13783_SW1BSTBYAND (0x1 << 1)
306 #define MC13783_SW2ASTBYAND (0x1 << 2)
307 #define MC13783_SW2BSTBYAND (0x1 << 3)
308 #define MC13783_SW3SEL0 (0x1 << 4)
309 #define MC13783_SW1ABDVS (0x1 << 5)
310 #define MC13783_SW2ABDVS (0x1 << 6)
311 #define MC13783_SW1ASEL (0x1 << 7)
312 #define MC13783_SW1BSEL (0x1 << 8)
313 #define MC13783_SW2ASEL (0x1 << 9)
314 #define MC13783_SW2BSEL (0x1 << 10)
315 #define MC13783_PLLSEL (0x1 << 12)
316 #define MC13783_PWGT1SEL (0x1 << 14)
317 #define MC13783_PWGT2SEL (0x1 << 15)
318
319 /* ARBITRATION_REGULATORS0 (11) */
320 #define MC13783_VAUDIOSEL (0x3 << 0)
321 #define MC13783_VAUDIOSEL_PRI (0x0 << 0)
322 #define MC13783_VIOHISEL (0x3 << 2)
323 #define MC13783_VIOHISEL_PRI (0x0 << 2)
324 #define MC13783_VIOLOSEL (0x3 << 4)
325 #define MC13783_VIOLOSEL_PRI (0x0 << 4)
326 #define MC13783_VDIGSEL (0x3 << 6)
327 #define MC13783_VDIGSEL_PRI (0x0 << 6)
328 #define MC13783_VGENSEL (0x3 << 8)
329 #define MC13783_VGENSEL_PRI (0x0 << 8)
330 #define MC13783_VRFDIGSEL (0x3 << 10)
331 #define MC13783_VRFDIGSEL_PRI (0x0 << 10)
332 #define MC13783_VRFREFSEL (0x3 << 12)
333 #define MC13783_VRFREFSEL_PRI (0x0 << 12)
334 #define MC13783_VRFCPSEL (0x3 << 14)
335 #define MC13783_VRFCPSEL_PRI (0x0 << 14)
336 #define MC13783_VSIMSEL (0x3 << 16)
337 #define MC13783_VSIMSEL_PRI (0x0 << 16)
338 #define MC13783_VESIMSEL (0x3 << 18)
339 #define MC13783_VESIMSEL_PRI (0x0 << 18)
340 #define MC13783_VCAMSEL (0x3 << 20)
341 #define MC13783_VCAMSEL_PRI (0x0 << 20)
342 #define MC13783_VRFBGSEL (0x3 << 22)
343 #define MC13783_VRFBGSEL_PRI (0x0 << 22)
344
345 /* ARBITRATION_REGULATORS1 (12) */
346 #define MC13783_VVIBSEL (0x3 << 0)
347 #define MC13783_VVIBSEL_PRI (0x0 << 0)
348 #define MC13783_VRF1SEL (0x3 << 2)
349 #define MC13783_VRF1SEL_PRI (0x0 << 2)
350 #define MC13783_VRF2SEL (0x3 << 4)
351 #define MC13783_VRF2SEL_PRI (0x0 << 4)
352 #define MC13783_VMMC1SEL (0x3 << 6)
353 #define MC13783_VMMC1SEL_PRI (0x0 << 6)
354 #define MC13783_VMMC2SEL (0x3 << 8)
355 #define MC13783_VMMC2SEL_PRI (0x0 << 8)
356 #define MC13783_GPO1SEL (0x3 << 14)
357 #define MC13783_GPO1SEL_PRI (0x0 << 14)
358 #define MC13783_GPO1SEL_BOTH (0x1 << 14)
359 #define MC13783_GPO1SEL_AND (0x3 << 14)
360 #define MC13783_GPO2SEL (0x3 << 16)
361 #define MC13783_GPO2SEL_PRI (0x0 << 16)
362 #define MC13783_GPO2SEL_BOTH (0x1 << 16)
363 #define MC13783_GPO2SEL_AND (0x3 << 16)
364 #define MC13783_GPO3SEL (0x3 << 18)
365 #define MC13783_GPO3SEL_PRI (0x0 << 18)
366 #define MC13783_GPO3SEL_BOTH (0x1 << 18)
367 #define MC13783_GPO3SEL_AND (0x3 << 18)
368 #define MC13783_GPO4SEL (0x3 << 20)
369 #define MC13783_GPO4SEL_PRI (0x0 << 20)
370 #define MC13783_GPO4SEL_BOTH (0x1 << 20)
371 #define MC13783_GPO4SEL_AND (0x3 << 20)
372
373 /* POWER_CONTROL0 (13) */
374 #define MC13783_PCEN (0x1 << 0)
375 #define MC13783_PCCOUNTEN (0x1 << 1)
376 #define MC13783_WARMEN (0x1 << 2)
377 #define MC13783_USEROFFSPI (0x1 << 3)
378 #define MC13783_USEROFFPC (0x1 << 4)
379 #define MC13783_USEROFFCLK (0x1 << 5)
380 #define MC13783_CLK32KMCUEN (0x1 << 6)
381 #define MC13783_VBKUP2AUTOMH (0x1 << 7)
382 #define MC13783_VBKUP1EN (0x1 << 8)
383 #define MC13783_VBKUPAUTO (0x1 << 9)
384 #define MC13783_VBKUP1 (0x3 << 10)
385 #define MC13783_VBKUP1_1_0V (0x0 << 10)
386 #define MC13783_VBKUP1_1_2V (0x1 << 10)
387 #define MC13783_VBKUP1_1_575V (0x2 << 10)
388 #define MC13783_VBKUP1_1_8V (0x3 << 10)
389 #define MC13783_VBKUP2EN (0x1 << 12)
390 #define MC13783_VBKUP2AUTO (0x1 << 13)
391 #define MC13783_VBKUP2 (0x3 << 14)
392 #define MC13783_VBKUP2_1_0V (0x0 << 14)
393 #define MC13783_VBKUP2_1_2V (0x1 << 14)
394 #define MC13783_VBKUP2_1_5V (0x2 << 14)
395 #define MC13783_VBKUP2_1_8V (0x3 << 14)
396 #define MC13783_BPDET (0x3 << 16)
397 /* 00: UVDET 2.6, LOBATL UVDET+0.2, LOBATH UVDET+0.4 BPON 3.2 */
398 #define MC13783_BPDET_2_4 (0x0 << 16)
399 /* 01: UVDET 2.6, LOBATL UVDET+0.3, LOBATH UVDET+0.5 BPON 3.2 */
400 #define MC13783_BPDET_3_5 (0x1 << 16)
401 /* 10: UVDET 2.6, LOBATL UVDET+0.4, LOBATH UVDET+0.7 BPON 3.2 */
402 #define MC13783_BPDET_4_7 (0x2 << 16)
403 /* 11: UVDET 2.6, LOBATL UVDET+0.5, LOBATH UVDET+0.8 BPON 3.2 */
404 #define MC13783_BPDET_5_8 (0x3 << 16)
405 #define MC13783_EOLSEL (0x1 << 18)
406 #define MC13783_BATTDETEN (0x1 << 19)
407 #define MC13783_VCOIN (0x7 << 20)
408 #define MC13783_VCOIN_2_50V (0x0 << 20)
409 #define MC13783_VCOIN_2_70V (0x1 << 20)
410 #define MC13783_VCOIN_2_80V (0x2 << 20)
411 #define MC13783_VCOIN_2_90V (0x3 << 20)
412 #define MC13783_VCOIN_3_00V (0x4 << 20)
413 #define MC13783_VCOIN_3_10V (0x5 << 20)
414 #define MC13783_VCOIN_3_20V (0x6 << 20)
415 #define MC13783_VCOIN_3_30V (0x7 << 20)
416 #define MC13783_COINCHEN (0x1 << 23)
417
418 /* POWER_CONTROL1 (14) */
419 /* Up to 8 seconds */
420 #define MC13783_PCT (0xff << 0)
421 #define MC13783_PCT_POS (0)
422 #define MC13783_PCCOUNT (0xf << 8)
423 #define MC13783_PCCOUNT_POS (8)
424 #define MC13783_PCMAXCNT (0xf << 12)
425 #define MC13783_PCMAXCNT_POS (12)
426 /* Up to 8 minutes with MEMALLON=0, <> 0 + MEMALLON=1: infinite */
427 #define MC13783_MEMTMR (0xf << 16)
428 #define MC13783_MEMTMR_POS (16)
429 #define MC13783_MEMALLON (0x1 << 20)
430
431 /* POWER_CONTROL2 (15) */
432 #define MC13783_RESTARTEN (0x1 << 0)
433 #define MC13783_ON1BRSTEN (0x1 << 1)
434 #define MC13783_ON2BRSTEN (0x1 << 2)
435 #define MC13783_ON3BTSTEN (0x1 << 3)
436 #define MC13783_ON1BDBNC (0x3 << 4)
437 #define MC13783_ON1BDBNC_0MS (0x0 << 4)
438 #define MC13783_ON1BDBNC_30MS (0x1 << 4)
439 #define MC13783_ON1BDBNC_150MS (0x2 << 4)
440 #define MC13783_ON1BDBNC_750MS (0x3 << 4)
441 #define MC13783_ON2BDBNC (0x3 << 6)
442 #define MC13783_ON2BDBNC_0MS (0x0 << 6)
443 #define MC13783_ON2BDBNC_30MS (0x1 << 6)
444 #define MC13783_ON2BDBNC_150MS (0x2 << 6)
445 #define MC13783_ON2BDBNC_750MS (0x3 << 6)
446 #define MC13783_ON3BDBNC (0x3 << 8)
447 #define MC13783_ON3BDBNC_0MS (0x0 << 8)
448 #define MC13783_ON3BDBNC_30MS (0x1 << 8)
449 #define MC13783_ON3BDBNC_150MS (0x2 << 8)
450 #define MC13783_ON3BDBNC_750MS (0x3 << 8)
451 #define MC13783_STANDBYPRIINV (0x1 << 10)
452 #define MC13783_STANDBYSECINV (0x1 << 11)
453
454 /* REGEN_ASSIGNMENT (16) */
455 #define MC13783_VAUDIOREGEN (0x1 << 0)
456 #define MC13783_VIOHIREGEN (0x1 << 1)
457 #define MC13783_VIOLOREGEN (0x1 << 2)
458 #define MC13783_VDIGREGEN (0x1 << 3)
459 #define MC13783_VGENREGEN (0x1 << 4)
460 #define MC13783_VRFDIGREGEN (0x1 << 5)
461 #define MC13783_VRFREFREGEN (0x1 << 6)
462 #define MC13783_VRFCPREGEN (0x1 << 7)
463 #define MC13783_VCAMREGEN (0x1 << 8)
464 #define MC13783_VRFBGREGEN (0x1 << 9)
465 #define MC13783_VRF1REGEN (0x1 << 10)
466 #define MC13783_VRF2REGEN (0x1 << 11)
467 #define MC13783_VMMC1REGEN (0x1 << 12)
468 #define MC13783_VMMC2REGEN (0x1 << 13)
469 #define MC13783_GPO1REGEN (0x1 << 16)
470 #define MC13783_GPO2REGEN (0x1 << 17)
471 #define MC13783_GPO3REGEN (0x1 << 18)
472 #define MC13783_GPO4REGEN (0x1 << 19)
473 #define MC13783_REGENINV (0x1 << 20)
474 #define MC13783_VESIMESIMEN (0x1 << 21)
475 #define MC13783_VMMC1ESIMEN (0x1 << 22)
476 #define MC13783_VMMC2ESIMEN (0x1 << 23)
477
478 /* MEMORYA (18) */
479 #define MC13783_MEMORYA_MASK (0xffffff)
480
481 /* MEMORYB (19) */
482 #define MC13783_MEMORYB_MASK (0xffffff)
483
484 /* RTC_TIME (20) */
485 #define MC13783_RTC_TIME_MASK (0x1ffff)
486
487 /* RTC_ALARM (21) */
488 #define MC13783_RTC_ALARM_MASK (0x1ffff)
489
490 /* RTC_DAY (22) */
491 #define MC13783_RTC_DAY_MASK (0x7fff)
492
493 /* RTC_DAY_ALARM (23) */
494 #define MC13783_RTC_DAY_ALARM_MASK (0x7fff)
495
496 /* SWITCHERS0 (24) */
497 #define MC13783_SW1A (0x3f << 0)
498 #define MC13783_SW1A_POS (0)
499 #define MC13783_SW1ADVS (0x3f << 6)
500 #define MC13783_SW1ADVS_POS (6)
501 #define MC13783_SW1ASTBY (0x3f << 12)
502 #define MC13783_SW1ASTBY_POS (12)
503
504 /* SWITCHERS1 (25) */
505 #define MC13783_SW1B (0x3f << 0)
506 #define MC13783_SW1B_POS (0)
507 #define MC13783_SW1BDVS (0x3f << 6)
508 #define MC13783_SW1BDVS_POS (6)
509 #define MC13783_SW1BSTBY (0x3f << 12)
510 #define MC13783_SW1BSTBY_POS (12)
511
512 /* SWITCHERS2 (26) */
513 #define MC13783_SW2A (0x3f << 0)
514 #define MC13783_SW2A_POS (0)
515 #define MC13783_SW2ADVS (0x3f << 6)
516 #define MC13783_SW2ADVS_POS (6)
517 #define MC13783_SW2ASTBY (0x3f << 12)
518 #define MC13783_SW2ASTBY_POS (12)
519
520 /* SWITCHERS3 (27) */
521 #define MC13783_SW2B (0x3f << 0)
522 #define MC13783_SW2B_POS (0)
523 #define MC13783_SW2BDVS (0x3f << 6)
524 #define MC13783_SW2BDVS_POS (6)
525 #define MC13783_SW2BSTBY (0x3f << 12)
526 #define MC13783_SW2BSTBY_POS (12)
527
528 /* Switcher Voltages (SWITCHERS0-SWITCHERS3) */
529 /* Switcher 1 and 2 */
530 #define MC13783_SW_0_900 0x00 /* 0.900 V */
531 #define MC13783_SW_0_925 0x01 /* 0.925 V */
532 #define MC13783_SW_0_950 0x02 /* 0.950 V */
533 #define MC13783_SW_0_975 0x03 /* 0.975 V */
534 #define MC13783_SW_1_000 0x04 /* 1.000 V */
535 #define MC13783_SW_1_025 0x05 /* 1.025 V */
536 #define MC13783_SW_1_050 0x06 /* 1.050 V */
537 #define MC13783_SW_1_075 0x07 /* 1.075 V */
538 #define MC13783_SW_1_100 0x08 /* 1.100 V */
539 #define MC13783_SW_1_125 0x09 /* 1.125 V */
540 #define MC13783_SW_1_150 0x0a /* 1.150 V */
541 #define MC13783_SW_1_175 0x0b /* 1.175 V */
542 #define MC13783_SW_1_200 0x0c /* 1.200 V */
543 #define MC13783_SW_1_225 0x0d /* 1.225 V */
544 #define MC13783_SW_1_250 0x0e /* 1.250 V */
545 #define MC13783_SW_1_275 0x0f /* 1.275 V */
546 #define MC13783_SW_1_300 0x10 /* 1.300 V */
547 #define MC13783_SW_1_325 0x11 /* 1.325 V */
548 #define MC13783_SW_1_350 0x12 /* 1.350 V */
549 #define MC13783_SW_1_375 0x13 /* 1.375 V */
550 #define MC13783_SW_1_400 0x14 /* 1.400 V */
551 #define MC13783_SW_1_425 0x15 /* 1.425 V */
552 #define MC13783_SW_1_450 0x16 /* 1.450 V */
553 #define MC13783_SW_1_475 0x17 /* 1.475 V */
554 #define MC13783_SW_1_500 0x18 /* 1.500 V */
555 #define MC13783_SW_1_525 0x19 /* 1.525 V */
556 #define MC13783_SW_1_550 0x1a /* 1.550 V */
557 #define MC13783_SW_1_575 0x1b /* 1.575 V */
558 #define MC13783_SW_1_600 0x1c /* 1.600 V */
559 #define MC13783_SW_1_625 0x1d /* 1.625 V */
560 #define MC13783_SW_1_650 0x1e /* 1.650 V */
561 #define MC13783_SW_1_675 0x1f /* 1.675 V */
562 #define MC13783_SW_1_700 0x20 /* 0x20 - 0x23 = 1.700V */
563 #define MC13783_SW_1_800 0x24 /* 0x24 - 0x27 = 1.800V */
564 /* Switcher 1 */
565 #define MC13783_SW1_1_850 0x28 /* 0x29 - 0x2b = 1.850V */
566 /* Switcher 2 */
567 #define MC13783_SW2_1_900 0x28 /* 0x29 - 0x2b = 1.900V */
568 /* Switcher 1 and 2 */
569 #define MC13783_SW_2_000 0x2c /* 0x2c - 0x2f = 2.000V */
570 #define MC13783_SW_2_100 0x30 /* 0x30 - 0x33 = 2.100V */
571 #define MC13783_SW_2_200 0x34 /* 0x34 - 0x3f = 2.200V */
572
573
574 /* SWITCHERS4 (28) */
575 #define MC13783_SW1AMODE (0x3 << 0)
576 #define MC13783_SW1AMODE_OFF (0x0 << 0)
577 #define MC13783_SW1AMODE_PWM (0x1 << 0)
578 #define MC13783_SW1AMODE_PWM_SKIP (0x2 << 0)
579 #define MC13783_SW1AMODE_PFM (0x3 << 0)
580 #define MC13783_SW1ASTBYMODE (0x3 << 2)
581 #define MC13783_SW1ASTBYMODE_OFF (0x0 << 2)
582 #define MC13783_SW1ASTBYMODE_PWM (0x1 << 2)
583 #define MC13783_SW1ASTBYMODE_PWM_SKIP (0x2 << 2)
584 #define MC13783_SW1ASTBYMODE_PFM (0x3 << 2)
585 #define MC13783_SW1ADVSSPEED (0x3 << 6)
586 /* 25mV every ... */
587 #define MC13783_SW1ADVSSPEED_4US_NO_PWR_RDY (0x0 << 6)
588 #define MC13783_SW1ADVSSPEED_4US (0x1 << 6)
589 #define MC13783_SW1ADVSSPEED_8US (0x2 << 6)
590 #define MC13783_SW1ADVSSPEED_16US (0x3 << 6)
591 #define MC13783_SW1APANIC (0x1 << 8)
592 #define MC13783_SW1ASFST (0x1 << 9)
593 #define MC13783_SW1BMODE (0x3 << 10)
594 #define MC13783_SW1BMODE_OFF (0x0 << 10)
595 #define MC13783_SW1BMODE_PWM (0x1 << 10)
596 #define MC13783_SW1BMODE_PWM_SKIP (0x2 << 10)
597 #define MC13783_SW1BMODE_PFM (0x3 << 10)
598 #define MC13783_SW1BSTBYMODE (0x3 << 12)
599 #define MC13783_SW1BSTBYMODE_OFF (0x0 << 12)
600 #define MC13783_SW1BSTBYMODE_PWM (0x1 << 12)
601 #define MC13783_SW1BSTBYMODE_PWM_SKIP (0x2 << 12)
602 #define MC13783_SW1BSTBYMODE_PFM (0x3 << 12)
603 #define MC13783_SW1BDVSSPEED (0x3 << 14)
604 /* 25mV every ... */
605 #define MC13783_SW1BDVSSPEED_4US_NO_PWR_RDY (0x0 << 14)
606 #define MC13783_SW1BDVSSPEED_4US (0x1 << 14)
607 #define MC13783_SW1BDVSSPEED_8US (0x2 << 14)
608 #define MC13783_SW1BDVSSPEED_16US (0x3 << 14)
609 #define MC13783_SW1BPANIC (0x1 << 16)
610 #define MC13783_SW1BSFST (0x1 << 17)
611 #define MC13783_PLLEN (0x1 << 18)
612 #define MC13783_PLLX (0x7 << 19)
613 #define MC13783_PLLX_28 (0x0 << 19)
614 #define MC13783_PLLX_29 (0x1 << 19)
615 #define MC13783_PLLX_30 (0x2 << 19)
616 #define MC13783_PLLX_31 (0x3 << 19)
617 #define MC13783_PLLX_32 (0x4 << 19)
618 #define MC13783_PLLX_33 (0x5 << 19)
619 #define MC13783_PLLX_34 (0x6 << 19)
620 #define MC13783_PLLX_35 (0x7 << 19)
621
622 /* SWITCHERS5 (29) */
623 #define MC13783_SW2AMODE (0x3 << 0)
624 #define MC13783_SW2AMODE_OFF (0x0 << 0)
625 #define MC13783_SW2AMODE_PWM (0x1 << 0)
626 #define MC13783_SW2AMODE_PWM_SKIP (0x2 << 0)
627 #define MC13783_SW2AMODE_PFM (0x3 << 0)
628 #define MC13783_SW2ASTBYMODE (0x3 << 2)
629 #define MC13783_SW2ASTBYMODE_OFF (0x0 << 2)
630 #define MC13783_SW2ASTBYMODE_PWM (0x1 << 2)
631 #define MC13783_SW2ASTBYMODE_PWM_SKIP (0x2 << 2)
632 #define MC13783_SW2ASTBYMODE_PFM (0x3 << 2)
633 #define MC13783_SW2ADVSSPEED (0x3 << 6)
634 #define MC13783_SW2ADVSSPEED_4US_NO_PWR_RDY (0x0 << 6)
635 #define MC13783_SW2ADVSSPEED_4US (0x1 << 6)
636 #define MC13783_SW2ADVSSPEED_8US (0x2 << 6)
637 #define MC13783_SW2ADVSSPEED_16US (0x3 << 6)
638 #define MC13783_SW2APANIC (0x1 << 8)
639 #define MC13783_SW2ASFST (0x1 << 9)
640 #define MC13783_SW2BMODE (0x3 << 10)
641 #define MC13783_SW2BMODE_OFF (0x0 << 10)
642 #define MC13783_SW2BMODE_PWM (0x1 << 10)
643 #define MC13783_SW2BMODE_PWM_SKIP (0x2 << 10)
644 #define MC13783_SW2BMODE_PFM (0x3 << 10)
645 #define MC13783_SW2BSTBYMODE (0x3 << 12)
646 #define MC13783_SW2BSTBYMODE_OFF (0x0 << 12)
647 #define MC13783_SW2BSTBYMODE_PWM (0x1 << 12)
648 #define MC13783_SW2BSTBYMODE_PWM_SKIP (0x2 << 12)
649 #define MC13783_SW2BSTBYMODE_PFM (0x3 << 12)
650 #define MC13783_SW2BDVSSPEED (0x3 << 14)
651 #define MC13783_SW2BDVSSPEED_4US_NO_PWR_RDY (0x0 << 14)
652 #define MC13783_SW2BDVSSPEED_4US (0x1 << 14)
653 #define MC13783_SW2BDVSSPEED_8US (0x2 << 14)
654 #define MC13783_SW2BDVSSPEED_16US (0x3 << 14)
655 #define MC13783_SW2BPANIC (0x1 << 16)
656 #define MC13783_SW2BSFST (0x1 << 17)
657 #define MC13783_SW3 (0x3 << 18)
658 #define MC13783_SW3_5_0V (0x0 << 18)
659 /* 0x1...0x2 same as 0x0 */
660 #define MC13783_SW3_5_5V (0x3 << 18)
661 #define MC13783_SW3EN (0x1 << 20)
662 #define MC13783_SW3STBY (0x1 << 21)
663 #define MC13783_SW3MODE (0x1 << 22)
664
665 /* REGULATOR_SETTING0 (30) */
666 #define MC13783_VIOLO (0x3 << 2)
667 #define MC13783_VIOLO_1_20V (0x0 << 2)
668 #define MC13783_VIOLO_1_30V (0x1 << 2)
669 #define MC13783_VIOLO_1_50V (0x2 << 2)
670 #define MC13783_VIOLO_1_80V (0x3 << 2)
671 #define MC13783_VDIG (0x3 << 4)
672 #define MC13783_VDIG_1_20V (0x0 << 4)
673 #define MC13783_VDIG_1_30V (0x1 << 4)
674 #define MC13783_VDIG_1_50V (0x2 << 4)
675 #define MC13783_VDIG_1_80V (0x3 << 4)
676 #define MC13783_VGEN (0x7 << 6)
677 #define MC13783_VGEN_1_20V (0x0 << 6)
678 #define MC13783_VGEN_1_30V (0x1 << 6)
679 #define MC13783_VGEN_1_50V (0x2 << 6)
680 #define MC13783_VGEN_1_80V (0x3 << 6)
681 #define MC13783_VGEN_1_10V (0x4 << 6)
682 #define MC13783_VGEN_2_00V (0x5 << 6)
683 #define MC13783_VGEN_2_775V (0x6 << 6)
684 #define MC13783_VGEN_2_40V (0x7 << 6)
685 #define MC13783_VRFDIG (0x3 << 9)
686 #define MC13783_VREFDIG_1_20V (0x0 << 9)
687 #define MC13783_VREFDIG_1_30V (0x1 << 9)
688 #define MC13783_VREFDIG_1_80V (0x2 << 9)
689 #define MC13783_VREFDIG_1_875V (0x3 << 9)
690 #define MC13783_VRFREF (0x3 << 11)
691 #define MC13783_VRFREF_2_475V (0x0 << 11)
692 #define MC13783_VRFREF_2_600V (0x1 << 11)
693 #define MC13783_VRFREF_2_700V (0x2 << 11)
694 #define MC13783_VRFREF_2_775V (0x3 << 11)
695 #define MC13783_VRFCP (0x1 << 13)
696 #define MC13783_VSIM (0x1 << 14)
697 #define MC13783_VESIM (0x1 << 15)
698 #define MC13783_VCAM (0x7 << 16)
699 #define MC13783_VCAM_1_50V (0x0 << 16)
700 #define MC13783_VCAM_1_80V (0x1 << 16)
701 #define MC13783_VCAM_2_50V (0x2 << 16)
702 #define MC13783_VCAM_2_55V (0x3 << 16)
703 #define MC13783_VCAM_2_60V (0x4 << 16)
704 #define MC13783_VCAM_2_75V (0x5 << 16)
705 #define MC13783_VCAM_2_80V (0x6 << 16)
706 #define MC13783_VCAM_3_00V (0x7 << 16)
707
708 /* REGULATOR_SETTING1 (31) */
709 #define MC13783_VVIB (0x3 << 0)
710 #define MC13783_VVIB_1_30V (0x0 << 0)
711 #define MC13783_VVIB_1_80V (0x1 << 0)
712 #define MC13783_VVIB_2_00V (0x2 << 0)
713 #define MC13783_VVIB_3_00V (0x3 << 0)
714 #define MC13783_VRF1 (0x3 << 2)
715 #define MC13783_VRF1_1_500V (0x0 << 2)
716 #define MC13783_VRF1_1_875V (0x1 << 2)
717 #define MC13783_VRF1_2_700V (0x2 << 2)
718 #define MC13783_VRF1_2_775V (0x3 << 2)
719 #define MC13783_VRF2 (0x3 << 4)
720 #define MC13783_VRF2_1_500V (0x0 << 4)
721 #define MC13783_VRF2_1_875V (0x1 << 4)
722 #define MC13783_VRF2_2_700V (0x2 << 4)
723 #define MC13783_VRF2_2_775V (0x3 << 4)
724 #define MC13783_VMMC1 (0x7 << 6)
725 #define MC13783_VMMC1_1_60V (0x0 << 6)
726 #define MC13783_VMMC1_1_80V (0x1 << 6)
727 #define MC13783_VMMC1_2_00V (0x2 << 6)
728 #define MC13783_VMMC1_2_60V (0x3 << 6)
729 #define MC13783_VMMC1_2_70V (0x4 << 6)
730 #define MC13783_VMMC1_2_80V (0x5 << 6)
731 #define MC13783_VMMC1_2_90V (0x6 << 6)
732 #define MC13783_VMMC1_3_00V (0x7 << 6)
733 #define MC13783_VMMC2 (0x7 << 9)
734 #define MC13783_VMMC2_1_60V (0x0 << 9)
735 #define MC13783_VMMC2_1_80V (0x1 << 9)
736 #define MC13783_VMMC2_2_00V (0x2 << 9)
737 #define MC13783_VMMC2_2_60V (0x3 << 9)
738 #define MC13783_VMMC2_2_70V (0x4 << 9)
739 #define MC13783_VMMC2_2_80V (0x5 << 9)
740 #define MC13783_VMMC2_2_90V (0x6 << 9)
741 #define MC13783_VMMC2_3_00V (0x7 << 9)
742
743 /* REGULATOR_MODE0 (32) */
744 #define MC13783_VAUDIOEN (0x1 << 0)
745 #define MC13783_VAUDIOSTBY (0x1 << 1)
746 #define MC13783_VAUDIOMODE (0x1 << 2)
747 #define MC13783_VIOHIEN (0x1 << 3)
748 #define MC13783_VIOHISTBY (0x1 << 4)
749 #define MC13783_VIOHIMODE (0x1 << 5)
750 #define MC13783_VIOLOEN (0x1 << 6)
751 #define MC13783_VIOLOSTBY (0x1 << 7)
752 #define MC13783_VIOLOMODE (0x1 << 8)
753 #define MC13783_VDIGEN (0x1 << 9)
754 #define MC13783_VDIGSTBY (0x1 << 10)
755 #define MC13783_VDIGMODE (0x1 << 11)
756 #define MC13783_VGENEN (0x1 << 12)
757 #define MC13783_VGENSTBY (0x1 << 13)
758 #define MC13783_VGENMODE (0x1 << 14)
759 #define MC13783_VRFDIGEN (0x1 << 15)
760 #define MC13783_VRFDIGSTBY (0x1 << 16)
761 #define MC13783_VRFDIGMODE (0x1 << 17)
762 #define MC13783_VRFREFEN (0x1 << 18)
763 #define MC13783_VRFREFSTBY (0x1 << 19)
764 #define MC13783_VRFREFMODE (0x1 << 20)
765 #define MC13783_VRFCPEN (0x1 << 21)
766 #define MC13783_VRFCPSTBY (0x1 << 22)
767 #define MC13783_VRFCPMODE (0x1 << 23)
768
769 /* REGULATOR_MODE1 (33) */
770 #define MC13783_VSIMEN (0x1 << 0)
771 #define MC13783_VSIMSTBY (0x1 << 1)
772 #define MC13783_VSIMMODE (0x1 << 2)
773 #define MC13783_VESIMEN (0x1 << 3)
774 #define MC13783_VESIMSTBY (0x1 << 4)
775 #define MC13783_VESIMMODE (0x1 << 5)
776 #define MC13783_VCAMEN (0x1 << 6)
777 #define MC13783_VCAMSTBY (0x1 << 7)
778 #define MC13783_VCAMMODE (0x1 << 8)
779 #define MC13783_VRFBGEN (0x1 << 9)
780 #define MC13783_VRFBGSTBY (0x1 << 10)
781 #define MC13783_VVIBEN (0x1 << 11)
782 #define MC13783_VRF1EN (0x1 << 12)
783 #define MC13783_VRF1STBY (0x1 << 13)
784 #define MC13783_VRF1MODE (0x1 << 14)
785 #define MC13783_VRF2EN (0x1 << 15)
786 #define MC13783_VRF2STBY (0x1 << 16)
787 #define MC13783_VRF2MODE (0x1 << 17)
788 #define MC13783_VMMC1EN (0x1 << 18)
789 #define MC13783_VMMC1STBY (0x1 << 19)
790 #define MC13783_VMMC1MODE (0x1 << 20)
791 #define MC13783_VMMC2EN (0x1 << 21)
792 #define MC13783_VMMC2STBY (0x1 << 22)
793 #define MC13783_VMMC2MODE (0x1 << 23)
794
795 /* POWER_MISCELLANEOUS (34) */
796 #define MC13783_GPO1EN (0x1 << 6)
797 #define MC13783_GPO1STBY (0x1 << 7)
798 #define MC13783_GPO2EN (0x1 << 8)
799 #define MC13783_GPO2STBY (0x1 << 9)
800 #define MC13783_GPO3EN (0x1 << 10)
801 #define MC13783_GPO3STBY (0x1 << 11)
802 #define MC13783_GPO4EN (0x1 << 12)
803 #define MC13783_GPO4STBY (0x1 << 13)
804 #define MC13783_VIBPINCTRL (0x1 << 14)
805 #define MC13783_PWGT1SPIEN (0x1 << 15)
806 #define MC13783_PWGT2SPIEN (0x1 << 16)
807
808 /* AUDIO_RX0 (36) */
809 #define MC13783_VAUDIOON (0x1 << 0)
810 #define MC13783_BIASEN (0x1 << 1)
811 #define MC13783_BIASSPEED (0x1 << 2)
812 #define MC13783_ASPEN (0x1 << 3)
813 #define MC13783_ASPSEL (0x1 << 4)
814 #define MC13783_ALSPEN (0x1 << 5)
815 #define MC13783_ALSPREF (0x1 << 6)
816 #define MC13783_ALSPSEL (0x1 << 7)
817 #define MC13783_LSPLEN (0x1 << 8)
818 #define MC13783_AHSREN (0x1 << 9)
819 #define MC13783_AHSLEN (0x1 << 10)
820 #define MC13783_AHSSEL (0x1 << 11)
821 #define MC13783_HSPGDIS (0x1 << 12)
822 #define MC13783_HSDETEN (0x1 << 13)
823 #define MC13783_HSDETAUTOB (0x1 << 14)
824 #define MC13783_ARXOUTREN (0x1 << 15)
825 #define MC13783_ARXOUTLEN (0x1 << 16)
826 #define MC13783_ARXOUTSEL (0x1 << 17)
827 #define MC13783_CDCOUTEN (0x1 << 18)
828 #define MC13783_HSLDETEN (0x1 << 19)
829 #define MC13783_ADDCDC (0x1 << 21)
830 #define MC13783_ADDSTDC (0x1 << 22)
831 #define MC13783_ADDRXIN (0x1 << 23)
832
833 /* AUDIO_RX1 (37) */
834 #define MC13783_PGARXEN (0x1 << 0)
835 /* <=0010=-33dB...1101=0dB...1111=+6dB in 3dB steps */
836 #define MC13783_PGARX (0xf << 1)
837 #define MC13783_PGARX_POS (1)
838 #define MC13783_PGASTEN (0x1 << 5)
839 /* <=0010=-33dB...1101=0dB...1111=+6dB in 3dB steps */
840 #define MC13783_PGAST (0xf << 6)
841 #define MC13783_PGAST_POS (6)
842 #define MC13783_ARXINEN (0x1 << 10)
843 #define MC13783_ARXIN (0x1 << 11)
844 /* <=0010=-33dB...1101=0dB...1111=+6dB in 3dB steps */
845 #define MC13783_PGARXIN (0xf << 12)
846 #define MC13783_PGARXIN_POS (12)
847 #define MC13783_MONO (0x3 << 16)
848 #define MC13783_MONO_LR_INDEPENDENT (0x0 << 16)
849 #define MC13783_MONO_ST_OPPOSITE (0x1 << 16)
850 #define MC13783_MONO_ST_TO_MONO (0x2 << 16)
851 #define MC13783_MONO_MONO_OPPOSITE (0x3 << 16)
852 /* 000=-21dB...3dB steps...111=0dB: left or right */
853 #define MC13783_BAL (0x7 << 18)
854 #define MC13783_BAL_POS (18)
855 #define MC13783_BALLR (0x1 << 21)
856
857 /* AUDIO_TX (38) */
858 #define MC13783_MC1BEN (0x1 << 0)
859 #define MC13783_MC2BEN (0x1 << 1)
860 #define MC13783_MC2BDETDBNC (0x1 << 2)
861 #define MC13783_MC2BDETEN (0x1 << 3)
862 #define MC13783_AMC1REN (0x1 << 5)
863 #define MC13783_AMC1RITOV (0x1 << 6)
864 #define MC13783_AMC1LEN (0x1 << 7)
865 #define MC13783_AMC1LITOV (0x1 << 8)
866 #define MC13783_AMC2EN (0x1 << 9)
867 #define MC13783_AMC2ITOV (0x1 << 10)
868 #define MC13783_ATXINEN (0x1 << 11)
869 #define MC13783_ATXOUTEN (0x1 << 12)
870 #define MC13783_RXINREC (0x1 << 13)
871 /* 00000=-8dB...01000=0dB...11111=+23dB */
872 #define MC13783_PGATXR (0x1f << 14)
873 #define MC13783_PGATXR_POS (14)
874 /* 00000=-8dB...01000=0dB...11111=+23dB */
875 #define MC13783_PGATXL (0x1f << 19)
876 #define MC13783_PGATXL_POS (19)
877
878 /* SSI_NETWORK (39) */
879 #define MC13783_CDCTXRXSLOT (0x3 << 2)
880 #define MC13783_CDCTXRXSLOT_TS0 (0x0 << 2)
881 #define MC13783_CDCTXRXSLOT_TS1 (0x1 << 2)
882 #define MC13783_CDCTXRXSLOT_TS2 (0x2 << 2)
883 #define MC13783_CDCTXRXSLOT_TS3 (0x3 << 2)
884 #define MC13783_CDCTXSECSLOT (0x3 << 4)
885 #define MC13783_CDCTXSECSLOT_TS0 (0x0 << 4)
886 #define MC13783_CDCTXSECSLOT_TS1 (0x1 << 4)
887 #define MC13783_CDCTXSECSLOT_TS2 (0x2 << 4)
888 #define MC13783_CDCTXSECSLOT_TS3 (0x3 << 4)
889 #define MC13783_CDCRXSECSLOT (0x3 << 6)
890 #define MC13783_CDCRXSECSLOT_TS0 (0x0 << 6)
891 #define MC13783_CDCRXSECSLOT_TS1 (0x1 << 6)
892 #define MC13783_CDCRXSECSLOT_TS2 (0x2 << 6)
893 #define MC13783_CDCRXSECSLOT_TS3 (0x3 << 6)
894 /* -inf, -0dB, -6dB, -12dB */
895 #define MC13783_CDCRXSECGAIN (0x3 << 8)
896 #define MC13783_CDCRXSECGAIN_POS (8)
897 #define MC13783_CDCSUMGAIN (0x1 << 10)
898 #define MC13783_CDCFSDLY (0x1 << 11)
899 #define MC13783_STDCSLOTS (0x3 << 12)
900 #define MC13783_STDCSLOTS_8 (0x0 << 12)
901 #define MC13783_STDCSLOTS_LR6 (0x1 << 12)
902 #define MC13783_STDCSLOTS_LR2 (0x2 << 12)
903 #define MC13783_STDCSLOTS_LR (0x3 << 12)
904 #define MC13783_STDCRXSLOT (0x3 << 14)
905 #define MC13783_STDCRXSLOT_TS0_TS1 (0x0 << 14)
906 #define MC13783_STDCRXSLOT_TS2_TS3 (0x1 << 14)
907 #define MC13783_STDCRXSLOT_TS4_TS5 (0x2 << 14)
908 #define MC13783_STDCRXSLOT_TS6_TS7 (0x3 << 14)
909 #define MC13783_STDCRXSECSLOT (0x3 << 16)
910 #define MC13783_STDCRXSECSLOT_TS0_TS1 (0x0 << 16)
911 #define MC13783_STDCRXSECSLOT_TS2_TS3 (0x1 << 16)
912 #define MC13783_STDCRXSECSLOT_TS4_TS5 (0x2 << 16)
913 #define MC13783_STDCRXSECSLOT_TS6_TS7 (0x3 << 16)
914 /* -inf, -0dB, -6dB, -12dB */
915 #define MC13783_STDCRXSECGAIN (0x3 << 18)
916 #define MC13783_STDCRXSECGAIN_POS (18)
917 #define MC13783_STDSUMGAIN (0x1 << 20)
918
919 /* AUDIO_CODEC (40) */
920 #define MC13783_CDCSSISEL (0x1 << 0)
921 #define MC13783_CDCCLKSEL (0x1 << 1)
922 #define MC13783_CDCSM (0x1 << 2)
923 #define MC13783_CDCBCLINV (0x1 << 3)
924 #define MC13783_CDCFSINV (0x1 << 4)
925 #define MC13783_CDCFS (0x3 << 5)
926 #define MC13783_CDCFS_NET (0x1 << 5)
927 #define MC13783_CDCFS_I2S (0x2 << 5)
928 #define MC13783_CDCCLK (0x7 << 7)
929 #define MC13783_CDCFS8K16K (0x1 << 10)
930 #define MC13783_CDCEN (0x1 << 11)
931 #define MC13783_CDCCLKEN (0x1 << 12)
932 #define MC13783_CDCTS (0x1 << 13)
933 #define MC13783_CDCDITH (0x1 << 14)
934 #define MC13783_CDCRESET (0x1 << 15)
935 #define MC13783_CDCBYP (0x1 << 16)
936 #define MC13783_CDCALM (0x1 << 17)
937 #define MC13783_CDCDLM (0x1 << 18)
938 #define MC13783_AUDIHPF (0x1 << 19)
939 #define MC13783_AUDOHPF (0x1 << 20)
940
941 /* AUDIO_STEREO_DAC (41) */
942 #define MC13783_STDCSSISEL (0x1 << 0)
943 #define MC13783_STDCCLKSEL (0x1 << 1)
944 #define MC13783_STDCSM (0x1 << 2)
945 #define MC13783_STDCBCLINV (0x1 << 3)
946 #define MC13783_STDCFSINV (0x1 << 4)
947 #define MC13783_STDCFS (0x3 << 5)
948 #define MC13783_STDCFS_NORMAL (0x0 << 5)
949 #define MC13783_STDCFS_NET (0x1 << 5)
950 #define MC13783_STDCFS_I2S (0x2 << 5)
951 #define MC13783_STDCCLK (0x7 << 7)
952 /* Master */
953 #define MC13783_STDCCLK_13_0MHZ (0x0 << 7)
954 #define MC13783_STDCCLK_15_36MHZ (0x1 << 7)
955 #define MC13783_STDCCLK_16_8MHZ (0x2 << 7)
956 #define MC13783_STDCCLK_26_0MHZ (0x4 << 7)
957 #define MC13783_STDCCLK_12_0MHZ (0x5 << 7)
958 #define MC13783_STDCCLK_3_6864MHZ (0x6 << 7)
959 #define MC13783_STDCCLK_33_6MHZ (0x7 << 7)
960 /* Slave */
961 #define MC13783_STDCCLK_CLIMCL (0x5 << 7)
962 #define MC13783_STDCCLK_FS (0x6 << 7)
963 #define MC13783_STDCCLK_BCL (0x7 << 7)
964 #define MC13783_STDCFSDLYB (0x1 << 10)
965 #define MC13783_STDCEN (0x1 << 11)
966 #define MC13783_STDCCLKEN (0x1 << 12)
967 #define MC13783_STDCRESET (0x1 << 15)
968 #define MC13783_SPDIF (0x1 << 16)
969 #define MC13783_SR (0xf << 17)
970 #define MC13783_SR_8000 (0x0 << 17)
971 #define MC13783_SR_11025 (0x1 << 17)
972 #define MC13783_SR_12000 (0x2 << 17)
973 #define MC13783_SR_16000 (0x3 << 17)
974 #define MC13783_SR_22050 (0x4 << 17)
975 #define MC13783_SR_24000 (0x5 << 17)
976 #define MC13783_SR_32000 (0x6 << 17)
977 #define MC13783_SR_44100 (0x7 << 17)
978 #define MC13783_SR_48000 (0x8 << 17)
979 #define MC13783_SR_64000 (0x9 << 17)
980 #define MC13783_SR_96000 (0xa << 17)
981
982 /* ADC0 (43) */
983 #define MC13783_LICELLCON (0x1 << 0)
984 #define MC13783_CHRGICON (0x1 << 1)
985 #define MC13783_BATICON (0x1 << 2)
986 #define MC13783_RTHEN (0x1 << 3)
987 #define MC13783_DTHEN (0x1 << 4)
988 #define MC13783_UIDEN (0x1 << 5)
989 #define MC13783_ADOUTEN (0x1 << 6)
990 #define MC13783_ADOUTPER (0x1 << 7)
991 #define MC13783_ADREFEN (0x1 << 10)
992 #define MC13783_ADREFMODE (0x1 << 11)
993 #define MC13783_TSMOD (0x7 << 12)
994 #define MC13783_TSMOD_INACTIVE (0x0 << 12)
995 #define MC13783_TSMOD_INTERRUPT (0x1 << 12)
996 #define MC13783_TSMOD_RESISTIVE (0x2 << 12)
997 #define MC13783_TSMOD_POSITION (0x3 << 12)
998 /* 0x4 - 0x7 = Inactive (same as 0x0) */
999 #define MC13783_CHRGRAWDIV (0x1 << 15)
1000 #define MC13783_ADINC1 (0x1 << 16)
1001 #define MC13783_ADINC2 (0x1 << 17)
1002 #define MC13783_WCOMP (0x1 << 18)
1003 #define MC13783_ADCBIS0_ACCESS (0x1 << 23)
1004
1005 /* ADC1 (44) */
1006 #define MC13783_ADEN (0x1 << 0)
1007 #define MC13783_RAND (0x1 << 1)
1008 #define MC13783_ADSEL (0x1 << 3)
1009 #define MC13783_TRIGMASK (0x1 << 4)
1010 #define MC13783_ADA1 (0x7 << 5)
1011 #define MC13783_ADA1_POS (5)
1012 #define MC13783_ADA2 (0x7 << 8)
1013 #define MC13783_ADA2_POS (8)
1014 #define MC13783_ATO (0xff << 11)
1015 #define MC13783_ATO_POS (11)
1016 #define MC13783_ATOX (0x1 << 19)
1017 #define MC13783_ASC (0x1 << 20)
1018 #define MC13783_ADTRIGIGN (0x1 << 21)
1019 #define MC13783_ADONESHOT (0x1 << 22)
1020 #define MC13783_ADCBIS1_ACCESS (0x1 << 23)
1021
1022 /* ADC2 (45) */
1023 #define MC13783_ADD1 (0x3ff << 2)
1024 #define MC13783_ADD1_POS (2)
1025 #define MC13783_ADD2 (0x3ff << 14)
1026 #define MC13783_ADD2_POS (14)
1027
1028 /* ADC3 (46) */
1029 #define MC13783_WHIGH (0x3f << 0)
1030 #define MC13783_WHIGH_POS (0)
1031 #define MC13783_ICID (0x7 << 6)
1032 #define MC13783_ICID_POS (6)
1033 #define MC13783_WLOW (0x3f << 9)
1034 #define MC13783_WLOW_POS (9)
1035 #define MC13783_ADCBIS2_ACCESS (0x1 << 23)
1036
1037 /* ADC4 (47) */
1038 #define MC13783_ADCBIS1 (0x3ff << 2)
1039 #define MC13783_ADCBIS1_POS (2)
1040 #define MC13783_ADCBIS2 (0x3ff << 14)
1041 #define MC13783_ADCBIS2_POS (14)
1042
1043 /* CHARGER (48) */
1044 #define MC13783_VCHRG (0x7 << 0)
1045 #define MC13783_VCHRG_4_050V (0x0 << 0)
1046 #define MC13783_VCHRG_4_375V (0x1 << 0)
1047 #define MC13783_VCHRG_4_150V (0x2 << 0)
1048 #define MC13783_VCHRG_4_200V (0x3 << 0)
1049 #define MC13783_VCHRG_4_250V (0x4 << 0)
1050 #define MC13783_VCHRG_4_300V (0x5 << 0)
1051 #define MC13783_VCHRG_3_800V (0x6 << 0)
1052 #define MC13783_VCHRG_4_500V (0x7 << 0)
1053 #define MC13783_ICHRG (0xf << 3) /* Min Nom Max */
1054 #define MC13783_ICHRG_POS (3)
1055 #define MC13783_ICHRG_0MA (0x0 << 3) /* 0 0 0 */
1056 #define MC13783_ICHRG_70MA (0x1 << 3) /* 55 70 85 */
1057 #define MC13783_ICHRG_177MA (0x2 << 3) /* 161 177 195 */
1058 #define MC13783_ICHRG_266MA (0x3 << 3) /* 242 266 293 */
1059 #define MC13783_ICHRG_355MA (0x4 << 3) /* 322 355 390 */
1060 #define MC13783_ICHRG_443MA (0x5 << 3) /* 403 443 488 */
1061 #define MC13783_ICHRG_532MA (0x6 << 3) /* 484 532 585 */
1062 #define MC13783_ICHRG_621MA (0x7 << 3) /* 564 621 683 */
1063 #define MC13783_ICHRG_709MA (0x8 << 3) /* 645 709 780 */
1064 #define MC13783_ICHRG_798MA (0x9 << 3) /* 725 798 878 */
1065 #define MC13783_ICHRG_886MA (0xa << 3) /* 806 886 975 */
1066 #define MC13783_ICHRG_975MA (0xb << 3) /* 886 975 1073 */
1067 #define MC13783_ICHRG_1064MA (0xc << 3) /* 967 1064 1170 */
1068 #define MC13783_ICHRG_1152MA (0xd << 3) /* 1048 1152 1268 */
1069 #define MC13783_ICHRG_1596MA (0xe << 3) /* 1450 1596 1755 */
1070 #define MC13783_ICHRG_FULLY_ON (0xf << 3) /* Disallow HW FET turn on */
1071 #define MC13783_ICHRGTR (0x7 << 7) /* Min Nom Max */
1072 #define MC13783_ICHRGTR_POS (7)
1073 #define MC13783_ICHRGTR_0MA (0x0 << 7) /* 0 0 0 */
1074 #define MC13783_ICHRGTR_9MA (0x1 << 7) /* 6 9 12 */
1075 #define MC13783_ICHRGTR_20MA (0x2 << 7) /* 14 20 26 */
1076 #define MC13783_ICHRGTR_36MA (0x3 << 7) /* 25 36 47 */
1077 #define MC13783_ICHRGTR_42MA (0x4 << 7) /* 29 42 55 */
1078 #define MC13783_ICHRGTR_50MA (0x5 << 7) /* 35 50 65 */
1079 #define MC13783_ICHRGTR_59MA (0x6 << 7) /* 41 59 77 */
1080 #define MC13783_ICHRGTR_68MA (0x7 << 7) /* 50 68 86 */
1081 #define MC13783_FETOVRD (0x1 << 10)
1082 #define MC13783_FETCTRL (0x1 << 11)
1083 #define MC13783_RVRSMODE (0x1 << 13)
1084 #define MC13783_OVCTRL (0x3 << 15)
1085 #define MC13783_OVCTRL_5_83V (0x0 << 15) /* Not for separate! */
1086 #define MC13783_OVCTRL_6_90V (0x1 << 15)
1087 #define MC13783_OVCTRL_9_80V (0x2 << 15)
1088 #define MC13783_OVCTRL_19_6V (0x3 << 15)
1089 #define MC13783_UCHEN (0x1 << 17)
1090 #define MC13783_CHRGLEDEN (0x1 << 18)
1091 #define MC13783_CHRGRAWPDEN (0x1 << 19)
1092
1093 /* USB0 (49) */
1094 #define MC13783_FSENB (0x1 << 0)
1095 #define MC13783_USBSUSPEND (0x1 << 1)
1096 #define MC13783_USBPU (0x1 << 2)
1097 #define MC13783_UDPPD (0x1 << 3)
1098 #define MC13783_UDMPD (0x1 << 4)
1099 #define MC13783_DP150KPU (0x1 << 5)
1100 #define MC13783_VBUS70KPDENB (0x1 << 6)
1101 #define MC13783_VBUSPULSETMR (0x7 << 7)
1102 #define MC13783_VBUSPULSETMR_NA (0x0 << 7)
1103 #define MC13783_VBUSPULSETMR_10MS (0x1 << 7)
1104 #define MC13783_VBUSPULSETMR_20MS (0x2 << 7)
1105 #define MC13783_VBUSPULSETMR_30MS (0x3 << 7)
1106 #define MC13783_VBUSPULSETMR_40MS (0x4 << 7)
1107 #define MC13783_VBUSPULSETMR_50MS (0x5 << 7)
1108 #define MC13783_VBUSPULSETMR_60MS (0x6 << 7)
1109 #define MC13783_VBUSPULSETMR_INF (0x7 << 7)
1110 #define MC13783_DLPSRP (0x1 << 10)
1111 #define MC13783_SE0CONN (0x1 << 11)
1112 #define MC13783_USBXCVREN (0x1 << 12)
1113 #define MC13783_CONMODE (0x7 << 14)
1114 #define MC13783_CONMODE_USB (0x0 << 14)
1115 #define MC13783_CONMODE_RS232 (0x1 << 14) /* and 0x2 */
1116 #define MC13783_CONMODE_CEA_936_A (0x4 << 14) /* and 0x5...0x7 */
1117 #define MC13783_DATSE0 (0x1 << 17)
1118 #define MC13783_BIDIR (0x1 << 18)
1119 #define MC13783_USBCNTRL (0x1 << 19)
1120 #define MC13783_IDPD (0x1 << 20)
1121 #define MC13783_IDPULSE (0x1 << 21)
1122 #define MC13783_IDPUCNTRL (0x1 << 22)
1123 #define MC13783_DMPULSE (0x1 << 23)
1124
1125 /* CHARGER_USB1 (50) */
1126 #define MC13783_USBIN (0x3 << 0)
1127 #define MC13783_USBIN_BOOST_VINBUS (0x0 << 0)
1128 #define MC13783_USBIN_VBUS (0x1 << 0) /* and 0x3 */
1129 #define MC13783_USBIN_BP (0x2 << 0) /* VINVIB */
1130 #define MC13783_VUSB (0x1 << 2) /* 0=3.2V, 1=3.3V */
1131 #define MC13783_VUSBEN (0x1 << 3)
1132 #define MC13783_VBUSEN (0x1 << 5)
1133 #define MC13783_RSPOL (0x1 << 6)
1134 #define MC13783_RSTRI (0x1 << 7)
1135 #define MC13783_ID100KPU (0x1 << 8)
1136
1137 /* LED_CONTROL0 (51) */
1138 #define MC13783_LEDEN (0x1 << 0)
1139 #define MC13783_LEDMDRAMPUP (0x1 << 1)
1140 #define MC13783_LEDADRAMPUP (0x1 << 2)
1141 #define MC13783_LEDKDRAMPUP (0x1 << 3)
1142 #define MC13783_LEDMDRAMPDOWN (0x1 << 4)
1143 #define MC13783_LEDADRAMPDOWN (0x1 << 5)
1144 #define MC13783_LEDKDRAMPDOWN (0x1 << 6)
1145 #define MC13783_TRIODEMD (0x1 << 7)
1146 #define MC13783_TRIODEAD (0x1 << 8)
1147 #define MC13783_TRIODEKD (0x1 << 9)
1148 #define MC13783_BOOSTEN (0x1 << 10)
1149 #define MC13783_ABMODE (0x7 << 11)
1150 #define MC13783_ABMODE_ADAPTIVE_BOOST_DISABLED (0x0 << 11)
1151 #define MC13783_ABMODE_MONCH_LEDMD1 (0x1 << 11)
1152 #define MC13783_ABMODE_MONCH_LEDMD12 (0x2 << 11)
1153 #define MC13783_ABMODE_MONCH_LEDMD123 (0x3 << 11)
1154 #define MC13783_ABMODE_MONCH_LEDMD1234 (0x4 << 11)
1155 #define MC13783_ABMODE_MONCH_LEDMD1234_LEADAD1 (0x5 << 11)
1156 #define MC13783_ABMODE_MONCH_LEDMD1234_LEADAD12 (0x6 << 11)
1157 #define MC13783_ABMODE_MONCH_LEDMD1_LEDAD_ACT (0x7 << 11)
1158 #define MC13783_ABREF (0x3 << 14)
1159 #define MC13783_ABREF_200MV (0x0 << 14)
1160 #define MC13783_ABREF_400MV (0x1 << 14)
1161 #define MC13783_ABREF_600MV (0x2 << 14)
1162 #define MC13783_ABREF_800MV (0x3 << 14)
1163 #define MC13783_FLPATTRN (0xf << 17)
1164 #define MC13783_FLPATTRN_POS (17)
1165 #define MC13783_FLBANK1 (0x1 << 21)
1166 #define MC13783_FLBANK2 (0x1 << 22)
1167 #define MC13783_FLBANK3 (0x1 << 23)
1168
1169 /* LED_CONTROL1 (52) */
1170 #define MC13783_LEDR1RAMPUP (0x1 << 0)
1171 #define MC13783_LEDG1RAMPUP (0x1 << 1)
1172 #define MC13783_LEDB1RAMPUP (0x1 << 2)
1173 #define MC13783_LEDR1RAMPDOWN (0x1 << 3)
1174 #define MC13783_LEDG1RAMPDOWN (0x1 << 4)
1175 #define MC13783_LEDB1RAMPDOWN (0x1 << 5)
1176 #define MC13783_LEDR2RAMPUP (0x1 << 6)
1177 #define MC13783_LEDG2RAMPUP (0x1 << 7)
1178 #define MC13783_LEDB2RAMPUP (0x1 << 8)
1179 #define MC13783_LEDR2RAMPDOWN (0x1 << 9)
1180 #define MC13783_LEDG2RAMPDOWN (0x1 << 10)
1181 #define MC13783_LEDB2RAMPDOWN (0x1 << 11)
1182 #define MC13783_LEDR3RAMPUP (0x1 << 12)
1183 #define MC13783_LEDG3RAMPUP (0x1 << 13)
1184 #define MC13783_LEDB3RAMPUP (0x1 << 14)
1185 #define MC13783_LEDR3RAMPDOWN (0x1 << 15)
1186 #define MC13783_LEDG3RAMPDOWN (0x1 << 16)
1187 #define MC13783_LEDB3RAMPDOWN (0x1 << 17)
1188 #define MC13783_TC1HALF (0x1 << 18)
1189 #define MC13783_SLEWLIMTC (0x1 << 23)
1190
1191 /* LED_CONTROL2 (53) */
1192 #define MC13783_LEDMD (0x7 << 0)
1193 #define MC13783_LEDMD_POS (0)
1194 #define MC13783_LEDAD (0x7 << 3)
1195 #define MC13783_LEDAD_POS (3)
1196 #define MC13783_LEDKP (0x7 << 6)
1197 #define MC13783_LEDKP_POS (6)
1198 #define MC13783_LEDMDDC (0xf << 9)
1199 #define MC13783_LEDMDDC_POS (9)
1200 #define MC13783_LEDADDC (0xf << 13)
1201 #define MC13783_LEDADDC_POS (13)
1202 #define MC13783_LEDKPDC (0xf << 17)
1203 #define MC13783_LEDKPDC_POS (17)
1204 #define MC13783_BLPERIOD (0x1 << 21)
1205 #define MC13783_BLPERIOD_POS (21)
1206 #define MC13783_SLEWLIMBL (0x1 << 23)
1207
1208 /* LED_CONTROL3 (54) */
1209 #define MC13783_LEDR1 (0x3 << 0)
1210 #define MC13783_LEDR1_POS (0)
1211 #define MC13783_LEDG1 (0x3 << 2)
1212 #define MC13783_LEDG1_POS (2)
1213 #define MC13783_LEDB1 (0x3 << 4)
1214 #define MC13783_LEDB1_POS (4)
1215 #define MC13783_LEDR1DC (0x1f << 6)
1216 #define MC13783_LEDR1DC_POS (6)
1217 #define MC13783_LEDG1DC (0x1f << 11)
1218 #define MC13783_LEDG1DC_POS (11)
1219 #define MC13783_LEDB1DC (0x1f << 16)
1220 #define MC13783_LEDB1DC_POS (16)
1221 #define MC13783_TC1PERIOD (0x3 << 21)
1222 #define MC13783_TC1PERIOD_POS (21)
1223 #define MC13783_TC1TRIODE (0x1 << 23)
1224
1225 /* LED_CONTROL4 (55) */
1226 #define MC13783_LEDR2 (0x3 << 0)
1227 #define MC13783_LEDR2_POS (0)
1228 #define MC13783_LEDG2 (0x3 << 2)
1229 #define MC13783_LEDG2_POS (2)
1230 #define MC13783_LEDB2 (0x3 << 4)
1231 #define MC13783_LEDB2_POS (4)
1232 #define MC13783_LEDR2DC (0x1f << 6)
1233 #define MC13783_LEDR2DC_POS (6)
1234 #define MC13783_LEDG2DC (0x1f << 11)
1235 #define MC13783_LEDG2DC_POS (11)
1236 #define MC13783_LEDB2DC (0x1f << 16)
1237 #define MC13783_LEDB2DC_POS (16)
1238 #define MC13783_TC2PERIOD (0x3 << 21)
1239 #define MC13783_TC2PERIOD_POS (21)
1240 #define MC13783_TC2TRIODE (0x1 << 23)
1241
1242 /* LED_CONTROL5 (56) */
1243 #define MC13783_LEDR3 (0x3 << 0)
1244 #define MC13783_LEDR3_POS (0)
1245 #define MC13783_LEDG3 (0x3 << 2)
1246 #define MC13783_LEDG3_POS (2)
1247 #define MC13783_LEDB3 (0x3 << 4)
1248 #define MC13783_LEDB3_POS (4)
1249 #define MC13783_LEDR3DC (0x1f << 6)
1250 #define MC13783_LEDR3DC_POS (6)
1251 #define MC13783_LEDG3DC (0x1f << 11)
1252 #define MC13783_LEDG3DC_POS (11)
1253 #define MC13783_LEDB3DC (0x1f << 16)
1254 #define MC13783_LEDB3DC_POS (16)
1255 #define MC13783_TC3PERIOD (0x3 << 21)
1256 #define MC13783_TC3PERIOD_POS (21)
1257 #define MC13783_TC3TRIODE (0x1 << 23)
1258
1259 /* For event enum values which are target-defined */
1260 #include "mc13783-target.h"
1261
1262 void mc13783_init(void);
1263 void mc13783_close(void);
1264 uint32_t mc13783_set(unsigned address, uint32_t bits);
1265 uint32_t mc13783_clear(unsigned address, uint32_t bits);
1266 uint32_t mc13783_read(unsigned address);
1267 int mc13783_write(unsigned address, uint32_t data);
1268 uint32_t mc13783_write_masked(unsigned address, uint32_t data, uint32_t mask);
1269 /* buffer must be available as packet workspace */
1270 int mc13783_read_regs(const unsigned char *regs, uint32_t *buffer, int count);
1271 /* buffer must be available as packet workspace */
1272 int mc13783_write_regs(const unsigned char *regs, uint32_t *buffer, int count);
1273 /* buffer must be available as packet workspace */
1274 bool mc13783_read_async(struct spi_transfer_desc *xfer,
1275 const unsigned char *regs, uint32_t *buffer,
1276 int count, spi_transfer_cb_fn_type callback);
1277 /* buffer must be available as packet workspace */
1278 bool mc13783_write_async(struct spi_transfer_desc *xfer,
1279 const unsigned char *regs, uint32_t *buffer,
1280 int count, spi_transfer_cb_fn_type callback);
1281
1282 #define MC13783_DATA_ERROR UINT32_MAX
1283
1284 /* Statically-registered event enable/disable */
1285 enum mc13783_event_sets
1286 {
1287 MC13783_EVENT_SET0 = 0, /* *STATUS0/MASK0/SENSE0 */
1288 MC13783_EVENT_SET1 = 1, /* *STATUS1/MASK1/SENSE1 */
1289 };
1290
1291 struct mc13783_event
1292 {
1293 enum mc13783_event_sets set : 8;
1294 uint32_t mask : 24;
1295 void (*callback)(void);
1296 };
1297
1298 struct mc13783_event_list
1299 {
1300 unsigned count;
1301 const struct mc13783_event *events;
1302 };
1303
1304 bool mc13783_enable_event(enum mc13783_event_ids event);
1305 void mc13783_disable_event(enum mc13783_event_ids event);
1306
1307 #endif /* _MC13783_H_ */
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