firmware/target/arm/s3c2440/system-target.h

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2007 by Greg White
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21 #ifndef SYSTEM_TARGET_H
  22 #define SYSTEM_TARGET_H
  23
  24 #include "system-arm.h"
  25 #include "mmu-arm.h"
  26
  27 /* NB: These values must match the register settings in s3c2440/crt0.S */
  28
  29 #ifdef GIGABEAT_F
  30     /* MPLLCON = 0x000C9042, 16.9344 MHz refclk, therefore:
  31      * MPLL = 294940800 = 2*(201 + 8)*16934400 / ((4 + 2) * 2^2) */
  32     #define CPUFREQ_DEFAULT 98313600
  33     #define CPUFREQ_NORMAL  98313600
  34     #define CPUFREQ_MAX    294940800
  35
  36     /* Uses 1:3:6 */
  37     #define FCLK    CPUFREQ_MAX
  38     #define HCLK    (FCLK/3)   /* = 98,313,600 */
  39     #define PCLK    (HCLK/2)   /* = 49,156,800 */
  40
  41     #ifdef BOOTLOADER
  42         /* All addresses within rockbox are in IRAM in the bootloader so
  43            are therefore uncached */
  44         #define UNCACHED_ADDR(a) (a)
  45     #else /* !BOOTLOADER */
  46         #define UNCACHED_BASE_ADDR 0x30000000
  47         #define UNCACHED_ADDR(a)  ((typeof(a))((unsigned int)(a) | UNCACHED_BASE_ADDR ))
  48     #endif /* BOOTLOADER */
  49
  50 #elif defined(MINI2440)
  51
  52     /* Uses 1:4:8 */
  53     #define FCLK 406000000
  54     #define HCLK (FCLK/4)   /* = 101,250,000 */
  55     #define PCLK (HCLK/2)   /* =  50,625,000 */
  56
  57     #define CPUFREQ_DEFAULT FCLK    /* 406 MHz */
  58     #define CPUFREQ_NORMAL  (FCLK/4)/* 101.25 MHz */
  59     #define CPUFREQ_MAX     FCLK    /* 406 MHz */
  60
  61     #define UNCACHED_BASE_ADDR 0x30000000
  62     #define UNCACHED_ADDR(a)  ((typeof(a))((unsigned int)(a) | UNCACHED_BASE_ADDR ))
  63
  64 #else
  65     #error Unknown target
  66 #endif
  67
  68
  69 void system_prepare_fw_start(void);
  70 void tick_stop(void);
  71
  72 /* Functions to set and clear register bits atomically */
  73
  74 /* Set and clear register bits */
  75 void s3c_regmod32(volatile unsigned long *reg, unsigned long bits,
  76                   unsigned long mask);
  77 /* Set register bits */
  78 void s3c_regset32(volatile unsigned long *reg, unsigned long bits);
  79 /* Clear register bits */
  80 void s3c_regclr32(volatile unsigned long *reg, unsigned long bits);
  81
  82 #endif /* SYSTEM_TARGET_H */