firmware/target/arm/as3525/usb-drv-as3525.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright © 2009 Rafaël Carré
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21
  22 #include "system.h"
  23 #include "usb.h"
  24 #include "usb_drv.h"
  25 #include "as3525.h"
  26 #include "clock-target.h"
  27 #include "ascodec.h"
  28 #include "as3514.h"
  29 #include <stdbool.h>
  30 #include "panic.h"
  31 /*#define LOGF_ENABLE*/
  32 #define LOGF_ENABLE
  33 #include "logf.h"
  34 #include "usb_ch9.h"
  35 #include "usb_core.h"
  36 #include "string.h"
  37
  38 #if defined(USE_ROCKBOX_USB) && CONFIG_USBOTG == USBOTG_AS3525
  39
  40 #define USB_NUM_EPS         4
  41
  42 typedef struct {
  43     volatile unsigned long offset[4096];
  44 } __regbase;
  45
  46 /*
  47  * This generates better code.
  48  * Stripped object size with __regbase construct:  5192
  49  * Stripped object size with *((volatile int)(x)): 5228
  50  */
  51 #define USB_REG(x)    ((__regbase *)(USB_BASE))->offset[(x)>>2]
  52
  53 /* 4 input endpoints */
  54 #define USB_IEP_CTRL(i)         USB_REG(0x0000 + i*0x20)
  55 #define USB_IEP_STS(i)          USB_REG(0x0004 + i*0x20)
  56 #define USB_IEP_TXFSIZE(i)      USB_REG(0x0008 + i*0x20)
  57 #define USB_IEP_MPS(i)          USB_REG(0x000C + i*0x20)
  58 #define USB_IEP_DESC_PTR(i)     USB_REG(0x0014 + i*0x20)
  59 #define USB_IEP_STS_MASK(i)     USB_REG(0x0018 + i*0x20)
  60
  61 /* 4 output endpoints */
  62 #define USB_OEP_CTRL(i)         USB_REG(0x0200 + i*0x20)
  63 #define USB_OEP_STS(i)          USB_REG(0x0204 + i*0x20)
  64 #define USB_OEP_RXFR(i)         USB_REG(0x0208 + i*0x20)
  65 #define USB_OEP_MPS(i)          USB_REG(0x020C + i*0x20)
  66 #define USB_OEP_SUP_PTR(i)      USB_REG(0x0210 + i*0x20)
  67 #define USB_OEP_DESC_PTR(i)     USB_REG(0x0214 + i*0x20)
  68 #define USB_OEP_STS_MASK(i)     USB_REG(0x0218 + i*0x20)
  69
  70 /* more general macro */
  71 /* d: true => IN, false => OUT */
  72 #define USB_EP_CTRL(i,d)        USB_REG(0x0000 + i*0x20 + (!d)*0x0200)
  73 #define USB_EP_STS(i,d)         USB_REG(0x0004 + i*0x20 + (!d)*0x0200)
  74 #define USB_EP_TXFSIZE(i,d)     USB_REG(0x0008 + i*0x20 + (!d)*0x0200)
  75 #define USB_EP_MPS(i,d)         USB_REG(0x000C + i*0x20 + (!d)*0x0200)
  76 #define USB_EP_DESC_PTR(i,d)    USB_REG(0x0014 + i*0x20 + (!d)*0x0200)
  77 #define USB_EP_STS_MASK(i,d)    USB_REG(0x0018 + i*0x20 + (!d)*0x0200)
  78
  79 #define USB_DEV_CFG             USB_REG(0x0400)
  80 #define USB_DEV_CTRL            USB_REG(0x0404)
  81 #define USB_DEV_STS             USB_REG(0x0408)
  82 #define USB_DEV_INTR            USB_REG(0x040C)
  83 #define USB_DEV_INTR_MASK       USB_REG(0x0410)
  84 #define USB_DEV_EP_INTR         USB_REG(0x0414)
  85 #define USB_DEV_EP_INTR_MASK    USB_REG(0x0418)
  86
  87 /* NOTE: Not written to in OF, most lied in host mode? */
  88 #define USB_PHY_EP0_INFO        USB_REG(0x0504)
  89 #define USB_PHY_EP1_INFO        USB_REG(0x0508)
  90 #define USB_PHY_EP2_INFO        USB_REG(0x050C)
  91 #define USB_PHY_EP3_INFO        USB_REG(0x0510)
  92 #define USB_PHY_EP4_INFO        USB_REG(0x0514)
  93 #define USB_PHY_EP5_INFO        USB_REG(0x0518)
  94
  95 /* 4 channels */
  96 #define USB_HOST_CH_SPLT(i)     USB_REG(0x1000 + i*0x20)
  97 #define USB_HOST_CH_STS(i)      USB_REG(0x1004 + i*0x20)
  98 #define USB_HOST_CH_TXFSIZE(i)  USB_REG(0x1008 + i*0x20)
  99 #define USB_HOST_CH_REQ(i)      USB_REG(0x100C + i*0x20)
 100 #define USB_HOST_CH_PER_INFO(i) USB_REG(0x1010 + i*0x20)
 101 #define USB_HOST_CH_DESC_PTR(i) USB_REG(0x1014 + i*0x20)
 102 #define USB_HOST_CH_STS_MASK(i) USB_REG(0x1018 + i*0x20)
 103
 104 #define USB_HOST_CFG            USB_REG(0x1400)
 105 #define USB_HOST_CTRL           USB_REG(0x1404)
 106 #define USB_HOST_INTR           USB_REG(0x140C)
 107 #define USB_HOST_INTR_MASK      USB_REG(0x1410)
 108 #define USB_HOST_CH_INTR        USB_REG(0x1414)
 109 #define USB_HOST_CH_INTR_MASK   USB_REG(0x1418)
 110 #define USB_HOST_FRAME_INT      USB_REG(0x141C)
 111 #define USB_HOST_FRAME_REM      USB_REG(0x1420)
 112 #define USB_HOST_FRAME_NUM      USB_REG(0x1424)
 113
 114 #define USB_HOST_PORT0_CTRL_STS USB_REG(0x1500)
 115
 116 #define USB_OTG_CSR             USB_REG(0x2000)
 117 #define USB_I2C_CSR             USB_REG(0x2004)
 118 #define USB_GPIO_CSR            USB_REG(0x2008)
 119 #define USB_SNPSID_CSR          USB_REG(0x200C)
 120 #define USB_USERID_CSR          USB_REG(0x2010)
 121 #define USB_USER_CONF1          USB_REG(0x2014)
 122 #define USB_USER_CONF2          USB_REG(0x2018)
 123 #define USB_USER_CONF3          USB_REG(0x201C)
 124 #define USB_USER_CONF4          USB_REG(0x2020)
 125 /* USER_CONF5 seems to the same as USBt least on read */
 126 #define USB_USER_CONF5          USB_REG(0x2024)
 127
 128 /* write bits 31..16 */
 129 #define USB_GPIO_IDDIG_SEL        (1<<30)
 130 #define USB_GPIO_FS_DATA_EXT      (1<<29)
 131 #define USB_GPIO_FS_SE0_EXT       (1<<28)
 132 #define USB_GPIO_FS_XCVR_OWNER    (1<<27)
 133 #define USB_GPIO_TX_ENABLE_N      (1<<26)
 134 #define USB_GPIO_TX_BIT_STUFF_EN  (1<<25)
 135 #define USB_GPIO_BSESSVLD_EXT     (1<<24)
 136 #define USB_GPIO_ASESSVLD_EXT     (1<<23)
 137 #define USB_GPIO_VBUS_VLD_EXT     (1<<22)
 138 #define USB_GPIO_VBUS_VLD_EXT_SEL (1<<21)
 139 #define USB_GPIO_XO_ON            (1<<20)
 140 #define USB_GPIO_CLK_SEL11        (3<<18)
 141 #define USB_GPIO_CLK_SEL10        (2<<18)
 142 #define USB_GPIO_CLK_SEL01        (1<<18)
 143 #define USB_GPIO_CLK_SEL00        (0<<18)
 144 #define USB_GPIO_XO_EXT_CLK_ENBN  (1<<17)
 145 #define USB_GPIO_XO_REFCLK_ENB    (1<<16)
 146 /* readronly bits 15..0 */
 147 #define USB_GPIO_PHY_VBUSDRV      (1<< 1)
 148 #define USB_GPIO_HS_INTR          (1<< 0)
 149
 150 /* Device Control Register and bit fields */
 151 #define USB_DEV_CTRL_REMOTE_WAKEUP      0x00000001  // set remote wake-up signal
 152 #define USB_DEV_CTRL_RDE                0x00000004  // receive dma enable
 153 #define USB_DEV_CTRL_DESC_UPDATE        0x00000010  // descriptor update
 154 #define USB_DEV_CTRL_THRES_ENABLE       0x00000080  // threshold enable
 155 #define USB_DEV_CTRL_BURST_CONTROL      0x00000100  // burst control
 156 #define USB_DEV_CTRL_SOFT_DISCONN       0x00000400  // soft disconnect
 157 #define USB_DEV_CTRL_APCSR_DONE         0x00002000  // app Prog CSR Done
 158 #define USB_DEV_CTRL_MASK_BURST_LEN     0x000f0000  // mask for burst length
 159 #define USB_DEV_CTRL_MASK_THRESHOLD_LEN 0xff000000  // mask for threshold length
 160
 161 /* settings of burst length for maskBurstLen_c field */
 162 #define USB_DEV_CTRL_BLEN_1DWORD        0x00000000
 163 #define USB_DEV_CTRL_BLEN_2DWORDS       0x00010000
 164 #define USB_DEV_CTRL_BLEN_4DWORDS       0x00020000
 165 #define USB_DEV_CTRL_BLEN_8DWORDS       0x00030000
 166 #define USB_DEV_CTRL_BLEN_16DWORDS      0x00040000
 167 #define USB_DEV_CTRL_BLEN_32DWORDS      0x00050000
 168 #define USB_DEV_CTRL_BLEN_64DWORDS      0x00060000
 169 #define USB_DEV_CTRL_BLEN_128DWORDS     0x00070000
 170 #define USB_DEV_CTRL_BLEN_256DWORDS     0x00080000
 171 #define USB_DEV_CTRL_BLEN_512DWORDS     0x00090000
 172
 173 /* settings of threshold length for maskThresholdLen_c field */
 174 #define USB_DEV_CTRL_TLEN_1DWORD        0x00000000
 175 #define USB_DEV_CTRL_TLEN_HALFMAXSIZE   0x01000000
 176 #define USB_DEV_CTRL_TLEN_4THMAXSIZE    0x02000000
 177 #define USB_DEV_CTRL_TLEN_8THMAXSIZE    0x03000000
 178
 179 #define USB_DEV_CFG_HS                  0x00000000
 180 #define USB_DEV_CFG_FS                  0x00000001 /* 30 or 60MHz */
 181 #define USB_DEV_CFG_LS                  0x00000002
 182 #define USB_DEV_CFG_FS_48               0x00000003 /* 48MHz */
 183 #define USB_DEV_CFG_REMOTE_WAKEUP       0x00000004
 184 #define USB_DEV_CFG_SELF_POWERED        0x00000008
 185 #define USB_DEV_CFG_SYNC_FRAME          0x00000010
 186 #define USB_DEV_CFG_PI_16BIT            0x00000000
 187 #define USB_DEV_CFG_PI_8BIT             0x00000020
 188 #define USB_DEV_CFG_UNI_DIR             0x00000000
 189 #define USB_DEV_CFG_BI_DIR              0x00000040
 190 #define USB_DEV_CFG_STAT_ACK            0x00000000
 191 #define USB_DEV_CFG_STAT_STALL          0x00000080
 192
 193 /* Device Status Register and bit fields */
 194 #define USB_DEV_STS_MASK_CFG            0x0000000f
 195 #define USB_DEV_STS_MASK_IF             0x000000f0
 196 #define USB_DEV_STS_MASK_ALT_SET        0x00000f00
 197 #define USB_DEV_STS_SUSPEND_STAT        0x00001000
 198 #define USB_DEV_STS_MASK_SPD            0x00006000 /* Enumerated Speed */
 199 #define USB_DEV_STS_SPD_HS                0x00000000
 200 #define USB_DEV_STS_SPD_FS                0x00002000
 201 #define USB_DEV_STS_SPD_LS                0x00004000
 202 #define USB_DEV_STS_RXF_EMPTY           0x00008000
 203 #define USB_DEV_STS_MASK_FRM_NUM        0xfffc0000 /* SOF frame number */
 204
 205
 206 /* Device Intr Register and bit fields */
 207 #define USB_DEV_INTR_SET_CONFIG         0x00000001  /* set configuration cmd rcvd */
 208 #define USB_DEV_INTR_SET_INTERFACE      0x00000002  /* set interface command rcvd */
 209 #define USB_DEV_INTR_EARLY_SUSPEND      0x00000004  /* idle on usb for 3ms */
 210 #define USB_DEV_INTR_USB_RESET          0x00000008  /* usb bus reset req */
 211 #define USB_DEV_INTR_USB_SUSPEND        0x00000010  /* usb bus suspend req */
 212 #define USB_DEV_INTR_SOF                0x00000020  /* SOF seen on bus */
 213 #define USB_DEV_INTR_ENUM_DONE          0x00000040  /* usb speed enum done */
 214 #define USB_DEV_INTR_OTG                0x00000080  /* otg status change? */
 215 #define USB_DEV_INTR_BUSERR             0x00000080  /* AHB DMA error */
 216
 217 /* EP Control Register Fields */
 218 #define USB_EP_CTRL_STALL               0x00000001
 219 #define USB_EP_CTRL_FLUSH               0x00000002     /* EP In data fifo Flush */
 220 #define USB_EP_CTRL_SNOOP_MODE          0x00000004     // snoop mode for out endpoint
 221 #define USB_EP_CTRL_PD                  0x00000008     /* EP Poll Demand */
 222 #define USB_EP_CTRL_EPTYPE_MASK         0x00000030     // bit 5-4: endpoint types
 223 #define USB_EP_TYPE_CONTROL               0x00000000   // control endpoint
 224 #define USB_EP_TYPE_ISO                   0x00000010   // isochronous endpoint
 225 #define USB_EP_TYPE_BULK                  0x00000020   // bulk endpoint
 226 #define USB_EP_TYPE_INTERRUPT             0x00000030   // interrupt endpoint
 227 #define USB_EP_CTRL_NAK                 0x00000040     /* EP NAK Status */
 228 #define USB_EP_CTRL_SNAK                0x00000080     /* EP Set NAK Bit */
 229 #define USB_EP_CTRL_CNAK                0x00000100     /* EP Clr NAK Bit */
 230 #define USB_EP_CTRL_ACT                 0x00000400     /* EP Clr NAK Bit */
 231
 232 /* bit fields in EP Status Register */
 233 #define USB_EP_STAT_OUT_RCVD            0x00000010     /* OUT token received */
 234 #define USB_EP_STAT_SETUP_RCVD          0x00000020     /* SETUP token received */
 235 #define USB_EP_STAT_IN                  0x00000040     /* IN token received? */
 236 #define USB_EP_STAT_BNA                 0x00000080     /* Buffer Not Available */
 237 #define USB_EP_STAT_BUFF_ERROR          0x00000100
 238 #define USB_EP_STAT_HERR                0x00000200     /* Host Error */
 239 #define USB_EP_STAT_AHB_ERROR           0x00000200
 240 #define USB_EP_STAT_TDC                 0x00000400     /* Transmit DMA Complete */
 241
 242 /*-------------------------*/
 243 /* DMA Related Definitions */
 244 /*-------------------------*/
 245
 246 /* dma status */
 247 #define USB_DMA_DESC_BUFF_STS           0x80000000    /* Buffer Status */
 248 #define USB_DMA_DESC_BS_HST_RDY         0x80000000    /* Host Ready */
 249 #define USB_DMA_DESC_BS_DMA_DONE        0x00000000    /* DMA Done */
 250 #define USB_DMA_DESC_ZERO_LEN           0x40000000    /* zero length packet */
 251 #define USB_DMA_DESC_EARY_INTR          0x20000000    /* early interrupt */
 252 #define USB_DMA_DESC_RXTX_STS           0x10000000
 253 #define USB_DMA_DESC_RTS_SUCC           0x00000000    /* Success */
 254 #define USB_DMA_DESC_RTS_BUFERR         0x10000000    /* Buffer Error */
 255 #define USB_DMA_DESC_LAST               0x08000000
 256 #define USB_DMA_DESC_MASK_FRAM_NUM      0x07ff0000    // bits 26-16: frame number for iso
 257 #define USB_DMA_DESC_RXTX_BYTES         0x0000FFFF
 258
 259 /* setup descriptor */
 260 #define SETUP_MASK_CONFIG_STAT          0x0fff0000
 261 #define SETUP_MASK_CONFIG_NUM           0x0f000000
 262 #define SETUP_MASK_IF_NUM               0x00f00000
 263 #define SETUP_MASK_ALT_SETNUM           0x000f0000
 264
 265 #define EP_STATE_ALLOCATED              0x00000001
 266 #define EP_STATE_BUSY                   0x00000002
 267 #define EP_STATE_ASYNC                  0x00000004
 268
 269 struct usb_dev_dma_desc {
 270     int   status;
 271     int   resv;
 272     void  *data_ptr;
 273     void  *next_desc;
 274 };
 275
 276 struct usb_dev_setup_buf {
 277     int   status;
 278     int   resv;
 279     int   data1; /* first 4 bytes of data */
 280     int   data2; /* last 4 bytes of data */
 281 };
 282
 283 struct usb_endpoint
 284 {
 285     void *buf;
 286     unsigned int len;
 287     volatile unsigned int state;
 288     int rc;
 289     struct wakeup complete;
 290     struct usb_dev_dma_desc *uc_desc;
 291 };
 292
 293 static struct usb_endpoint endpoints[USB_NUM_EPS][2];
 294
 295 /*
 296  * dma/setup descriptors and buffers should avoid sharing
 297  * a cacheline with other data.
 298  * dmadescs may share with each other, since we only access them uncached.
 299  */
 300 static struct usb_dev_dma_desc dmadescs[USB_NUM_EPS][2] __attribute__((aligned(32)));
 301
 302 static struct usb_dev_setup_buf setup_desc;
 303 /* Dummy buffer, to keep rx_buf out of this cacheline */
 304 static struct usb_dev_setup_buf dummy __attribute__((unused));
 305
 306 static char rx_buf[1024];
 307 static char tx_buf[1024];
 308
 309 void usb_attach(void)
 310 {
 311     usb_enable(true);
 312 }
 313
 314 static inline void usb_delay(int delay)
 315 {   //TUNEME : delay is in milliseconds
 316     delay <<= 14;
 317     while(delay--) ;
 318 }
 319
 320 static void usb_phy_on(void)
 321 {
 322     /* PHY clock */
 323     CGU_USB = 1<<5 /* enable */
 324         | (CLK_DIV(AS3525_PLLB_FREQ, 48000000) / 2) << 2
 325         | 2; /* source = PLLB */
 326
 327     /* UVDD on */
 328     ascodec_write(AS3515_USB_UTIL, ascodec_read(AS3515_USB_UTIL) | (1<<4));
 329     usb_delay(100);
 330
 331     /* reset */
 332     CCU_SRC = CCU_SRC_USB_AHB_EN|CCU_SRC_USB_PHY_EN;
 333     CCU_SRL = CCU_SRL_MAGIC_NUMBER;
 334     usb_delay(1);
 335     CCU_SRC = CCU_SRC_USB_AHB_EN;
 336     usb_delay(1);
 337     CCU_SRC = CCU_SRL = 0;
 338
 339     USB_GPIO_CSR = USB_GPIO_TX_ENABLE_N
 340                  | USB_GPIO_TX_BIT_STUFF_EN
 341                  | USB_GPIO_XO_ON
 342                  | USB_GPIO_CLK_SEL10; /* 0x06180000; */
 343 }
 344
 345 static void usb_phy_suspend(void)
 346 {
 347     USB_GPIO_CSR |= USB_GPIO_ASESSVLD_EXT |
 348                     USB_GPIO_BSESSVLD_EXT |
 349                     USB_GPIO_VBUS_VLD_EXT;
 350     usb_delay(3);
 351     USB_GPIO_CSR |= USB_GPIO_VBUS_VLD_EXT_SEL;
 352     usb_delay(10);
 353 }
 354
 355 static void usb_phy_resume(void)
 356 {
 357     USB_GPIO_CSR &= ~(USB_GPIO_ASESSVLD_EXT |
 358                       USB_GPIO_BSESSVLD_EXT |
 359                       USB_GPIO_VBUS_VLD_EXT);
 360     usb_delay(3);
 361     USB_GPIO_CSR &= ~USB_GPIO_VBUS_VLD_EXT_SEL;
 362     usb_delay(10);
 363 }
 364
 365 static void setup_desc_init(struct usb_dev_setup_buf *desc)
 366 {
 367     struct usb_dev_setup_buf *uc_desc = UNCACHED_ADDR(desc);
 368
 369     uc_desc->status = USB_DMA_DESC_BS_HST_RDY;
 370     uc_desc->resv   = 0xffffffff;
 371     uc_desc->data1  = 0xffffffff;
 372     uc_desc->data2  = 0xffffffff;
 373 }
 374
 375 static void dma_desc_init(int ep, int dir)
 376 {
 377     struct usb_dev_dma_desc *desc = &dmadescs[ep][dir];
 378     struct usb_dev_dma_desc *uc_desc = UNCACHED_ADDR(desc);
 379
 380     endpoints[ep][dir].uc_desc = uc_desc;
 381
 382     if (dir == 0) {
 383         uc_desc->status    = USB_DMA_DESC_BS_DMA_DONE | USB_DMA_DESC_LAST | 0x40;
 384         uc_desc->resv      = 0xffffffff;
 385         uc_desc->data_ptr  = tx_buf;
 386         uc_desc->next_desc = 0;
 387     } else {
 388         uc_desc->status    = USB_DMA_DESC_BS_HST_RDY | /*USB_DMA_DESC_LAST |*/ 0x40;
 389         uc_desc->resv      = 0xffffffff;
 390         uc_desc->data_ptr  = rx_buf;
 391         uc_desc->next_desc = 0;
 392     }
 393 }
 394
 395 static void reset_endpoints(int init)
 396 {
 397     int i;
 398
 399     /*
 400      * OUT EP 2 is an alias for OUT EP 0 on this HW!
 401      *
 402      * Resonates with "3 bidirectional- plus 1 in-endpoints in device mode"
 403      * from the datasheet, but why ep2 and not ep3?
 404      *
 405      * Reserve it here so we will skip over it in request_endpoint().
 406      */
 407     endpoints[2][1].state |= EP_STATE_ALLOCATED;
 408
 409     for(i = 0; i < USB_NUM_EPS; i++) {
 410         int mps = i == 0 ? 64 : 2048; /* For HS */
 411
 412         if (init) {
 413             endpoints[i][0].state = 0;
 414             wakeup_init(&endpoints[i][0].complete);
 415
 416             if (i != 2) { /* Skip the OUT EP0 alias */
 417                 endpoints[i][1].state = 0;
 418                 wakeup_init(&endpoints[i][1].complete);
 419                 USB_OEP_SUP_PTR(i)    = 0;
 420             }
 421         }
 422
 423         dma_desc_init(i, 0);
 424         USB_IEP_CTRL    (i) = USB_EP_CTRL_FLUSH|USB_EP_CTRL_SNAK;
 425         USB_IEP_MPS     (i) = mps;
 426         /* We don't care about the 'IN token received' event */
 427         USB_IEP_STS_MASK(i) = USB_EP_STAT_IN; /* OF: 0x840 */
 428         USB_IEP_TXFSIZE (i) = 0x20;
 429         USB_IEP_STS     (i) = 0xffffffff; /* clear status */
 430         USB_IEP_DESC_PTR(i) = 0;
 431
 432         if (i != 2) { /* Skip the OUT EP0 alias */
 433             dma_desc_init(i, 1);
 434             USB_OEP_CTRL    (i) = USB_EP_CTRL_FLUSH|USB_EP_CTRL_SNAK;
 435             USB_OEP_MPS     (i) = 0x08000000|mps;
 436             USB_OEP_STS_MASK(i) = 0x0000; /* OF: 0x1800 */
 437             USB_OEP_RXFR    (i) = 0x00;
 438             USB_OEP_STS     (i) = 0xffffffff; /* clear status */
 439             USB_OEP_DESC_PTR(i) = 0;
 440         }
 441     }
 442
 443     setup_desc_init(&setup_desc);
 444     USB_OEP_SUP_PTR(0)    = (int)&setup_desc;
 445 }
 446
 447 void usb_drv_init(void)
 448 {
 449     logf("usb_drv_init() !!!!\n");
 450
 451     /* length regulator: normal operation */
 452     ascodec_write(AS3514_CVDD_DCDC3, ascodec_read(AS3514_CVDD_DCDC3) | 1<<2);
 453
 454     /* AHB part */
 455     CGU_PERI |= CGU_USB_CLOCK_ENABLE;
 456
 457     /* reset AHB */
 458     CCU_SRC = CCU_SRC_USB_AHB_EN;
 459     CCU_SRL = CCU_SRL_MAGIC_NUMBER;
 460     usb_delay(1);
 461     CCU_SRC = CCU_SRL = 0;
 462
 463     USB_GPIO_CSR = USB_GPIO_TX_ENABLE_N
 464                  | USB_GPIO_TX_BIT_STUFF_EN
 465                  | USB_GPIO_XO_ON
 466                  | USB_GPIO_CLK_SEL10; /* 0x06180000; */
 467
 468     /* bug workaround according to linux patch */
 469     USB_DEV_CFG = (USB_DEV_CFG & ~3) | 1; /* full speed */
 470
 471     /* enable soft disconnect */
 472     USB_DEV_CTRL |= USB_DEV_CTRL_SOFT_DISCONN;
 473
 474     usb_phy_on();
 475     usb_phy_suspend();
 476     USB_DEV_CTRL |= USB_DEV_CTRL_SOFT_DISCONN;
 477
 478     /* We don't care about OTG or SOF events */
 479     /* Right now we don't handle suspend or reset, so mask those too */
 480     USB_DEV_INTR_MASK = USB_DEV_INTR_OTG |
 481                         USB_DEV_INTR_SOF |
 482                         USB_DEV_INTR_USB_SUSPEND |
 483                         USB_DEV_INTR_EARLY_SUSPEND;
 484
 485     USB_DEV_CFG = USB_DEV_CFG_STAT_ACK     |
 486                   USB_DEV_CFG_UNI_DIR      |
 487                   USB_DEV_CFG_PI_16BIT     |
 488                   USB_DEV_CFG_HS           |
 489                   USB_DEV_CFG_SELF_POWERED |
 490                   0x20200;
 491
 492     USB_DEV_CTRL = USB_DEV_CTRL_BLEN_1DWORD  |
 493                    USB_DEV_CTRL_DESC_UPDATE  |
 494                    USB_DEV_CTRL_THRES_ENABLE |
 495                    USB_DEV_CTRL_RDE          |
 496                    0x04000000;
 497
 498     USB_DEV_EP_INTR_MASK &= ~((1<<0) | (1<<16));    /* ep 0 */
 499
 500     reset_endpoints(1);
 501
 502     /* clear pending interrupts */
 503     USB_DEV_EP_INTR = 0xffffffff;
 504     USB_DEV_INTR    = 0xffffffff;
 505
 506     VIC_INT_ENABLE = INTERRUPT_USB;
 507
 508     usb_phy_resume();
 509     USB_DEV_CTRL &= ~USB_DEV_CTRL_SOFT_DISCONN;
 510
 511     USB_GPIO_CSR = USB_GPIO_TX_ENABLE_N
 512                  | USB_GPIO_TX_BIT_STUFF_EN
 513                  | USB_GPIO_XO_ON
 514                  | USB_GPIO_HS_INTR
 515                  | USB_GPIO_CLK_SEL10; /* 0x06180000; */
 516
 517 }
 518
 519 void usb_drv_exit(void)
 520 {
 521     USB_DEV_CTRL |= (1<<10); /* soft disconnect */
 522     VIC_INT_EN_CLEAR = INTERRUPT_USB;
 523     CGU_USB &= ~(1<<5);
 524     CGU_PERI &= ~CGU_USB_CLOCK_ENABLE;
 525     /* Disable UVDD generating LDO */
 526     ascodec_write(AS3515_USB_UTIL, ascodec_read(AS3515_USB_UTIL) & ~(1<<4));
 527     logf("usb_drv_exit() !!!!\n");
 528 }
 529
 530 int usb_drv_port_speed(void)
 531 {
 532     return (USB_DEV_STS & USB_DEV_STS_MASK_SPD) ? 0 : 1;
 533 }
 534
 535 int usb_drv_request_endpoint(int type, int dir)
 536 {
 537     int d = dir == USB_DIR_IN ? 0 : 1;
 538     int i = 1; /* skip the control EP */
 539
 540     for(; i < USB_NUM_EPS; i++) {
 541         if (endpoints[i][d].state & EP_STATE_ALLOCATED)
 542             continue;
 543
 544         endpoints[i][d].state |= EP_STATE_ALLOCATED;
 545
 546         if (dir == USB_DIR_IN) {
 547             USB_IEP_CTRL(i) = USB_EP_CTRL_FLUSH |
 548                               USB_EP_CTRL_SNAK  |
 549                               USB_EP_CTRL_ACT   |
 550                               (type << 4);
 551             USB_DEV_EP_INTR_MASK &= ~(1<<i);
 552         } else {
 553             USB_OEP_CTRL(i) = USB_EP_CTRL_FLUSH |
 554                               USB_EP_CTRL_SNAK  |
 555                               USB_EP_CTRL_ACT   |
 556                               (type << 4);
 557             USB_DEV_EP_INTR_MASK &= ~(1<<(16+i));
 558         }
 559         logf("usb_drv_request_endpoint(%d, %d): returning %02x\n", type, dir, i | dir);
 560         return i | dir;
 561     }
 562
 563     logf("usb_drv_request_endpoint(%d, %d): no free endpoint found\n", type, dir);
 564     return -1;
 565 }
 566
 567 void usb_drv_release_endpoint(int ep)
 568 {
 569     int i = ep & 0x7f;
 570     int d = ep & USB_DIR_IN ? 0 : 1;
 571
 572     if (i >= USB_NUM_EPS)
 573         return;
 574     /*
 575      * Check for control EP and ignore it.
 576      * Unfortunately the usb core calls
 577      * usb_drv_release_endpoint() for ep=0..(USB_NUM_ENDPOINTS-1),
 578      * but doesn't request a new control EP after that...
 579      */
 580     if (i == 0 || /* Don't mask control EP */
 581         (i == 2 && d == 1)) /* See reset_endpoints(), EP2_OUT == EP0_OUT */
 582         return;
 583
 584     if (!(endpoints[i][d].state & EP_STATE_ALLOCATED))
 585         return;
 586
 587     logf("usb_drv_release_endpoint(%d, %d)\n", i, d);
 588     endpoints[i][d].state = 0;
 589     USB_DEV_EP_INTR_MASK |= (1<<(16*d+i));
 590     USB_EP_CTRL(i, !d) = USB_EP_CTRL_FLUSH | USB_EP_CTRL_SNAK;
 591 }
 592
 593 void usb_drv_cancel_all_transfers(void)
 594 {
 595     logf("usb_drv_cancel_all_transfers()\n");
 596     return;
 597
 598     int flags = disable_irq_save();
 599     reset_endpoints(0);
 600     restore_irq(flags);
 601 }
 602
 603 static void *virt_to_bus(void *addr)
 604 {
 605     unsigned int x = (long)addr;
 606
 607     x -= (x & 0x40000000) >> 2; /* fix uncached address */
 608
 609     if (x >= IRAM_ORIG) { /* iram address */
 610         x -= IRAM_ORIG;
 611     }
 612
 613     return (void*)x;
 614 }
 615
 616 int usb_drv_recv(int ep, void *ptr, int len)
 617 {
 618     struct usb_dev_dma_desc *uc_desc = endpoints[ep][1].uc_desc;
 619
 620     ep &= 0x7f;
 621     logf("usb_drv_recv(%d,%x,%d)\n", ep, (int)ptr, len);
 622
 623     if ((int)ptr & 31) {
 624         logf("addr %08x not aligned!\n", (int)ptr);
 625     }
 626
 627     endpoints[ep][1].state |= EP_STATE_BUSY;
 628     endpoints[ep][1].len = len;
 629     endpoints[ep][1].rc = -1;
 630
 631     /* remove data buffer from cache */
 632     invalidate_dcache();
 633     /* DMA setup */
 634     uc_desc->status    = USB_DMA_DESC_BS_HST_RDY |
 635                          USB_DMA_DESC_LAST |
 636                          len;
 637     if (len == 0) {
 638         uc_desc->status   |= USB_DMA_DESC_ZERO_LEN;
 639         uc_desc->data_ptr  = 0;
 640     } else {
 641         uc_desc->data_ptr  = virt_to_bus(ptr);
 642     }
 643     USB_OEP_DESC_PTR(ep) = (int)&dmadescs[ep][1];
 644     USB_OEP_STS(ep)      = USB_EP_STAT_OUT_RCVD; /* clear status */
 645     USB_OEP_CTRL(ep)    |= USB_EP_CTRL_CNAK;
 646
 647     return 0;
 648 }
 649
 650 #if defined(LOGF_ENABLE)
 651 static char hexbuf[1025];
 652 static char hextab[16] = "0123456789abcdef";
 653
 654 char *make_hex(char *data, int len)
 655 {
 656     int i;
 657     if (!((int)data & 0x40000000))
 658         data = UNCACHED_ADDR(data); /* don't pollute the cache */
 659
 660     if (len > 512)
 661         len = 512;
 662
 663     for (i=0; i<len; i++) {
 664         hexbuf[2*i  ] = hextab[(unsigned char)data[i] >> 4 ];
 665         hexbuf[2*i+1] = hextab[(unsigned char)data[i] & 0xf];
 666     }
 667     hexbuf[2*i] = 0;
 668
 669     return hexbuf;
 670 }
 671 #endif
 672
 673 void ep_send(int ep, void *ptr, int len)
 674 {
 675     struct usb_dev_dma_desc *uc_desc = endpoints[ep][0].uc_desc;
 676     int i;
 677
 678     endpoints[ep][0].state |= EP_STATE_BUSY;
 679     endpoints[ep][0].len = len;
 680     endpoints[ep][0].rc = -1;
 681
 682     USB_IEP_CTRL(ep)     |= USB_EP_CTRL_CNAK;
 683
 684     /* TEST: delay a little here */
 685     for (i=0; i<1000; i++) asm volatile ("nop\n");
 686
 687     /* Make sure data is committed to memory */
 688     clean_dcache();
 689
 690     logf("xx%s\n", make_hex(ptr, len));
 691
 692     uc_desc->status    = USB_DMA_DESC_BS_HST_RDY |
 693                          USB_DMA_DESC_LAST |
 694                          len;
 695     if (len == 0)
 696         uc_desc->status |= USB_DMA_DESC_ZERO_LEN;
 697
 698     uc_desc->data_ptr  = virt_to_bus(ptr);
 699
 700     USB_IEP_CTRL(ep)     |= USB_EP_CTRL_FLUSH;
 701     USB_IEP_DESC_PTR(ep) = (int)&dmadescs[ep][0];
 702     USB_IEP_STS(ep)      = 0xffffffff; /* clear status */
 703     /* start transfer */
 704     USB_IEP_CTRL(ep)     |= USB_EP_CTRL_PD;
 705 }
 706
 707 int usb_drv_send(int ep, void *ptr, int len)
 708 {
 709     logf("usb_drv_send(%d,%x,%d): ", ep, (int)ptr, len);
 710
 711     ep &= 0x7f;
 712     ep_send(ep, ptr, len);
 713     while (endpoints[ep][0].state & EP_STATE_BUSY)
 714         wakeup_wait(&endpoints[ep][0].complete, TIMEOUT_BLOCK);
 715
 716     return endpoints[ep][0].rc;
 717 }
 718
 719 int usb_drv_send_nonblocking(int ep, void *ptr, int len)
 720 {
 721     logf("usb_drv_send_nonblocking(%d,%x,%d): ", ep, (int)ptr, len);
 722     ep &= 0x7f;
 723     endpoints[ep][0].state |= EP_STATE_ASYNC;
 724     ep_send(ep, ptr, len);
 725     return 0;
 726 }
 727
 728 static void handle_in_ep(int ep)
 729 {
 730     int ep_sts = USB_IEP_STS(ep) & ~USB_IEP_STS_MASK(ep);
 731
 732     if (ep > 3)
 733         panicf("in_ep > 3?!");
 734
 735     USB_IEP_STS(ep) = ep_sts; /* ack */
 736
 737     if (ep_sts & USB_EP_STAT_TDC) {
 738         ep_sts &= ~USB_EP_STAT_TDC;
 739         /* OF does SNAK and FLUSH at once here */
 740         USB_IEP_CTRL(ep) |= USB_EP_CTRL_SNAK | USB_EP_CTRL_FLUSH;
 741         endpoints[ep][0].state &= ~EP_STATE_BUSY;
 742         endpoints[ep][0].rc = 0;
 743         logf("EP%d %stx done len %x stat %08x\n",
 744              ep, endpoints[ep][0].state & EP_STATE_ASYNC ? "async " :"",
 745              endpoints[ep][0].len,
 746              endpoints[ep][0].uc_desc->status);
 747         if (endpoints[ep][0].state & EP_STATE_ASYNC) {
 748             endpoints[ep][0].state &= ~EP_STATE_ASYNC;
 749             usb_core_transfer_complete(ep, USB_DIR_IN, 0, endpoints[ep][0].len);
 750         } else {
 751             wakeup_signal(&endpoints[ep][0].complete);
 752         }
 753     }
 754
 755     if (ep_sts) {
 756         logf("ep%d IN, hwstat %lx, epstat %x\n", ep, USB_IEP_STS(ep), endpoints[ep][0].state);
 757         panicf("ep%d IN 0x%x", ep, ep_sts);
 758     }
 759
 760     /* HW automatically disables RDE, re-enable it */
 761     /* But this an IN ep, I wonder... */
 762     USB_DEV_CTRL |= USB_DEV_CTRL_RDE;
 763 }
 764
 765 static void handle_out_ep(int ep)
 766 {
 767     struct usb_ctrlrequest *req = (void*)UNCACHED_ADDR(&setup_desc.data1);
 768     int ep_sts = USB_OEP_STS(ep) & ~USB_OEP_STS_MASK(ep);
 769     struct usb_dev_dma_desc *uc_desc = endpoints[ep][1].uc_desc;
 770
 771     if (ep > 3)
 772         panicf("out_ep > 3!?");
 773
 774     USB_OEP_STS(ep) = ep_sts; /* ACK */
 775
 776     if (ep_sts & USB_EP_STAT_BNA) { /* Buffer was not set up */
 777         logf("ep%d OUT, status %x (BNA)\n", ep, ep_sts);
 778         panicf("ep%d OUT 0x%x (BNA)", ep, ep_sts);
 779     }
 780
 781     if (ep_sts & USB_EP_STAT_OUT_RCVD) {
 782         int dma_sts = uc_desc->status;
 783         int dma_len = dma_sts & 0xffff;
 784         int dma_frm = (dma_sts >> 16) & 0x7ff;
 785         int dma_mst = dma_sts & 0xf8000000;
 786
 787         uc_desc->status    = USB_DMA_DESC_BS_HST_RDY |
 788                              USB_DMA_DESC_LAST |
 789                              0x40;
 790         uc_desc->data_ptr  = rx_buf;
 791         USB_OEP_DESC_PTR(ep) = (int)&dmadescs[ep][1];
 792
 793         if (!(dma_sts & USB_DMA_DESC_ZERO_LEN)) {
 794              logf("EP%d OUT token, st:%08x len:%d frm:%x data=%s\n", ep,
 795                  dma_mst, dma_len, dma_frm, make_hex(uc_desc->data_ptr, dma_len));
 796              /*
 797               * If parts of the just dmaed range are in cache, dump them now.
 798               */
 799              dump_dcache_range(uc_desc->data_ptr, dma_len);
 800         } else{
 801              logf("EP%d OUT token, st:%08x len:%d frm:%x\n", ep,
 802                  dma_mst, dma_len, dma_frm);
 803         }
 804
 805         if (endpoints[ep][1].state & EP_STATE_BUSY) {
 806             endpoints[ep][1].state &= ~EP_STATE_BUSY;
 807             endpoints[ep][1].rc = 0;
 808             usb_core_transfer_complete(ep, 0, 0, endpoints[ep][0].len);
 809         } else {
 810             logf("EP%d OUT, but no one was listening?\n", ep);
 811         }
 812
 813         USB_OEP_CTRL(ep) |= USB_EP_CTRL_SNAK; /* make sure NAK is set */
 814
 815         ep_sts &= ~USB_EP_STAT_OUT_RCVD;
 816     }
 817
 818     if (ep_sts & USB_EP_STAT_SETUP_RCVD) {
 819         static struct usb_ctrlrequest req_copy;
 820
 821         req_copy = *req;
 822         logf("t%ld:got SETUP packet: type=%d req=%d val=%d ind=%d len=%d\n",
 823              current_tick,
 824              req->bRequestType,
 825              req->bRequest,
 826              req->wValue,
 827              req->wIndex,
 828              req->wLength);
 829
 830         usb_core_control_request(&req_copy);
 831         setup_desc_init(&setup_desc);
 832
 833         ep_sts &= ~USB_EP_STAT_SETUP_RCVD;
 834     }
 835
 836     if (ep_sts) {
 837         logf("ep%d OUT, status %x\n", ep, ep_sts);
 838         panicf("ep%d OUT 0x%x", ep, ep_sts);
 839     }
 840
 841     /* HW automatically disables RDE, re-enable it */
 842     /* THEORY: Because we only set up one DMA buffer... */
 843     USB_DEV_CTRL |= USB_DEV_CTRL_RDE;
 844 }
 845
 846 /* interrupt service routine */
 847 void INT_USB(void)
 848 {
 849     int ep = USB_DEV_EP_INTR & ~USB_DEV_EP_INTR_MASK;
 850     int intr = USB_DEV_INTR & ~USB_DEV_INTR_MASK;
 851
 852     /* ACK interrupt sources */
 853     USB_DEV_EP_INTR = ep;
 854     USB_DEV_INTR = intr;
 855
 856     /* Handle endpoint interrupts */
 857     while (ep) {
 858         int onebit = 31-__builtin_clz(ep);
 859
 860         if (onebit < 16) handle_in_ep(onebit);
 861         else handle_out_ep(onebit-16);
 862
 863         ep &= ~(1 << onebit);
 864     }
 865
 866     /* Handle general device interrupts */
 867     if (intr) {
 868         if (intr & USB_DEV_INTR_SET_INTERFACE) {/* SET_INTERFACE received */
 869             logf("set interface\n");
 870             panicf("set interface");
 871             intr &= ~USB_DEV_INTR_SET_INTERFACE;
 872         }
 873         if (intr & USB_DEV_INTR_SET_CONFIG) {/* SET_CONFIGURATION received */
 874             /*
 875              * This is handled in HW, we have to fake a request here
 876              * for usb_core.
 877              */
 878             static struct usb_ctrlrequest set_config = {
 879             bRequestType: USB_TYPE_STANDARD | USB_RECIP_DEVICE,
 880             bRequest: USB_REQ_SET_CONFIGURATION,
 881             wValue: 0,
 882             wIndex: 0,
 883             wLength: 0,
 884             };
 885
 886             logf("set config\n");
 887
 888             set_config.wValue = USB_DEV_STS & USB_DEV_STS_MASK_CFG;
 889             usb_core_control_request(&set_config);
 890
 891             /* Tell the HW we handled the request */
 892             USB_DEV_CTRL |= USB_DEV_CTRL_APCSR_DONE;
 893             intr &= ~USB_DEV_INTR_SET_CONFIG;
 894         }
 895         if (intr & USB_DEV_INTR_EARLY_SUSPEND) {/* idle >3ms detected */
 896             logf("usb idle\n");
 897             intr &= ~USB_DEV_INTR_EARLY_SUSPEND;
 898         }
 899         if (intr & USB_DEV_INTR_USB_RESET) {/* usb reset from host? */
 900             logf("usb reset\n");
 901             reset_endpoints(1);
 902             usb_core_bus_reset();
 903             intr &= ~USB_DEV_INTR_USB_RESET;
 904         }
 905         if (intr & USB_DEV_INTR_USB_SUSPEND) {/* suspend req from host? */
 906             logf("usb suspend\n");
 907             intr &= ~USB_DEV_INTR_USB_SUSPEND;
 908         }
 909         if (intr & USB_DEV_INTR_SOF) {/* sof received */
 910             logf("sof\n");
 911             intr &= ~USB_DEV_INTR_SOF;
 912         }
 913         if (intr & USB_DEV_INTR_ENUM_DONE) {/* speed enumeration complete */
 914             int spd = USB_DEV_STS & USB_DEV_STS_MASK_SPD;  /* Enumerated Speed */
 915
 916             logf("speed enum complete: ");
 917             if (spd == USB_DEV_STS_SPD_HS) logf("hs\n");
 918             if (spd == USB_DEV_STS_SPD_FS) logf("fs\n");
 919             if (spd == USB_DEV_STS_SPD_LS) logf("ls\n");
 920
 921             USB_PHY_EP0_INFO = 0x00200000;
 922             USB_DEV_CTRL |= USB_DEV_CTRL_APCSR_DONE;
 923             USB_IEP_CTRL(0) |= USB_EP_CTRL_ACT;
 924             USB_OEP_CTRL(0) |= USB_EP_CTRL_ACT;
 925             intr &= ~USB_DEV_INTR_ENUM_DONE;
 926         }
 927         if (intr & USB_DEV_INTR_BUSERR) {
 928             panicf("usb dma bus error");
 929             intr &= ~USB_DEV_INTR_BUSERR;
 930         }
 931         if (intr)
 932             panicf("usb devirq 0x%x", intr);
 933     }
 934
 935     if (!(USB_DEV_CTRL & USB_DEV_CTRL_RDE)){
 936         logf("re-enabling receive DMA\n");
 937         USB_DEV_CTRL |= USB_DEV_CTRL_RDE;
 938     }
 939
 940 }
 941
 942 /* (not essential? , not implemented in usb-tcc.c) */
 943 void usb_drv_set_test_mode(int mode)
 944 {
 945     (void)mode;
 946 }
 947
 948 /* handled internally by controller */
 949 void usb_drv_set_address(int address)
 950 {
 951     (void)address;
 952 }
 953
 954 void usb_drv_stall(int ep, bool stall, bool in)
 955 {
 956    if (stall) USB_EP_CTRL(ep, in) |= USB_EP_CTRL_STALL;
 957    else USB_EP_CTRL(ep, in) &= ~USB_EP_CTRL_STALL;
 958 }
 959
 960 bool usb_drv_stalled(int ep, bool in)
 961 {
 962     return USB_EP_CTRL(ep, in) & USB_EP_CTRL_STALL ? true : false;
 963 }
 964
 965 #else
 966
 967 void usb_attach(void)
 968 {
 969 }
 970
 971 void usb_drv_init(void)
 972 {
 973 }
 974
 975 void usb_drv_exit(void)
 976 {
 977 }
 978
 979 int usb_drv_port_speed(void)
 980 {
 981     return 0;
 982 }
 983
 984 int usb_drv_request_endpoint(int type, int dir)
 985 {
 986     (void)type;
 987     (void)dir;
 988
 989     return -1;
 990 }
 991
 992 void usb_drv_release_endpoint(int ep)
 993 {
 994     (void)ep;
 995 }
 996
 997 void usb_drv_cancel_all_transfers(void)
 998 {
 999 }
1000
1001 void usb_drv_set_test_mode(int mode)
1002 {
1003     (void)mode;
1004 }
1005
1006 /* handled internally by controller */
1007 void usb_drv_set_address(int address)
1008 {
1009     (void)address;
1010 }
1011
1012 int usb_drv_recv(int ep, void *ptr, int len)
1013 {
1014     (void)ep;
1015     (void)ptr;
1016     (void)len;
1017
1018     return -1;
1019 }
1020
1021 int usb_drv_send(int ep, void *ptr, int len)
1022 {
1023     (void)ep;
1024     (void)ptr;
1025     (void)len;
1026
1027     return -1;
1028 }
1029
1030 int usb_drv_send_nonblocking(int ep, void *ptr, int len)
1031 {
1032     (void)ep;
1033     (void)ptr;
1034     (void)len;
1035
1036     return -1;
1037 }
1038
1039 void usb_drv_stall(int ep, bool stall, bool in)
1040 {
1041     (void)ep;
1042     (void)stall;
1043     (void)in;
1044 }
1045
1046 bool usb_drv_stalled(int ep, bool in)
1047 {
1048     (void)ep;
1049     (void)in;
1050
1051     return 0;
1052 }
1053
1054 #endif