Also fix Debug->View partitions when SECTOR_SIZE!=512
[kugel-rb.git] / firmware / target / arm / system-target.h
blob764cd18d153b9ac8ba128ea2e49e65685b3e40ff
1 /***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
10 * Copyright (C) 2002 by Alan Korr
11 * Copyright (C) 2007 by Michael Sevakis
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version 2
16 * of the License, or (at your option) any later version.
18 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
19 * KIND, either express or implied.
21 ****************************************************************************/
22 #ifndef SYSTEM_TARGET_H
23 #define SYSTEM_TARGET_H
25 #include "system-arm.h"
27 #ifdef CPU_PP
28 /* TODO: This header is actually portalplayer specific, and should be
29 * moved into an appropriate subdir (or even split in 2). */
31 #if CONFIG_CPU == PP5002
32 #define CPUFREQ_SLEEP 32768
33 #define CPUFREQ_DEFAULT 24000000
34 #define CPUFREQ_NORMAL 30000000
35 #define CPUFREQ_MAX 80000000
37 #else /* PP5022, PP5024 */
38 #define CPUFREQ_SLEEP 32768
39 #define CPUFREQ_DEFAULT 24000000
40 #define CPUFREQ_NORMAL 30000000
41 #define CPUFREQ_MAX 80000000
42 #endif
44 #define inl(a) (*(volatile unsigned long *) (a))
45 #define outl(a,b) (*(volatile unsigned long *) (b) = (a))
46 #define inb(a) (*(volatile unsigned char *) (a))
47 #define outb(a,b) (*(volatile unsigned char *) (b) = (a))
48 #define inw(a) (*(volatile unsigned short *) (a))
49 #define outw(a,b) (*(volatile unsigned short *) (b) = (a))
51 static inline void udelay(unsigned usecs)
53 unsigned stop = USEC_TIMER + usecs;
54 while (TIME_BEFORE(USEC_TIMER, stop));
57 static inline unsigned int current_core(void)
60 * PROCESSOR_ID seems to be 32-bits:
61 * CPU = 0x55555555 = |01010101|01010101|01010101|01010101|
62 * COP = 0xaaaaaaaa = |10101010|10101010|10101010|10101010|
63 * ^
65 unsigned int core;
66 asm volatile (
67 "ldrb %0, [%1] \n" /* Just load the LSB */
68 "mov %0, %0, lsr #7 \n" /* Bit 7 => index */
69 : "=r"(core) /* CPU=0, COP=1 */
70 : "r"(&PROCESSOR_ID)
72 return core;
75 /* Return the actual ID instead of core index */
76 static inline unsigned int processor_id(void)
78 unsigned int id;
80 asm volatile (
81 "ldrb %0, [%1] \n"
82 : "=r"(id)
83 : "r"(&PROCESSOR_ID)
86 return id;
89 #if CONFIG_CPU == PP5002
90 static inline void sleep_core(int core)
92 asm volatile (
93 /* Sleep: PP5002 crashes if the instruction that puts it to sleep is
94 * located at 0xNNNNNNN0. 4/8/C works. This sequence makes sure
95 * that the correct alternative is executed. Don't change the order
96 * of the next 4 instructions! */
97 "tst pc, #0x0c \n"
98 "mov r0, #0xca \n"
99 "strne r0, [%[ctl]] \n"
100 "streq r0, [%[ctl]] \n"
101 "nop \n" /* nop's needed because of pipeline */
102 "nop \n"
103 "nop \n"
105 : [ctl]"r"(&PROC_CTL(core))
106 : "r0"
109 static inline void wake_core(int core)
111 asm volatile (
112 "mov r0, #0xce \n"
113 "str r0, [%[ctl]] \n"
115 : [ctl]"r"(&PROC_CTL(core))
116 : "r0"
119 #else /* PP502x */
120 static inline void sleep_core(int core)
122 asm volatile (
123 "mov r0, #0x80000000 \n"
124 "str r0, [%[ctl]] \n"
125 "nop \n"
127 : [ctl]"r"(&PROC_CTL(core))
128 : "r0"
131 static inline void wake_core(int core)
133 asm volatile (
134 "mov r0, #0 \n"
135 "str r0, [%[ctl]] \n"
137 : [ctl]"r"(&PROC_CTL(core))
138 : "r0"
141 #endif
143 #ifdef BOOTLOADER
144 /* All addresses within rockbox are in IRAM in the bootloader so
145 are therefore uncached */
146 #define UNCACHED_ADDR(a) (a)
148 #else /* !BOOTLOADER */
150 #if CONFIG_CPU == PP5002
151 #define UNCACHED_BASE_ADDR 0x28000000
152 #else /* PP502x */
153 #define UNCACHED_BASE_ADDR 0x10000000
154 #endif
156 #define UNCACHED_ADDR(a) \
157 ((typeof (a))((uintptr_t)(a) | UNCACHED_BASE_ADDR))
158 #endif /* BOOTLOADER */
160 /* Certain data needs to be out of the way of cache line interference
161 * such as data for COP use or for use with UNCACHED_ADDR */
162 #define PROC_NEEDS_CACHEALIGN
163 #define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */
165 /** cache functions **/
166 #ifndef BOOTLOADER
167 #define HAVE_CPUCACHE_INVALIDATE
168 #define HAVE_CPUCACHE_FLUSH
169 #endif
171 #endif /* CPU_PP */
173 #endif /* SYSTEM_TARGET_H */