firmware/export/mc13783.h

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (c) 2008 by Michael Sevakis
  11  *
  12  * All files in this archive are subject to the GNU General Public License.
  13  * See the file COPYING in the source tree root for full license agreement.
  14  *
  15  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  16  * KIND, either express or implied.
  17  *
  18  ****************************************************************************/
  19 #ifndef _MC13783_H_
  20 #define _MC13783_H_
  21
  22 enum mc13783_regs_enum
  23 {
  24     MC13783_INTERRUPT_STATUS0 = 0x00,
  25     MC13783_INTERRUPT_MASK0,
  26     MC13783_INTERRUPT_SENSE0,
  27     MC13783_INTERRUPT_STATUS1,
  28     MC13783_INTERRUPT_MASK1,
  29     MC13783_INTERRUPT_SENSE1,
  30     MC13783_POWER_UP_MODE_SENSE,
  31     MC13783_IDENTIFICATION,
  32     MC13783_SEMAPHORE,
  33     MC13783_ARBITRATION_PERIPHERAL_AUDIO,
  34     MC13783_ARBITRATION_SWITCHERS,
  35     MC13783_ARBITRATION_REGULATORS0,
  36     MC13783_ARBITRATION_REGULATORS1,
  37     MC13783_POWER_CONTROL0,
  38     MC13783_POWER_CONTROL1,
  39     MC13783_POWER_CONTROL2,
  40     MC13783_REGEN_ASSIGNMENT,
  41     MC13783_CONTROL_SPARE,
  42     MC13783_MEMORYA,
  43     MC13783_MEMORYB,
  44     MC13783_RTC_TIME,
  45     MC13783_RTC_ALARM,
  46     MC13783_RTC_DAY,
  47     MC13783_RTC_DAY_ALARM,
  48     MC13783_SWITCHERS0,
  49     MC13783_SWITCHERS1,
  50     MC13783_SWITCHERS2,
  51     MC13783_SWITCHERS3,
  52     MC13783_SWITCHERS4,
  53     MC13783_SWITCHERS5,
  54     MC13783_REGULATOR_SETTING0,
  55     MC13783_REGULATOR_SETTING1,
  56     MC13783_REGULATOR_MODE0,
  57     MC13783_REGULATOR_MODE1,
  58     MC13783_POWER_MISCELLANEOUS,
  59     MC13783_POWER_SPARE,
  60     MC13783_AUDIO_RX0,
  61     MC13783_AUDIO_RX1,
  62     MC13783_AUDIO_TX,
  63     MC13783_SSI_NETWORK,
  64     MC13783_AUDIO_CODEC,
  65     MC13783_AUDIO_STEREO_CODEC,
  66     MC13783_AUDIO_SPARE,
  67     MC13783_ADC0,
  68     MC13783_ADC1,
  69     MC13783_ADC2,
  70     MC13783_ADC3,
  71     MC13783_ADC4,
  72     MC13783_CHARGER,
  73     MC13783_USB0,
  74     MC13783_CHARGER_USB1,
  75     MC13783_LED_CONTROL0,
  76     MC13783_LED_CONTROL1,
  77     MC13783_LED_CONTROL2,
  78     MC13783_LED_CONTROL3,
  79     MC13783_LED_CONTROL4,
  80     MC13783_LED_CONTROL5,
  81     MC13783_SPARE,
  82     MC13783_TRIM0,
  83     MC13783_TRIM1,
  84     MC13783_TEST0,
  85     MC13783_TEST1,
  86     MC13783_TEST2,
  87     MC13783_TEST3,
  88     MC13783_NUM_REGS,
  89 };
  90
  91 /* INTERRUPT_STATUS0, INTERRUPT_MASK0, INTERRUPT_SENSE0 */
  92 #define MC13783_ADCDONE     (1 << 0)  /* x */
  93 #define MC13783_ADCBISDONE  (1 << 1)  /* x */
  94 #define MC13783_TS          (1 << 2)  /* x */
  95 #define MC13783_WHIGH       (1 << 3)  /* x */
  96 #define MC13783_WLOW        (1 << 4)  /* x */
  97 #define MC13783_CHGDET      (1 << 6)
  98 #define MC13783_CHGOV       (1 << 7)
  99 #define MC13783_CHGREV      (1 << 8)
 100 #define MC13783_CHGSHORT    (1 << 9)
 101 #define MC13783_CCCV        (1 << 10)
 102 #define MC13783_CHGCURR     (1 << 11)
 103 #define MC13783_BPONI       (1 << 12)
 104 #define MC13783_LOBATL      (1 << 13)
 105 #define MC13783_LOBATH      (1 << 14)
 106 #define MC13783_UDP         (1 << 15)
 107 #define MC13783_USB4V4      (1 << 16)
 108 #define MC13783_USB2V0      (1 << 17)
 109 #define MC13783_USB0V8      (1 << 18)
 110 #define MC13783_IDFLOAT     (1 << 19)
 111 #define MC13783_SE1         (1 << 21)
 112 #define MC13783_CKDET       (1 << 22)
 113 #define MC13783_UDM         (1 << 23)
 114 /* x = no sense bit */
 115
 116 /* INTERRUPT_STATUS1, INTERRUPT_MASK1, INTERRUPT_SENSE1 */
 117 #define MC13783_1HZ         (1 << 0)  /* x */
 118 #define MC13783_TODA        (1 << 1)  /* x */
 119 #define MC13783_ONOFD1      (1 << 3)  /* ON1B */
 120 #define MC13783_ONOFD2      (1 << 4)  /* ON2B */
 121 #define MC13783_ONOFD3      (1 << 5)  /* ON3B */
 122 #define MC13783_SYSRST      (1 << 6)  /* x */
 123 #define MC13783_RTCRST      (1 << 7)  /* x */
 124 #define MC13783_PCI         (1 << 8)  /* x */
 125 #define MC13783_WARM        (1 << 9)  /* x */
 126 #define MC13783_MEMHLD      (1 << 10) /* x */
 127 #define MC13783_PWRRDY      (1 << 11)
 128 #define MC13783_THWARNL     (1 << 12)
 129 #define MC13783_THWARNH     (1 << 13)
 130 #define MC13783_CLK         (1 << 14)
 131 #define MC13783_SEMAF       (1 << 15) /* x */
 132 #define MC13783_MC2B        (1 << 17)
 133 #define MC13783_HSDET       (1 << 18)
 134 #define MC13783_HSL         (1 << 19)
 135 #define MC13783_ALSPTH      (1 << 20)
 136 #define MC13783_AHSSHORT    (1 << 21)
 137 /* x = no sense bit */
 138
 139 /* POWER_UP_MODE_SENSE */
 140
 141 #define MC13783_ICTESTS     (1 << 0)
 142 #define MC13783_CLKSELS     (1 << 1)
 143 #define MC13783_PUMS1Sr(r)  (((r) >> 2) & 0x3)
 144 #define MC13783_PUMS2S      (((r) >> 4) & 0x3)
 145 #define MC13783_PUMS3S      (((r) >> 6) & 0x3)
 146     #define PUMS_LOW        0x0
 147     #define PUMS_OPEN       0x1
 148     #define PUMS_HIGH       0x2
 149 #define MC13783_CHRGMOD0Sr(r) (((r) >> 8) & 0x3)
 150 #define MC13783_CHRGMOD1Sr(r) (((r) >> 10) & 0x3)
 151     #define CHRGMOD_LOW     0x0
 152     #define CHRGMOD_OPEN    0x1
 153     #define CHRGMOD_HIGH    0x3
 154 #define MC13783_UMODSr(r)   (((r) >> 12) & 0x3)
 155     #define UMODS0_LOW_UMODS1_LOW       0x0
 156     #define UMODS0_OPEN_UMODS1_LOW      0x1
 157     #define UMODS0_DONTCARE_UMODS1_HIGH 0x2
 158     #define UMODS0_HIGH_UMODS1_LOW      0x3
 159 #define MC13783_USBEN       (1 << 14)
 160 #define MC13783_SW1ABS      (1 << 15)
 161 #define MC13783_SW2ABS      (1 << 16)
 162
 163 /* IDENTIFICATION */
 164 /* SEMAPHORE */
 165 /* ARBITRATION_PERIPHERAL_AUDIO */
 166 /* ARBITRATION_SWITCHERS */
 167 /* ARBITRATION_REGULATORS0 */
 168 /* ARBITRATION_REGULATORS1 */
 169
 170 /* POWER_CONTROL0 */
 171 #define MC13783_USEROFFSPI  (1 << 3)
 172
 173 /* POWER_CONTROL1 */
 174 /* POWER_CONTROL2 */
 175 /* REGEN_ASSIGNMENT */
 176 /* MEMORYA */
 177 /* MEMORYB */
 178 /* RTC_TIME */
 179 /* RTC_ALARM */
 180 /* RTC_DAY */
 181 /* RTC_DAY_ALARM */
 182 /* SWITCHERS0 */
 183 /* SWITCHERS1 */
 184 /* SWITCHERS2 */
 185 /* SWITCHERS3 */
 186 /* SWITCHERS4 */
 187 /* SWITCHERS5 */
 188 /* REGULATOR_SETTING0 */
 189 /* REGULATOR_SETTING1 */
 190 /* REGULATOR_MODE0 */
 191 /* REGULATOR_MODE1 */
 192 /* POWER_MISCELLANEOUS */
 193 /* AUDIO_RX0 */
 194 /* AUDIO_RX1 */
 195 /* AUDIO_TX */
 196 /* SSI_NETWORK */
 197 /* AUDIO_CODEC */
 198 /* AUDIO_STEREO_CODEC */
 199
 200 /* ADC0 */
 201 #define MC13783_LICELLCON   (1 << 0)
 202 #define MC13783_CHRGICON    (1 << 1)
 203 #define MC13783_BATICON     (1 << 2)
 204 #define MC13783_RTHEN       (1 << 3)
 205 #define MC13783_DTHEN       (1 << 4)
 206 #define MC13783_UIDEN       (1 << 5)
 207 #define MC13783_ADOUTEN     (1 << 6)
 208 #define MC13783_ADOUTPER    (1 << 7)
 209 #define MC13783_ADREFEN     (1 << 10)
 210 #define MC13783_ADREFMODE   (1 << 11)
 211 #define MC13783_TSMODw(w)   ((w) << 12)
 212 #define MC13783_TSMODr(r)   (((r) >> 12) & 0x3)
 213 #define MC13783_CHRGRAWDIV  (1 << 15)
 214 #define MC13783_ADINC1      (1 << 16)
 215 #define MC13783_ADINC2      (1 << 17)
 216 #define MC13783_WCOMP       (1 << 18)
 217 #define MC13783_ADCBIS0     (1 << 23)
 218
 219 /* ADC1 */
 220 #define MC13783_ADEN        (1 << 0)
 221 #define MC13783_RAND        (1 << 1)
 222 #define MC13783_ADSEL       (1 << 3)
 223 #define MC13783_TRIGMASK    (1 << 4)
 224 #define MC13783_ADA1w(w)    ((w) << 5)
 225 #define MC13783_ADA1r(r)    (((r) >> 5) & 0x3)
 226 #define MC13783_ADA2w(w)    ((w) << 8)
 227 #define MC13783_ADA2r(r)    (((r) >> 8) & 0x3)
 228 #define MC13783_ATOw(w)     ((w) << 11)
 229 #define MC13783_ATOr(r)     (((r) >> 11) & 0xff)
 230 #define MC13783_ATOX        (1 << 19)
 231 #define MC13783_ASC         (1 << 20)
 232 #define MC13783_ADTRIGIGN   (1 << 21)
 233 #define MC13783_ADONESHOT   (1 << 22)
 234 #define MC13783_ADCBIS1     (1 << 23)
 235
 236 /* ADC2 */
 237 #define MC13783_ADD1r(r)    (((r) >> 2) & 0x3ff)
 238 #define MC13783_ADD2r(r)    (((r) >> 14) & 0x3ff)
 239
 240 /* ADC3 */
 241 #define MC13783_WHIGHw(w)   ((w) << 0)
 242 #define MC13783_WHIGHr(r)   ((r) & 0x3f)
 243 #define MC13783_ICIDr(r)    (((r) >> 6) & 0x3)
 244 #define MC13783_WLOWw(w)    ((w) << 9)
 245 #define MC13783_WLOWr(r)    (((r) >> 9) & 0x3f)
 246 #define MC13783_ADCBIS2     (1 << 23)
 247
 248 /* ADC4 */
 249 #define MC13783_ADCBIS1r(r) (((r) >> 2) & 0x3ff)
 250 #define MC13783_ADCBIS2r(r) (((r) >> 14) & 0x3ff)
 251
 252 /* CHARGER */
 253 /* USB0 */
 254 /* CHARGER_USB1 */
 255
 256 /* LED_CONTROL0 */
 257 #define MC13783_LEDEN       (1 << 0)
 258
 259 /* LED_CONTROL1 */
 260 /* LED_CONTROL2 */
 261 /* LED_CONTROL3 */
 262 /* LED_CONTROL4 */
 263 /* LED_CONTROL5 */
 264 /* TRIM0 */
 265 /* TRIM1 */
 266 /* TEST0 */
 267 /* TEST1 */
 268 /* TEST2 */
 269 /* TEST3 */
 270
 271 void mc13783_init(void);
 272 uint32_t mc13783_set(unsigned address, uint32_t bits);
 273 uint32_t mc13783_clear(unsigned address, uint32_t bits);
 274 int mc13783_write(unsigned address, uint32_t data);
 275 int mc13783_write_multiple(unsigned start, const uint32_t *buffer, int count);
 276 int mc13783_write_regset(const unsigned char *regs, const uint32_t *data, int count);
 277 uint32_t mc13783_read(unsigned address);
 278 int mc13783_read_multiple(unsigned start, uint32_t *buffer, int count);
 279 int mc13783_read_regset(const unsigned char *regs, uint32_t *buffer, int count);
 280
 281 #endif /* _MC13783_H_ */