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Nano2G NAND interleaved erase support
[kugel-rb.git] / firmware / target / arm / s5l8700 / ipodnano2g / nand-nano2g.c
blobba1f0df534b5247ce6ea2db1671a2d56bd68a02f
1 /***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2009 by Michael Sparmann
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
16 *
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
19 *
20 ****************************************************************************/
21
22
23 #include "config.h"
24 #include "panic.h"
25 #include "system.h"
26 #include "kernel.h"
27 #include "cpu.h"
28 #include "inttypes.h"
29 #include "nand-target.h"
30 #include <pmu-target.h>
31 #include <mmu-target.h>
32 #include <string.h>
33 #include "led.h"
34
35
36 #define NAND_CMD_READ 0x00
37 #define NAND_CMD_PROGCNFRM 0x10
38 #define NAND_CMD_READ2 0x30
39 #define NAND_CMD_BLOCKERASE 0x60
40 #define NAND_CMD_GET_STATUS 0x70
41 #define NAND_CMD_PROGRAM 0x80
42 #define NAND_CMD_ERASECNFRM 0xD0
43 #define NAND_CMD_RESET 0xFF
44
45 #define NAND_STATUS_READY 0x40
46
47 #define NAND_DEVICEINFOTABLE_ENTRIES 33
48
49 static const struct nand_device_info_type nand_deviceinfotable[] =
50 {
51 {0x1580F1EC, 1024, 968, 0x40, 6, 2, 1, 2, 1},
52 {0x1580DAEC, 2048, 1936, 0x40, 6, 2, 1, 2, 1},
53 {0x15C1DAEC, 2048, 1936, 0x40, 6, 2, 1, 2, 1},
54 {0x1510DCEC, 4096, 3872, 0x40, 6, 2, 1, 2, 1},
55 {0x95C1DCEC, 4096, 3872, 0x40, 6, 2, 1, 2, 1},
56 {0x2514DCEC, 2048, 1936, 0x80, 7, 2, 1, 2, 1},
57 {0x2514D3EC, 4096, 3872, 0x80, 7, 2, 1, 2, 1},
58 {0x2555D3EC, 4096, 3872, 0x80, 7, 2, 1, 2, 1},
59 {0x2555D5EC, 8192, 7744, 0x80, 7, 2, 1, 2, 1},
60 {0x2585D3AD, 4096, 3872, 0x80, 7, 3, 2, 3, 2},
61 {0x9580DCAD, 4096, 3872, 0x40, 6, 3, 2, 3, 2},
62 {0xA514D3AD, 4096, 3872, 0x80, 7, 3, 2, 3, 2},
63 {0xA550D3AD, 4096, 3872, 0x80, 7, 3, 2, 3, 2},
64 {0xA560D5AD, 4096, 3872, 0x80, 7, 3, 2, 3, 2},
65 {0xA555D5AD, 8192, 7744, 0x80, 7, 3, 2, 3, 2},
66 {0xA585D598, 8320, 7744, 0x80, 7, 3, 1, 2, 1},
67 {0xA584D398, 4160, 3872, 0x80, 7, 3, 1, 2, 1},
68 {0x95D1D32C, 8192, 7744, 0x40, 6, 2, 1, 2, 1},
69 {0x1580DC2C, 4096, 3872, 0x40, 6, 2, 1, 2, 1},
70 {0x15C1D32C, 8192, 7744, 0x40, 6, 2, 1, 2, 1},
71 {0x9590DC2C, 4096, 3872, 0x40, 6, 2, 1, 2, 1},
72 {0xA594D32C, 4096, 3872, 0x80, 7, 2, 1, 2, 1},
73 {0x2584DC2C, 2048, 1936, 0x80, 7, 2, 1, 2, 1},
74 {0xA5D5D52C, 8192, 7744, 0x80, 7, 3, 2, 2, 1},
75 {0x95D1D389, 8192, 7744, 0x40, 6, 2, 1, 2, 1},
76 {0x1580DC89, 4096, 3872, 0x40, 6, 2, 1, 2, 1},
77 {0x15C1D389, 8192, 7744, 0x40, 6, 2, 1, 2, 1},
78 {0x9590DC89, 4096, 3872, 0x40, 6, 2, 1, 2, 1},
79 {0xA594D389, 4096, 3872, 0x80, 7, 2, 1, 2, 1},
80 {0x2584DC89, 2048, 1936, 0x80, 7, 2, 1, 2, 1},
81 {0xA5D5D589, 8192, 7744, 0x80, 7, 2, 1, 2, 1},
82 {0xA514D320, 4096, 3872, 0x80, 7, 2, 1, 2, 1},
83 {0xA555D520, 8192, 3872, 0x80, 7, 2, 1, 2, 1}
84 };
85
86 uint8_t nand_tunk1[4];
87 uint8_t nand_twp[4];
88 uint8_t nand_tunk2[4];
89 uint8_t nand_tunk3[4];
90 uint32_t nand_type[4];
91 int nand_powered = 0;
92 long nand_last_activity_value = -1;
93 static long nand_stack[32];
94
95 static struct mutex nand_mtx;
96 static struct wakeup nand_wakeup;
97 static struct mutex ecc_mtx;
98 static struct wakeup ecc_wakeup;
99
100 static uint8_t nand_data[0x800] __attribute__((aligned(16)));
101 static uint8_t nand_ctrl[0x200] __attribute__((aligned(16)));
102 static uint8_t nand_spare[0x40] __attribute__((aligned(16)));
103 static uint8_t nand_ecc[0x30] __attribute__((aligned(16)));
104
105
106 uint32_t nand_unlock(uint32_t rc)
107 {
108 led(false);
109 nand_last_activity_value = current_tick;
110 mutex_unlock(&nand_mtx);
111 return rc;
112 }
113
114 uint32_t ecc_unlock(uint32_t rc)
115 {
116 mutex_unlock(&ecc_mtx);
117 return rc;
118 }
119
120 uint32_t nand_timeout(long timeout)
121 {
122 if (TIME_AFTER(current_tick, timeout)) return 1;
123 else
124 {
125 yield();
126 return 0;
127 }
128 }
129
130 uint32_t nand_wait_rbbdone(void)
131 {
132 long timeout = current_tick + HZ / 50;
133 while (!(FMCSTAT & FMCSTAT_RBBDONE))
134 if (nand_timeout(timeout)) return 1;
135 FMCSTAT = FMCSTAT_RBBDONE;
136 return 0;
137 }
138
139 uint32_t nand_wait_cmddone(void)
140 {
141 long timeout = current_tick + HZ / 50;
142 while (!(FMCSTAT & FMCSTAT_CMDDONE))
143 if (nand_timeout(timeout)) return 1;
144 FMCSTAT = FMCSTAT_CMDDONE;
145 return 0;
146 }
147
148 uint32_t nand_wait_addrdone(void)
149 {
150 long timeout = current_tick + HZ / 50;
151 while (!(FMCSTAT & FMCSTAT_ADDRDONE))
152 if (nand_timeout(timeout)) return 1;
153 FMCSTAT = FMCSTAT_ADDRDONE;
154 return 0;
155 }
156
157 uint32_t nand_wait_chip_ready(uint32_t bank)
158 {
159 long timeout = current_tick + HZ / 50;
160 while (!(FMCSTAT & (FMCSTAT_BANK0READY << bank)))
161 if (nand_timeout(timeout)) return 1;
162 FMCSTAT = (FMCSTAT_BANK0READY << bank);
163 return 0;
164 }
165
166 void nand_set_fmctrl0(uint32_t bank, uint32_t flags)
167 {
168 FMCTRL0 = (nand_tunk1[bank] << 16) | (nand_twp[bank] << 12)
169 | (1 << 11) | 1 | (1 << (bank + 1)) | flags;
170 }
171
172 uint32_t nand_send_cmd(uint32_t cmd)
173 {
174 FMCMD = cmd;
175 return nand_wait_rbbdone();
176 }
177
178 uint32_t nand_send_address(uint32_t page, uint32_t offset)
179 {
180 FMANUM = 4;
181 FMADDR0 = (page << 16) | offset;
182 FMADDR1 = (page >> 16) & 0xFF;
183 FMCTRL1 = FMCTRL1_DOTRANSADDR;
184 return nand_wait_cmddone();
185 }
186
187 uint32_t nand_reset(uint32_t bank)
188 {
189 nand_set_fmctrl0(bank, 0);
190 if (nand_send_cmd(NAND_CMD_RESET)) return 1;
191 if (nand_wait_chip_ready(bank)) return 1;
192 FMCTRL1 = FMCTRL1_CLEARRFIFO | FMCTRL1_CLEARWFIFO;
193 sleep(0);
194 return 0;
195 }
196
197 uint32_t nand_wait_status_ready(uint32_t bank)
198 {
199 long timeout = current_tick + HZ / 50;
200 nand_set_fmctrl0(bank, 0);
201 if ((FMCSTAT & (FMCSTAT_BANK0READY << bank)))
202 FMCSTAT = (FMCSTAT_BANK0READY << bank);
203 FMCTRL1 = FMCTRL1_CLEARRFIFO;
204 if (nand_send_cmd(NAND_CMD_GET_STATUS)) return 1;
205 while (1)
206 {
207 if (nand_timeout(timeout)) return 1;
208 FMDNUM = 0;
209 FMCTRL1 = FMCTRL1_DOREADDATA;
210 if (nand_wait_addrdone()) return 1;
211 if ((FMFIFO & NAND_STATUS_READY)) break;
212 FMCTRL1 = FMCTRL1_CLEARRFIFO;
213 }
214 FMCTRL1 = FMCTRL1_CLEARRFIFO;
215 return nand_send_cmd(NAND_CMD_READ);
216 }
217
218 void nand_transfer_data_start(uint32_t bank, uint32_t direction,
219 void* buffer, uint32_t size)
220 {
221 nand_set_fmctrl0(bank, FMCTRL0_ENABLEDMA);
222 FMDNUM = size - 1;
223 FMCTRL1 = FMCTRL1_DOREADDATA << direction;
224 DMACON3 = (2 << DMACON_DEVICE_SHIFT)
225 | (direction << DMACON_DIRECTION_SHIFT)
226 | (2 << DMACON_DATA_SIZE_SHIFT)
227 | (3 << DMACON_BURST_LEN_SHIFT);
228 while ((DMAALLST & DMAALLST_CHAN3_MASK))
229 DMACOM3 = DMACOM_CLEARBOTHDONE;
230 DMABASE3 = (uint32_t)buffer;
231 DMATCNT3 = (size >> 4) - 1;
232 clean_dcache();
233 DMACOM3 = 4;
234 }
235
236 uint32_t nand_transfer_data_collect(uint32_t direction)
237 {
238 long timeout = current_tick + HZ / 50;
239 while ((DMAALLST & DMAALLST_DMABUSY3))
240 if (nand_timeout(timeout)) return 1;
241 if (!direction) invalidate_dcache();
242 if (nand_wait_addrdone()) return 1;
243 if (!direction) FMCTRL1 = FMCTRL1_CLEARRFIFO | FMCTRL1_CLEARWFIFO;
244 else FMCTRL1 = FMCTRL1_CLEARRFIFO;
245 return 0;
246 }
247
248 uint32_t nand_transfer_data(uint32_t bank, uint32_t direction,
249 void* buffer, uint32_t size)
250 {
251 nand_transfer_data_start(bank, direction, buffer, size);
252 uint32_t rc = nand_transfer_data_collect(direction);
253 return rc;
254 }
255
256 void ecc_start(uint32_t size, void* databuffer, void* sparebuffer, uint32_t type)
257 {
258 mutex_lock(&ecc_mtx);
259 ECC_INT_CLR = 1;
260 SRCPND = INTMSK_ECC;
261 ECC_UNK1 = size;
262 ECC_DATA_PTR = (uint32_t)databuffer;
263 ECC_SPARE_PTR = (uint32_t)sparebuffer;
264 clean_dcache();
265 ECC_CTRL = type;
266 }
267
268 uint32_t ecc_collect(void)
269 {
270 long timeout = current_tick + HZ / 50;
271 while (!(SRCPND & INTMSK_ECC))
272 if (nand_timeout(timeout)) return ecc_unlock(1);
273 invalidate_dcache();
274 ECC_INT_CLR = 1;
275 SRCPND = INTMSK_ECC;
276 return ecc_unlock(ECC_RESULT);
277 }
278
279 uint32_t ecc_decode(uint32_t size, void* databuffer, void* sparebuffer)
280 {
281 ecc_start(size, databuffer, sparebuffer, ECCCTRL_STARTDECODING);
282 uint32_t rc = ecc_collect();
283 return rc;
284 }
285
286 uint32_t ecc_encode(uint32_t size, void* databuffer, void* sparebuffer)
287 {
288 ecc_start(size, databuffer, sparebuffer, ECCCTRL_STARTENCODING);
289 ecc_collect();
290 return 0;
291 }
292
293 uint32_t nand_check_empty(uint8_t* buffer)
294 {
295 uint32_t i, count;
296 count = 0;
297 for (i = 0; i < 0x40; i++) if (buffer[i] != 0xFF) count++;
298 if (count < 2) return 1;
299 return 0;
300 }
301
302 uint32_t nand_get_chip_type(uint32_t bank)
303 {
304 mutex_lock(&nand_mtx);
305 uint32_t result;
306 if (nand_reset(bank)) return nand_unlock(0xFFFFFFFF);
307 if (nand_send_cmd(0x90)) return nand_unlock(0xFFFFFFFF);
308 FMANUM = 0;
309 FMADDR0 = 0;
310 FMCTRL1 = FMCTRL1_DOTRANSADDR;
311 if (nand_wait_cmddone()) return nand_unlock(0xFFFFFFFF);
312 FMDNUM = 4;
313 FMCTRL1 = FMCTRL1_DOREADDATA;
314 if (nand_wait_addrdone()) return nand_unlock(0xFFFFFFFF);
315 result = FMFIFO;
316 FMCTRL1 = FMCTRL1_CLEARRFIFO;
317 return nand_unlock(result);
318 }
319
320 void nand_set_active(void)
321 {
322 nand_last_activity_value = current_tick;
323 }
324
325 long nand_last_activity(void)
326 {
327 return nand_last_activity_value;
328 }
329
330 void nand_power_up(void)
331 {
332 uint32_t i;
333 mutex_lock(&nand_mtx);
334 nand_last_activity_value = current_tick;
335 PWRCONEXT &= ~0x40;
336 PWRCON &= ~0x100000;
337 PCON2 = 0x33333333;
338 PDAT2 = 0;
339 PCON3 = 0x11113333;
340 PDAT3 = 0;
341 PCON4 = 0x33333333;
342 PDAT4 = 0;
343 PCON5 = (PCON5 & ~0xF) | 3;
344 PUNK5 = 1;
345 pmu_ldo_set_voltage(4, 0x15);
346 pmu_ldo_power_on(4);
347 sleep(HZ / 20);
348 nand_last_activity_value = current_tick;
349 for (i = 0; i < 4; i++)
350 {
351 if(nand_type[i] != 0xFFFFFFFF)
352 {
353 if(nand_reset(i))
354 panicf("nand_power_up: nand_reset(bank=%d) failed.",(unsigned int)i);
355 }
356 }
357 nand_powered = 1;
358 nand_last_activity_value = current_tick;
359 mutex_unlock(&nand_mtx);
360 }
361
362 void nand_power_down(void)
363 {
364 if (!nand_powered) return;
365 mutex_lock(&nand_mtx);
366 pmu_ldo_power_off(4);
367 PCON2 = 0x11111111;
368 PDAT2 = 0;
369 PCON3 = 0x11111111;
370 PDAT3 = 0;
371 PCON4 = 0x11111111;
372 PDAT4 = 0;
373 PCON5 = (PCON5 & ~0xF) | 1;
374 PUNK5 = 1;
375 PWRCONEXT |= 0x40;
376 PWRCON |= 0x100000;
377 nand_powered = 0;
378 mutex_unlock(&nand_mtx);
379 }
380
381 uint32_t nand_read_page(uint32_t bank, uint32_t page, void* databuffer,
382 void* sparebuffer, uint32_t doecc,
383 uint32_t checkempty)
384 {
385 uint8_t* data = nand_data;
386 uint8_t* spare = nand_spare;
387 if (databuffer && !((uint32_t)databuffer & 0xf))
388 data = (uint8_t*)databuffer;
389 if (sparebuffer && !((uint32_t)sparebuffer & 0xf))
390 spare = (uint8_t*)sparebuffer;
391 mutex_lock(&nand_mtx);
392 nand_last_activity_value = current_tick;
393 led(true);
394 if (!nand_powered) nand_power_up();
395 uint32_t rc, eccresult;
396 nand_set_fmctrl0(bank, FMCTRL0_ENABLEDMA);
397 if (nand_send_cmd(NAND_CMD_READ)) return nand_unlock(1);
398 if (nand_send_address(page, databuffer ? 0 : 0x800))
399 return nand_unlock(1);
400 if (nand_send_cmd(NAND_CMD_READ2)) return nand_unlock(1);
401 if (nand_wait_status_ready(bank)) return nand_unlock(1);
402 if (databuffer)
403 if (nand_transfer_data(bank, 0, data, 0x800))
404 return nand_unlock(1);
405 rc = 0;
406 if (!doecc)
407 {
408 if (databuffer && data != databuffer) memcpy(databuffer, data, 0x800);
409 if (sparebuffer)
410 {
411 if (nand_transfer_data(bank, 0, spare, 0x40))
412 return nand_unlock(1);
413 if (sparebuffer && spare != sparebuffer)
414 memcpy(sparebuffer, spare, 0x800);
415 if (checkempty)
416 rc = nand_check_empty((uint8_t*)sparebuffer) << 1;
417 }
418 return nand_unlock(rc);
419 }
420 if (nand_transfer_data(bank, 0, spare, 0x40)) return nand_unlock(1);
421 if (databuffer)
422 {
423 memcpy(nand_ecc, &spare[0xC], 0x28);
424 rc |= (ecc_decode(3, data, nand_ecc) & 0xF) << 4;
425 if (data != databuffer) memcpy(databuffer, data, 0x800);
426 }
427 memset(nand_ctrl, 0xFF, 0x200);
428 memcpy(nand_ctrl, spare, 0xC);
429 memcpy(nand_ecc, &spare[0x34], 0xC);
430 eccresult = ecc_decode(0, nand_ctrl, nand_ecc);
431 rc |= (eccresult & 0xF) << 8;
432 if (sparebuffer)
433 {
434 if (spare != sparebuffer) memcpy(sparebuffer, spare, 0x40);
435 if (eccresult & 1) memset(sparebuffer, 0xFF, 0xC);
436 else memcpy(sparebuffer, nand_ctrl, 0xC);
437 }
438 if (checkempty) rc |= nand_check_empty(spare) << 1;
439
440 return nand_unlock(rc);
441 }
442
443 uint32_t nand_write_page_int(uint32_t bank, uint32_t page, void* databuffer,
444 void* sparebuffer, uint32_t doecc, uint32_t wait)
445 {
446 uint8_t* data = nand_data;
447 uint8_t* spare = nand_spare;
448 if (databuffer && !((uint32_t)databuffer & 0xf))
449 data = (uint8_t*)databuffer;
450 if (sparebuffer && !((uint32_t)sparebuffer & 0xf))
451 spare = (uint8_t*)sparebuffer;
452 mutex_lock(&nand_mtx);
453 nand_last_activity_value = current_tick;
454 led(true);
455 if (!nand_powered) nand_power_up();
456 if (sparebuffer)
457 {
458 if (spare != sparebuffer) memcpy(spare, sparebuffer, 0x40);
459 }
460 else memset(spare, 0xFF, 0x40);
461 nand_set_fmctrl0(bank, FMCTRL0_ENABLEDMA);
462 if (nand_send_cmd(NAND_CMD_PROGRAM)) return nand_unlock(1);
463 if (nand_send_address(page, databuffer ? 0 : 0x800))
464 return nand_unlock(1);
465 if (databuffer && data != databuffer) memcpy(data, databuffer, 0x800);
466 if (databuffer) nand_transfer_data_start(bank, 1, data, 0x800);
467 if (doecc)
468 {
469 if (ecc_encode(3, data, nand_ecc)) return nand_unlock(1);
470 memcpy(&spare[0xC], nand_ecc, 0x28);
471 memset(nand_ctrl, 0xFF, 0x200);
472 memcpy(nand_ctrl, spare, 0xC);
473 if (ecc_encode(0, nand_ctrl, nand_ecc)) return nand_unlock(1);
474 memcpy(&spare[0x34], nand_ecc, 0xC);
475 }
476 if (databuffer)
477 if (nand_transfer_data_collect(1))
478 return nand_unlock(1);
479 if (sparebuffer || doecc)
480 if (nand_transfer_data(bank, 1, spare, 0x40))
481 return nand_unlock(1);
482 if (nand_send_cmd(NAND_CMD_PROGCNFRM)) return nand_unlock(1);
483 if (wait) if (nand_wait_status_ready(bank)) return nand_unlock(1);
484 return nand_unlock(0);
485 }
486
487 uint32_t nand_block_erase(uint32_t bank, uint32_t page)
488 {
489 mutex_lock(&nand_mtx);
490 nand_last_activity_value = current_tick;
491 led(true);
492 if (!nand_powered) nand_power_up();
493 nand_set_fmctrl0(bank, 0);
494 if (nand_send_cmd(NAND_CMD_BLOCKERASE)) return nand_unlock(1);
495 FMANUM = 2;
496 FMADDR0 = page;
497 FMCTRL1 = FMCTRL1_DOTRANSADDR;
498 if (nand_wait_cmddone()) return nand_unlock(1);
499 if (nand_send_cmd(NAND_CMD_ERASECNFRM)) return nand_unlock(1);
500 if (nand_wait_status_ready(bank)) return nand_unlock(1);
501 return nand_unlock(0);
502 }
503
504 uint32_t nand_read_page_fast(uint32_t page, void* databuffer,
505 void* sparebuffer, uint32_t doecc,
506 uint32_t checkempty)
507 {
508 uint32_t i, rc = 0;
509 if (((uint32_t)databuffer & 0xf) || ((uint32_t)sparebuffer & 0xf)
510 || !databuffer || !sparebuffer || !doecc)
511 {
512 for (i = 0; i < 4; i++)
513 {
514 if (nand_type[i] == 0xFFFFFFFF) continue;
515 void* databuf = (void*)0;
516 void* sparebuf = (void*)0;
517 if (databuffer) databuf = (void*)((uint32_t)databuffer + 0x800 * i);
518 if (sparebuffer) sparebuf = (void*)((uint32_t)sparebuffer + 0x40 * i);
519 uint32_t ret = nand_read_page(i, page, databuf, sparebuf, doecc, checkempty);
520 if (ret & 1) rc |= 1 << (i << 2);
521 if (ret & 2) rc |= 2 << (i << 2);
522 if (ret & 0x10) rc |= 4 << (i << 2);
523 if (ret & 0x100) rc |= 8 << (i << 2);
524 }
525 return rc;
526 }
527 mutex_lock(&nand_mtx);
528 nand_last_activity_value = current_tick;
529 led(true);
530 if (!nand_powered) nand_power_up();
531 for (i = 0; i < 4; i++)
532 {
533 if (nand_type[i] == 0xFFFFFFFF) continue;
534 nand_set_fmctrl0(i, FMCTRL0_ENABLEDMA);
535 if (nand_send_cmd(NAND_CMD_READ))
536 {
537 rc |= 1 << (i << 2);
538 continue;
539 }
540 if (nand_send_address(page, databuffer ? 0 : 0x800))
541 {
542 rc |= 1 << (i << 2);
543 continue;
544 }
545 if (nand_send_cmd(NAND_CMD_READ2))
546 {
547 rc |= 1 << (i << 2);
548 continue;
549 }
550 }
551 uint8_t status[4];
552 for (i = 0; i < 4; i++) status[i] = (nand_type[i] == 0xFFFFFFFF);
553 if (!status[0])
554 if (nand_wait_status_ready(0))
555 status[0] = 1;
556 if (!status[0])
557 if (nand_transfer_data(0, 0, databuffer, 0x800))
558 status[0] = 1;
559 if (!status[0])
560 if (nand_transfer_data(0, 0, sparebuffer, 0x40))
561 status[0] = 1;
562 for (i = 1; i < 4; i++)
563 {
564 if (!status[i])
565 if (nand_wait_status_ready(i))
566 status[i] = 1;
567 if (!status[i])
568 nand_transfer_data_start(i, 0, (void*)((uint32_t)databuffer
569 + 0x800 * i), 0x800);
570 if (!status[i - 1])
571 {
572 memcpy(nand_ecc, (void*)((uint32_t)sparebuffer + 0x40 * (i - 1) + 0xC), 0x28);
573 ecc_start(3, (void*)((uint32_t)databuffer
574 + 0x800 * (i - 1)), nand_ecc, ECCCTRL_STARTDECODING);
575 }
576 if (!status[i])
577 if (nand_transfer_data_collect(0))
578 status[i] = 1;
579 if (!status[i])
580 nand_transfer_data_start(i, 0, (void*)((uint32_t)sparebuffer
581 + 0x40 * i), 0x40);
582 if (!status[i - 1])
583 if (ecc_collect() & 1)
584 status[i - 1] = 4;
585 if (!status[i - 1])
586 {
587 memset(nand_ctrl, 0xFF, 0x200);
588 memcpy(nand_ctrl, (void*)((uint32_t)sparebuffer + 0x40 * (i - 1)), 0xC);
589 memcpy(nand_ecc, (void*)((uint32_t)sparebuffer + 0x40 * (i - 1) + 0x34), 0xC);
590 ecc_start(0, nand_ctrl, nand_ecc, ECCCTRL_STARTDECODING);
591 }
592 if (!status[i])
593 if (nand_transfer_data_collect(0))
594 status[i] = 1;
595 if (!status[i - 1])
596 {
597 if (ecc_collect() & 1)
598 {
599 status[i - 1] |= 8;
600 memset((void*)((uint32_t)sparebuffer + 0x40 * (i - 1)), 0xFF, 0xC);
601 }
602 else memcpy((void*)((uint32_t)sparebuffer + 0x40 * (i - 1)), nand_ctrl, 0xC);
603 if (checkempty)
604 status[i - 1] |= nand_check_empty((void*)((uint32_t)sparebuffer
605 + 0x40 * (i - 1))) << 1;
606 }
607 }
608 if (!status[i - 1])
609 {
610 memcpy(nand_ecc,(void*)((uint32_t)sparebuffer + 0x40 * (i - 1) + 0xC), 0x28);
611 if (ecc_decode(3, (void*)((uint32_t)databuffer
612 + 0x800 * (i - 1)), nand_ecc) & 1)
613 status[i - 1] = 4;
614 }
615 if (!status[i - 1])
616 {
617 memset(nand_ctrl, 0xFF, 0x200);
618 memcpy(nand_ctrl, (void*)((uint32_t)sparebuffer + 0x40 * (i - 1)), 0xC);
619 memcpy(nand_ecc, (void*)((uint32_t)sparebuffer + 0x40 * (i - 1) + 0x34), 0xC);
620 if (ecc_decode(0, nand_ctrl, nand_ecc) & 1)
621 {
622 status[i - 1] |= 8;
623 memset((void*)((uint32_t)sparebuffer + 0x40 * (i - 1)), 0xFF, 0xC);
624 }
625 else memcpy((void*)((uint32_t)sparebuffer + 0x40 * (i - 1)), nand_ctrl, 0xC);
626 if (checkempty)
627 status[i - 1] |= nand_check_empty((void*)((uint32_t)sparebuffer
628 + 0x40 * (i - 1))) << 1;
629 }
630 for (i = 0; i < 4; i++)
631 if (nand_type[i] != 0xFFFFFFFF)
632 rc |= status[i] << (i << 2);
633 return nand_unlock(rc);
634 }
635
636 uint32_t nand_write_page(uint32_t bank, uint32_t page, void* databuffer,
637 void* sparebuffer, uint32_t doecc)
638 {
639 return nand_write_page_int(bank, page, databuffer, sparebuffer, doecc, 1);
640 }
641
642 uint32_t nand_write_page_start(uint32_t bank, uint32_t page, void* databuffer,
643 void* sparebuffer, uint32_t doecc)
644 {
645 if (((uint32_t)databuffer & 0xf) || ((uint32_t)sparebuffer & 0xf)
646 || !databuffer || !sparebuffer || !doecc)
647 return nand_write_page_int(bank, page, databuffer, sparebuffer, doecc, 0);
648
649 mutex_lock(&nand_mtx);
650 nand_last_activity_value = current_tick;
651 led(true);
652 if (!nand_powered) nand_power_up();
653 nand_set_fmctrl0(bank, FMCTRL0_ENABLEDMA);
654 if (nand_send_cmd(NAND_CMD_PROGRAM))
655 return nand_unlock(1);
656 if (nand_send_address(page, 0))
657 return nand_unlock(1);
658 nand_transfer_data_start(bank, 1, databuffer, 0x800);
659 if (ecc_encode(3, databuffer, nand_ecc))
660 return nand_unlock(1);
661 memcpy((void*)((uint32_t)sparebuffer + 0xC), nand_ecc, 0x28);
662 memset(nand_ctrl, 0xFF, 0x200);
663 memcpy(nand_ctrl, sparebuffer, 0xC);
664 if (ecc_encode(0, nand_ctrl, nand_ecc))
665 return nand_unlock(1);
666 memcpy((void*)((uint32_t)sparebuffer + 0x34), nand_ecc, 0xC);
667 if (nand_transfer_data_collect(0))
668 return nand_unlock(1);
669 if (nand_transfer_data(bank, 1, sparebuffer, 0x40))
670 return nand_unlock(1);
671 return nand_unlock(nand_send_cmd(NAND_CMD_PROGCNFRM));
672 }
673
674 uint32_t nand_write_page_collect(uint32_t bank)
675 {
676 return nand_wait_status_ready(bank);
677 }
678
679 uint32_t nand_block_erase_fast(uint32_t page)
680 {
681 uint32_t i, rc = 0;
682 mutex_lock(&nand_mtx);
683 nand_last_activity_value = current_tick;
684 led(true);
685 if (!nand_powered) nand_power_up();
686 for (i = 0; i < 4; i++)
687 {
688 if (nand_type[i] == 0xFFFFFFFF) continue;
689 nand_set_fmctrl0(i, 0);
690 if (nand_send_cmd(NAND_CMD_BLOCKERASE))
691 {
692 rc |= 1 << i;
693 continue;
694 }
695 FMANUM = 2;
696 FMADDR0 = page;
697 FMCTRL1 = FMCTRL1_DOTRANSADDR;
698 if (nand_wait_cmddone())
699 {
700 rc |= 1 << i;
701 continue;
702 }
703 if (nand_send_cmd(NAND_CMD_ERASECNFRM)) rc |= 1 << i;
704 }
705 for (i = 0; i < 4; i++)
706 {
707 if (nand_type[i] == 0xFFFFFFFF) continue;
708 if (rc & (1 << i)) continue;
709 if (nand_wait_status_ready(i)) rc |= 1 << i;
710 }
711 return nand_unlock(rc);
712 }
713
714 const struct nand_device_info_type* nand_get_device_type(uint32_t bank)
715 {
716 if (nand_type[bank] == 0xFFFFFFFF)
717 return (struct nand_device_info_type*)0;
718 return &nand_deviceinfotable[nand_type[bank]];
719 }
720
721 static void nand_thread(void)
722 {
723 while (1)
724 {
725 if (TIME_AFTER(current_tick, nand_last_activity_value + HZ / 5)
726 && nand_powered)
727 nand_power_down();
728 sleep(HZ / 10);
729 }
730 }
731
732 uint32_t nand_device_init(void)
733 {
734 mutex_init(&nand_mtx);
735 wakeup_init(&nand_wakeup);
736 mutex_init(&ecc_mtx);
737 wakeup_init(&ecc_wakeup);
738
739 uint32_t type;
740 uint32_t i, j;
741
742 /* Assume there are 0 banks, to prevent
743 nand_power_up from talking with them yet. */
744 for(i = 0; i < 4; i++) nand_type[i] = 0xFFFFFFFF;
745 nand_power_up();
746
747 /* Now that the flash is powered on, detect how
748 many banks we really have and initialize them. */
749 for (i = 0; i < 4; i++)
750 {
751 nand_tunk1[i] = 7;
752 nand_twp[i] = 7;
753 nand_tunk2[i] = 7;
754 nand_tunk3[i] = 7;
755 type = nand_get_chip_type(i);
756 if (type == 0xFFFFFFFF) continue;
757 for (j = 0; ; j++)
758 {
759 if (j == ARRAYLEN(nand_deviceinfotable)) break;
760 else if (nand_deviceinfotable[j].id == type)
761 {
762 nand_type[i] = j;
763 break;
764 }
765 }
766 nand_tunk1[i] = nand_deviceinfotable[nand_type[i]].tunk1;
767 nand_twp[i] = nand_deviceinfotable[nand_type[i]].twp;
768 nand_tunk2[i] = nand_deviceinfotable[nand_type[i]].tunk2;
769 nand_tunk3[i] = nand_deviceinfotable[nand_type[i]].tunk3;
770 }
771 if (nand_type[0] == 0xFFFFFFFF) return 1;
772
773 nand_last_activity_value = current_tick;
774 create_thread(nand_thread, nand_stack,
775 sizeof(nand_stack), 0, "nand"
776 IF_PRIO(, PRIORITY_USER_INTERFACE)
777 IF_COP(, CPU));
778
779 return 0;
780 }
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