1 /***************************************************************************
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
10 * Copyright (C) 2010 by Michael Sevakis
12 * i.MX31 DVFS and DPTC driver declarations
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License
16 * as published by the Free Software Foundation; either version 2
17 * of the License, or (at your option) any later version.
19 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
20 * KIND, either express or implied.
22 ****************************************************************************/
24 #ifndef _DVFS_DPTC_IMX31_H_
25 #define _DVFS_DPTC_IMX31_H_
27 /* DVFS load tracking signals */
30 DVFS_LT_SIG_M3IF_M0_BUF
= 0, /* Hready signal of M3IF's master #0
32 DVFS_LT_SIG_M3IF_M1
= 1, /* Hready signal of M3IF's master #1
34 DVFS_LT_SIG_MBX_MBXCLKGATE
= 2, /* Hready signal of M3IF's master #2
36 DVFS_LT_SIG_M3IF_M3
= 3, /* Hready signal of M3IF's master #3
38 DVFS_LT_SIG_M3IF_M4
= 4, /* Hready signal of M3IF's master #4
40 DVFS_LT_SIG_M3IF_M5
= 5, /* Hready signal of M3IF's master #5
41 (mpeg4_vga_encoder) */
42 DVFS_LT_SIG_M3IF_M6
= 6, /* Hready signal of M3IF's master #6
44 DVFS_LT_SIG_M3IF_M7
= 7, /* Hready signal of M3IF's master #7
46 DVFS_LT_SIG_ARM11_P_IRQ_B_RBT_GATE
= 8, /* ARM normal interrupt */
47 DVFS_LT_SIG_ARM11_P_FIQ_B_RBT_GATE
= 9, /* ARM fast interrupt */
48 DVFS_LT_SIG_IPI_GPIO1_INT0
= 10, /* Interrupt line from GPIO */
49 DVFS_LT_SIG_IPI_INT_IPU_FUNC
= 11, /* Interrupt line from IPU */
50 DVFS_LT_SIG_DVGP0
= 12, /* Software-controllable general-purpose
52 DVFS_LT_SIG_DVGP1
= 13, /* Software-controllable general-purpose
54 DVFS_LT_SIG_DVGP2
= 14, /* Software-controllable general-purpose
56 DVFS_LT_SIG_DVGP3
= 15, /* Software-controllable general-purpose
69 union dvfs_dptc_voltage_table_entry
71 uint8_t sw
[4]; /* Access as array */
75 /* Chosen by PMIC pin states */
76 /* when SWxABDVS bit is 1: */
78 uint8_t sw1a
; /* 0 0 */
79 uint8_t sw1advs
; /* 1 0 */
80 uint8_t sw1bdvs
; /* 0 1 */
81 uint8_t sw1bstby
; /* 1 1 */
86 struct dptc_dcvr_table_entry
88 uint32_t dcvr0
; /* DCVR register values for working point */
95 struct dvfs_clock_table_entry
97 uint32_t pll_val
; /* Setting for target PLL */
98 uint32_t pdr_val
; /* Post-divider for target setting */
99 uint32_t pll_num
: 1; /* 1 = MCU PLL, 0 = Serial PLL */
100 uint32_t vscnt
: 3; /* Voltage scaling counter, CKIL delay */
104 struct dvfs_lt_signal_descriptor
106 uint8_t weight
: 3; /* Signal weight = 0-7 */
107 uint8_t detect
: 1; /* 1 = edge-detected */
110 #define DVFS_NUM_LEVELS 4
111 #define DPTC_NUM_WP 17
113 /* 0 and 3 are *required*. DVFS hardware depends upon DVSUP pins showing
114 * minimum (11) and maximum (00) levels or interrupts will be continuously
116 #define DVFS_LEVEL_0 (1u << 0)
117 #define DVFS_LEVEL_1 (1u << 1)
118 #define DVFS_LEVEL_2 (1u << 2)
119 #define DVFS_LEVEL_3 (1u << 3)
121 extern long cpu_voltage_setting
;
123 void dvfs_dptc_init(void);
124 void dvfs_dptc_start(void);
125 void dvfs_dptc_stop(void);
127 void dvfs_start(void);
128 void dvfs_stop(void);
129 bool dvfs_enabled(void);
130 void dvfs_wfi_monitor(bool on
);
131 void dvfs_set_lt_weight(enum DVFS_LT_SIGS index
, unsigned long value
);
132 unsigned long dvfs_get_lt_weight(enum DVFS_LT_SIGS index
);
133 void dvfs_set_lt_detect(enum DVFS_LT_SIGS index
, bool edge
);
134 bool dvfs_get_lt_detect(enum DVFS_LT_SIGS index
);
135 void dvfs_set_gp_bit(enum DVFS_DVGPS dvgp
, bool assert);
136 bool dvfs_get_gp_bit(enum DVFS_DVGPS dvgp
);
137 void dvfs_int_mask(bool mask
);
138 void dvfs_set_gp_sense(int level_code
, unsigned long detect_mask
);
139 void dvfs_get_gp_sense(int *level_code
, unsigned long *detect_mask
);
140 unsigned int dvfs_level_mask(void);
142 unsigned int dvfs_dptc_get_voltage(void);
143 unsigned int dvfs_get_level(void);
144 void dvfs_set_level(unsigned int level
);
146 void dptc_start(void);
147 void dptc_stop(void);
148 bool dptc_enabled(void);
149 unsigned int dptc_get_wp(void);
150 void dptc_set_wp(unsigned int wp
);
152 #endif /* _DVFS_DPTC_IMX31_H_ */