firmware/target/arm/imx31/dvfs_dptc-imx31.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2010 by Michael Sevakis
  11  *
  12  * i.MX31 DVFS and DPTC drivers
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License
  16  * as published by the Free Software Foundation; either version 2
  17  * of the License, or (at your option) any later version.
  18  *
  19  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  20  * KIND, either express or implied.
  21  *
  22  ****************************************************************************/
  23 #include "config.h"
  24 #include "system.h"
  25 #include "logf.h"
  26 #include "mc13783.h"
  27 #include "iomuxc-imx31.h"
  28 #include "ccm-imx31.h"
  29 #include "avic-imx31.h"
  30 #include "dvfs_dptc-imx31.h"
  31 #include "dvfs_dptc_tables-target.h"
  32
  33 /* Most of the code in here is based upon the Linux BSP provided by Freescale
  34  * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. */
  35
  36 /* The current DVFS index level */
  37 static volatile unsigned int dvfs_level = DVFS_LEVEL_DEFAULT;
  38 /* The current DPTC working point */
  39 static volatile unsigned int dptc_wp = DPTC_WP_DEFAULT;
  40
  41
  42 static void update_dptc_counts(unsigned int level, unsigned int wp)
  43 {
  44     int oldlevel = disable_irq_save();
  45     const struct dptc_dcvr_table_entry *entry = &dptc_dcvr_table[level][wp];
  46
  47     CCM_DCVR0 = entry->dcvr0;
  48     CCM_DCVR1 = entry->dcvr1;
  49     CCM_DCVR2 = entry->dcvr2;
  50     CCM_DCVR3 = entry->dcvr3;
  51
  52     restore_irq(oldlevel);
  53 }
  54
  55
  56 static uint32_t check_regulator_setting(uint32_t setting)
  57 {
  58     /* Simply a safety check *in case* table gets scrambled */
  59     if (setting < VOLTAGE_SETTING_MIN)
  60         setting = VOLTAGE_SETTING_MIN;
  61     else if (setting > VOLTAGE_SETTING_MAX)
  62         setting = VOLTAGE_SETTING_MAX;
  63
  64     return setting;
  65 }
  66
  67
  68 /** DVFS **/
  69 static bool dvfs_running = false; /* Has driver enabled DVFS? */
  70
  71 /* Request tracking since boot */
  72 unsigned int dvfs_nr_dn = 0;
  73 unsigned int dvfs_nr_up = 0;
  74 unsigned int dvfs_nr_pnc = 0;
  75 unsigned int dvfs_nr_no = 0;
  76
  77
  78 /* Wait for the UPDTEN flag to be set so that all bits may be written */
  79 static inline void wait_for_dvfs_update_en(void)
  80 {
  81     while (!(CCM_PMCR0 & CCM_PMCR0_UPDTEN));
  82 }
  83
  84
  85 static void do_dvfs_update(unsigned int level, bool in_isr)
  86 {
  87     const struct dvfs_clock_table_entry *setting = &dvfs_clock_table[level];
  88     unsigned long pmcr0 = CCM_PMCR0;
  89
  90     if (pmcr0 & CCM_PMCR0_DPTEN)
  91     {
  92         /* Ignore voltage change request from DPTC. Voltage is *not* valid. */
  93         pmcr0 &= ~CCM_PMCR0_DPVCR;
  94     }
  95
  96     pmcr0 &= ~CCM_PMCR0_VSCNT;
  97
  98     if (level < ((pmcr0 & CCM_PMCR0_DVSUP) >> CCM_PMCR0_DVSUP_POS))
  99     {
 100         pmcr0 |= CCM_PMCR0_UDSC; /* Up scaling, increase */
 101         pmcr0 |= setting->vscnt << CCM_PMCR0_VSCNT_POS;
 102     }
 103     else
 104     {
 105         pmcr0 &= ~CCM_PMCR0_UDSC; /* Down scaling, decrease */
 106         pmcr0 |= 0x1 << CCM_PMCR0_VSCNT_POS;
 107     }
 108
 109     /* DVSUP (new frequency index) setup */
 110     pmcr0 = (pmcr0 & ~CCM_PMCR0_DVSUP) | (level << CCM_PMCR0_DVSUP_POS);
 111
 112     dvfs_level = level;
 113
 114     if ((setting->pll_num << CCM_PMCR0_DFSUP_MCUPLL_POS) ^
 115         (pmcr0 & CCM_PMCR0_DFSUP_MCUPLL))
 116     {
 117         /* Update pll and post-dividers. */
 118         pmcr0 ^= CCM_PMCR0_DFSUP_MCUPLL;
 119         pmcr0 &= ~CCM_PMCR0_DFSUP_POST_DIVIDERS;
 120     }
 121     else
 122     {
 123         /* Post-dividers update only */
 124         pmcr0 |= CCM_PMCR0_DFSUP_POST_DIVIDERS;
 125     }
 126
 127     CCM_PMCR0 = pmcr0;
 128     /* Note: changes to frequency with ints unmaked seem to cause spurious
 129      * DVFS interrupts with value CCM_PMCR0_FSVAI_NO_INT. These aren't
 130      * supposed to happen. Only do the lengthy delay with them enabled iff
 131      * called from the IRQ handler. */
 132     if (in_isr)
 133         enable_irq();
 134     udelay(100); /* Software wait for voltage ramp-up */
 135     if (in_isr)
 136         disable_irq();
 137     CCM_PDR0 = setting->pdr_val;
 138
 139     if (!(pmcr0 & CCM_PMCR0_DFSUP_POST_DIVIDERS))
 140     {
 141         /* Update the PLL settings */
 142         if (pmcr0 & CCM_PMCR0_DFSUP_MCUPLL)
 143             CCM_MPCTL = setting->pll_val;
 144         else
 145             CCM_SPCTL = setting->pll_val;
 146     }
 147
 148     cpu_frequency = ccm_get_mcu_clk();
 149
 150     if (pmcr0 & CCM_PMCR0_DPTEN)
 151     {
 152         update_dptc_counts(level, dptc_wp);
 153         /* Enable DPTC to request voltage changes. Voltage is valid. */
 154         CCM_PMCR0 |= CCM_PMCR0_DPVCR;
 155         udelay(2);
 156         CCM_PMCR0 |= CCM_PMCR0_DPVV;
 157     }
 158 }
 159
 160
 161 /* Start DVFS, change the set point and stop it */
 162 static void set_current_dvfs_level(unsigned int level)
 163 {
 164     int oldlevel = disable_irq_save();
 165
 166     CCM_PMCR0 |= CCM_PMCR0_DVFEN;
 167
 168     wait_for_dvfs_update_en();
 169
 170     do_dvfs_update(level, false);
 171
 172     wait_for_dvfs_update_en();
 173
 174     CCM_PMCR0 &= ~CCM_PMCR0_DVFEN;
 175
 176     restore_irq(oldlevel);
 177 }
 178
 179
 180 /* DVFS Interrupt handler */
 181 static void __attribute__((used)) dvfs_int(void)
 182 {
 183     unsigned long pmcr0 = CCM_PMCR0;
 184     unsigned long fsvai = pmcr0 & CCM_PMCR0_FSVAI;
 185     unsigned int level = (pmcr0 & CCM_PMCR0_DVSUP) >> CCM_PMCR0_DVSUP_POS;
 186
 187     if (pmcr0 & CCM_PMCR0_FSVAIM)
 188         return; /* Do nothing. DVFS interrupt is masked. */
 189
 190     if (!(pmcr0 & CCM_PMCR0_UPDTEN))
 191         return; /* Do nothing. DVFS didn't finish previous flow update. */
 192
 193     switch (fsvai)
 194     {
 195     case CCM_PMCR0_FSVAI_DECREASE:
 196         if (level >= DVFS_NUM_LEVELS - 1)
 197             return; /* DVFS already at lowest level */
 198
 199         /* Upon the DECREASE event, the frequency will be changed to the next
 200          * higher state index. */
 201         while (((1u << ++level) & DVFS_LEVEL_MASK) == 0);
 202
 203         dvfs_nr_dn++;
 204         break;
 205
 206     /* Single-step frequency increase */
 207     case CCM_PMCR0_FSVAI_INCREASE:
 208         if (level == 0)
 209             return; /* DVFS already at highest level */
 210
 211         /* Upon the INCREASE event, the frequency will be changed to the next
 212          * lower state index. */
 213         while (((1u << --level) & DVFS_LEVEL_MASK) == 0);
 214
 215         dvfs_nr_up++;
 216         break;
 217
 218     /* Right to highest if panic */
 219     case CCM_PMCR0_FSVAI_INCREASE_NOW:
 220         if (level == 0)
 221             return; /* DVFS already at highest level */
 222
 223         /* Upon the INCREASE_NOW event, the frequency will be increased to
 224          * the maximum (index 0). */
 225         level = 0;
 226         dvfs_nr_pnc++;
 227         break;
 228
 229     case CCM_PMCR0_FSVAI_NO_INT:
 230         dvfs_nr_no++;
 231         return;     /* Do nothing. Freq change is not required */
 232     } /* end switch */
 233
 234     do_dvfs_update(level, true);
 235 }
 236
 237
 238 /* Interrupt vector for DVFS */
 239 static __attribute__((naked, interrupt("IRQ"))) void CCM_DVFS_HANDLER(void)
 240 {
 241     /* Audio can glitch with the long udelay if nested IRQ isn't allowed. */
 242     AVIC_NESTED_NI_CALL_PROLOGUE(INT_PRIO_DVFS, 32*4);
 243     asm volatile ("bl dvfs_int");
 244     AVIC_NESTED_NI_CALL_EPILOGUE(32*4);
 245 }
 246
 247
 248 /* Initialize the DVFS hardware */
 249 static void INIT_ATTR dvfs_init(void)
 250 {
 251     if (CCM_PMCR0 & CCM_PMCR0_DVFEN)
 252     {
 253         /* Turn it off first. Really, shouldn't happen though. */
 254         dvfs_running = true;
 255         dvfs_stop();
 256     }
 257
 258     /* Combine SW1A and SW1B DVS pins for a possible five DVS levels
 259      * per working point. Four, MAXIMUM, are actually used, one for each
 260      * frequency. */
 261     mc13783_set(MC13783_ARBITRATION_SWITCHERS, MC13783_SW1ABDVS);
 262
 263     /* Set DVS speed to 25mV every 4us. */
 264     mc13783_write_masked(MC13783_SWITCHERS4, MC13783_SW1ADVSSPEED_4US,
 265                          MC13783_SW1ADVSSPEED);
 266
 267     /* Set DVFS pins to functional outputs. Input mode and pad setting is
 268      * fixed in hardware. */
 269     iomuxc_set_pin_mux(IOMUXC_DVFS0,
 270                        IOMUXC_MUX_OUT_FUNCTIONAL | IOMUXC_MUX_IN_NONE);
 271     iomuxc_set_pin_mux(IOMUXC_DVFS1,
 272                        IOMUXC_MUX_OUT_FUNCTIONAL | IOMUXC_MUX_IN_NONE);
 273
 274 #ifndef DVFS_NO_PWRRDY
 275     /* Configure PWRRDY signal pin. */
 276     bitclr32(&GPIO1_GDIR, (1 << 5));
 277     iomuxc_set_pin_mux(IOMUXC_GPIO1_5,
 278                        IOMUXC_MUX_OUT_FUNCTIONAL | IOMUXC_MUX_IN_FUNCTIONAL);
 279 #endif
 280
 281     /* GP load bits disabled */
 282     bitclr32(&CCM_PMCR1, 0xf);
 283
 284     /* Initialize DVFS signal weights and detection modes. */
 285     int i;
 286     for (i = 0; i < 16; i++)
 287     {
 288         dvfs_set_lt_weight(i, lt_signals[i].weight);
 289         dvfs_set_lt_detect(i, lt_signals[i].detect);
 290     }
 291
 292     /* Set up LTR0. */
 293     bitmod32(&CCM_LTR0,
 294              DVFS_UPTHR << CCM_LTR0_UPTHR_POS |
 295              DVFS_DNTHR << CCM_LTR0_DNTHR_POS |
 296              DVFS_DIV3CK << CCM_LTR0_DIV3CK_POS,
 297              CCM_LTR0_UPTHR | CCM_LTR0_DNTHR | CCM_LTR0_DIV3CK);
 298
 299     /* Set up LTR1. */
 300     bitmod32(&CCM_LTR1,
 301              DVFS_DNCNT << CCM_LTR1_DNCNT_POS |
 302              DVFS_UPCNT << CCM_LTR1_UPCNT_POS |
 303              DVFS_PNCTHR << CCM_LTR1_PNCTHR_POS |
 304              CCM_LTR1_LTBRSR,
 305              CCM_LTR1_DNCNT | CCM_LTR1_UPCNT |
 306              CCM_LTR1_PNCTHR | CCM_LTR1_LTBRSR);
 307
 308     /* Set up LTR2-- EMA configuration. */
 309     bitmod32(&CCM_LTR2, DVFS_EMAC << CCM_LTR2_EMAC_POS, CCM_LTR2_EMAC);
 310
 311     /* DVFS interrupt goes to MCU. Mask load buffer full interrupt. */
 312     bitset32(&CCM_PMCR0, CCM_PMCR0_DVFIS | CCM_PMCR0_LBMI);
 313
 314     /* Initialize current core PLL and dividers for default level. Assumes
 315      * clocking scheme has been set up appropriately in other init code. */
 316     ccm_set_mcupll_and_pdr(dvfs_clock_table[DVFS_LEVEL_DEFAULT].pll_val,
 317                            dvfs_clock_table[DVFS_LEVEL_DEFAULT].pdr_val);
 318
 319     /* Set initial level and working point. */
 320     set_current_dvfs_level(DVFS_LEVEL_DEFAULT);
 321
 322     logf("DVFS: Initialized");
 323 }
 324
 325 /** DPTC **/
 326
 327 /* Request tracking since boot */
 328 static bool dptc_running = false; /* Has driver enabled DPTC? */
 329
 330 unsigned int dptc_nr_dn = 0;
 331 unsigned int dptc_nr_up = 0;
 332 unsigned int dptc_nr_pnc = 0;
 333 unsigned int dptc_nr_no = 0;
 334
 335 static struct spi_transfer_desc dptc_pmic_xfer; /* Transfer descriptor */
 336 static const unsigned char dptc_pmic_regs[2] =  /* Register subaddresses */
 337 { MC13783_SWITCHERS0, MC13783_SWITCHERS1 };
 338 static uint32_t dptc_reg_shadows[2];            /* shadow regs */
 339 static uint32_t dptc_regs_buf[2];               /* buffer for async write */
 340
 341
 342 /* Enable DPTC and unmask interrupt. */
 343 static void enable_dptc(void)
 344 {
 345     int oldlevel = disable_irq_save();
 346
 347     /* Enable DPTC, assert voltage change request. */
 348     CCM_PMCR0 = (CCM_PMCR0 & ~CCM_PMCR0_PTVAIM) | CCM_PMCR0_DPTEN |
 349                     CCM_PMCR0_DPVCR;
 350
 351     udelay(2);
 352
 353     /* Set voltage valid *after* setting change request */
 354     CCM_PMCR0 |= CCM_PMCR0_DPVV;
 355
 356     restore_irq(oldlevel);
 357 }
 358
 359
 360 /* Called after asynchronous PMIC write is completed */
 361 static void dptc_transfer_done_callback(struct spi_transfer_desc *xfer)
 362 {
 363     if (xfer->count != 0)
 364         return;
 365
 366     update_dptc_counts(dvfs_level, dptc_wp);
 367
 368     if (dptc_running)
 369         enable_dptc();
 370 }
 371
 372
 373 /* Handle the DPTC interrupt and sometimes the manual setting */
 374 static void dptc_int(unsigned long pmcr0)
 375 {
 376     const union dvfs_dptc_voltage_table_entry *entry;
 377     uint32_t sw1a, sw1advs, sw1bdvs, sw1bstby;
 378     uint32_t switchers0, switchers1;
 379
 380     int wp = dptc_wp;
 381
 382     /* Mask DPTC interrupt and disable DPTC until the change request is
 383      * serviced. */
 384     CCM_PMCR0 = (pmcr0 & ~CCM_PMCR0_DPTEN) | CCM_PMCR0_PTVAIM;
 385
 386     switch (pmcr0 & CCM_PMCR0_PTVAI)
 387     {
 388     case CCM_PMCR0_PTVAI_DECREASE:
 389         wp++;
 390         dptc_nr_dn++;
 391         break;
 392
 393     case CCM_PMCR0_PTVAI_INCREASE:
 394         wp--;
 395         dptc_nr_up++;
 396         break;
 397
 398     case CCM_PMCR0_PTVAI_INCREASE_NOW:
 399         if (--wp > DPTC_WP_PANIC)
 400             wp = DPTC_WP_PANIC;
 401         dptc_nr_pnc++;
 402         break;
 403
 404     case CCM_PMCR0_PTVAI_NO_INT:
 405         break; /* Just maintain at global level */
 406     }
 407
 408     if (wp < 0)
 409         wp = 0;
 410     else if (wp >= DPTC_NUM_WP)
 411         wp = DPTC_NUM_WP - 1;
 412
 413     entry = &dvfs_dptc_voltage_table[wp];
 414
 415     sw1a = check_regulator_setting(entry->sw1a);
 416     sw1advs = check_regulator_setting(entry->sw1advs);
 417     sw1bdvs = check_regulator_setting(entry->sw1bdvs);
 418     sw1bstby = check_regulator_setting(entry->sw1bstby);
 419
 420     switchers0 = dptc_reg_shadows[0] & ~(MC13783_SW1A | MC13783_SW1ADVS);
 421     dptc_regs_buf[0] = switchers0 |
 422                        sw1a << MC13783_SW1A_POS |         /* SW1A */
 423                        sw1advs << MC13783_SW1ADVS_POS;    /* SW1ADVS */
 424     switchers1 = dptc_reg_shadows[1] & ~(MC13783_SW1BDVS | MC13783_SW1BSTBY);
 425     dptc_regs_buf[1] = switchers1 |
 426                        sw1bdvs << MC13783_SW1BDVS_POS |   /* SW1BDVS */
 427                        sw1bstby << MC13783_SW1BSTBY_POS;  /* SW1BSTBY */
 428
 429     dptc_wp = wp;
 430
 431     mc13783_write_async(&dptc_pmic_xfer, dptc_pmic_regs,
 432                         dptc_regs_buf, 2, dptc_transfer_done_callback);
 433 }
 434
 435
 436 static void dptc_new_wp(unsigned int wp)
 437 {
 438     dptc_wp = wp;
 439     /* "NO_INT" so the working point isn't incremented, just set. */
 440     dptc_int((CCM_PMCR0 & ~CCM_PMCR0_PTVAI) | CCM_PMCR0_PTVAI_NO_INT);
 441 }
 442
 443
 444 /* Interrupt vector for DPTC */
 445 static __attribute__((interrupt("IRQ"))) void CCM_CLK_HANDLER(void)
 446 {
 447     unsigned long pmcr0 = CCM_PMCR0;
 448
 449     if ((pmcr0 & CCM_PMCR0_PTVAI) == CCM_PMCR0_PTVAI_NO_INT)
 450         dptc_nr_no++;
 451
 452     dptc_int(pmcr0);
 453 }
 454
 455
 456 /* Initialize the DPTC hardware */
 457 static void INIT_ATTR dptc_init(void)
 458 {
 459     /* Force DPTC off if running for some reason. */
 460     bitmod32(&CCM_PMCR0, CCM_PMCR0_PTVAIM,
 461              CCM_PMCR0_PTVAIM | CCM_PMCR0_DPTEN);
 462
 463      /* Shadow the regulator registers */
 464     mc13783_read_regs(dptc_pmic_regs, dptc_reg_shadows, 2);
 465
 466     /* Set default, safe working point. */
 467     dptc_new_wp(DPTC_WP_DEFAULT);
 468
 469     /* Interrupt goes to MCU, specified reference circuits enabled when
 470      * DPTC is active. */
 471     bitset32(&CCM_PMCR0, CCM_PMCR0_PTVIS);
 472
 473     bitmod32(&CCM_PMCR0, DPTC_DRCE_MASK,
 474              CCM_PMCR0_DRCE0 | CCM_PMCR0_DRCE1 |
 475              CCM_PMCR0_DRCE2 | CCM_PMCR0_DRCE3);
 476
 477     /* DPTC counting range = 256 system clocks */
 478     bitclr32(&CCM_PMCR0, CCM_PMCR0_DCR);
 479
 480     logf("DPTC: Initialized");
 481 }
 482
 483
 484 /** Main module interface **/
 485
 486 /* Initialize DVFS and DPTC */
 487 void INIT_ATTR dvfs_dptc_init(void)
 488 {
 489     dptc_init();
 490     dvfs_init();
 491 }
 492
 493
 494 /* Start DVFS and DPTC */
 495 void dvfs_dptc_start(void)
 496 {
 497     dvfs_start();
 498     dptc_start();
 499 }
 500
 501
 502 /* Stop DVFS and DPTC */
 503 void dvfs_dptc_stop(void)
 504 {
 505     dptc_stop();
 506     dvfs_stop();
 507 }
 508
 509 /* Start the DVFS hardware */
 510 void dvfs_start(void)
 511 {
 512     int oldlevel;
 513
 514     /* Have to wait at least 3 div3 clocks before enabling after being
 515      * stopped. */
 516     udelay(1500);
 517
 518     oldlevel = disable_irq_save();
 519
 520     if (!dvfs_running)
 521     {
 522         dvfs_running = true;
 523
 524         /* Unmask DVFS interrupt source and enable DVFS. */
 525         avic_enable_int(INT_CCM_DVFS, INT_TYPE_IRQ, INT_PRIO_DVFS,
 526                         CCM_DVFS_HANDLER);
 527
 528         CCM_PMCR0 = (CCM_PMCR0 & ~CCM_PMCR0_FSVAIM) | CCM_PMCR0_DVFEN;
 529     }
 530
 531     restore_irq(oldlevel);
 532
 533     logf("DVFS: started");
 534 }
 535
 536
 537 /* Stop the DVFS hardware and return to default frequency */
 538 void dvfs_stop(void)
 539 {
 540     int oldlevel = disable_irq_save();
 541
 542     if (dvfs_running)
 543     {
 544         /* Mask DVFS interrupts. */
 545         CCM_PMCR0 |= CCM_PMCR0_FSVAIM | CCM_PMCR0_LBMI;
 546         avic_disable_int(INT_CCM_DVFS);
 547
 548         if (((CCM_PMCR0 & CCM_PMCR0_DVSUP) >> CCM_PMCR0_DVSUP_POS) !=
 549                 DVFS_LEVEL_DEFAULT)
 550         {
 551             /* Set default frequency level */
 552             wait_for_dvfs_update_en();
 553             do_dvfs_update(DVFS_LEVEL_DEFAULT, false);
 554             wait_for_dvfs_update_en();
 555         }
 556
 557         /* Disable DVFS. */
 558         CCM_PMCR0 &= ~CCM_PMCR0_DVFEN;
 559         dvfs_running = false;
 560     }
 561
 562     restore_irq(oldlevel);
 563
 564     logf("DVFS: stopped");
 565 }
 566
 567
 568 /* Mask the DVFS interrupt without affecting running status */
 569 void dvfs_int_mask(bool mask)
 570 {
 571     if (mask)
 572     {
 573         /* Just disable, not running = already disabled */
 574         avic_mask_int(INT_CCM_DVFS);
 575     }
 576     else if (dvfs_running)
 577     {
 578         /* DVFS is running; unmask it */
 579         avic_unmask_int(INT_CCM_DVFS);
 580     }
 581 }
 582
 583
 584 /* Set a signal load tracking weight */
 585 void dvfs_set_lt_weight(enum DVFS_LT_SIGS index, unsigned long value)
 586 {
 587     volatile unsigned long *reg_p = &CCM_LTR2;
 588     unsigned int shift = 3 * index;
 589
 590     if (index < 9)
 591     {
 592         reg_p = &CCM_LTR3;
 593         shift += 5; /* Bits 7:5, 10:8 ... 31:29 */
 594     }
 595     else if (index < 16)
 596     {
 597         shift -= 16; /* Bits 13:11, 16:14 ... 31:29 */
 598     }
 599
 600     bitmod32(reg_p, value << shift, 0x7 << shift);
 601 }
 602
 603
 604 /* Return a signal load tracking weight */
 605 unsigned long dvfs_get_lt_weight(enum DVFS_LT_SIGS index)
 606 {
 607     volatile unsigned long *reg_p = &CCM_LTR2;
 608     unsigned int shift = 3 * index;
 609
 610     if (index < 9)
 611     {
 612         reg_p = &CCM_LTR3;
 613         shift += 5; /* Bits 7:5, 10:8 ... 31:29 */
 614     }
 615     else if (index < 16)
 616     {
 617         shift -= 16; /* Bits 13:11, 16:14 ... 31:29 */
 618     }
 619
 620     return (*reg_p & (0x7 << shift)) >> shift;
 621 }
 622
 623
 624 /* Set a signal load detection mode */
 625 void dvfs_set_lt_detect(enum DVFS_LT_SIGS index, bool edge)
 626 {
 627     unsigned long bit = 0;
 628
 629     if ((unsigned)index < 13)
 630         bit = 1ul << (index + 3);
 631     else if ((unsigned)index < 16)
 632         bit = 1ul << (index + 29);
 633
 634     bitmod32(&CCM_LTR0, edge ? bit : 0, bit);
 635 }
 636
 637
 638 /* Returns a signal load detection mode */
 639 bool dvfs_get_lt_detect(enum DVFS_LT_SIGS index)
 640 {
 641     unsigned int shift = 32;
 642
 643     if ((unsigned)index < 13)
 644         shift = index + 3;
 645     else if ((unsigned)index < 16)
 646         shift = index + 29;
 647
 648     return !!((CCM_LTR0 & (1ul << shift)) >> shift);
 649 }
 650
 651
 652 /* Set/clear the general-purpose load tracking bit */
 653 void dvfs_set_gp_bit(enum DVFS_DVGPS dvgp, bool assert)
 654 {
 655     if ((unsigned)dvgp <= 3)
 656     {
 657         unsigned long bit = 1ul << dvgp;
 658         bitmod32(&CCM_PMCR1, assert ? bit : 0, bit);
 659     }
 660 }
 661
 662
 663 /* Return the general-purpose load tracking bit */
 664 bool dvfs_get_gp_bit(enum DVFS_DVGPS dvgp)
 665 {
 666     if ((unsigned)dvgp <= 3)
 667         return (CCM_PMCR1 & (1ul << dvgp)) != 0;
 668     return false;
 669 }
 670
 671
 672 /* Set GP load tracking by code.
 673  * level_code:
 674  *     lt 0  =defaults
 675  *     0     =all off ->
 676  *     28    =highest load
 677  *     gte 28=highest load
 678  * detect_mask bits:
 679  *     b[3:0]: 1=LTn edge detect, 0=LTn level detect
 680  */
 681 void dvfs_set_gp_sense(int level_code, unsigned long detect_mask)
 682 {
 683     int i;
 684
 685     for (i = 0; i <= 3; i++)
 686     {
 687         int ltsig_num = DVFS_LT_SIG_DVGP0 + i;
 688         int gpw_num = DVFS_DVGP_0 + i;
 689         unsigned long weight;
 690         bool edge;
 691         bool assert;
 692
 693         if (level_code < 0)
 694         {
 695             /* defaults */
 696             detect_mask = 0;
 697             assert = 0;
 698             weight = lt_signals[ltsig_num].weight;
 699             edge = lt_signals[ltsig_num].detect != 0;
 700         }
 701         else
 702         {
 703             weight = MIN(level_code, 7);
 704             edge = !!(detect_mask & 1);
 705             assert = weight > 0;
 706             detect_mask >>= 1;
 707             level_code -= 7;
 708             if (level_code < 0)
 709                 level_code = 0;
 710         }
 711
 712         dvfs_set_lt_weight(ltsig_num, weight);  /* set weight */
 713         dvfs_set_lt_detect(ltsig_num, edge);    /* set detect mode */
 714         dvfs_set_gp_bit(gpw_num, assert);       /* set activity */
 715     }
 716 }
 717
 718 /* Return GP weight settings */
 719 void dvfs_get_gp_sense(int *level_code, unsigned long *detect_mask)
 720 {
 721     int i;
 722     int code = 0;
 723     unsigned long mask = 0;
 724
 725     for (i = DVFS_LT_SIG_DVGP0; i <= DVFS_LT_SIG_DVGP3; i++)
 726     {
 727         code += dvfs_get_lt_weight(i);
 728         mask = (mask << 1) | (dvfs_get_lt_detect(i) ? 1 : 0);
 729     }
 730
 731     if (level_code)
 732         *level_code = code;
 733
 734     if (detect_mask)
 735         *detect_mask = mask;
 736 }
 737
 738
 739 /* Turn the wait-for-interrupt monitoring on or off */
 740 void dvfs_wfi_monitor(bool on)
 741 {
 742     bitmod32(&CCM_PMCR0, on ? 0 : CCM_PMCR0_WFIM, CCM_PMCR0_WFIM);
 743 }
 744
 745
 746 /* Obtain the current core voltage setting, in millivolts 8-) */
 747 unsigned int dvfs_dptc_get_voltage(void)
 748 {
 749     unsigned int v;
 750
 751     int oldlevel = disable_irq_save();
 752     v = dvfs_dptc_voltage_table[dptc_wp].sw[dvfs_level];
 753     restore_irq(oldlevel);
 754
 755     /* 25mV steps from 0.900V to 1.675V */
 756     return v * 25 + 900;
 757 }
 758
 759
 760 /* Get the current DVFS level */
 761 unsigned int dvfs_get_level(void)
 762 {
 763     return dvfs_level;
 764 }
 765
 766
 767 /* Is DVFS enabled? */
 768 bool dvfs_enabled(void)
 769 {
 770    return dvfs_running;
 771 }
 772
 773
 774 /* Get bitmask of levels supported */
 775 unsigned int dvfs_level_mask(void)
 776 {
 777     return DVFS_LEVEL_MASK;
 778 }
 779
 780
 781 /* If DVFS is disabled, set the level explicitly */
 782 void dvfs_set_level(unsigned int level)
 783 {
 784     int oldlevel = disable_irq_save();
 785
 786     if (!dvfs_running && level < DVFS_NUM_LEVELS)
 787     {
 788         unsigned int currlevel =
 789             (CCM_PMCR0 & CCM_PMCR0_DVSUP) >> CCM_PMCR0_DVSUP_POS;
 790         if (level != currlevel && ((1 << level) & DVFS_LEVEL_MASK))
 791             set_current_dvfs_level(level);
 792     }
 793
 794     restore_irq(oldlevel);
 795 }
 796
 797
 798 /* Start DPTC module */
 799 void dptc_start(void)
 800 {
 801     int oldlevel = disable_irq_save();
 802
 803     if (!dptc_running)
 804     {
 805         dptc_running = true;
 806
 807         /* Enable DPTC and unmask interrupt. */
 808         avic_enable_int(INT_CCM_CLK, INT_TYPE_IRQ, INT_PRIO_DPTC,
 809                         CCM_CLK_HANDLER);
 810
 811         update_dptc_counts(dvfs_level, dptc_wp);
 812         enable_dptc();
 813     }
 814
 815     restore_irq(oldlevel);
 816
 817     logf("DPTC: started");
 818 }
 819
 820
 821 /* Stop the DPTC hardware if running and go back to default working point */
 822 void dptc_stop(void)
 823 {
 824     int oldlevel = disable_irq_save();
 825
 826     if (dptc_running)
 827     {
 828         dptc_running = false;
 829
 830         /* Disable DPTC and mask interrupt. */
 831         CCM_PMCR0 = (CCM_PMCR0 & ~CCM_PMCR0_DPTEN) | CCM_PMCR0_PTVAIM;
 832         avic_disable_int(INT_CCM_CLK);
 833
 834         /* Go back to default working point. */
 835         dptc_new_wp(DPTC_WP_DEFAULT);
 836     }
 837
 838     restore_irq(oldlevel);
 839
 840     logf("DPTC: stopped");
 841 }
 842
 843
 844 /* Get the current DPTC working point */
 845 unsigned int dptc_get_wp(void)
 846 {
 847     return dptc_wp;
 848 }
 849
 850
 851 /* Is DPTC enabled? */
 852 bool dptc_enabled(void)
 853 {
 854     return dptc_running;
 855 }
 856
 857
 858 /* If DPTC is not running, set the working point explicitly */
 859 void dptc_set_wp(unsigned int wp)
 860 {
 861     int oldlevel = disable_irq_save();
 862
 863     if (!dptc_running && wp < DPTC_NUM_WP)
 864         dptc_new_wp(wp);
 865
 866     restore_irq(oldlevel);
 867 }