firmware/target/mips/ingenic_jz47xx/ata-nand-jz4740.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2008 by Maurus Cuelenaere
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21
  22 #include "config.h"
  23 #include "jz4740.h"
  24 #include "ata.h"
  25 //#include "ata-nand-target.h" /* TODO */
  26 #include "nand_id.h"
  27 #include "system.h"
  28 #include "panic.h"
  29 #include "kernel.h"
  30 #include "storage.h"
  31 #include "string.h"
  32 /*#define LOGF_ENABLE*/
  33 #include "logf.h"
  34
  35 //#define USE_DMA
  36 //#define USE_ECC
  37
  38 /*
  39  * Standard NAND flash commands
  40  */
  41 #define NAND_CMD_READ0         0
  42 #define NAND_CMD_READ1         1
  43 #define NAND_CMD_RNDOUT        5
  44 #define NAND_CMD_PAGEPROG      0x10
  45 #define NAND_CMD_READOOB       0x50
  46 #define NAND_CMD_ERASE1        0x60
  47 #define NAND_CMD_STATUS        0x70
  48 #define NAND_CMD_STATUS_MULTI  0x71
  49 #define NAND_CMD_SEQIN         0x80
  50 #define NAND_CMD_RNDIN         0x85
  51 #define NAND_CMD_READID        0x90
  52 #define NAND_CMD_ERASE2        0xd0
  53 #define NAND_CMD_RESET         0xff
  54
  55 /* Extended commands for large page devices */
  56 #define NAND_CMD_READSTART     0x30
  57 #define NAND_CMD_RNDOUTSTART   0xE0
  58 #define NAND_CMD_CACHEDPROG    0x15
  59
  60 /* Status bits */
  61 #define NAND_STATUS_FAIL       0x01
  62 #define NAND_STATUS_FAIL_N1    0x02
  63 #define NAND_STATUS_TRUE_READY 0x20
  64 #define NAND_STATUS_READY      0x40
  65 #define NAND_STATUS_WP         0x80
  66
  67 /*
  68  * NAND parameter struct
  69  */
  70 struct nand_param
  71 {
  72     unsigned int bus_width;        /* data bus width: 8-bit/16-bit */
  73     unsigned int row_cycle;        /* row address cycles: 2/3 */
  74     unsigned int page_size;        /* page size in bytes: 512/2048/4096 */
  75     unsigned int oob_size;         /* oob size in bytes: 16/64/128 */
  76     unsigned int page_per_block;   /* pages per block: 32/64/128 */
  77 };
  78
  79 /*
  80  * jz4740_nand.c
  81  *
  82  * NAND read routine for JZ4740
  83  *
  84  * Copyright (c) 2005-2008 Ingenic Semiconductor Inc.
  85  *
  86  */
  87
  88 static volatile unsigned long nand_address;
  89 #define NAND_DATAPORT      (nand_address)
  90 #define NAND_ADDRPORT      (nand_address+0x10000)
  91 #define NAND_COMMPORT      (nand_address+0x08000)
  92
  93 #define ECC_BLOCK          512
  94 #define ECC_POS            6
  95 #define PAR_SIZE           9
  96
  97 #define __nand_cmd(n)      (REG8(NAND_COMMPORT) = (n))
  98 #define __nand_addr(n)     (REG8(NAND_ADDRPORT) = (n))
  99 #define __nand_data8()     (REG8(NAND_DATAPORT))
 100 #define __nand_data16()    (REG16(NAND_DATAPORT))
 101
 102 #define __nand_ecc_rs_encoding() \
 103     (REG_EMC_NFECR = EMC_NFECR_ECCE | EMC_NFECR_ERST | EMC_NFECR_RS | EMC_NFECR_RS_ENCODING)
 104 #define __nand_ecc_rs_decoding() \
 105     (REG_EMC_NFECR = EMC_NFECR_ECCE | EMC_NFECR_ERST | EMC_NFECR_RS | EMC_NFECR_RS_DECODING)
 106 #define __nand_ecc_disable()     (REG_EMC_NFECR &= ~EMC_NFECR_ECCE)
 107 #define __nand_ecc_encode_sync() while (!(REG_EMC_NFINTS & EMC_NFINTS_ENCF))
 108 #define __nand_ecc_decode_sync() while (!(REG_EMC_NFINTS & EMC_NFINTS_DECF))
 109
 110 /*--------------------------------------------------------------*/
 111
 112 static struct nand_info* chip_info = NULL;
 113 static struct nand_info* banks[4];
 114 static unsigned int nr_banks = 1;
 115 static unsigned long bank_size;
 116 static struct nand_param internal_param;
 117 static struct mutex nand_mtx;
 118 #ifdef USE_DMA
 119 static struct mutex nand_dma_mtx;
 120 static struct wakeup nand_wkup;
 121 #endif
 122 static unsigned char temp_page[4096]; /* Max page size */
 123
 124 static inline void jz_nand_wait_ready(void)
 125 {
 126     register unsigned int timeout = 1000;
 127     while ((REG_GPIO_PXPIN(2) & 0x40000000) && timeout--);
 128     while (!(REG_GPIO_PXPIN(2) & 0x40000000));
 129 }
 130
 131 #ifndef USE_DMA
 132 static inline void jz_nand_read_buf16(void *buf, int count)
 133 {
 134     register int i;
 135     register unsigned short *p = (unsigned short *)buf;
 136
 137     for (i = 0; i < count; i += 2)
 138         *p++ = __nand_data16();
 139 }
 140
 141 static inline void jz_nand_read_buf8(void *buf, int count)
 142 {
 143     register int i;
 144     register unsigned char *p = (unsigned char *)buf;
 145
 146     for (i = 0; i < count; i++)
 147         *p++ = __nand_data8();
 148 }
 149 #else
 150 static void jz_nand_write_dma(void *source, unsigned int len, int bw)
 151 {
 152     mutex_lock(&nand_dma_mtx);
 153
 154     if(((unsigned int)source < 0xa0000000) && len)
 155          dma_cache_wback_inv((unsigned long)source, len);
 156
 157     dma_enable();
 158
 159     REG_DMAC_DCCSR(DMA_NAND_CHANNEL) = DMAC_DCCSR_NDES;
 160     REG_DMAC_DSAR(DMA_NAND_CHANNEL) = PHYSADDR((unsigned long)source);
 161     REG_DMAC_DTAR(DMA_NAND_CHANNEL) = PHYSADDR((unsigned long)NAND_DATAPORT);
 162     REG_DMAC_DTCR(DMA_NAND_CHANNEL) = len / 16;
 163     REG_DMAC_DRSR(DMA_NAND_CHANNEL) = DMAC_DRSR_RS_AUTO;
 164     REG_DMAC_DCMD(DMA_NAND_CHANNEL) = (DMAC_DCMD_SAI| DMAC_DCMD_DAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DS_16BYTE |
 165                                        (bw == 8 ? DMAC_DCMD_DWDH_8 : DMAC_DCMD_DWDH_16));
 166
 167     REG_DMAC_DCCSR(DMA_NAND_CHANNEL) |= DMAC_DCCSR_EN; /* Enable DMA channel */
 168 #if 1
 169     while( REG_DMAC_DTCR(DMA_NAND_CHANNEL) )
 170         yield();
 171 #else
 172     REG_DMAC_DCMD(DMA_NAND_CHANNEL) |= DMAC_DCMD_TIE;  /* Enable DMA interrupt */
 173     wakeup_wait(&nand_wkup, TIMEOUT_BLOCK);
 174 #endif
 175
 176     REG_DMAC_DCCSR(DMA_NAND_CHANNEL) &= ~DMAC_DCCSR_EN; /* Disable DMA channel */
 177
 178     dma_disable();
 179
 180     mutex_unlock(&nand_dma_mtx);
 181 }
 182
 183 static void jz_nand_read_dma(void *target, unsigned int len, int bw)
 184 {
 185     mutex_lock(&nand_dma_mtx);
 186
 187     if(((unsigned int)target < 0xa0000000) && len)
 188         dma_cache_wback_inv((unsigned long)target, len);
 189
 190     dma_enable();
 191
 192     REG_DMAC_DCCSR(DMA_NAND_CHANNEL) = DMAC_DCCSR_NDES ;
 193     REG_DMAC_DSAR(DMA_NAND_CHANNEL) = PHYSADDR((unsigned long)NAND_DATAPORT);
 194     REG_DMAC_DTAR(DMA_NAND_CHANNEL) = PHYSADDR((unsigned long)target);
 195     REG_DMAC_DTCR(DMA_NAND_CHANNEL) = len / 4;
 196     REG_DMAC_DRSR(DMA_NAND_CHANNEL) = DMAC_DRSR_RS_AUTO;
 197     REG_DMAC_DCMD(DMA_NAND_CHANNEL) = (DMAC_DCMD_SAI| DMAC_DCMD_DAI | DMAC_DCMD_DWDH_32 | DMAC_DCMD_DS_32BIT |
 198                                        (bw == 8 ? DMAC_DCMD_SWDH_8 : DMAC_DCMD_SWDH_16));
 199     REG_DMAC_DCCSR(DMA_NAND_CHANNEL) |= DMAC_DCCSR_EN; /* Enable DMA channel */
 200 #if 1
 201     while( REG_DMAC_DTCR(DMA_NAND_CHANNEL) )
 202         yield();
 203 #else
 204     REG_DMAC_DCMD(DMA_NAND_CHANNEL) |= DMAC_DCMD_TIE;  /* Enable DMA interrupt */
 205     wakeup_wait(&nand_wkup, TIMEOUT_BLOCK);
 206 #endif
 207
 208     //REG_DMAC_DCCSR(DMA_NAND_CHANNEL) &= ~DMAC_DCCSR_EN; /* Disable DMA channel */
 209
 210     dma_disable();
 211
 212     mutex_unlock(&nand_dma_mtx);
 213 }
 214
 215 void DMA_CALLBACK(DMA_NAND_CHANNEL)(void)
 216 {
 217     if (REG_DMAC_DCCSR(DMA_NAND_CHANNEL) & DMAC_DCCSR_HLT)
 218         REG_DMAC_DCCSR(DMA_NAND_CHANNEL) &= ~DMAC_DCCSR_HLT;
 219
 220     if (REG_DMAC_DCCSR(DMA_NAND_CHANNEL) & DMAC_DCCSR_AR)
 221         REG_DMAC_DCCSR(DMA_NAND_CHANNEL) &= ~DMAC_DCCSR_AR;
 222
 223     if (REG_DMAC_DCCSR(DMA_NAND_CHANNEL) & DMAC_DCCSR_CT)
 224         REG_DMAC_DCCSR(DMA_NAND_CHANNEL) &= ~DMAC_DCCSR_CT;
 225
 226     if (REG_DMAC_DCCSR(DMA_NAND_CHANNEL) & DMAC_DCCSR_TT)
 227         REG_DMAC_DCCSR(DMA_NAND_CHANNEL) &= ~DMAC_DCCSR_TT;
 228
 229     wakeup_signal(&nand_wkup);
 230 }
 231 #endif /* USE_DMA */
 232
 233 static inline void jz_nand_read_buf(void *buf, int count, int bw)
 234 {
 235 #ifdef USE_DMA
 236     if (bw == 8)
 237         jz_nand_read_dma(buf, count, 8);
 238     else
 239         jz_nand_read_dma(buf, count, 16);
 240 #else
 241     if (bw == 8)
 242         jz_nand_read_buf8(buf, count);
 243     else
 244         jz_nand_read_buf16(buf, count);
 245 #endif
 246 }
 247
 248 #ifdef USE_ECC
 249 /*
 250  * Correct 1~9-bit errors in 512-bytes data
 251  */
 252 static void jz_rs_correct(unsigned char *dat, int idx, int mask)
 253 {
 254     int i, j;
 255     unsigned short d, d1, dm;
 256
 257     i = (idx * 9) >> 3;
 258     j = (idx * 9) & 0x7;
 259
 260     i = (j == 0) ? (i - 1) : i;
 261     j = (j == 0) ? 7 : (j - 1);
 262
 263     if (i > 512)
 264         return;
 265
 266     if (i == 512)
 267         d = dat[i - 1];
 268     else
 269         d = (dat[i] << 8) | dat[i - 1];
 270
 271     d1 = (d >> j) & 0x1ff;
 272     d1 ^= mask;
 273
 274     dm = ~(0x1ff << j);
 275     d = (d & dm) | (d1 << j);
 276
 277     dat[i - 1] = d & 0xff;
 278     if (i < 512)
 279         dat[i] = (d >> 8) & 0xff;
 280 }
 281 #endif
 282
 283 /*
 284  * Read oob
 285  */
 286 static int jz_nand_read_oob(unsigned long page_addr, unsigned char *buf, int size)
 287 {
 288     struct nand_param *nandp = &internal_param;
 289     int page_size, row_cycle, bus_width;
 290     int col_addr;
 291
 292     page_size = nandp->page_size;
 293     row_cycle = nandp->row_cycle;
 294     bus_width = nandp->bus_width;
 295
 296     if (page_size >= 2048)
 297         col_addr = page_size;
 298     else
 299         col_addr = 0;
 300
 301     if (page_size >= 2048)
 302         /* Send READ0 command */
 303         __nand_cmd(NAND_CMD_READ0);
 304     else
 305         /* Send READOOB command */
 306         __nand_cmd(NAND_CMD_READOOB);
 307
 308     /* Send column address */
 309     __nand_addr(col_addr & 0xff);
 310     if (page_size >= 2048)
 311         __nand_addr((col_addr >> 8) & 0xff);
 312
 313     /* Send page address */
 314     __nand_addr(page_addr & 0xff);
 315     __nand_addr((page_addr >> 8) & 0xff);
 316     if (row_cycle == 3)
 317         __nand_addr((page_addr >> 16) & 0xff);
 318
 319     /* Send READSTART command for 2048 ps NAND */
 320     if (page_size >= 2048)
 321         __nand_cmd(NAND_CMD_READSTART);
 322
 323     /* Wait for device ready */
 324     jz_nand_wait_ready();
 325
 326     /* Read oob data */
 327     jz_nand_read_buf(buf, size, bus_width);
 328
 329     return 0;
 330 }
 331
 332
 333 /*
 334  * nand_read_page()
 335  *
 336  * Input:
 337  *
 338  *    block - block number: 0, 1, 2, ...
 339  *    page - page number within a block: 0, 1, 2, ...
 340  *    dst - pointer to target buffer
 341  */
 342 static int jz_nand_read_page(unsigned long page_addr, unsigned char *dst)
 343 {
 344     struct nand_param *nandp = &internal_param;
 345     int page_size, oob_size, page_per_block;
 346     int row_cycle, bus_width, ecc_count;
 347     int i;
 348 #ifdef USE_ECC
 349     int j;
 350 #endif
 351     unsigned char *data_buf;
 352     unsigned char oob_buf[nandp->oob_size];
 353
 354     if(nand_address == 0)
 355         return -1;
 356
 357     page_size = nandp->page_size;
 358     oob_size = nandp->oob_size;
 359     page_per_block = nandp->page_per_block;
 360     row_cycle = nandp->row_cycle;
 361     bus_width = nandp->bus_width;
 362
 363     /*
 364      * Read oob data
 365      */
 366     jz_nand_read_oob(page_addr, oob_buf, oob_size);
 367
 368     /*
 369      * Read page data
 370      */
 371
 372     /* Send READ0 command */
 373     __nand_cmd(NAND_CMD_READ0);
 374
 375     /* Send column address */
 376     __nand_addr(0);
 377     if (page_size >= 2048)
 378         __nand_addr(0);
 379
 380     /* Send page address */
 381     __nand_addr(page_addr & 0xff);
 382     __nand_addr((page_addr >> 8) & 0xff);
 383     if (row_cycle >= 3)
 384         __nand_addr((page_addr >> 16) & 0xff);
 385
 386     /* Send READSTART command for 2048 ps NAND */
 387     if (page_size >= 2048)
 388         __nand_cmd(NAND_CMD_READSTART);
 389
 390     /* Wait for device ready */
 391     jz_nand_wait_ready();
 392
 393     /* Read page data */
 394     data_buf = dst;
 395
 396     ecc_count = page_size / ECC_BLOCK;
 397
 398     for (i = 0; i < ecc_count; i++)
 399     {
 400 #ifdef USE_ECC
 401         volatile unsigned char *paraddr = (volatile unsigned char *)EMC_NFPAR0;
 402         unsigned int stat;
 403
 404         /* Enable RS decoding */
 405         REG_EMC_NFINTS = 0x0;
 406         __nand_ecc_rs_decoding();
 407 #endif
 408
 409         /* Read data */
 410         jz_nand_read_buf((void *)data_buf, ECC_BLOCK, bus_width);
 411
 412 #ifdef USE_ECC
 413         /* Set PAR values */
 414         for (j = 0; j < PAR_SIZE; j++)
 415             *paraddr++ = oob_buf[ECC_POS + i*PAR_SIZE + j];
 416
 417         /* Set PRDY */
 418         REG_EMC_NFECR |= EMC_NFECR_PRDY;
 419
 420         /* Wait for completion */
 421         __nand_ecc_decode_sync();
 422
 423         /* Disable decoding */
 424         __nand_ecc_disable();
 425
 426         /* Check result of decoding */
 427         stat = REG_EMC_NFINTS;
 428         if (stat & EMC_NFINTS_ERR)
 429         {
 430             /* Error occurred */
 431             if (stat & EMC_NFINTS_UNCOR)
 432             {
 433                 /* Uncorrectable error occurred */
 434                 logf("Uncorrectable ECC error at NAND page address 0x%lx", page_addr);
 435                 return -1;
 436             }
 437             else
 438             {
 439                 unsigned int errcnt, index, mask;
 440
 441                 errcnt = (stat & EMC_NFINTS_ERRCNT_MASK) >> EMC_NFINTS_ERRCNT_BIT;
 442                 switch (errcnt)
 443                 {
 444                 case 4:
 445                     index = (REG_EMC_NFERR3 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT;
 446                     mask = (REG_EMC_NFERR3 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT;
 447                     jz_rs_correct(data_buf, index, mask);
 448                 case 3:
 449                     index = (REG_EMC_NFERR2 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT;
 450                     mask = (REG_EMC_NFERR2 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT;
 451                     jz_rs_correct(data_buf, index, mask);
 452                 case 2:
 453                     index = (REG_EMC_NFERR1 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT;
 454                     mask = (REG_EMC_NFERR1 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT;
 455                     jz_rs_correct(data_buf, index, mask);
 456                 case 1:
 457                     index = (REG_EMC_NFERR0 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT;
 458                     mask = (REG_EMC_NFERR0 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT;
 459                     jz_rs_correct(data_buf, index, mask);
 460                     break;
 461                 default:
 462                     break;
 463                 }
 464             }
 465         }
 466 #endif
 467
 468         data_buf += ECC_BLOCK;
 469     }
 470
 471     return 0;
 472 }
 473
 474 /*
 475  * Disable NAND controller
 476  */
 477 static void jz_nand_disable(void)
 478 {
 479     REG_EMC_NFCSR &= ~(EMC_NFCSR_NFCE1 | EMC_NFCSR_NFCE2 |
 480                        EMC_NFCSR_NFCE3 | EMC_NFCSR_NFCE4 |
 481                        EMC_NFCSR_NFE1 | EMC_NFCSR_NFE2   |
 482                        EMC_NFCSR_NFE3 | EMC_NFCSR_NFE4   );
 483 }
 484
 485 /*
 486  * Enable NAND controller
 487  */
 488 static void jz_nand_enable(void)
 489 {
 490 #if 0
 491     /* OF RE */
 492     REG_GPIO_PXFUNS(1) = 0x1E018000; // __gpio_as_func0() start
 493     REG_GPIO_PXSELC(1) = 0x1E018000; // __gpio_as_func0() end
 494
 495     REG_GPIO_PXFUNS(2) = 0x3000<<16; // __gpio_as_func0() start
 496     REG_GPIO_PXSELC(2) = 0x3000<<16; // __gpio_as_func0() end
 497
 498     REG_GPIO_PXFUNC(2) = 0x4000<<16; // __gpio_port_as_input() start
 499     REG_GPIO_PXSELC(2) = 0x4000<<16;
 500     REG_GPIO_PXDIRC(2) = 0x4000<<16; // __gpio_port_as_input() end
 501     REG_GPIO_PXPES(2) = 0x4000<<16; // __gpio_disable_pull()
 502
 503     REG_GPIO_PXFUNS(1) = 0x40<<16; // __gpio_as_func0() start
 504     REG_GPIO_PXSELC(1) = 0x40<<16; // __gpio_as_func0() end
 505
 506     REG_EMC_SMCR1 = (REG_EMC_SMCR1 & 0xFF) | 0x4621200;
 507     REG_EMC_SMCR2 = (REG_EMC_SMCR2 & 0xFF) | 0x4621200;
 508     REG_EMC_SMCR3 = (REG_EMC_SMCR3 & 0xFF) | 0x4621200;
 509     REG_EMC_SMCR4 = (REG_EMC_SMCR4 & 0xFF) | 0x4621200;
 510
 511     REG_EMC_SMCR1 = REG_EMC_SMCR2 = REG_EMC_SMCR3 = REG_EMC_SMCR4 = 0x6621200;
 512 #else
 513     REG_EMC_SMCR1 = REG_EMC_SMCR2 = REG_EMC_SMCR3 = REG_EMC_SMCR4 = 0x04444400;
 514 #endif
 515 }
 516
 517 static void jz_nand_select(int bank)
 518 {
 519     REG_EMC_NFCSR |= (EMC_NFCSR_NFE(bank+1) | EMC_NFCSR_NFCE(bank+1));
 520
 521     switch(bank)
 522     {
 523         case 0:
 524             nand_address = 0xB8000000;
 525             break;
 526         case 1:
 527             nand_address = 0xB4000000;
 528             break;
 529         case 2:
 530             nand_address = 0xAC000000;
 531             break;
 532         case 3:
 533             nand_address = 0xA8000000;
 534             break;
 535     }
 536 }
 537
 538 static void jz_nand_deselect(int bank)
 539 {
 540     REG_EMC_NFCSR &= ~(EMC_NFCSR_NFE(bank+1) | EMC_NFCSR_NFCE(bank+1));
 541     nand_address = 0;
 542 }
 543
 544 static int jz_nand_init(void)
 545 {
 546     unsigned char cData[5];
 547     int i;
 548
 549     jz_nand_enable();
 550
 551     for(i=0; i<4; i++)
 552     {
 553         jz_nand_select(i);
 554
 555         __nand_cmd(NAND_CMD_READID);
 556         __nand_addr(NAND_CMD_READ0);
 557         cData[0] = __nand_data8();
 558         cData[1] = __nand_data8();
 559         cData[2] = __nand_data8();
 560         cData[3] = __nand_data8();
 561         cData[4] = __nand_data8();
 562
 563         jz_nand_deselect(i);
 564
 565         logf("NAND chip %d: 0x%x 0x%x 0x%x 0x%x 0x%x", i+1, cData[0], cData[1],
 566                                                   cData[2], cData[3], cData[4]);
 567
 568         banks[i] = nand_identify(cData);
 569
 570         if(banks[i] != NULL)
 571             nr_banks++;
 572
 573         if(i == 0 && banks[i] == NULL)
 574         {
 575             panicf("Unknown NAND flash chip: 0x%x 0x%x 0x%x 0x%x 0x%x", cData[0],
 576                                           cData[1], cData[2], cData[3], cData[4]);
 577             return -1; /* panicf() doesn't return though */
 578         }
 579     }
 580     chip_info = banks[0];
 581
 582     internal_param.bus_width = 8;
 583     internal_param.row_cycle = chip_info->row_cycles;
 584     internal_param.page_size = chip_info->page_size;
 585     internal_param.oob_size = chip_info->spare_size;
 586     internal_param.page_per_block = chip_info->pages_per_block;
 587
 588     bank_size = chip_info->page_size * chip_info->blocks_per_bank / 512 * chip_info->pages_per_block;
 589
 590     jz_nand_disable();
 591
 592     return 0;
 593 }
 594
 595 int nand_init(void)
 596 {
 597     int res = 0;
 598     static bool inited = false;
 599
 600     if(!inited)
 601     {
 602         res = jz_nand_init();
 603         mutex_init(&nand_mtx);
 604 #ifdef USE_DMA
 605         mutex_init(&nand_dma_mtx);
 606         wakeup_init(&nand_wkup);
 607         system_enable_irq(DMA_IRQ(DMA_NAND_CHANNEL));
 608 #endif
 609
 610         inited = true;
 611     }
 612
 613     return res;
 614 }
 615
 616 static inline int read_sector(unsigned long start, unsigned int count,
 617                                void* buf, unsigned int chip_size)
 618 {
 619     register int ret;
 620
 621     if(UNLIKELY(start % chip_size == 0 && count == chip_size))
 622         ret = jz_nand_read_page(start / chip_size, buf);
 623     else
 624     {
 625         ret = jz_nand_read_page(start / chip_size, temp_page);
 626         memcpy(buf, temp_page + (start % chip_size), count);
 627     }
 628
 629     return ret;
 630 }
 631
 632 int nand_read_sectors(IF_MV2(int drive,) unsigned long start, int count, void* buf)
 633 {
 634 #ifdef HAVE_MULTIVOLUME
 635     (void)drive;
 636 #endif
 637     int ret = 0;
 638     unsigned int i, _count, chip_size = chip_info->page_size;
 639     unsigned long _start;
 640
 641     logf("start");
 642     mutex_lock(&nand_mtx);
 643
 644     _start = start << 9;
 645     _count = count << 9;
 646
 647     if(_count <= chip_size)
 648     {
 649         jz_nand_select(start / bank_size);
 650         ret = read_sector(_start, _count, buf, chip_size);
 651         jz_nand_deselect(start / bank_size);
 652     }
 653     else
 654     {
 655         for(i=0; i<_count && ret==0; i+=chip_size)
 656         {
 657             jz_nand_select((start+(i>>9)) / bank_size);
 658
 659             ret = read_sector(_start+i, (_count-i < chip_size ?
 660                                          _count-i : chip_size),
 661                                buf+i, chip_size);
 662
 663             jz_nand_deselect((start+(i>>9)) / bank_size);
 664         }
 665     }
 666
 667     mutex_unlock(&nand_mtx);
 668
 669     logf("nand_read_sectors(%ld, %d, 0x%x): %d", start, count, (int)buf, ret);
 670
 671     return ret;
 672 }
 673
 674 /* TODO */
 675 int nand_write_sectors(IF_MV2(int drive,) unsigned long start, int count, const void* buf)
 676 {
 677     (void)start;
 678     (void)count;
 679     (void)buf;
 680 #ifdef HAVE_MULTIVOLUME
 681     (void)drive;
 682 #endif
 683
 684     return -1;
 685 }
 686
 687 #ifdef HAVE_STORAGE_FLUSH
 688 int nand_flush(void)
 689 {
 690     return 0;
 691 }
 692 #endif
 693
 694 void nand_spindown(int seconds)
 695 {
 696     /* null */
 697     (void)seconds;
 698 }
 699
 700 void nand_sleep(void)
 701 {
 702     /* null */
 703 }
 704
 705 void nand_spin(void)
 706 {
 707     /* null */
 708 }
 709
 710 void nand_enable(bool on)
 711 {
 712     /* null - flash controller is enabled/disabled as needed. */
 713     (void)on;
 714 }
 715
 716 /* TODO */
 717 long nand_last_disk_activity(void)
 718 {
 719     return 0;
 720 }
 721
 722 int nand_spinup_time(void)
 723 {
 724     return 0;
 725 }
 726
 727 void nand_sleepnow(void)
 728 {
 729 }
 730
 731 #ifdef STORAGE_GET_INFO
 732 void nand_get_info(IF_MV2(int drive,) struct storage_info *info)
 733 {
 734 #ifdef HAVE_MULTIVOLUME
 735     (void)drive;
 736 #endif
 737
 738     /* firmware version */
 739     info->revision="0.00";
 740
 741     info->vendor="Rockbox";
 742     info->product="NAND Storage";
 743
 744     /* blocks count */
 745     info->num_sectors = bank_size * nr_banks;
 746     info->sector_size = 512;
 747 }
 748 #endif
 749
 750 #ifdef CONFIG_STORAGE_MULTI
 751 int nand_num_drives(int first_drive)
 752 {
 753     /* We don't care which logical drive number(s) we have been assigned */
 754     (void)first_drive;
 755
 756     return 1;
 757 }
 758 #endif