1 /***************************************************************************
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
10 * Copyright (C) 2004 by Jens Arnold
11 * Based on the work of Alan Korr and Jörg Hohensohn
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version 2
16 * of the License, or (at your option) any later version.
18 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
19 * KIND, either express or implied.
21 ****************************************************************************/
26 #define LCDR (PBDR_ADDR+1)
28 #define LCD_SD 1 /* PB0 = 1 --- 0001 */
29 #define LCD_SC 2 /* PB1 = 1 --- 0010 */
30 #define LCD_DS 4 /* PB2 = 1 --- 0100 */
31 #define LCD_CS 8 /* PB3 = 1 --- 1000 */
37 * LCD on JBP and JBR uses a SPI protocol to receive orders (SDA and SCK lines)
39 * - /CS -> Chip Selection line :
40 * 0 : LCD chipset is activated.
41 * - DS -> Data Selection line, latched at the rising edge
42 * of the 8th serial clock (*) :
43 * 0 : instruction register,
45 * - SC -> Serial Clock line (SDA).
46 * - SD -> Serial Data line (SCK), latched at the rising edge
47 * of each serial clock (*).
51 * \______________________________________________________/
52 * _____ ____ ____ ____ ____ ____ ____ ____ ____ _____
53 * SD \/ D7 \/ D6 \/ D5 \/ D4 \/ D3 \/ D2 \/ D1 \/ D0 \/
54 * _____/\____/\____/\____/\____/\____/\____/\____/\____/\_____
56 * _____ _ _ _ _ _ _ _ ________
57 * SC \ * \ * \ * \ * \ * \ * \ * \ *
58 * \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/
59 * _ _________________________________________________________
61 * _/\_________________________________________________________
65 .section .icode,"ax",@progbits
68 .global _lcd_write_command
69 .type _lcd_write_command,@function
71 /* Write a command byte to the lcd controller
74 * r4 - data byte (int)
78 * r1 - data byte (copied)
79 * r2 - precalculated port value (CS, DS and SC low, SD high),
81 * r3 - lcd port address
82 * r5 - 1 (byte count for reuse of the loop in _lcd_write_data)
86 mov.l .lcdr, r3 /* put lcd data port address in r3 */
87 mov r4, r1 /* copy data byte to r1 */
89 /* This code will fail if an interrupt changes the contents of PBDRL.
90 * If so, we must disable the interrupt here. */
92 mov.b @r3, r0 /* r0 = PBDRL */
93 mov #0, r5 /* fake end address - stop after first iteration */
94 or #(LCD_SD), r0 /* r0 |= LCD_SD */
95 and #(~(LCD_CS|LCD_DS|LCD_SC)), r0 /* r0 &= ~(LCD_CS|LCD_DS|LCD_SC) */
97 bra .single_transfer /* jump into the transfer loop */
98 neg r0, r2 /* r2 = 0 - r0 */
102 .global _lcd_write_data
103 .type _lcd_write_data,@function
105 /* A high performance function to write data to the display,
106 * one or multiple bytes.
114 * r1 - current data byte
115 * r2 - precalculated port value (CS and SC low, DS and SD high),
117 * r3 - lcd port address
121 mov.l .lcdr, r3 /* put lcd data port address in r3 */
122 add r4, r5 /* end address */
124 /* This code will fail if an interrupt changes the contents of PBDRL.
125 * If so, we must disable the interrupt here. If disabling interrupts
126 * for a long time (~9200 clks = ~830 µs for transferring 112 bytes on
127 * recorders)is undesirable, the loop has to be rewritten to
128 * disable/precalculate/transfer/enable for each iteration. However,
129 * this would significantly decrease performance. */
131 mov.b @r3, r0 /* r0 = PBDRL */
132 or #(LCD_DS|LCD_SD), r0 /* r0 |= LCD_DS|LCD_SD */
133 and #(~(LCD_CS|LCD_SC)), r0 /* r0 &= ~(LCD_CS|LCD_SC) */
134 neg r0, r2 /* r2 = 0 - r0 */
136 /* loop exploits that SD is on bit 0 for recorders and Ondios */
140 mov.b @r4+, r1 /* load data byte from memory */
144 shll16 r1 /* shift data to most significant byte */
146 not r1, r1 /* and invert for use with negc */
148 shll r1 /* shift the MSB into carry */
149 negc r2, r0 /* carry to SD, SC low */
150 shll r1 /* next shift here for alignment */
151 mov.b r0, @r3 /* set data to port */
152 or #(LCD_SC), r0 /* rise SC (independent of SD level) */
153 mov.b r0, @r3 /* set to port */
196 cmp/hi r4, r5 /* some blocks left? */
199 or #(LCD_CS|LCD_DS|LCD_SD|LCD_SC), r0 /* restore port */
203 /* This is the place to reenable the interrupts, if we have disabled
204 * them. See above. */
208 .global _lcd_grey_data
209 .type _lcd_grey_data,@function
211 /* A high performance function to write grey phase data to the display,
212 * one or multiple pixels.
215 * r4 - pixel value data address
216 * r5 - pixel phase data address
217 * r6 - pixel block count
220 * r0 - scratch / phase signs mask
222 * r2 - precalculated port value (CS and SC low, DS and SD high),
224 * r3 - lcd port address
225 * r4 - current value address
226 * r5 - current phase address
228 * r7/r8 - current/next block of phases (alternating)
229 * r9/r10 - current blocks of values
231 * r12 - 0x00008000 > for phase sign check
236 mov.l r8, @-r15 /* save r8 */
237 mov.l r9, @-r15 /* save r9 */
238 mov.l r10, @-r15 /* save r10 */
240 mov.l r11, @-r15 /* save r11 */
241 shll r6 /* r6 *= 8; (8 pixels per block) */
242 mov.l .lcdr, r3 /* put lcd data port address in r3 */
243 add r4, r6 /* end address */
245 /* This code will fail if an interrupt changes the contents of PBDRL.
246 * If so, we must disable the interrupt here. If disabling interrupts
247 * for a long time is undesirable, the loop has to be rewritten to
248 * disable/precalculate/transfer/enable for each iteration. However,
249 * this would significantly decrease performance. */
251 mov.b @r3, r0 /* r0 = PBDRL */
252 or #(LCD_DS|LCD_SD), r0 /* r0 |= LCD_DS|LCD_SD */
253 mov.l r12, @-r15 /* save r12 */
254 and #(~(LCD_CS|LCD_SC)), r0 /* r0 &= ~(LCD_CS|LCD_SC) */
255 mov.l r13, @-r15 /* save r13 */
256 neg r0, r2 /* r2 = 0 - r0 */
258 /* loop exploits that SD is on bit 0 for recorders and Ondios */
330 mov.l @r15+, r13 /* restore r13 */
331 mov #(LCD_CS|LCD_DS|LCD_SD|LCD_SC), r0
332 mov.l @r15+, r12 /* restore r12 */
333 or r0, r1 /* restore port */
334 mov.l @r15+, r11 /* restore r11 */
335 mov.l @r15+, r10 /* restore r10 */
336 mov.l @r15+, r9 /* restore r9 */
337 mov.l @r15+, r8 /* restore r8 */
341 /* This is the place to reenable the interrupts, if we have disabled
342 * them. See above. */