1 /***************************************************************************
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
10 * Copyright (C) 2002 by Alan Korr
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
20 ****************************************************************************/
24 #include "adc-target.h"
25 #include "button-target.h"
27 extern void TIMER1(void);
28 extern void TIMER2(void);
30 void __attribute__((interrupt("IRQ"))) irq_handler(void)
32 if(CURRENT_CORE
== CPU
)
34 if (CPU_INT_STAT
& TIMER1_MASK
)
36 else if (CPU_INT_STAT
& TIMER2_MASK
)
38 else if (CPU_INT_STAT
& GPIO_MASK
)
43 if (GPIOB_INT_STAT
& 0x04)
50 if (COP_INT_STAT
& TIMER2_MASK
)
57 /* TODO: The following two function have been lifted straight from IPL, and
58 hence have a lot of numeric addresses used straight. I'd like to use
59 #defines for these, but don't know what most of them are for or even what
60 they should be named. Because of this I also have no way of knowing how
61 to extend the funtions to do alternate cache configurations and/or
62 some other CPU frequency scaling. */
65 void ICODE_ATTR
__attribute__((naked
)) cpucache_flush(void)
68 "mov r0, #0xf0000000 \n"
69 "add r0, r0, #0xc000 \n" /* r0 = CACHE_FLUSH_BASE */
70 "add r1, r0, #0x2000 \n" /* r1 = CACHE_FLUSH_BASE + CACHE_SIZE */
73 "str r2, [r0], #16 \n" /* Flush */
80 void ICODE_ATTR
__attribute__((naked
)) cpucache_invalidate(void)
83 "mov r0, #0xf0000000 \n"
84 "add r2, r0, #0x4000 \n" /* r1 = CACHE_INVALIDATE_BASE */
85 "add r0, r0, #0xc000 \n" /* r0 = CACHE_FLUSH_BASE */
86 "add r1, r0, #0x2000 \n" /* r2 = CACHE_FLUSH_BASE + CACHE_SIZE */
89 "str r3, [r0], #16 \n" /* Flush */
90 "str r3, [r2], #16 \n" /* Invalidate */
97 static void ipod_init_cache(void)
99 /* Initialising the cache in the iPod bootloader prevents Rockbox from starting */
101 outl(0x4000, 0xcf004020);
103 CACHE_CTL
= CACHE_CTL_INIT
;
106 "mov r0, #0xf0000000 \n"
107 "add r0, r0, #0x4000 \n" /* r0 = CACHE_INVALIDATE_BASE */
108 "add r1, r0, #0x2000 \n" /* r1 = CACHE_INVALIDATE_BASE + CACHE_SIZE */
111 "str r2, [r0], #16 \n" /* Invalidate */
114 : : : "r0", "r1", "r2"
117 /* Cache if (addr & mask) >> 16 == (mask & match) >> 16:
118 * yes: 0x00000000 - 0x03ffffff
119 * no: 0x04000000 - 0x1fffffff
120 * yes: 0x20000000 - 0x23ffffff
121 * no: 0x24000000 - 0x3fffffff <= range containing uncached alias
123 CACHE_MASK
= 0x00001c00;
124 CACHE_OPERATION
= 0x3fc0;
126 CACHE_CTL
= CACHE_CTL_INIT
| CACHE_CTL_RUN
;
129 #ifdef HAVE_ADJUSTABLE_CPU_FREQ
130 void set_cpu_frequency(long frequency
)
132 static void pp_set_cpu_frequency(long frequency
)
135 cpu_frequency
= frequency
;
137 PLL_CONTROL
|= 0x6000; /* make sure some enable bits are set */
138 CLOCK_ENABLE
= 0x01; /* select source #1 */
143 PLL_UNLOCK
= 0xd19b; /* unlock frequencies > 66MHz */
144 CLOCK_SOURCE
= 0xa9; /* source #1: 24 Mhz, source #2..#4: PLL */
145 PLL_CONTROL
= 0xe000; /* PLL enabled */
146 PLL_DIV
= 3; /* 10/3 * 24MHz */
148 udelay(200); /* wait for relock */
152 CLOCK_SOURCE
= 0xa9; /* source #1: 24 Mhz, source #2..#4: PLL */
153 PLL_CONTROL
= 0xe000; /* PLL enabled */
154 PLL_DIV
= 4; /* 5/4 * 24MHz */
156 udelay(200); /* wait for relock */
160 CLOCK_SOURCE
= 0x51; /* source #2: 32kHz, #1, #2, #4: 24MHz */
161 PLL_CONTROL
= 0x6000; /* PLL disabled */
162 udelay(10000); /* let 32kHz source stabilize? */
166 CLOCK_SOURCE
= 0x55; /* source #1..#4: 24 Mhz */
167 PLL_CONTROL
= 0x6000; /* PLL disabled */
168 cpu_frequency
= CPUFREQ_DEFAULT
;
171 CLOCK_ENABLE
= 0x02; /* select source #2 */
173 #endif /* !BOOTLOADER */
175 void system_init(void)
178 if (CURRENT_CORE
== CPU
)
180 /* Remap the flash ROM on CPU, keep hidden from COP:
181 * 0x00000000-0x03ffffff = 0x20000000-0x23ffffff */
182 MMAP1_LOGICAL
= 0x20003c00;
183 MMAP1_PHYSICAL
= 0x00003f84;
185 #if defined(IPOD_1G2G) || defined(IPOD_3G)
186 DEV_EN
= 0x0b9f; /* don't clock unused PP5002 hardware components */
187 outl(0x0035, 0xcf005004); /* DEV_EN2 ? */
199 #ifdef HAVE_ADJUSTABLE_CPU_FREQ
204 pp_set_cpu_frequency(CPUFREQ_MAX
);
211 void system_reboot(void)
217 void system_exception_wait(void)
219 /* FIXME: we just need the right buttons */
224 sleep_core(CURRENT_CORE
);
228 int system_memory_guard(int newmode
)